Bus voltage discharge circuit and energy storage power supply

Abstract

This application relates to a bus voltage discharge circuit and an energy storage power supply. The bus voltage discharge circuit includes a discharge judgment module, a switch module, and a discharge transfer module. The input ends of the discharge judgment module are respectively connected to a first inductor and a second inductor in an inverter. The output end of the discharge judgment module is connected to the controlled end of the switch module. A first bus capacitor and a second bus capacitor in the inverter are respectively connected to the discharge transfer module through the switch module. The discharge judgment module is configured to respectively collect the current signals of the first inductor and the second inductor, determine the bus capacitor to be discharged according to the two collected current signals, and generate a control signal for the switch module. The control signal is used to conduct the path between the bus capacitor to be discharged and the discharge transfer module. The bus capacitor to be discharged includes the first bus capacitor and / or the second bus capacitor. The bus voltage discharge circuit can prevent the bus capacitor from being broken down.

Description

Technical Field

[0001] The present application relates to the technical field of energy storage power supplies, and particularly to a bus voltage discharge circuit and an energy storage power supply. Background Art

[0002] With the continuous development of new energy technologies, energy storage power supplies, as a key link connecting energy production and consumption, have become increasingly important. In the energy storage power supply technology system, an inverter is the core component for realizing energy transfer. The Neutral-Point-Clamped (NPC) topology has become the mainstream application solution due to its advantages such as high output voltage level, excellent harmonic characteristics, and low switching losses.

[0003] In related technologies, when the inverter in the energy storage power supply outputs overcurrent or the output terminal of the inverter is short-circuited, the energy stored in the inductor in the inverter will discharge its own energy to the bus capacitor through a freewheeling method. However, since the withstand voltage value of the bus capacitor needs to balance cost and performance, the withstand voltage margin is usually limited, and continuous energy impact is likely to break through its withstand voltage limit, resulting in the breakdown of the capacitor.

[0004] Therefore, there is an urgent need for a bus voltage discharge circuit that can prevent the bus capacitor from being broken down. Summary of the Invention

[0005] Based on this, in view of the above technical problems, it is necessary to provide a bus voltage discharge circuit and an energy storage power supply that can prevent the bus capacitor from being broken down.

[0006] In a first aspect, the present application provides a bus voltage discharge circuit. The bus voltage discharge circuit includes a discharge judgment module, a switch module, and a discharge transfer module. The input terminals of the discharge judgment module are respectively connected to a first inductor and a second inductor in the inverter. The output terminal of the discharge judgment module is connected to the controlled terminal of the switch module. The first bus capacitor and the second bus capacitor in the inverter are respectively connected to the discharge transfer module through the switch module.

[0007] The discharge judgment module is configured to respectively collect the current signals of the first inductor and the second inductor, determine the bus capacitor to be discharged according to the two collected current signals, and generate a control signal for the switch module. The control signal is used to conduct the path between the bus capacitor to be discharged and the discharge transfer module. The bus capacitor to be discharged includes the first bus capacitor and / or the second bus capacitor.

[0008] In one embodiment, the discharge judgment module is configured to determine the bus capacitor to be discharged according to the directions and magnitudes of the two current signals, and generate a control signal for the switch module.

[0009] In one embodiment, the discharge judgment module includes a wave blocking judgment unit and a control signal generation unit. The input end of the wave blocking judgment unit is respectively connected to the first inductor and the second inductor in the inverter, and the control signal generation unit is used to connect the output end of the wave blocking judgment unit to the switch module;

[0010] The wave blocking judgment unit is configured to output a wave blocking signal corresponding to the first inductor based on the direction of the current signal of the first inductor when the current signal of the first inductor is greater than a preset value; and, output a wave blocking signal corresponding to the second inductor based on the direction of the current signal of the second inductor when the current signal of the second inductor is greater than a preset value; the wave blocking signal includes a positive wave blocking signal and a negative wave blocking signal;

[0011] The control signal generation unit is configured to output a first control signal when the wave blocking signals corresponding to the first inductor and the second inductor are both positive wave blocking signals; the first control signal is used to conduct the path between the second bus capacitor and the discharge transfer module;

[0012] Output a second control signal when the wave blocking signals corresponding to the first inductor and the second inductor are both negative wave blocking signals; the second control signal is used to conduct the path between the first bus capacitor and the discharge transfer module;

[0013] And, output a third control signal when one of the wave blocking signal corresponding to the first inductor and the wave blocking signal corresponding to the second inductor is a positive wave blocking signal and the other is a negative wave blocking signal; the third control signal is used to conduct the path between the first bus capacitor and the discharge transfer module and the path between the second bus capacitor and the discharge transfer module.

[0014] In one embodiment, the control signal generation unit includes a positive wave blocking signal conversion sub-unit and a negative wave blocking signal conversion sub-unit, the switch module includes a positive switch unit and a negative switch unit, and the discharge transfer module includes a positive discharge transfer unit and a negative discharge transfer unit;

[0015] The input end of the positive wave blocking signal conversion sub-unit and the input end of the negative wave blocking signal conversion sub-unit are both connected to the output end of the wave blocking judgment unit, the output end of the positive wave blocking signal conversion sub-unit is connected to the positive switch unit, and the output end of the negative wave blocking signal conversion sub-unit is connected to the negative switch unit;

[0016] The positive wave blocking signal conversion sub-unit is configured to receive the positive wave blocking signal output by the wave blocking judgment unit and convert the positive wave blocking signal into a positive control signal of the positive switch unit; the positive control signal is used to conduct the path between the second bus capacitor and the discharge transfer module;

[0017] The negative wave signal conversion sub-unit is used to receive the negative wave signal output by the wave sealing judgment unit and convert the negative wave signal into a negative control signal for the negative switch unit; the negative control signal is used to conduct the path between the first bus capacitor and the discharge transfer module.

[0018] In one embodiment, the positive wave signal conversion sub-unit includes a positive switching control component and a positive transfer control component, the positive switch unit includes a positive switch switching sub-unit and a positive switch sub-unit, and the positive discharge transfer unit includes a positive discharge transfer resistor;

[0019] The input end of the positive switching control component and the input end of the positive transfer control component are both connected to the output end of the wave sealing judgment unit. The output end of the positive switching control component is connected to the coil of the positive switch switching sub-unit. The normally closed end of the positive switch switching sub-unit is connected to the positive pole of the first bus capacitor, and the normally open end of the positive switch switching sub-unit is connected to the negative pole of the second bus capacitor;

[0020] The output end of the positive transfer control component is connected to the coil of the positive switch sub-unit. The normally open end of the positive switch sub-unit is connected to the common end of the first bus capacitor and the second bus capacitor connected in series;

[0021] The positive discharge transfer resistor is arranged between the common end of the positive switch switching sub-unit and the common end of the positive switch sub-unit.

[0022] In one embodiment, the positive switching control component includes a first resistor, a second resistor, a third resistor, a first diode, a second diode, and a first switching tube, and the positive switch switching sub-unit includes a first relay;

[0023] The negative poles of the first diode and the second diode are both connected to the output end of the wave sealing judgment unit. The positive poles of the first diode and the second diode are both connected to the input end of the first resistor. The output end of the first resistor is respectively connected to the input end of the second resistor and the base of the first switching tube. The emitter of the first switching tube is connected to the input end of the third resistor. The output ends of the second resistor and the third resistor are both connected to the coil of the first relay. The input end of the first relay is connected to the power supply. The common end of the first relay is connected to the positive discharge transfer resistor. The normally closed end of the first relay is connected to the positive pole of the first bus capacitor. The normally open end of the first relay is connected to the negative pole of the second bus capacitor, and the collector of the first switching tube is grounded.

[0024] In one embodiment, the positive transfer control component includes a fourth resistor, a fifth resistor, a sixth resistor, a third diode, a fourth diode, a fifth diode, a sixth diode, and a second switching tube, and the positive switch sub-unit includes a second relay;

[0025] The cathodes of the third diode, the fourth diode, the fifth diode, and the sixth diode are all connected to the wave blocking judgment unit. The anodes of the third diode, the fourth diode, the fifth diode, and the sixth diode are all connected to the input end of resistor four. The output end of resistor four is respectively connected to the input end of resistor five and the base of the second switching transistor. The emitter of the second switching transistor is connected to the input end of resistor six. The input end of the second relay is connected to the power supply. The output ends of resistor five and resistor six are both connected to the coil of the second relay. The normally open terminal of the second relay is connected to the common terminal of the first bus capacitor and the second bus capacitor connected in series. The common terminal of the second relay is connected to the positive discharge transfer resistor, and the collector of the second switching transistor is grounded.

[0026] In one embodiment, the negative wave blocking signal conversion sub-unit includes a negative switching control component and a negative transfer control component. The negative switching unit includes a negative switch switching sub-unit and a negative switch sub-unit. The negative discharge transfer unit includes a negative discharge transfer resistor.

[0027] The input ends of the negative switching control component and the negative transfer control component are both connected to the output end of the wave blocking judgment unit. The output end of the negative switching control component is connected to the coil of the negative switch switching sub-unit. The normally closed terminal of the negative switch switching sub-unit is connected to the cathode of the second bus capacitor. The normally open terminal of the negative switch switching sub-unit is connected to the anode of the first bus capacitor.

[0028] The output end of the negative transfer control component is connected to the coil of the negative switch sub-unit. The normally open terminal of the negative switch sub-unit is connected to the common terminal of the first bus capacitor and the second bus capacitor connected in series.

[0029] The negative discharge transfer resistor is arranged between the common terminal of the negative switch switching sub-unit and the common terminal of the negative switch sub-unit.

[0030] In one embodiment, the negative switching control component includes resistor seven, resistor eight, resistor nine, the seventh diode, the eighth diode, and the third switching transistor. The negative switch switching sub-unit includes the third relay.

[0031] The cathodes of the seventh diode and the eighth diode are both connected to the wave blocking judgment unit. The anodes of the seventh diode and the eighth diode are both connected to the input end of resistor seven. The output end of resistor seven is respectively connected to the input end of resistor eight and the base of the third switching transistor. The emitter of the third switching transistor is connected to the input end of resistor nine. The output ends of resistor eight and resistor nine are both connected to the coil of the third relay. The input end of the third relay is connected to the power supply. The common terminal of the third relay is connected to the negative discharge transfer resistor. The normally closed terminal of the third relay is connected to the cathode of the second bus capacitor. The normally open terminal of the third relay is connected to the anode of the first bus capacitor, and the collector of the third switching transistor is grounded.

[0032] In one embodiment, the negative transfer control component includes a resistor R10, a resistor R11, a resistor R12, a ninth diode, a twelfth diode, an eleventh diode, a twelfth diode, and a fourth switching transistor. The negative switching sub-unit includes a fourth relay.

[0033] The negative electrodes of the ninth diode, the twelfth diode, the eleventh diode, and the twelfth diode are all connected to the wave-blocking judgment unit. The positive electrodes of the ninth diode, the twelfth diode, the eleventh diode, and the twelfth diode are all connected to the input end of the resistor R10.

[0034] The output end of the resistor R10 is respectively connected to the input end of the resistor R11 and the base of the fourth switching transistor. The emitter of the fourth switching transistor is connected to the input end of the resistor R12. The input end of the fourth relay is connected to the power supply. The output ends of the resistor R11 and the resistor R12 are both connected to the coil of the fourth relay. The normally open terminal of the fourth relay is connected to the common terminal of the first bus capacitor and the second bus capacitor connected in series. The common terminal of the fourth relay is connected to the negative discharge transfer resistor, and the collector of the fourth switching transistor is grounded.

[0035] In one embodiment, the wave-blocking judgment unit includes a current sampling sub-unit and an identification sub-unit. The input end of the current sampling sub-unit is respectively connected to the first inductor and the second inductor in the inverter. The identification sub-unit is used to connect the output end of the current sampling sub-unit to the control signal generation unit.

[0036] The current sampling sub-unit is used to collect the current signals of the first inductor and the second inductor.

[0037] The identification sub-unit is used to identify the positive and negative of the wave-blocking signal corresponding to the first inductor according to the direction of the current signal of the first inductor and output the wave-blocking signal corresponding to the first inductor. And, according to the direction of the current signal of the second inductor, identify the positive and negative of the wave-blocking signal corresponding to the second inductor and output the wave-blocking signal corresponding to the second inductor.

[0038] In a second aspect, the present application also provides an energy storage power supply, which includes an inverter and any one of the bus voltage discharge circuits in the first aspect.

[0039] The above-mentioned bus voltage discharge circuit and energy storage power supply. The bus voltage discharge circuit includes a discharge judgment module, a switch module, and a discharge transfer module. The input terminals of the discharge judgment module are respectively connected to a first inductor and a second inductor in the inverter. The output terminal of the discharge judgment module is connected to the controlled terminal of the switch module. A first bus capacitor and a second bus capacitor in the inverter are respectively connected to the discharge transfer module through the switch module. The discharge judgment module is used to respectively collect the current signals of the first inductor and the second inductor, determine the bus capacitor to be discharged according to the two collected current signals, and generate a control signal for the switch module. The control signal is used to conduct the path between the bus capacitor to be discharged and the discharge transfer module. The bus capacitor to be discharged includes the first bus capacitor and / or the second bus capacitor. The discharge judgment module in the bus voltage discharge circuit can collect the current signals of the first inductor and the second inductor in the inverter, accurately judge the bus capacitor to be discharged, and by outputting a control signal to the switch module, timely conduct the path between the bus capacitor to be discharged and the discharge transfer module, so that the bus capacitor to be discharged is maintained within a relatively stable range, preventing the bus capacitor from being broken down. In this way, the influence of voltage fluctuation on the output of the inverter can be reduced, the quality of the electric energy output by the inverter can be improved, and the stable operation of the load connected to the inverter can be ensured. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments of the present application or related technologies. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0041] Figure 1 It is a circuit schematic diagram of an inverter in an embodiment;

[0042] Figure 2 It is a first schematic diagram of a bus voltage discharge circuit in an embodiment;

[0043] Figure 3 It is a second schematic diagram of a bus voltage discharge circuit in an embodiment;

[0044] Figure 4 It is a third schematic diagram of a bus voltage discharge circuit in an embodiment;

[0045] Figure 5 It is a fourth schematic diagram of a bus voltage discharge circuit in an embodiment;

[0046] Figure 6 It is a schematic diagram of a wave blocking judgment unit in an embodiment.

[0047] Description of the drawing reference numerals:

[0048] 10: Bus voltage discharge circuit; 11: Discharge judgment module; 12: Switch module; 121: Positive switch unit; 1211: Positive switch switching subunit; 1212: Positive switch subunit; 122: Negative switch unit; 1221: Negative switch switching subunit; 1222: Negative switch subunit; 13: Discharge transfer module; 131: Positive discharge transfer unit; 132: Negative discharge transfer unit; 14: Wave blocking judgment unit; 141: Current sampling subunit; 142: Identification subunit; 15: Control signal generation unit; 151: Positive wave blocking signal conversion subunit; 1511: Positive switching control component; 1512: Positive transfer control component; 152: Negative wave blocking signal conversion subunit; 1521: Negative switching control component; 1522: Negative transfer control component; 20: Inverter. Detailed implementation manners

[0049] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0050] In the description of the present application, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present application, the meaning of "a plurality" is at least two, for example, two, three, etc., unless otherwise specifically defined.

[0051] In the present application, unless otherwise clearly defined and limited, the terms "connected" and "connected" should be understood in a broad sense. For example, it may be an electrical connection, may be directly connected, or may be indirectly connected through an intermediate medium, unless otherwise clearly limited. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.

[0052] Before introducing the technical solutions of the present application in detail, the background technology of the present application will be briefly introduced.

[0053] With the continuous development of new energy technologies, energy storage power supplies, as a key link connecting energy production and consumption, are becoming increasingly important. For high-power energy storage power supplies, in order to meet a wide range of application scenarios, high-power energy storage power supplies are compatible with single-phase single-wire AC output, two-way single-phase single-wire AC parallel output, and split-phase double-wire AC output.

[0054] To be compatible with the above functions, the inverter in the energy storage power supply uses an NPC topology structure. Figure 1 Figure 1 is a circuit schematic diagram of the inverter, which is a two-phase "T"-type three-level inverter. The inverter is composed of eight switching tubes (the eleventh switching tube Q11, the twelfth switching tube Q12, the thirteenth switching tube Q13, the fourteenth switching tube Q14, the fifteenth switching tube Q15, the sixteenth switching tube Q16, the seventeenth switching tube Q17, and the eighteenth switching tube Q18), two inductors (the first inductor LD1 and the second inductor LD2), and four capacitors (the first capacitor C1, the second capacitor C2, the first bus capacitor CE1, and the second bus capacitor CE2). Since the inductor current cannot change suddenly and needs to freewheel, the energy stored in the inductor will be dissipated through the freewheeling method. When the current of the first inductor LD1 or the current of the second inductor LD2 exceeds the protection limit in the positive half-wave, that is, the clockwise loop in the figure, all the energy stored in the first inductor LD1 and the second inductor LD2 is dissipated to the second bus capacitor CE2, causing the voltage of the second bus capacitor CE2 to rise.

[0055] When the current of the first inductor LD1 or the current of the second inductor LD2 exceeds the protection limit in the negative half-wave, that is, the counterclockwise loop in the figure, all the energy stored in the first inductor LD1 and the second inductor LD2 is dissipated to the first bus capacitor CE1, causing the voltage of the first bus capacitor CE1 to rise.

[0056] When the first inductor LD1 and the second inductor LD2 are both triggered to block the wave, the first inductor LD1 is triggered to block the wave in the positive half-wave and the second inductor LD2 is triggered to block the wave in the negative half-wave, or the first inductor LD1 is triggered to block the wave in the negative half-wave and the second inductor LD2 is triggered to block the wave in the positive half-wave. According to the freewheeling loop, the voltages of the first bus capacitor CE1 and the second bus capacitor CE2 will both rise.

[0057] If both the first inductor LD1 and the second inductor LD2 are triggered to block the wave in the positive half-wave, according to the freewheeling loop, the voltage of the second bus capacitor CE2 will rise higher. If both the first inductor LD1 and the second inductor LD2 are triggered to block the wave in the negative half-wave, according to the freewheeling loop, the voltage of the first bus capacitor CE1 will rise higher.

[0058] When it is detected that the voltage of the first bus capacitor CE1 and / or the second bus capacitor CE2 exceeds the protection limit value, it is determined that the inverter overvoltage fault is triggered. When the inverter outputs overcurrent (the inductor current exceeds the protection limit value) or the output terminal of the inverter is short-circuited, the system only needs to report the overcurrent protection fault or the short-circuit protection fault. However, due to the current circuit defect, the system will simultaneously report the BUS overvoltage fault, resulting in a non-corresponding fault. In addition, due to cost considerations in design, the withstand voltage margin of the bus capacitor is not very redundant. Especially when the first inductor LD1 and the second inductor LD2 trigger and block the wave in the same half-wave, there is a risk of raising the voltage of the bus capacitor above the capacitor withstand voltage and causing the capacitor to break down.

[0059] In view of the above problems, the present application provides a bus voltage discharging circuit and an energy storage power supply, which can prevent the bus capacitor from being broken down. Of course, the technical solutions provided in the embodiments of the present application are not limited to only solving the above problems, and there are other technical effects. For specific details, please refer to the following embodiments. Next, the technical solutions of the present application will be introduced in detail.

[0060] In one embodiment, as Figure 2 shown, a bus voltage discharging circuit 10 is provided. The bus voltage discharging circuit 10 includes a discharging judgment module 11, a switch module 12, and a discharging transfer module 13. The input terminals of the discharging judgment module 11 are respectively connected to the first inductor LD1 and the second inductor LD2 in the inverter 20. The output terminal of the discharging judgment module 11 is connected to the controlled terminal of the switch module 12. The first bus capacitor CE1 and the second bus capacitor CE2 in the inverter 20 are respectively connected to the discharging transfer module 13 through the switch module 12;

[0061] The discharging judgment module 11 is configured to respectively collect the current signals of the first inductor LD1 and the second inductor LD2, determine the bus capacitor to be discharged according to the two collected current signals, and generate a control signal for the switch module 12; the control signal is used to conduct the path between the bus capacitor to be discharged and the discharging transfer module 13; the bus capacitor to be discharged includes the first bus capacitor CE1 and / or the second bus capacitor CE2.

[0062] In the embodiment of the present application, the bus voltage discharging circuit 10 mainly further discharges the voltage on the first bus capacitor CE1 and / or the second bus capacitor CE2 to avoid the breakdown of the bus capacitor due to excessive voltage, that is, to protect the inverter 20. Among them, the bus voltage discharging circuit 10 can be integrally arranged with the inverter 20, or the bus voltage discharging circuit 10 and the inverter 20 can also be arranged in the energy storage power supply at the same time.

[0063] When the currents flowing through the first inductor LD1 and the second inductor LD2 in the inverter 20 are both normal, the voltages of the first inductor LD1 and the second inductor LD2 in the inverter 20 are normal, and there is no need for discharging, nor is it necessary to further discharge using the bus voltage discharging circuit 10. At this time, the bus voltage discharging circuit 10 does not work.

[0064] When the current flowing through the first inductor LD1 and / or the second inductor LD2 in the inverter 20 is relatively large, the voltages of the first bus capacitor CE1 and / or the second bus capacitor CE2 are relatively high, and discharging is required. Considering Figure 1 it, when the currents of the first inductor LD1 and the second inductor LD2 are clockwise, the voltage of the second bus capacitor CE2 is relatively high and discharging is required; when the currents of the first inductor LD1 and the second inductor LD2 are counterclockwise, the voltage of the first bus capacitor CE1 is relatively high and discharging is required; when the first inductor LD1 is counterclockwise and the second inductor LD2 is clockwise, or when the first inductor LD1 is clockwise and the second inductor LD2 is counterclockwise, the voltages of both the first bus capacitor CE1 and the second bus capacitor CE2 are relatively high and both need to be discharged. In the above cases, it is necessary for the bus voltage discharging circuit 10 to further discharge the voltages in the first bus capacitor CE1 and / or the second bus capacitor CE2. At this time, the switch module 12 in the bus voltage discharging circuit 10 is in the conducting state to discharge the voltages of the first bus capacitor CE1 and / or the second bus capacitor CE2.

[0065] During the operation of the bus voltage discharging circuit 10, the discharging judgment module 11 is mainly used to respectively collect the current signals of the first inductor LD1 and the second inductor LD2, and determine the bus capacitor with a relatively high voltage to be discharged according to the current signals of the first inductor LD1 and the second inductor LD2. Then, a control signal for the switch module 12 is generated according to the bus capacitor to be discharged to conduct the path between the bus capacitor to be discharged and the discharging transfer module 13.

[0066] If the bus capacitor to be discharged is the first bus capacitor CE1, control the switch module 12 to conduct the path between the first bus capacitor CE1 and the discharging transfer module 13; if the bus capacitor to be discharged is the second bus capacitor CE2, control the switch module 12 to conduct the path between the second bus capacitor CE2 and the discharging transfer module 13; if the bus capacitors to be discharged are the first bus capacitor CE1 and the second bus capacitor CE2, control the switch module 12 to conduct the path between the first bus capacitor CE1 and the discharging transfer module 13 and the path between the second bus capacitor CE2 and the discharging transfer module 13.

[0067] In one embodiment, the discharging judgment module 11 is used to determine the bus capacitor to be discharged according to the directions and magnitudes of the two current signals, and generate a control signal for the switch module 12.

[0068] Specifically, if the currents of the first inductor LD1 and the second inductor LD2 do not exceed the preset current threshold, it indicates that the inverter 20 is operating normally and there is no need for the bus voltage discharge circuit 10 to discharge. If the current of any one of the first inductor LD1 and the second inductor LD2 exceeds the preset current threshold, or the currents of both the first inductor LD1 and the second inductor LD2 exceed the preset current threshold, then the bus voltage discharge circuit 10 is required to discharge.

[0069] Exemplarily, the currents of the first inductor LD1 and the second inductor LD2 are both clockwise, and the voltages of the first inductor LD1 and the second inductor LD2 are both applied to the second bus capacitor CE2. At this time, the bus capacitor to be discharged is the second bus capacitor CE2. The currents of the first inductor LD1 and the second inductor LD2 are both counterclockwise, and the voltages of the first inductor LD1 and the second inductor LD2 are both applied to the first bus capacitor CE1. At this time, the bus capacitor to be discharged is the first bus capacitor CE1. The first inductor LD1 is counterclockwise and the second inductor LD2 is clockwise, or the first inductor LD1 is clockwise and the second inductor LD2 is counterclockwise. Both the first bus capacitor CE1 and the second bus capacitor CE2 are the bus capacitors to be discharged.

[0070] Among them, the discharge judgment module 11 can be implemented by a logic circuit. For example, the logic circuit can be basic logic gate circuits such as an inverter, an AND gate, or an OR gate. When the current signals of the first inductor LD1 and the second inductor LD2 are collected, the discharge judgment module 11 can generate a control signal through logical operations to control the switch module 12 to conduct.

[0071] The switch module 12 is mainly used to conduct or cut off the path between the first bus capacitor CE1 and the discharge transfer module 13, and / or the path between the second bus capacitor CE2 and the discharge transfer module 13. When receiving the control signal output by the discharge judgment module 11, it conducts the path between the first bus capacitor CE1 and / or the second bus capacitor CE2 and the discharge transfer module 13. Since the switch module 12 is used to conduct or cut off the paths between the two bus capacitors and the discharge transfer module 13 respectively, then, two different switches can be set for the switch module 12, and these two switches are respectively used to conduct or cut off the paths between the two bus capacitors and the discharge transfer module 13. Among them, the switch module 12 can be implemented by a power switch device. For example, a semiconductor field effect transistor or an insulated gate bipolar transistor.

[0072] The discharge transfer module 13 is mainly used to receive the voltage discharged from the first bus capacitor CE1 and / or the second bus capacitor CE2, and consume or transfer it. Among them, the discharge transfer module 13 can be implemented by a resistor, a combinational circuit (including a resistor and a capacitor).

[0073] The above-mentioned bus voltage discharge circuit 10 includes a discharge judgment module 11, a switch module 12, and a discharge transfer module 13. The input terminals of the discharge judgment module 11 are respectively connected to the first inductor LD1 and the second inductor LD2 in the inverter 20. The output terminal of the discharge judgment module 11 is connected to the controlled terminal of the switch module 12. The first bus capacitor CE1 and the second bus capacitor CE2 in the inverter 20 are respectively connected to the discharge transfer module 13 through the switch module 12. The discharge judgment module 11 is configured to respectively collect the current signals of the first inductor LD1 and the second inductor LD2, determine the bus capacitor to be discharged according to the two collected current signals, and generate a control signal for the switch module 12. The control signal is used to conduct the path between the bus capacitor to be discharged and the discharge transfer module 13. The bus capacitor to be discharged includes the first bus capacitor CE1 and / or the second bus capacitor CE2. The discharge judgment module 11 in the bus voltage discharge circuit 10 can collect the current signals of the first inductor LD1 and the second inductor LD2 in the inverter 20, accurately judge the bus capacitor to be discharged, and timely conduct the path between the bus capacitor to be discharged and the discharge transfer module 13 by outputting a control signal to the switch module 12, so that the bus capacitor to be discharged is maintained within a relatively stable range, preventing the bus capacitor from being broken down. In this way, the influence of voltage fluctuation on the output of the inverter 20 can be reduced, the quality of the electric energy output by the inverter 20 can be improved, and it is ensured that the load connected to the inverter 20 can operate stably.

[0074] Next, a specific example is used to introduce the discharge judgment module 11 in the bus voltage discharge circuit 10, as Figure 3 shown, the discharge judgment module 11 includes a wave blocking judgment unit 14 and a control signal generation unit 15. The input terminals of the wave blocking judgment unit 14 are respectively connected to the first inductor LD1 and the second inductor LD2 in the inverter 20. The control signal generation unit 15 is used to connect the output terminal of the wave blocking judgment unit 14 to the switch module 12;

[0075] The wave blocking judgment unit 14 is configured to output a wave blocking signal corresponding to the first inductor LD1 based on the direction of the current signal of the first inductor LD1 when the current signal of the first inductor LD1 is greater than a preset value; and output a wave blocking signal corresponding to the second inductor LD2 based on the direction of the current signal of the second inductor LD2 when the current signal of the second inductor LD2 is greater than a preset value. The wave blocking signal includes a positive wave blocking signal and a negative wave blocking signal;

[0076] The control signal generation unit 15 is configured to output a first control signal when the wave blocking signals corresponding to the first inductor LD1 and the second inductor LD2 are both positive wave blocking signals. The first control signal is used to conduct the path between the second bus capacitor CE2 and the discharge transfer module 13;

[0077] When the clamping signals corresponding to the first inductor LD1 and the second inductor LD2 are both negative clamping signals, a second control signal is output; the second control signal is used to conduct the path between the first bus capacitor CE1 and the discharge transfer module 13.

[0078] In addition, when one of the clamping signals corresponding to the first inductor LD1 and the clamping signal corresponding to the second inductor LD2 is a positive clamping signal and the other is a negative clamping signal, a third control signal is output; the third control signal is used to conduct the path between the first bus capacitor CE1 and the discharge transfer module 13, and the path between the second bus capacitor CE2 and the discharge transfer module 13.

[0079] In the embodiment of the present application, the above discharge judgment module 11 can be subdivided into two units, namely a clamping judgment unit 14 and a control signal generation unit 15. The clamping judgment unit 14 is arranged between the control signal generation unit 15 and the inverter 20, and is mainly used to collect the currents of the first inductor LD1 and the second inductor LD2 in the inverter 20, and judge whether the currents of the first inductor LD1 and the second inductor LD2 exceed a preset value, so as to determine whether the voltages of the first bus capacitor CE1 and the second bus capacitor CE2 need to be discharged. If the preset value is exceeded, continue to determine the clamping signal corresponding to the first inductor LD1 based on the direction of the current signal of the first inductor LD1, and determine the clamping signal corresponding to the second inductor LD2 based on the direction of the current signal of the second inductor LD2.

[0080] Exemplarily, the current of the first inductor LD1 is clockwise, and the clamping signal corresponding to the first inductor LD1 is a positive clamping signal; the current of the second inductor LD2 is clockwise, and the clamping signal corresponding to the second inductor LD2 is a positive clamping signal. The current of the first inductor LD1 is counterclockwise, and the clamping signal corresponding to the first inductor LD1 is a negative clamping signal; the current of the second inductor LD2 is counterclockwise, and the clamping signal corresponding to the second inductor LD2 is a negative clamping signal.

[0081] After receiving the clamping signal corresponding to the first inductor LD1 and the clamping signal corresponding to the second inductor LD2, the control signal generation unit 15 outputs different control signals based on the positive and negative of the clamping signal. Specifically, if both clamping signals are positive clamping signals, a first control signal is output to conduct the path between the second bus capacitor CE2 and the discharge transfer module 13. If both clamping signals are negative clamping signals, a second control signal is output to conduct the path between the first bus capacitor CE1 and the discharge transfer module 13.

[0082] If any one of the two clamped-wave signals is a positive clamped-wave signal and the other is a negative clamped-wave signal, a third control signal is output to turn on the path between the first bus capacitor CE1 and the discharge transfer module 13 and the path between the second bus capacitor CE2 and the discharge transfer module 13.

[0083] If there is only one inductor corresponding to a clamped-wave signal among the two inductors, and the other inductor has no clamped-wave signal due to a small current. When the clamped-wave signal is a positive clamped-wave signal, a fourth control signal is output to turn on the path between the second bus capacitor CE2 and the discharge transfer module 13. When the clamped-wave signal is a negative clamped-wave signal, a fifth control signal is output to turn on the path between the first bus capacitor CE1 and the discharge transfer module 13.

[0084] The above discharge judgment module 11 includes a clamped-wave judgment unit 14 and a control signal generation unit 15. The input ends of the clamped-wave judgment unit 14 are respectively connected to the first inductor LD1 and the second inductor LD2 in the inverter 20. The control signal generation unit 15 is used to connect the output end of the clamped-wave judgment unit 14 to the switch module 12. The clamped-wave judgment unit 14 is configured to output a clamped-wave signal corresponding to the first inductor LD1 based on the direction of the current signal of the first inductor LD1 when the current signal of the first inductor LD1 is greater than a preset value; and output a clamped-wave signal corresponding to the second inductor LD2 based on the direction of the current signal of the second inductor LD2 when the current signal of the second inductor LD2 is greater than a preset value. The clamped-wave signals include positive clamped-wave signals and negative clamped-wave signals. The control signal generation unit 15 is configured to output a first control signal when the clamped-wave signals corresponding to the first inductor LD1 and the second inductor LD2 are both positive clamped-wave signals. The first control signal is used to turn on the path between the second bus capacitor CE2 and the discharge transfer module 13. Output a second control signal when the clamped-wave signals corresponding to the first inductor LD1 and the second inductor LD2 are both negative clamped-wave signals. The second control signal is used to turn on the path between the first bus capacitor CE1 and the discharge transfer module 13. And output a third control signal when one of the clamped-wave signal corresponding to the first inductor LD1 and the clamped-wave signal corresponding to the second inductor LD2 is a positive clamped-wave signal and the other is a negative clamped-wave signal. The third control signal is used to turn on the path between the first bus capacitor CE1 and the discharge transfer module 13 and the path between the second bus capacitor CE2 and the discharge transfer module 13. Through the clamped-wave judgment unit 14, the discharge judgment module 11 can accurately determine the positive and negative of the clamped-wave signals respectively corresponding to the two inductors based on the current magnitudes and current directions of the two inductors. The control signal generation unit 15 can accurately output control signals based on the positive and negative of the clamped-wave signals respectively corresponding to the two inductors to turn on the path between the corresponding bus capacitor and the discharge transfer module 13. At the same time, when the electrical energy of the two inductors is transmitted to one bus capacitor, the voltage of the bus capacitor can be discharged more quickly, thereby avoiding breakdown of the bus capacitor.

[0085] Next, a specific example is used to illustrate the above-mentioned control signal generation unit 15. Continuing to refer to Figure 3 As shown, the control signal generation unit 15 includes a positive envelope signal conversion subunit 151 and a negative envelope signal conversion subunit 152. The switch module 12 includes a positive switch unit 121 and a negative switch unit 122. The discharge transfer module 13 includes a positive discharge transfer unit 131 and a negative discharge transfer unit 132;

[0086] The input ends of the positive envelope signal conversion subunit 151 and the negative envelope signal conversion subunit 152 are both connected to the output end of the envelope judgment unit 14. The output end of the positive envelope signal conversion subunit 151 is connected to the positive switch unit 121, and the output end of the negative envelope signal conversion subunit 152 is connected to the negative switch unit 122;

[0087] The positive envelope signal conversion subunit 151 is configured to receive the positive envelope signal output by the envelope judgment unit 14 and convert the positive envelope signal into a positive control signal for the positive switch unit 121. The positive control signal is used to conduct the path between the second bus capacitor CE2 and the discharge transfer module 13;

[0088] The negative envelope signal conversion subunit 152 is configured to receive the negative envelope signal output by the envelope judgment unit 14 and convert the negative envelope signal into a negative control signal for the negative switch unit 122. The negative control signal is used to conduct the path between the first bus capacitor CE1 and the discharge transfer module 13.

[0089] Among them, the positive envelope signal refers to the envelope signal generated when the current direction of the inductor is clockwise, and the negative envelope signal refers to the envelope signal generated when the current direction of the inductor is counterclockwise.

[0090] In the embodiment of the present application, the positive envelope signal conversion subunit 151 mainly receives the positive envelope signal output by the envelope judgment unit 14 and then converts the positive envelope signal into a control signal capable of controlling the positive switch unit 121. The negative envelope signal conversion subunit 152 mainly receives the negative envelope signal output by the envelope judgment unit 14 and then converts the negative envelope signal into a control signal capable of controlling the negative switch unit 122. Among them, both the positive envelope signal conversion subunit 151 and the negative envelope signal conversion subunit 152 can be implemented by a logic gate circuit.

[0091] The above control signal generation unit 15 includes a positive envelope signal conversion sub-unit 151 and a negative envelope signal conversion sub-unit 152. The switch module 12 includes a positive switch unit 121 and a negative switch unit 122. The discharge transfer module 13 includes a positive discharge transfer unit 131 and a negative discharge transfer unit 132. The input ends of the positive envelope signal conversion sub-unit 151 and the negative envelope signal conversion sub-unit 152 are both connected to the output end of the envelope judgment unit 14. The output end of the positive envelope signal conversion sub-unit 151 is connected to the positive switch unit 121, and the output end of the negative envelope signal conversion sub-unit 152 is connected to the negative switch unit 122. The positive envelope signal conversion sub-unit 151 is used to receive the positive envelope signal output by the envelope judgment unit 14 and convert the positive envelope signal into a positive control signal of the positive switch unit 121. The positive control signal is used to conduct the path between the second bus capacitor CE2 and the discharge transfer module 13. The negative envelope signal conversion sub-unit 152 is used to receive the negative envelope signal output by the envelope judgment unit 14 and convert the negative envelope signal into a negative control signal of the negative switch unit 122. The negative control signal is used to conduct the path between the first bus capacitor CE1 and the discharge transfer module 13. By setting the positive envelope signal conversion sub-unit 151 and the negative envelope signal conversion sub-unit 152, the positive envelope signal and the negative envelope signal output by the envelope judgment unit 14 can be received respectively and converted into corresponding positive control signal and negative control signal, so as to accurately control the conduction and cut-off of the positive switch unit 121 and the negative switch unit 122.

[0092] For the positive envelope signal conversion sub-unit 151, as Figure 4 shown, the positive envelope signal conversion sub-unit 151 includes a positive switching control component 1511 and a positive transfer control component 1512. The positive switch unit 121 includes a positive switch switching sub-unit 1211 and a positive switch sub-unit 1212. The positive discharge transfer unit 131 includes a positive discharge transfer resistor R13.

[0093] The input ends of the positive switching control component 1511 and the positive transfer control component 1512 are both connected to the output end of the envelope judgment unit 14. The output end of the positive switching control component 1511 is connected to the coil of the positive switch switching sub-unit 1211. The normally closed end of the positive switch switching sub-unit 1211 is connected to the positive electrode of the first bus capacitor CE1, and the normally open end of the positive switch switching sub-unit 1211 is connected to the negative electrode of the second bus capacitor CE2.

[0094] The output end of the positive transfer control component 1512 is connected to the coil of the positive switch sub-unit 1212. The normally open end of the positive switch sub-unit 1212 is connected to the common end of the first bus capacitor CE1 and the second bus capacitor CE2 connected in series.

[0095] The positive discharge transfer resistor R13 is disposed between the common terminal of the positive switch switching subunit 1211 and the common terminal of the positive switch subunit 1212.

[0096] In the embodiment of the present application, during the non-operating process of the positive switching control component 1511, by default, the positive electrode of the first bus capacitor CE1 is connected to the normally closed terminal of the positive switch switching subunit 1211, and the negative electrode of the second bus capacitor CE2 is connected to the normally open terminal of the positive switch switching subunit 1211. Then, when the positive switching control component 1511 receives a positive wave sealing signal from the wave sealing judgment unit 14, it is necessary to conduct the normally open terminal and the common terminal of the positive switch switching subunit 1211 through the internal logic circuit, that is, conduct the connection between the second bus capacitor CE2 and the positive discharge transfer resistor R13. In this way, the voltage of the second bus capacitor CE2 can be transferred to both ends of the positive discharge transfer resistor R13. When the positive wave sealing signal from the wave sealing judgment unit 14 is not received, the positive switch switching subunit 1211 maintains the default connection state, that is, the positive electrode of the first bus capacitor CE1 is connected to the normally closed terminal of the positive switch switching subunit 1211.

[0097] It can be understood that the positive switching control component 1511 is used to determine whether to switch the internal connection relationship of the positive switching control component 1511 according to the wave sealing signal output by the wave sealing judgment unit 14, which determines whether the discharge process is for the first bus capacitor CE1 or the second bus capacitor CE2. When the wave sealing signal is a positive wave sealing signal, switching is required to discharge the voltage of the second bus capacitor CE2; when the wave sealing signal is a negative wave sealing signal, no switching is required to discharge the voltage of the first bus capacitor CE1.

[0098] Figure 5 FIG. is a schematic diagram of the bus voltage discharge circuit. Specifically, for the positive switching control component 1511, it includes a first resistor R1, a second resistor R2, a third resistor R3, a first diode D1, a second diode D2, and a first switching transistor Q1, and the positive switch switching subunit 1211 includes a first relay RLY1;

[0099] The negative electrodes of the first diode D1 and the second diode D2 are both connected to the output terminal of the wave blocking judgment unit 14. The positive electrodes of the first diode D1 and the second diode D2 are both connected to the input terminal of the first resistor R1. The output terminal of the first resistor R1 is respectively connected to the input terminal of the second resistor R2 and the base of the first switching transistor Q1. The emitter of the first switching transistor Q1 is connected to the input terminal of the third resistor R3. The output terminals of the second resistor R2 and the third resistor R3 are both connected to the coil of the first relay RLY1. The input terminal of the first relay RLY1 is connected to the power supply. The common terminal of the first relay RLY1 is connected to the positive discharge transfer resistor R13. The normally closed terminal of the first relay RLY1 is connected to the positive electrode of the first bus capacitor CE1. The normally open terminal of the first relay RLY1 is connected to the negative electrode of the second bus capacitor CE2. And the collector of the first switching transistor Q1 is grounded.

[0100] For the positive transfer control component 1512, it is connected to the output terminal of the wave blocking judgment unit 14, receives the wave blocking signal output by the wave blocking judgment unit 14, and converts it into a signal for controlling the positive switching sub-unit 1212. Different from the positive switching control component 1511, the positive transfer control component 1512 does not involve the switching inside the switch, that is, it only has two states: conduction and cutoff. As long as the positive transfer control component 1512 receives a wave blocking signal, whether it is a positive wave blocking signal or a negative wave blocking signal, it can output a control signal to control the positive switching sub-unit 1212 to conduct. Its main purpose is to determine when to conduct.

[0101] Specifically, continue to refer to Figure 5 , the positive transfer control component 1512 includes a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a third diode D3, a fourth diode D4, a fifth diode D5, a sixth diode D6 and a second switching transistor Q2, and the positive switching sub-unit 1212 includes a second relay RLY2;

[0102] The cathodes of the third diode D3, the fourth diode D4, the fifth diode D5, and the sixth diode D6 are all connected to the wave blocking judgment unit 14. The anodes of the third diode D3, the fourth diode D4, the fifth diode D5, and the sixth diode D6 are all connected to the input end of the fourth resistor R4. The output end of the fourth resistor R4 is respectively connected to the input end of the fifth resistor R5 and the base of the second switching transistor Q2. The emitter of the second switching transistor Q2 is connected to the input end of the sixth resistor R6. The input end of the second relay RLY2 is connected to the power supply. The output ends of the fifth resistor R5 and the sixth resistor R6 are both connected to the coil of the second relay RLY2. The normally open contact of the second relay RLY2 is connected to the common end of the first bus capacitor CE1 and the second bus capacitor CE2 connected in series. The common contact of the second relay RLY2 is connected to the positive discharge transfer resistor R13, and the collector of the second switching transistor Q2 is grounded.

[0103] The above-mentioned positive wave blocking signal conversion sub-unit 151 includes a positive switching control component 1511 and a positive transfer control component 1512. The positive switch unit 121 includes a positive switch switching sub-unit 1211 and a positive switch sub-unit 1212. The input ends of the positive switching control component 1511 and the positive transfer control component 1512 are both connected to the output end of the wave blocking judgment unit 14. The output end of the positive switching control component 1511 is connected to the coil of the positive switch switching sub-unit 1211. The normally closed contact of the positive switch switching sub-unit 1211 is connected to the positive pole of the first bus capacitor CE1. The normally open contact of the positive switch switching sub-unit 1211 is connected to the negative pole of the second bus capacitor CE2. The output end of the positive transfer control component 1512 is connected to the coil of the positive switch sub-unit 1212. The normally open contact of the positive switch sub-unit 1212 is connected to the common end of the first bus capacitor CE1 and the second bus capacitor CE2 connected in series. The positive discharge transfer resistor R13 is arranged between the common contact of the positive switch switching sub-unit 1211 and the common contact of the positive switch sub-unit 1212. Two switches, namely the positive switch switching sub-unit 1211 and the positive switch sub-unit 1212, are provided in this circuit. The positive switch switching sub-unit 1211 switches only when it is a positive wave blocking signal. The positive switch sub-unit 1212 conducts as long as it is a wave blocking signal. Then, the two switches control the conduction timing and the conduction object at the same time, so that the voltage of the bus capacitor can be accurately discharged.

[0104] For the negative wave blocking signal conversion sub-unit 152, continue to refer to Figure 4 As shown, the negative wave blocking signal conversion sub-unit 152 includes a negative switching control component 1521 and a negative transfer control component 1522. The negative switch unit 122 includes a negative switch switching sub-unit 1221 and a negative switch sub-unit 1222. The negative discharge transfer unit 132 includes a negative discharge transfer resistor R14;

[0105] The input terminal of the negative switching control component 1521 and the input terminal of the negative transfer control component 1522 are both connected to the output terminal of the wave blocking judgment unit 14. The output terminal of the negative switching control component 1521 is connected to the coil of the negative switch switching sub-unit 1221. The normally closed terminal of the negative switch switching sub-unit 1221 is connected to the negative electrode of the second bus capacitor CE2, and the normally open terminal of the negative switch switching sub-unit 1221 is connected to the positive electrode of the first bus capacitor CE1;

[0106] The output terminal of the negative transfer control component 1522 is connected to the coil of the negative switch sub-unit 1222. The normally open terminal of the negative switch sub-unit 1222 is connected to the common terminal of the first bus capacitor CE1 and the second bus capacitor CE2 connected in series;

[0107] The negative discharge transfer resistor R14 is arranged between the common terminal of the negative switch switching sub-unit 1221 and the common terminal of the negative switch sub-unit 1222.

[0108] In the embodiment of the present application, the functions of each sub-unit in the negative wave blocking signal conversion sub-unit 152 are the same as those of each sub-unit in the positive wave blocking signal. During the non-operating process of the negative switching control component 1521, it is default that the negative electrode of the second bus capacitor CE2 is connected to the normally closed terminal of the negative switch switching sub-unit 1221.

[0109] The negative switching control component 1521 is used to determine whether to switch the internal connection relationship of the negative switch switching sub-unit 1221 according to the wave blocking signal output by the wave blocking judgment unit 14, which determines whether the discharge process is for the first bus capacitor CE1 or the second bus capacitor CE2. When the wave blocking signal is a negative wave blocking signal, switching is required to discharge the voltage of the first bus capacitor CE1; when the wave blocking signal is a positive wave blocking signal, no switching is required to discharge the voltage of the second bus capacitor CE2.

[0110] Combined with the positive wave blocking signal conversion sub-unit 151 and the negative wave blocking signal conversion sub-unit 152, if the wave blocking signal output by the wave blocking judgment unit 14 is a positive wave blocking signal, at this time, the connection relationship in the positive switch switching sub-unit 1211 needs to be switched, and the normally open terminal of the positive switch switching sub-unit 1211 is connected to the common terminal, that is, the negative electrode of the second bus capacitor CE2 is connected to the positive discharge transfer resistor R13. At the same time, the connection relationship in the negative switch switching sub-unit 1221 does not need to be switched, that is, the negative electrode of the second bus capacitor CE2 is connected to the normally closed terminal of the negative switch switching sub-unit 1221. At this time, both the positive discharge transfer resistor R13 and the negative discharge transfer resistor R14 are connected to the second bus capacitor CE2 to discharge the voltage in the second bus capacitor CE2.

[0111] If the wave blocking judgment unit 14 determines that the wave blocking signal output by the inverter 20 is a negative wave blocking signal, at this time, the connection relationship in the positive switch switching sub-unit 1211 does not need to be switched, that is, the positive electrode of the first bus capacitor CE1 is connected to the normally closed end of the positive switch switching sub-unit 1211. At the same time, the connection relationship in the negative switch switching sub-unit 1221 needs to be switched, and the normally open end of the negative switch switching sub-unit 1221 is connected to the common end, that is, the negative electrode of the first bus capacitor CE1 is connected to the negative discharge transfer resistor R14. At this time, both the positive discharge transfer resistor R13 and the negative discharge transfer resistor R14 are connected to the first bus capacitor CE1 to discharge the voltage in the first bus capacitor CE1.

[0112] Continue to refer to Figure 5 , the negative switching control component 1521 includes resistor seven R7, resistor eight R8, resistor nine R9, seventh diode D7, eighth diode D8 and third switching tube Q3, and the negative switch switching sub-unit 1221 includes third relay RLY3;

[0113] The negative electrodes of the seventh diode D7 and the eighth diode D8 are both connected to the output end of the wave blocking judgment unit 14, the positive electrodes of the seventh diode D7 and the eighth diode D8 are both connected to the input end of the resistor seven R7, the output end of the resistor seven R7 is respectively connected to the input end of the resistor eight R8 and the base of the third switching tube Q3, the emitter of the third switching tube Q3 is connected to the input end of the resistor nine R9, the output ends of the resistor eight R8 and the resistor nine R9 are both connected to the coil of the third relay RLY3, the input end of the third relay RLY3 is connected to the power supply, the common end of the third relay RLY3 is connected to the negative discharge transfer resistor R14, the normally closed end of the third relay RLY3 is connected to the negative electrode of the second bus capacitor CE2, the normally open end of the third relay RLY3 is connected to the positive electrode of the first bus capacitor CE1, and the collector of the third switching tube Q3 is grounded.

[0114] The negative transfer control component 1522 includes resistor ten R10, resistor eleven R11, resistor twelve R12, ninth diode D9, tenth diode D10, eleventh diode D11, twelfth diode D12 and fourth switching tube Q4, and the negative switch sub-unit 1222 includes fourth relay RLY4;

[0115] The negative electrodes of the ninth diode D9, the tenth diode D10, the eleventh diode D11 and the twelfth diode D12 are all connected to the wave blocking judgment unit 14, and the positive electrodes of the ninth diode D9, the tenth diode D10, the eleventh diode D11 and the twelfth diode D12 are all connected to the input end of the resistor ten R10;

[0116] The output terminals of resistor R10 are respectively connected to the input terminals of resistor R11 and the base of the fourth switching transistor Q4. The emitter of the fourth switching transistor Q4 is connected to the input terminal of resistor R12. The input terminal of the fourth relay RLY4 is connected to the power supply. The output terminals of resistor R11 and resistor R12 are both connected to the coil of the fourth relay RLY4. The normally open terminal of the fourth relay RLY4 is connected to the common terminal of the first bus capacitor CE1 and the second bus capacitor CE2 connected in series. The common terminal of the fourth relay RLY4 is connected to the negative discharge transfer resistor R14, and the collector of the fourth switching transistor Q4 is grounded.

[0117] The above-mentioned negative pulse signal conversion sub-unit 152 includes a negative switching control component 1521 and a negative transfer control component 1522. The negative switch unit 122 includes a negative switch switching sub-unit 1221 and a negative switch sub-unit 1222. The input terminals of the negative switching control component 1521 and the negative transfer control component 1522 are both connected to the output terminal of the pulse judgment unit 14. The output terminal of the negative switching control component 1521 is connected to the coil of the negative switch switching sub-unit 1221. The normally closed terminal of the negative switch switching sub-unit 1221 is connected to the negative electrode of the second bus capacitor CE2, and the normally open terminal of the negative switch switching sub-unit 1221 is connected to the positive electrode of the first bus capacitor CE1. The output terminal of the negative transfer control component 1522 is connected to the coil of the negative switch sub-unit 1222. The normally open terminal of the negative switch sub-unit 1222 is connected to the common terminal of the first bus capacitor CE1 and the second bus capacitor CE2 connected in series. The negative discharge transfer resistor R14 is arranged between the common terminal of the negative switch switching sub-unit 1221 and the common terminal of the negative switch sub-unit 1222. Two switches, namely the negative switch switching sub-unit 1221 and the negative switch sub-unit 1222, are provided in this circuit. The negative switch switching sub-unit 1221 switches only when it is a negative pulse signal, and the negative switch sub-unit 1222 conducts as long as it is a pulse signal. Then, the two switches control both the conduction timing and the conduction object simultaneously, so that the voltage of the bus capacitor can be accurately discharged.

[0118] Next, in combination with Figure 1 and Figure 5 the content in, the working principle of the bus voltage discharge circuit 10 will be described in detail.

[0119] When the current of the first inductor LD1 in the inverter 20 is in the positive half-wave trigger blocking state, the positive blocking signal output by the blocking judgment unit 14 is a low-level signal INV_OCP1. At this time, the cathode of the first diode D1 is at a low level, and the coil of the first relay RLY1, the first resistor R1, and the second resistor R2 all divide the supply voltage. The base potential of the first switching transistor Q1 is lower than the emitter potential, and the first switching transistor Q1 conducts. The first relay RLY1 switches from the default normally closed terminal and common terminal connection to the normally open terminal and common terminal connection. At the same time, the base and emitter of the third switching transistor Q3 are at the same potential, and the third switching transistor Q3 is turned off. The third relay RLY3 maintains the default connection relationship, that is, the normally closed terminal and the common terminal are connected. In addition, the cathodes of the third diode D3 and the ninth diode D9 are at a low level, and the second relay RLY2 and the fourth relay RLY4 are both turned on (normally open terminal and common terminal connection). At this time, both the positive discharge transfer resistor R13 and the negative discharge transfer resistor R14 are connected to the second bus capacitor CE2 to simultaneously discharge the voltage of the second bus capacitor CE2, preventing the voltage of the second bus capacitor CE2 from rising due to the discharge of the voltage stored in the first inductor LD1.

[0120] When the current of the first inductor LD1 in the inverter 20 is in the negative half-wave trigger blocking state, the negative blocking signal output by the inverter 20 is a low-level signal INV_OCP2. At this time, the cathode of the seventh diode D7 is at a low level, and the coil of the third relay RLY3, the seventh resistor R7, and the eighth resistor R8 all divide the supply voltage. The base potential of the third switching transistor Q3 is lower than the emitter voltage, and the third switching transistor Q3 conducts. At this time, the third relay RLY3 switches from the default normally closed terminal and common terminal connection to the normally open terminal and common terminal connection. The base and emitter of the first switching transistor Q1 are at the same potential, and the first switching transistor Q1 is turned off. The first relay RLY1 maintains the default connection relationship, that is, the normally closed terminal and the common terminal are connected. In addition, the cathodes of the fourth diode D4 and the twelfth diode D10 are at a low level, and the second relay RLY2 and the fourth relay RLY4 are both turned on (normally open terminal and common terminal connection). At this time, both the positive discharge transfer resistor R13 and the negative discharge transfer resistor R14 are connected to the first bus capacitor CE1 to simultaneously discharge the voltage of the first bus capacitor CE1, preventing the voltage of the first bus capacitor CE1 from rising due to the discharge of the voltage stored in the first inductor LD1.

[0121] When the current of the second inductor LD2 in the inverter 20 is in the positive half-wave trigger blocking wave, the positive blocking wave signal output by the inverter 20 is a low-level signal INV_OCP3. At this time, the cathode of the second diode D2 is at a low level, and the coil of the first relay RLY1, the first resistor R1, and the second resistor R2 all divide the supply voltage. The base potential of the first switching transistor Q1 is lower than the emitter potential, and the first switching transistor Q1 conducts. The first relay RLY1 switches from the default normally closed terminal and common terminal connection to the normally open terminal and common terminal connection. At the same time, the base and emitter of the third switching transistor Q3 are at the same potential, and the third switching transistor Q3 is turned off. The third relay RLY3 maintains the default connection relationship, that is, the normally closed terminal and the common terminal are connected. In addition, the cathodes of the fifth diode D5 and the eleventh diode D11 are at a low level, and the second relay RLY2 and the fourth relay RLY4 are both turned on (the normally open terminal and the common terminal are connected). At this time, both the positive discharge transfer resistor R13 and the negative discharge transfer resistor R14 are connected to the second bus capacitor CE2 to simultaneously discharge the voltage of the second bus capacitor CE2, preventing the voltage of the second bus capacitor CE2 from rising due to the discharge of the voltage stored in the second inductor LD2.

[0122] When the current of the second inductor LD2 in the inverter 20 is in the negative half-wave trigger blocking wave, the negative blocking wave signal output by the inverter 20 is a low-level signal INV_OCP4. At this time, the cathode of the eighth diode D8 is at a low level, and the coil of the third relay RLY3, the seventh resistor R7, and the eighth resistor R8 all divide the supply voltage. The base potential of the third switching transistor Q3 is lower than the emitter voltage, and the third switching transistor Q3 conducts. At this time, the third relay RLY3 switches from the default normally closed terminal and common terminal connection to the normally open terminal and common terminal connection. The base and emitter of the first switching transistor Q1 are at the same potential, and the first switching transistor Q1 is turned off and conducts. The first relay RLY1 maintains the default connection relationship, that is, the normally closed terminal and the common terminal are connected. In addition, the cathodes of the sixth diode D6 and the twelfth diode D12 are at a low level, and the second relay RLY2 and the fourth relay RLY4 are both turned on (the normally open terminal and the common terminal are connected). At this time, both the positive discharge transfer resistor R13 and the negative discharge transfer resistor R14 are connected to the first bus capacitor CE1 to simultaneously discharge the voltage of the first bus capacitor CE1, preventing the voltage of the first bus capacitor CE1 from rising due to the discharge of the voltage stored in the first inductor LD1.

[0123] If the first inductor LD1 and the second inductor LD2 in the inverter 20 trigger wave blocking simultaneously, and the first inductor LD1 triggers wave blocking in the positive half-wave while the second inductor LD2 triggers wave blocking in the negative half-wave, at this time, the inverter 20 generates low-level signals INV_OCP1 and INV_OCP4. At this time, the cathode of the first diode D1 is at a low level, and the coil of the first relay RLY1, resistor one R1, and resistor two R2 all divide the supply voltage. The base potential of the first switching transistor Q1 is lower than the emitter potential, and the first switching transistor Q1 conducts. The first relay RLY1 switches from the default normally closed terminal, common terminal connection to the normally open terminal, common terminal connection. The cathode of the eighth diode D8 is at a low level, and the coil of the third relay RLY3, resistor seven R7, and resistor eight R8 all divide the supply voltage. The base potential of the third switching transistor Q3 is lower than the emitter voltage, and the third switching transistor Q3 conducts. At this time, the third relay RLY3 switches from the default normally closed terminal, common terminal connection to the normally open terminal, common terminal connection. Also, the cathodes of the third diode D3, sixth diode D6, ninth diode D9, and twelfth diode D12 are all at a low level, and the second relay RLY2 and the fourth relay RLY4 both conduct (normally open terminal, common terminal connection). At this time, the positive discharge transfer resistor R13 is connected across the second bus capacitor CE2, and the negative discharge transfer resistor R14 is connected across the first bus capacitor CE1, simultaneously discharging the voltages of the first bus capacitor CE1 and the second bus capacitor CE2 respectively to prevent the voltages of the first bus capacitor CE1 and the second bus capacitor CE2 from rising due to the discharge of the voltages stored in the first inductor LD1 and the second inductor LD2.

[0124] If the first inductor LD1 and the second inductor LD2 in the inverter 20 are simultaneously triggered to block the wave, and the first inductor LD1 is triggered to block the wave in the negative half-wave, and the second inductor LD2 is triggered to block the wave in the positive half-wave. At this time, the inverter 20 generates low-level signals INV_OCP2 and INV_OCP3. At this time, the cathode of the seventh diode D7 is at a low level, and the coil of the third relay RLY3, the seventh resistor R7, and the eighth resistor R8 all divide the supply voltage. The base potential of the third switching transistor Q3 is lower than the voltage of the emitter, and the third switching transistor Q3 conducts. At this time, the third relay RLY3 switches from the default normally closed terminal and common terminal connection to the normally open terminal and common terminal connection. At the same time, the cathode of the second diode D2 is at a low level, and the coil of the first relay RLY1, the first resistor R1, and the second resistor R2 all divide the supply voltage. The base potential of the first switching transistor Q1 is lower than the emitter potential, and the first switching transistor Q1 conducts. The first relay RLY1 switches from the default normally closed terminal and common terminal connection to the normally open terminal and common terminal connection. And the cathodes of the fourth diode D4, the fifth diode D5, the twelfth diode D10, and the eleventh diode D11 are all at a low level, and the second relay RLY2 and the fourth relay RLY4 are both conducting (normally open terminal and common terminal connection). At this time, the positive discharge transfer resistor R13 is connected across the second bus capacitor CE2, and the negative discharge transfer resistor R14 is connected across the first bus capacitor CE1, and at the same time discharges the voltages of the first bus capacitor CE1 and the second bus capacitor CE2 respectively, so as to prevent the voltages of the first bus capacitor CE1 and the second bus capacitor CE2 from rising due to the discharge of the voltages stored in the first inductor LD1 and the second inductor LD2.

[0125] If the currents of the first inductor LD1 and the second inductor LD2 in the inverter 20 are both triggered to block the wave in the positive half-wave, the positive blocked wave signals output by the inverter 20 are low-level INV_OCP1 and INV_OCP3. At this time, the first diode D1 and the second diode D2 are both at a low level, and the coil of the first relay RLY1, the first resistor R1, and the second resistor R2 all divide the supply voltage. The first switching transistor Q1 conducts. The first relay RLY1 switches from the default normally closed terminal and common terminal connection to the normally open terminal and common terminal connection. At the same time, the third switching transistor Q3 is cut off, and the third relay RLY3 maintains the default connection relationship, that is, the normally closed terminal and the common terminal are connected. In addition, the cathodes of the third diode D3, the fifth diode D5, the ninth diode D9, and the eleventh diode D11 are at a low level, and the second relay RLY2 and the fourth relay RLY4 are both conducting (normally open terminal and common terminal connection). At this time, both the positive discharge transfer resistor R13 and the negative discharge transfer resistor R14 are connected to the second bus capacitor CE2 to simultaneously discharge the voltage of the second bus capacitor CE2, preventing the voltage of the second bus capacitor CE2 from rising due to the discharge of the voltage stored in the first inductor LD1.

[0126] When the currents of the first inductor LD1 and the second inductor LD2 in the inverter 20 are both in the negative half-wave trigger blocking wave, the negative blocking wave signals output by the inverter 20 are low-level signals INV_OCP2 and INV_OCP4. At this time, the cathodes of the seventh diode D7 and the eighth diode D8 are both at low level. The coil of the third relay RLY3, the seventh resistor R7, and the eighth resistor R8 all divide the supply voltage, and the third switching transistor Q3 conducts. At this time, the third relay RLY3 switches from the default normally closed terminal and common terminal connection to the normally open terminal and common terminal connection. The first switching transistor Q1 is cut off and conducts, and the first relay RLY1 maintains the default connection relationship, that is, the normally closed terminal and the common terminal are connected. In addition, the cathodes of the fourth diode D4, the sixth diode D6, the tenth diode D10, and the twelfth diode D12 are at low level, and the second relay RLY2 and the fourth relay RLY4 are both conducting (normally open terminal and common terminal connection). At this time, the positive discharge transfer resistor R13 and the negative discharge transfer resistor R14 are both connected to the first bus capacitor CE1 to simultaneously discharge the voltage of the first bus capacitor CE1, preventing the voltage of the first bus capacitor CE1 from rising due to the discharge of the voltage stored in the first inductor LD1.

[0127] In one embodiment, continue to refer to Figure 3 As shown, the above-mentioned blocking wave judgment unit 14 includes a current sampling sub-unit 141 and an identification sub-unit 142. The input ends of the current sampling sub-unit 141 are respectively connected to the first inductor LD1 and the second inductor LD2 in the inverter 20, and the identification sub-unit 142 is used to connect the output end of the current sampling sub-unit 141 to the control signal generation unit 15;

[0128] The current sampling sub-unit 141 is used to collect the current signals of the first inductor LD1 and the second inductor LD2;

[0129] The identification sub-unit 142 is used to identify the positive and negative of the blocking wave signal corresponding to the first inductor LD1 according to the direction of the current signal of the first inductor LD1, and output the blocking wave signal corresponding to the first inductor LD1; and, according to the direction of the current signal of the second inductor LD2, identify the positive and negative of the blocking wave signal corresponding to the second inductor LD2, and output the blocking wave signal corresponding to the second inductor LD2.

[0130] In an embodiment of the present application, the current sampling sub-unit 141 in the wave blocking judgment unit 14 is mainly used to sample the current signals of the first inductor LD1 and the second inductor LD2. The current sampling sub-unit 141 can perform current sampling through a resistance sampling method, an inductive transformer sampling method, or a Hall effect sensor sampling method. Taking the resistance sampling method as an example, a small-value sampling resistor can be connected in series in the inductor loop. After measuring the voltage across the sampling resistor, the current flowing through the two ends of the sampling resistor, that is, the current flowing through the first inductor LD1 and the second inductor LD2 of the inverter 20, can be calculated based on Ohm's law.

[0131] The identification sub-unit 142 is mainly used to compare the sampled current with a preset current threshold, and based on the comparison result, determine whether the wave blocking signal is a positive wave blocking signal or a negative wave blocking signal. Among them, the identification sub-unit 142 can be implemented by a comparator. Among them, the preset current threshold can be a reference value preset according to the operating characteristics and design requirements of the inverter 20.

[0132] Further, after the identification sub-unit 142 determines the positive and negative half-waves of the wave blocking signal, it can also control Figure 1 the switching tubes in the shown inverter 20. Taking the first inductor LD1 as an example, Figure 6 FIG. is a schematic diagram of the wave blocking judgment unit. The wave blocking judgment unit 14 in the figure includes a current sampling sub-unit 141, an identification sub-unit 142, and a drive control sub-unit 143. The current sampling sub-unit 141 includes a resistor twenty R20, a resistor twenty-one R21, a resistor twenty-two R22, a resistor twenty-three R23, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, and a first comparator U1. The two input ends of the current sampling sub-unit 141 are respectively connected to the positive electrode I_INVL1+ and the negative electrode I_INVL1- of the first inductor LD1 to collect the current signal flowing through the first inductor LD1.

[0133] The identification sub-unit 142 includes a resistor twenty-four R24, a resistor twenty-five R25, a resistor twenty-six R26, a resistor twenty-seven R27, a resistor twenty-eight R28, a resistor twenty-nine R29, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, a thirteenth diode D13, a fourteenth diode D14, a second comparator U2, and a third comparator U3. When the current of the first inductor LD1 exceeds the protection limit value in the positive half-wave, the second comparator U2 generates a wave blocking signal INV_OCP1; when the current of the first inductor LD1 exceeds the protection limit value in the negative half-wave, the third comparator U3 generates a wave blocking signal INV_OCP2.

[0134] The drive control sub-unit 143 includes resistor R30, resistor R31, resistor R32, resistor R33, resistor R34, resistor R35, resistor R36, resistor R37, resistor R38, the eleventh capacitor C11, the twelfth capacitor C12, and four AND gate circuits (U4, U5, U6, U7). The eleventh switch tube Q11, the thirteenth switch tube Q13, the fifteenth switch tube Q15, and the seventeenth switch tube Q17 in the figure are all Figure 1 switch tubes in the inverter. In the figure, EPWM1_A, EPWM1_B, EPWM2_A, and EPWM2_B are all control signals output by the controller, while INVPWM_H1, INVPWM_L1, INVPWM_S1, and INVPWM_S2 are receiving ends of the generated drive signals corresponding to controlling the eleventh switch tube Q11, the thirteenth switch tube Q13, the fifteenth switch tube Q15, and the seventeenth switch tube Q17. The controller outputs drive signals based on the blocking signals INV_OCP1 or INV_OCP2 output by the identification sub-unit 142, causing the switch tubes Q11, Q13, Q15, and Q17 to turn off. Figure 6 The circuit schematic of the overcurrent of the first inductor LD1 is exemplified in it. The blocking judgment unit 14 of the second inductor LD2 is the same as that of the first inductor LD1. When the current of the second inductor LD2 exceeds the protection limit value in the positive half-wave, the protection circuit generates a blocking signal INV_OCP3; when the current of the second inductor LD2 exceeds the protection limit value in the negative half-wave, the protection circuit generates a blocking signal INV_OCP4. The controller outputs drive signals according to the blocking signals INV_OCP3 or INV_OCP4 output by the identification sub-unit 142 to turn off the twelfth switch tube Q12, the fourteenth switch tube Q14, the sixteenth switch tube Q16, and the eighteenth switch tube Q18. The above blocking signals INV_OCP1, INV_OCP2, INV_OCP3, and INV_OCP4 are all at low level.

[0135] The above-mentioned wave blocking judgment unit 14 includes a current sampling sub-unit 141 and an identification sub-unit 142. The input ends of the current sampling sub-unit 141 are respectively connected to the first inductor LD1 and the second inductor LD2 in the inverter 20. The identification sub-unit 142 is used to connect the output end of the current sampling sub-unit 141 to the control signal generation unit 15. The current sampling sub-unit 141 is used to collect the current signals of the first inductor LD1 and the second inductor LD2. The identification sub-unit 142 is used to identify the positive and negative of the wave blocking signal corresponding to the first inductor LD1 according to the direction of the current signal of the first inductor LD1, and output the wave blocking signal corresponding to the first inductor LD1. And, according to the direction of the current signal of the second inductor LD2, identify the positive and negative of the wave blocking signal corresponding to the second inductor LD2, and output the wave blocking signal corresponding to the second inductor LD2. The current sampling sub-unit 141 in the wave blocking judgment unit 14 can timely capture the abnormal change of the current by sampling the current flowing through the first inductor LD1 and the second inductor LD2 in the inverter 20 in real time. The identification sub-unit 142 compares the sampled current with a preset current threshold. Once it detects that the current exceeds the safe range, it can quickly further relieve the voltage of the first bus capacitor CE1 and / or the second bus capacitor CE2.

[0136] In one embodiment, an energy storage power supply is further provided. The energy storage power supply includes an inverter 20 and a bus voltage discharge circuit 10.

[0137] The above content is a further detailed description of the embodiments of the present application in combination with specific / preferred implementation manners. It cannot be determined that the specific implementation of the embodiments of the present application is only limited to these descriptions. For those of ordinary skill in the technical field to which the embodiments of the present application belong, without departing from the concept of the embodiments of the present application, they can also make several substitutions or modifications to these described implementation manners, and these substitution or modification manners should all be regarded as belonging to the protection scope of the embodiments of the present application. In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "preferred embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0138] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this application.

[0139] The above embodiments only express several implementation manners of this application. The description is relatively specific and detailed, but it should not be construed as a limitation on the patent scope of this application. It should be noted that for those of ordinary skill in the art, without departing from the concept of this application, several deformations and improvements can still be made, and these all belong to the protection scope of this application. Therefore, the protection scope of this application should be subject to the appended claims.

[0140] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of this application, rather than to limit it; although this application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of this application, and they should all be covered by the scope of the claims and the description of this application. In particular, as long as there is no structural conflict, the technical features mentioned in each embodiment can be combined in any way. This application is not limited to the specific embodiments disclosed in the text, but includes all technical solutions falling within the scope of the claims.

Claims

1. A bus voltage discharge circuit, characterized in that The bus voltage discharge circuit includes a discharge judgment module, a switch module, and a discharge transfer module. The input ends of the discharge judgment module are respectively connected to a first inductor and a second inductor in the inverter. The output end of the discharge judgment module is connected to the controlled end of the switch module. The first bus capacitor and the second bus capacitor in the inverter are respectively connected to the discharge transfer module through the switch module; The discharge judgment module is configured to respectively collect the current signals of the first inductor and the second inductor. If both of the collected current signals are greater than a preset value, and the currents of the first inductor and the second inductor are clockwise, it is determined that the bus capacitor to be discharged is the second bus capacitor; if the currents of the first inductor and the second inductor are counterclockwise, it is determined that the bus capacitor to be discharged is the first bus capacitor; if the current of any one of the first inductor and the second inductor is clockwise and the current of the other inductor is counterclockwise, it is determined that the bus capacitors to be discharged are the first bus capacitor and the second bus capacitor, and a control signal for the switch module is generated; the control signal is used to conduct the path between the bus capacitor to be discharged and the discharge transfer module.

2. The circuit according to claim 1, characterized in that, The discharge judgment module includes a wave blocking judgment unit and a control signal generation unit. The input ends of the wave blocking judgment unit are respectively connected to the first inductor and the second inductor in the inverter. The control signal generation unit is used to connect the output end of the wave blocking judgment unit to the switch module; The wave blocking judgment unit is configured to, when the current signal of the first inductor is greater than the preset value, output a wave blocking signal corresponding to the first inductor based on the direction of the current signal of the first inductor; and, when the current signal of the second inductor is greater than the preset value, output a wave blocking signal corresponding to the second inductor based on the direction of the current signal of the second inductor; the wave blocking signal includes a positive wave blocking signal and a negative wave blocking signal; The control signal generation unit is configured to, when the wave blocking signals corresponding to the first inductor and the second inductor are both positive wave blocking signals, output a first control signal; the first control signal is used to conduct the path between the second bus capacitor and the discharge transfer module; When the wave blocking signals corresponding to the first inductor and the second inductor are both negative wave blocking signals, output a second control signal; the second control signal is used to conduct the path between the first bus capacitor and the discharge transfer module; And, when one of the wave blocking signal corresponding to the first inductor and the wave blocking signal corresponding to the second inductor is a positive wave blocking signal and the other is a negative wave blocking signal, output a third control signal; the third control signal is used to conduct the path between the first bus capacitor and the discharge transfer module and the path between the second bus capacitor and the discharge transfer module.

3. The circuit according to claim 2, wherein The control signal generation unit includes a positive wave blocking signal conversion sub-unit and a negative wave blocking signal conversion sub-unit. The switch module includes a positive switch unit and a negative switch unit. The discharge transfer module includes a positive discharge transfer unit and a negative discharge transfer unit; The input ends of the positive envelope signal conversion sub-unit and the negative envelope signal conversion sub-unit are both connected to the output end of the envelope signal judgment unit. The output end of the positive envelope signal conversion sub-unit is connected to the positive switch unit, and the output end of the negative envelope signal conversion sub-unit is connected to the negative switch unit; The positive envelope signal conversion sub-unit is configured to receive the positive envelope signal output by the envelope signal judgment unit and convert the positive envelope signal into a positive control signal for the positive switch unit. The positive control signal is used to conduct the path between the second bus capacitor and the discharge transfer module; The negative envelope signal conversion sub-unit is configured to receive the negative envelope signal output by the envelope signal judgment unit and convert the negative envelope signal into a negative control signal for the negative switch unit. The negative control signal is used to conduct the path between the first bus capacitor and the discharge transfer module.

4. The circuit according to claim 3, wherein The positive envelope signal conversion sub-unit includes a positive switching control component and a positive transfer control component. The positive switch unit includes a positive switch switching sub-unit and a positive switch sub-unit. The positive discharge transfer unit includes a positive discharge transfer resistor; The input ends of the positive switching control component and the positive transfer control component are both connected to the output end of the envelope signal judgment unit. The output end of the positive switching control component is connected to the coil of the positive switch switching sub-unit. The normally closed end of the positive switch switching sub-unit is connected to the positive pole of the first bus capacitor, and the normally open end of the positive switch switching sub-unit is connected to the negative pole of the second bus capacitor; The output end of the positive transfer control component is connected to the coil of the positive switch sub-unit. The normally open end of the positive switch sub-unit is connected to the common end of the first bus capacitor and the second bus capacitor connected in series; The positive discharge transfer resistor is arranged between the common end of the positive switch switching sub-unit and the common end of the positive switch sub-unit.

5. The circuit according to claim 4, characterized in that, The positive switching control component includes a first resistor, a second resistor, a third resistor, a first diode, a second diode, and a first switching tube. The positive switch switching sub-unit includes a first relay; The negative poles of the first diode and the second diode are both connected to the output end of the envelope signal judgment unit. The positive poles of the first diode and the second diode are both connected to the input end of the first resistor. The output end of the first resistor is respectively connected to the input end of the second resistor and the base of the first switching tube. The emitter of the first switching tube is connected to the input end of the third resistor. The output ends of the second resistor and the third resistor are both connected to the coil of the first relay. The input end of the first relay is connected to the power supply. The common end of the first relay is connected to the positive discharge transfer resistor. The normally closed end of the first relay is connected to the positive pole of the first bus capacitor. The normally open end of the first relay is connected to the negative pole of the second bus capacitor, and the collector of the first switching tube is grounded.

6. The circuit according to claim 4, wherein, The positive transfer control component includes resistor four, resistor five, resistor six, the third diode, the fourth diode, the fifth diode, the sixth diode, and the second switching transistor, and the positive switching sub-unit includes a second relay; The negative electrodes of the third diode, the fourth diode, the fifth diode, and the sixth diode are all connected to the wave suppression judgment unit. The positive electrodes of the third diode, the fourth diode, the fifth diode, and the sixth diode are all connected to the input end of resistor four. The output end of resistor four is respectively connected to the input end of resistor five and the base of the second switching transistor. The emitter of the second switching transistor is connected to the input end of resistor six. The input end of the second relay is connected to the power supply. The output ends of resistor five and resistor six are both connected to the coil of the second relay. The normally open end of the second relay is connected to the common end of the first bus capacitor and the second bus capacitor connected in series. The common end of the second relay is connected to the positive discharge transfer resistor, and the collector of the second switching transistor is grounded.

7. The circuit according to claim 3, characterized in that, The negative wave suppression signal conversion sub-unit includes a negative switching control component and a negative transfer control component. The negative switching unit includes a negative switch switching sub-unit and a negative switch sub-unit. The negative discharge transfer unit includes a negative discharge transfer resistor; The input ends of the negative switching control component and the negative transfer control component are both connected to the output end of the wave suppression judgment unit. The output end of the negative switching control component is connected to the coil of the negative switch switching sub-unit. The normally closed end of the negative switch switching sub-unit is connected to the negative electrode of the second bus capacitor. The normally open end of the negative switch switching sub-unit is connected to the positive electrode of the first bus capacitor; The output end of the negative transfer control component is connected to the coil of the negative switch sub-unit. The normally open end of the negative switch sub-unit is connected to the common end of the first bus capacitor and the second bus capacitor connected in series; The negative discharge transfer resistor is arranged between the common end of the negative switch switching sub-unit and the common end of the negative switch sub-unit.

8. The circuit according to claim 7, wherein The negative switching control component includes resistor seven, resistor eight, resistor nine, the seventh diode, the eighth diode, and the third switching transistor, and the negative switch switching sub-unit includes a third relay; The negative electrodes of the seventh diode and the eighth diode are both connected to the wave blocking judgment unit. The positive electrodes of the seventh diode and the eighth diode are both connected to the input end of the seventh resistor. The output end of the seventh resistor is respectively connected to the input end of the eighth resistor and the base of the third switching transistor. The emitter of the third switching transistor is connected to the input end of the ninth resistor. The output ends of the eighth resistor and the ninth resistor are both connected to the coil of the third relay. The input end of the third relay is connected to the power supply. The common end of the third relay is connected to the negative discharge transfer resistor. The normally closed end of the third relay is connected to the negative electrode of the second bus capacitor. The normally open end of the third relay is connected to the positive electrode of the first bus capacitor. And the collector of the third switching transistor is grounded.

9. The circuit according to claim 7, wherein The negative transfer control component includes a tenth resistor, an eleventh resistor, a twelfth resistor, a ninth diode, a twelfth diode, an eleventh diode, a twelfth diode, and a fourth switching transistor. The negative switch sub-unit includes a fourth relay. The negative electrodes of the ninth diode, the twelfth diode, the eleventh diode, and the twelfth diode are all connected to the wave blocking judgment unit. The positive electrodes of the ninth diode, the twelfth diode, the eleventh diode, and the twelfth diode are all connected to the input end of the tenth resistor. The output end of the tenth resistor is respectively connected to the input end of the eleventh resistor and the base of the fourth switching transistor. The emitter of the fourth switching transistor is connected to the input end of the twelfth resistor. The input end of the fourth relay is connected to the power supply. The output ends of the eleventh resistor and the twelfth resistor are both connected to the coil of the fourth relay. The normally open end of the fourth relay is connected to the common end of the first bus capacitor and the second bus capacitor connected in series. The common end of the fourth relay is connected to the negative discharge transfer resistor. And the collector of the fourth switching transistor is grounded.

10. The circuit according to claim 2, wherein, The wave blocking judgment unit includes a current sampling sub-unit and an identification sub-unit. The input end of the current sampling sub-unit is respectively connected to the first inductor and the second inductor in the inverter. The identification sub-unit is used to connect the output end of the current sampling sub-unit to the control signal generation unit. The current sampling sub-unit is used to collect the current signals of the first inductor and the second inductor. The identification sub-unit is used to identify the positive and negative of the wave blocking signal corresponding to the first inductor according to the direction of the current signal of the first inductor, and output the wave blocking signal corresponding to the first inductor. And, according to the direction of the current signal of the second inductor, identify the positive and negative of the wave blocking signal corresponding to the second inductor, and output the wave blocking signal corresponding to the second inductor.

11. A energy storage power supply, characterized in that, The energy storage power supply includes an inverter and the bus voltage discharge circuit according to any one of claims 1-10.

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