Doherty amplifier circuit

Abstract

A Doherty amplifier circuit is provided with: a distribution node that distributes an input signal that is input into a first signal and a second signal; a main amplifier provided with a first GaN HEMT, the main amplifier amplifying the first signal and outputting the amplified first signal as a third signal; a first peak amplifier provided with a second GaN HEMT, the first peak amplifier amplifying the second signal and outputting the amplified second signal as a fourth signal; and a combining node that combines the third signal and the fourth signal and outputs the combined signal as an output signal to the output terminal, a first electrical length that is a sum of an electrical length between the distribution node and the main amplifier and an electrical length between the main amplifier and the combining node, and a second electrical length that is a sum of an electrical length between the distribution node and the main amplifier and an electrical length between the main amplifier and the combining node. The second electrical length is a sum of an electrical length between the distribution node and the first peaking amplifier and an electrical length between the first peaking amplifier and the synthesis node.

Description

Technical Field

[0001] The present invention relates to a Doherty amplifier circuit. Background Art

[0002] There is known an N-way (N≥3) Doherty amplifier circuit that uses a main amplifier and two or more peak amplifiers (for example, Patent Document 1 and Patent Document 2).

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: US Patent No. 8022760 Specification

[0006] Patent Document 2: US Patent No. 10601375 Specification

[0007] However, in a Doherty amplifier circuit, when the phases of the signals at the combining node where the signals amplified by the respective amplifiers are combined are different, characteristics such as gain deteriorate. Summary of the Invention

[0008] An object of the present disclosure is to suppress deterioration of characteristics.

[0009] One embodiment of the present disclosure is a Doherty amplifier circuit including: a distribution node that distributes an input signal input thereto into a first signal and a second signal; a main amplifier including a first GaN HEMT, the main amplifier amplifying the first signal and outputting the amplified first signal as a third signal; a first peak amplifier including a second GaN HEMT, the first peak amplifier amplifying the second signal and outputting the amplified second signal as a fourth signal; and a combining node that combines the third signal and the fourth signal and outputs the combined signal as an output signal to an output terminal, where a first electrical length is shorter than a second electrical length, the first electrical length being the total electrical length between the distribution node and the main amplifier and between the main amplifier and the combining node, and the second electrical length being the total electrical length between the distribution node and the first peak amplifier and between the first peak amplifier and the combining node.

[0010] Advantages of the Invention

[0011] According to the present disclosure, deterioration of characteristics can be suppressed. Brief Description of the Drawings

[0012] Figure 1 is a block diagram of the Doherty amplifier circuit of Embodiment 1.

[0013] Figure 2It is a schematic diagram showing the probability with respect to the output power Pout in Example 1, the output power Pout of each amplifier with respect to the input power Pin, the gain of each amplifier with respect to the input power Pin, and the overall gain with respect to the input power Pin.

[0014] Figure 3 It is a cross-sectional view of the GaN HEMT in Example 1.

[0015] Figure 4 It is a graph showing the phase with respect to the input power Pin in the GaN HMET.

[0016] Figure 5 It is a graph showing the output power Pout of each amplifier with respect to the input power Pin and the phase of each amplifier with respect to the input power Pin.

[0017] Figure 6 It is a graph showing the output power Pout of each amplifier with respect to the input power Pin and the phase of each amplifier with respect to the input power Pin.

[0018] Figure 7 It is a diagram for explaining the phase adjustment method in Example 1.

[0019] Description of reference numerals:

[0020] 10: Main amplifier;

[0021] 12 (first peak amplifier), 14 (second peak amplifier): Peak amplifiers;

[0022] 16: Divider;

[0023] 18: Combiner;

[0024] 20 (first phase adjuster), 21 (second phase adjuster), 22 (third phase adjuster): Phase adjusters;

[0025] 23 (first impedance transformer), 24 (second impedance transformer): Impedance transformers;

[0026] 25, 26, 27: Paths;

[0027] 30, 31, 32, 33, 34, 35: Matching circuits;

[0028] 36, 37, 38, 39: Bias circuits;

[0029] 40, 40a: Substrates;

[0030] 40b: Semiconductor layer;

[0031] 40c: Transit layer;

[0032] 40d: Blocking layer;

[0033] 42: Source electrode;

[0034] 44: Gate electrode;

[0035] 46: Drain electrode;

[0036] 100: Doherty amplifier circuit;

[0037] N1: Distribution node;

[0038] N2: Combining node;

[0039] Pin: Input power;

[0040] S1 (first signal), S2 (second signal), S3 (fifth signal), S4 (third signal), S5 (fourth signal), S6 (sixth signal);

[0041] Sin: Input signal;

[0042] Sout: Output signal;

[0043] Δθ1, Δθ2a, Δθ2b, Difference;

[0044] θ1, θ2, θ3, θ4, Change amount;

[0045] θ5, θ6, θ7: Adjustment amount;

[0046] Tin: Input terminal;

[0047] Tout: Output terminal. Detailed implementation manners

[0048] [Description of the embodiments of the present disclosure]

[0049] First, the content of the embodiments of the present disclosure will be listed for description.

[0050] (1) One embodiment of the present disclosure is a Doherty amplifier circuit, comprising: a distribution node that distributes an input signal into a first signal and a second signal; a main amplifier including a first GaN HEMT, which amplifies the first signal and outputs the amplified first signal as a third signal; a first peak amplifier including a second GaN HEMT, which amplifies the second signal and outputs the amplified second signal as a fourth signal; and a combining node that combines the third signal and the fourth signal and outputs the combined signal as an output signal to an output terminal. The first electrical length is shorter than the second electrical length, where the first electrical length is the sum of the electrical lengths between the distribution node and the main amplifier and between the main amplifier and the combining node, and the second electrical length is the sum of the electrical lengths between the distribution node and the first peak amplifier and between the first peak amplifier and the combining node. Thereby, the phase difference between the third signal and the fourth signal at the combining node can be reduced. Thereby, the characteristics can be improved.

[0051] (2) In the above (1), it may also be that the difference between the second electrical length and the first electrical length, when converted into a phase at the center frequency of the operating frequency band, is 2° or more and 20° or less. Thereby, the characteristics can be further improved.

[0052] (3) In the above (2), it may also be that when the input power of the input signal is the power for the main amplifier and the first peak amplifier to operate, the difference between the change amount of the phase of the signal at the center frequency when passing through the main amplifier and the change amount of the phase of the signal at the center frequency when passing through the first peak amplifier, and the value obtained by converting the difference between the second electrical length and the first electrical length into a phase at the center frequency, is 2° or less. Thereby, the characteristics can be further improved.

[0053] (4) In the above (1), it may also be that the Doherty amplifier circuit includes: a second peak amplifier, which includes a third GaN HEMT, the second peak amplifier amplifies the fifth signal and outputs the amplified signal as the sixth signal, the distribution node distributes the input signal into the first signal, the second signal, and the fifth signal, the combining node combines the third signal, the fourth signal, and the sixth signal and outputs the combined signal as the output signal to the output terminal, the input power of the input signal for turning on the second peak amplifier is greater than the input power of the input signal for turning on the first peak amplifier, and the third electrical length is longer than the second electrical length, where the third electrical length is the total electrical length of the electrical length between the distribution node and the second peak amplifier and the electrical length between the second peak amplifier and the combining node. Thereby, the phase difference among the third signal, the fourth signal, and the sixth signal at the combining node can be reduced. Thereby, the characteristics can be improved.

[0054] (5) In the above (4), it may also be that the difference between the second electrical length and the first electrical length, when converted into a phase at the center frequency of the operating frequency band, is 2° or more and 20° or less, and the difference between the third electrical length and the second electrical length, when converted into a phase at the center frequency, is 2° or more and 20° or less. Thereby, the characteristics can be further improved.

[0055] (6) In the above (5), it may also be that the difference between the change amount of the phase of the signal at the center frequency when passing through the main amplifier and the change amount of the phase of the signal at the center frequency when passing through the first peak amplifier, and the value obtained by converting the difference between the second electrical length and the first electrical length into a phase at the center frequency, is 2° or less, and the difference between the change amount of the phase of the signal at the center frequency when passing through the first peak amplifier and the change amount of the phase of the signal at the center frequency when passing through the second peak amplifier, and the value obtained by converting the difference between the third electrical length and the second electrical length into a phase at the center frequency, is 2° or less. Thereby, the characteristics can be further improved.

[0056] (7)In any one of the above (4) to (6), it is also possible that the Doherty amplifier circuit includes: a first impedance converter connected between the first peak amplifier and the combining node; a second impedance converter connected between the second peak amplifier and the combining node; a first phase adjuster connected between the splitting node and the main amplifier; a second phase adjuster connected between the splitting node and the first peak amplifier; and a third phase adjuster connected between the splitting node and the second peak amplifier. The electrical length of the second phase adjuster, when converted to the phase of a signal at the center frequency of the operating frequency band, is 2° or more and 20° or less, and the electrical length of the third phase adjuster, when converted to the phase of the signal at the center frequency, is 4° or more and 40° or less. Thereby, the design of the second phase adjuster and the third phase adjuster becomes easier.

[0057] (8)In the above (7), it is also possible that no impedance converter is provided between the main amplifier and the combining node, and the electrical length of the first phase adjuster, when converted to the phase of the signal at the center frequency, is 67.5° or more and 112.5° or less. Thereby, the design of the first phase adjuster becomes easier.

[0058] [Details of Embodiments of the Present Disclosure]

[0059] Hereinafter, with reference to the drawings, specific examples of the Doherty amplifier circuit according to the embodiments of the present disclosure will be described. It should be noted that the present disclosure is not limited to these examples, but is shown by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0060] [Embodiment 1]

[0061] As the Doherty amplifier circuit, a high-output high-frequency amplifier circuit for a mobile communication base station will be described as an example. In this case, the frequency of the high-frequency signal is, for example, 0.5 GHz or more and 10 GHz or less. Figure 1 It is a block diagram of the Doherty amplifier circuit of Embodiment 1.

[0062] As shown in Figure 1 , in the Doherty amplifier circuit 100, a main amplifier 10, a peak amplifier 12 (first peak amplifier), and a peak amplifier 14 (second peak amplifier) are connected in parallel between the splitting node N1 of the splitter 16 and the combining node N2 of the combiner 18. Paths 25 to 27 are paths from the splitting node N1 to the combining node N2 through the main amplifier 10, the peak amplifier 12, and the peak amplifier 14, respectively. In this way, the Doherty amplifier circuit 100 is a three-way amplifier circuit. The Doherty amplifier circuit may also be an N-way Doherty amplifier circuit having one or three or more peak amplifiers.

[0063] A high-frequency signal is input as an input signal Sin to the input terminal Tin. The distributor 16 distributes the input signal Sin input to the input terminal Tin into a signal S1 (first signal), a signal S2 (second signal), and a signal S3 (fifth signal). The distributor 16 is, for example, a Wilkinson type distributor. The distributor 16 has a distribution node N1 for distributing the signals S1, S2, and S3.

[0064] The path 25 includes a phase adjuster 20 (first phase adjuster), a matching circuit 30, a bias circuit 36, a main amplifier 10, a bias circuit 39, and a matching circuit 33. The path 26 includes a phase adjuster 21 (second phase adjuster), a matching circuit 31, a bias circuit 37, a peak amplifier 12, a matching circuit 34, and an impedance transformer 23 (first impedance transformer). The path 27 includes a phase adjuster 22 (third phase adjuster), a matching circuit 32, a bias circuit 38, a peak amplifier 14, a matching circuit 35, and an impedance transformer 24 (second impedance transformer).

[0065] The matching circuits 30 to 32 match the impedances when looking from the distributor 16 to the matching circuits 30 to 32 respectively with the impedances when looking from the matching circuits 30 to 32 to the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 respectively. The bias circuits 36 to 38 supply gate bias voltages VG1 to VG3 to the gates G of the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 respectively.

[0066] The phase adjuster 20 adjusts the phase of the signal S1 so that the signals S5 and S6 changed by the impedance transformers 23 and 24 are in phase with the signal S4. The phase adjusters 21 and 22 adjust the phase difference between the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 described later. The phase adjusters 20 to 22 are, for example, transmission lines such as microstrip lines or coplanar lines, and the phase can be adjusted by setting the electrical length of the transmission line to a desired length.

[0067] The main amplifier 10, the peak amplifier 12, and the peak amplifier 14 amplify the signal S1, the signal S2, and the signal S3 respectively, and output the amplified signal S4 (the fourth signal), the signal S5 (the fifth signal), and the signal S6 (the sixth signal) respectively. The bias circuit 39 supplies the drain bias voltage VD to the drains D of the main amplifier 10, the peak amplifier 12, and the peak amplifier 14. The matching circuits 33 to 35 match the impedances when looking from the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 to the matching circuits 33 to 35 respectively with the impedances when looking from the matching circuits 33 to 35 to the synthesizer 18 respectively.

[0068] The synthesizer 18 includes a synthesis node N2, an impedance transformer 23, and an impedance transformer 24. The first end of the impedance transformer 23 is electrically connected to the peak amplifier 12 via the matching circuit 34, and the second end of the impedance transformer 23 is electrically connected to the synthesis node N2. The first end of the impedance transformer 24 is electrically connected to the peak amplifier 14 via the matching circuit 35, and the second end of the impedance transformer 24 is electrically connected to the synthesis node N2. The synthesis node N2 synthesizes the signals S4 to S6, and outputs the synthesized signal as the output signal Sout to the output terminal Tout.

[0069] The impedance transformer 23 and the impedance transformer 24 transform the impedance on the real axis of the Smith chart when looking from the matching circuit 34 and the matching circuit 35 to the impedance transformer 23 and the impedance transformer 24 into the impedance at different positions on the real axis of the Smith chart when looking from the impedance transformer 23 and the impedance transformer 24 to the synthesis node N2. In addition, when the peak amplifier 12 is not operating, the impedance transformer 23 sets the impedance when looking from the synthesis node N2 to the peak amplifier 12 to infinity. When the peak amplifier 14 is not operating, the impedance transformer 24 sets the impedance when looking from the synthesis node N2 to the peak amplifier 14 to infinity.

[0070] The impedance transformer 23 and the impedance transformer 24 are, for example, transmission lines such as microstrip lines or coplanar lines, and are 1 / 4 wavelength lines at the center frequency of the operating frequency band. The electrical length of the 1 / 4 wavelength line does not have to be strictly 1 / 4 wavelength. The 1 / 4 wavelength line only needs to have an electrical length that functions as the impedance transformer 23 and the impedance transformer 24. For example, the electrical length of the 1 / 4 wavelength line can be 3 / 16 wavelength or more and 5 / 16 wavelength or less, or can be 7 / 32 wavelength or more and 9 / 32 wavelength or less. The impedance on the real axis in the Smith chart does not have to be strictly on the real axis (the reactance component is 0). The absolute value of the reactance component of the impedance can be 0.2 times or less of the resistance component, or can be 0.1 times or less.

[0071] The main amplifier 10, the peak amplifier 12, and the peak amplifier 14 each include transistors Q1 to Q3. The transistors Q1 to Q3 are, for example, GaN HEMTs (Gallium Nitride High Electron Mobility Transistors). The sources S of the transistors Q1 to Q3 are grounded, signals S1 to S3 are respectively input to the gates G, and signals S4 to S6 are respectively output from the drains D.

[0072] Figure 2 It is a schematic diagram showing the probability with respect to the output power Pout in Embodiment 1, the output power Pout of each amplifier with respect to the input power Pin, the gain of each amplifier with respect to the input power Pin, and the overall gain with respect to the input power Pin.

[0073] The probability is the probability of the modulated wave signal of the high-frequency signal for mobile communication amplified by the Doherty amplifier circuit 100. That is, it is the probability that the Doherty amplifier circuit 100 outputs a certain output power Pout. Each Pout is the output power Pout of the main amplifier 10, the peak amplifier 12, and the peak amplifier 14. Each gain is the power gain of the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 respectively. The overall gain is the power gain of the output power Pout of the output signal Sout with respect to the input power Pin of the input signal Sin. It should be noted that Pin and Pout are expressed in dB. The gain of the main amplifier 10 below the power P1 is greater than the gain of the peak amplifier 12 above the power P1 and below the power P2. That is, the slope of Pout of the main amplifier 10 below the power P1 with respect to the input power Pin is greater than the slope of Pout of the peak amplifier 12 above the power P1 and below the power P2 with respect to the input power Pin. However, Figure 2 For the schematic diagram, the slope of Pout of the main amplifier 10 below the power P1 with respect to the input power Pin is shown as less than the slope of Pout of the peak amplifier 12 above the power P1 and below the power P2 with respect to the input power Pin.

[0074] As Figure 2As shown, when the output power Pout is the power P0, the probability of the modulation wave is the highest. That is, when the signal of the output modulation wave is output, the time when the output power Pout is the power P0 is the longest. The main amplifier 10 is an A-class or AB-class amplifier, and the peak amplifiers 12 and 14 are C-class amplifiers. The input power Pin for turning on the peak amplifier 12 is greater than the input power Pin for turning on the main amplifier 10, and the input power Pin for turning on the peak amplifier 14 is greater than the input power Pin for turning on the peak amplifier 12. In order to operate in this way, it can be achieved by making the gate bias voltage VG2 of the transistor Q2 greater than the gate bias voltage VG1 of the transistor Q1 in the negative direction, and making the gate bias voltage VG3 of the transistor Q3 greater than the gate bias voltage VG2 of the transistor Q2 in the negative direction.

[0075] As the input power Pin of the input signal Sin increases, the input power Pin exceeds the power P0 and reaches up to the power P1. The main amplifier 10 operates, but the peak amplifiers 12 and 14 do not operate. When the input power Pin is below the power P1, if the input power Pin increases, the output power Pout of the main amplifier 10 will increase linearly. Therefore, when the input power Pin is below the power P0, each gain and the overall gain are approximately fixed.

[0076] When the input power Pin is above the power P1 and below the power P2, the main amplifier 10 and the peak amplifier 12 operate, but the peak amplifier 14 does not operate. In this range, the main amplifier 10 saturates. Therefore, the gain of the main amplifier 10 decreases. The overall gain also decreases accordingly. The peak amplifier 12 operates in class C. Therefore, the gain of the peak amplifier 12 between the power P1 and the power P2 is lower than the gain of the main amplifier 10 below the power P1. In addition, the saturation power of the peak amplifier 12 is less than the saturation power of the main amplifier 10.

[0077] When the input power Pin is above the power P2 and below P3, the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 all operate. In this range, in addition to the main amplifier 10, the peak amplifier 12 also saturates. Therefore, the gain of the peak amplifier 12 decreases. The overall gain also decreases accordingly. The operating point of the peak amplifier 14 is greater than that of the peak amplifier 12 in the negative direction. Therefore, the gain of the peak amplifier 14 between the power P2 and the power P3 is lower than the gain of the peak amplifier 12 between the power P1 and the power P2. In addition, the saturation power of the peak amplifier 14 is less than the saturation power of the peak amplifier 12.

[0078] When the input power Pin is above the power P3, in addition to the main amplifier 10 and the peak amplifier 12, the peak amplifier 14 also saturates. Therefore, the gain of the peak amplifier 14 decreases. The overall gain also decreases accordingly.

[0079] The product of the probability and the overall gain corresponds to the gain of the modulation wave. To increase the gain of the modulation wave, the overall gain at Pout with a high probability is increased.

[0080] [Description of GaN HEMT]

[0081] Figure 3 is a cross-sectional view of the GaN HEMT of Example 1. As Figure 3 shown, in the GaN HEMT, a source electrode 42, a gate electrode 44, and a drain electrode 46 are provided on a substrate 40. The substrate 40 includes a substrate 40a and a semiconductor layer 40b provided on the substrate 40a. The semiconductor layer 40b includes a transit layer 40c provided on the substrate 40a and a barrier layer 40d provided on the transit layer 40c. The substrate 40a is, for example, a silicon carbide (SiC) substrate, a sapphire substrate, or a gallium nitride (GaN) substrate. The semiconductor layer 40b is a nitride semiconductor layer, the transit layer 40c is, for example, a gallium nitride layer, and the barrier layer 40d is, for example, a gallium aluminum nitride layer.

[0082] Figure 4 is a diagram showing the phase with respect to the input power Pin in the GaN HMET, and is a diagram showing the AM (Amplitude Modulation) - PM (Phase Modulation) characteristics. The input power Pin is the power of a high-frequency signal at the center frequency of the operating band input to the gate of the GaN HEMT. The phase is the phase difference between the high-frequency signal input to the gate and the high-frequency signal output from the drain, and the phase when the input power Pin is 0 dBm is set to 0°. In Figure 4 the measurement results and simulation results are shown. The values of the input power Pin and the phase vary depending on the structure such as the gate width of the GaN HEMT, and thus this is an example.

[0083] As Figure 4 shown, when the input power Pin increases from 0 dBm, the phase moves in the negative direction. When the input power Pin exceeds the power Pth (23 dBm), the phase moves in the positive direction. Compared with when the input power Pin is below Pth, when the input power Pin is above Pth, the absolute value of the slope of the phase with respect to the input power Pin is larger.

[0084] [Description of the phase of each amplifier]

[0085] Figure 5 is a diagram showing the output power Pout of each amplifier with respect to the input power Pin and the phase of each amplifier with respect to the input power Pin. The input power Pin corresponds to Figure 1The input power of the input signal Sin. Each Pout is the output power of the main amplifier 10, the peak amplifier 12, and the peak amplifier 14. The phases of the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 correspond to the amounts of change in phase θ1, change in phase θ2, and change in phase θ3, respectively, when the signals corresponding to the center frequencies of the operating frequency bands pass through the main amplifier 10, the peak amplifier 12, and the peak amplifier 14. A large change in the positive direction of the changes in phase θ1 to θ3 indicates an advance in phase, which is equivalent to an increase in electrical length.

[0086] As Figure 5 shown, the powers Pth at the amounts of change in phase θ1 to θ3 are slightly smaller than the powers P1 to P3, respectively. Therefore, the phase difference between the main amplifier 10 and the peak amplifier 12 when the input power Pin is the power P2 is Δθ1. The phase difference between the main amplifier 10 and the peak amplifier 12 when the input power Pin is the power P3 is Δθ2a, and the phase difference between the main amplifier 10 and the peak amplifier 14 is Δθ2b. Δθ1 and Δθ2a are substantially equal, but they may also be different.

[0087] In this way, when signals S4 to S6 are combined at the combining node N2 in the presence of the phase differences Δθ1, Δθ2a, and Δθ2b, the power of the output signal Sout decreases and the overall gain decreases.

[0088] Figure 6 is a graph showing the output power Pout of each amplifier with respect to the input power Pin and the phase of each amplifier with respect to the input power Pin. The thin dashed line indicates before the phase is adjusted by the phase adjuster 21 and the phase adjuster 22.

[0089] As Figure 6 shown, the phase of the path 26 when the input power Pin is the power P2 is advanced The phases of the path 26 and the path 27 when the input power Pin is the power P3 are advanced respectively and Thereby, at the power P2, the phases of the main amplifier 10 and the peak amplifier 12 are substantially the same. At the power P3, the phases of the main amplifier 10 and the peak amplifier 12 are substantially the same, and the phases of the main amplifier 10 and the peak amplifier 14 are substantially the same.

[0090] [Method for adjusting phase]

[0091] Figure 7 is a diagram for explaining the method for adjusting the phase of the first embodiment. The figure shows the paths 25 to 27 between the distribution node N1 and the combining node N2. The illustration of the matching circuits 30 to 35 and the bias circuits 36 to 39 is omitted.

[0092] When the change amount θ1 of the phase becomes larger, corresponding to further rotation of the phase, i.e., phase advance, it is equivalent to an increase in the electrical length of the signal passing through the main amplifier 10. The phase Phase And the phase Is the amount of phase obtained by converting the electrical lengths between the distribution node N1 and the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 into the phase at the center frequency of the operating frequency band respectively. The phase Phase And the phase Is the amount of phase obtained by converting the electrical lengths between the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 and the synthesis node N2 into the phase at the center frequency of the operating frequency band respectively. The change amount of the phase Is And The sum of, the change amount of the phase Is And The sum of, the change amount of the phase Is And The sum of.

[0093] The change amount of the phase when passing through the impedance transformers 23 and 24 at the center frequency of the operating frequency band of the impedance transformers 23 and 24 is θ4. Therefore, the adjustment amount of the phase of the phase adjuster 20 is set to θ5. For example, in the case where the phase adjuster 20 is formed by a transmission line, the electrical length of the transmission line is set to a length corresponding to the adjustment amount θ5. For example, θ5 is 90°. Thus, the change amount of the phase based on the impedance transformers 23 and 24 can be adjusted by the phase adjuster 20.

[0094] However, as Figure 5 Shown, the phases when passing through the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 are different. Therefore, the adjustment amount θ6 of the phase of the phase adjuster 21 is set to Δθ1 and Δθ2a. The adjustment amount θ7 of the phase of the phase adjuster 22 is set to Δθ2b. Thus, as Figure 6 Shown, the difference in the phases when passing through the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 can be adjusted. In the case where Δθ1 and Δθ2a are different, the adjustment amount θ6 can also be set to a value between Δθ1 and Δθ2a. For the increase in the gain of the modulated wave, the adjustment of the phase at power P2 is more important than the adjustment of the phase at power P3. Therefore, the adjustment amount θ6 can also be set to Δθ1.

[0095] According to Embodiment 1, the first electrical length (corresponding to ) is longer than the second electrical length (corresponding to ) is short, where the first electrical length is the electrical length between the distribution node N1 and the main amplifier 10 (equivalent to ) and the electrical length between the main amplifier 10 and the combining node N2 (equivalent to ) of the total electrical length. The second electrical length is the electrical length between the distribution node N1 and the peak amplifier 12 (equivalent to ) and the electrical length between the peak amplifier 12 and the combining node N2 (equivalent to ) of the total electrical length. In GaN HEMT, as Figure 5 shown, when the input power Pin is the power P2 and the power P3 at which the main amplifier 10 and the peak amplifier 12 operate, the change amount θ1 of the phase of the main amplifier 10 is greater than the change amount θ2 of the phase of the peak amplifier 12. Therefore, the first electrical length corresponding to path 25 is made shorter than the second electrical length corresponding to path 26 . Thereby, the phase difference between the signal S4 and the signal S5 at the combining node N2 can be reduced. Thereby, the overall gain when the input power Pin is the power P2 can be improved, and the characteristics can be improved.

[0096] The difference between the second electrical length and the first electrical length, converted into the phase at the center frequency of the operating frequency band can be set to be 2° or more and 20° or less, and can be set to be 5° or more and 15° or less. Thereby, the phase difference between the signal S4 and the signal S5 at the combining node N2 can be further reduced. Thereby, the characteristics can be further improved.

[0097] When the input power Pin is the power P2 or the power P3, the difference Δθ1 between the change amount θ1 of the phase when passing through the main amplifier 10 and the change amount θ2 of the phase when passing through the peak amplifier 12, and the difference with the difference or can be set to be 2° or less, can be set to be 1.5° or less, and can be set to be 1° or less. Thereby, the phase difference between the signal S4 and the signal S5 at the combining node N2 can be further reduced. Thereby, the characteristics can be further improved.

[0098] The third electrical length (equivalent to ) is longer than the first electrical length (equivalent to ) and longer than the second electrical length (equivalent to ), where the third electrical length is the electrical length between the distribution node N1 and the peak amplifier 14 (equivalent to ) and the electrical length between the peak amplifier 14 and the combining node N2 (equivalent to ) of the total electrical length. In GaN HEMT, as Figure 5As shown, when the input power Pin is the power P3 at which the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 operate, the change amount θ2 of the phase of the peak amplifier 12 is greater than the change amount θ3 of the phase of the peak amplifier 14. Therefore, the third electrical length corresponding to path 27 is made longer than the second electrical length corresponding to path 26. Thereby, the phase difference between the signal S5 and the signal S6 at the synthesis node N2 can be reduced. Thereby, the overall gain when the input power Pin is the power P3 can be increased, and the characteristics can be improved. is longer than the second electrical length corresponding to path 26 . Thereby, the phase difference between the signal S5 and the signal S6 at the synthesis node N2 can be reduced. Thereby, the overall gain when the input power Pin is the power P3 can be increased, and the characteristics can be improved.

[0099] The difference between the third electrical length and the second electrical length, converted to the phase at the center frequency of the operating frequency band can be set to be 2° or more and 20° or less, and can be set to be 5° or more and 15° or less. Thereby, the phase difference between the signal S5 and the signal S6 at the synthesis node N2 can be further reduced. Thereby, the characteristics can be further improved.

[0100] When the input power Pin is the power P3, the difference (Δθ2b - Δθ2a) between the change amount θ2 of the phase when passing through the peak amplifier 12 and the change amount θ3 of the phase when passing through the peak amplifier 14, and the difference from can be set to be 2° or less, can be set to be 1.5° or less, can be set to be 1° or less. Thereby, the phase difference between the signal S5 and the signal S6 at the synthesis node N2 can be further reduced. Thereby, the characteristics can be further improved.

[0101] To achieve the above, the adjustment amount θ5 of the phase of the phase adjuster 20 corresponds to the change amount θ4 of the phases of the signals S5 and S6 based on the impedance transformers 23 and 24. When the input power Pin is the power P2 or the power P3, the adjustment amount θ6 of the phase of the phase adjuster 21 corresponds to Δθ1 and Δθ2a. When the input power Pin is the power P3, the adjustment amount of the phase of the phase adjuster 22 corresponds to Δθ2b.

[0102] In the case where the impedance transformers 23 and 24 are provided, the electrical length of the phase adjuster 21, converted to the phase of the signal at the center frequency, can be set to be 2° or more and 20° or less, and can be set to be 5° or more and 15° or less. The electrical length of the phase adjuster 22, converted to the phase of the signal at the center frequency, can be set to be 4° or more and 40° or less, and can be set to be 10° or more and 30° or less. Thereby, when designing the Doherty amplifier circuit, the electrical length of the phase adjuster 20 is set to adjust the phase corresponding to and The phase difference of the difference. Then, the electrical length of the phase adjuster 21 is set to adjust the phase differences Δθ1 and Δθ2a between the main amplifier 10 and the peak amplifier 12. The phase adjuster 22 is set to adjust the phase difference Δθ2b between the peak amplifier 12 and the peak amplifier 14. Thus, the design of the phase adjuster 21 and the phase adjuster 22 becomes easy.

[0103] When no impedance converter is provided between the main amplifier 10 and the combining node N2, the electrical length of the phase adjuster 20 converted into the phase of the signal at the center frequency of the operating frequency band can be set to be 67.5° or more and 112.5° or less, can be set to be 78.75° or more and 101.25° or less, can be set to be 85° or more and 95° or less. Thus, the electrical length of the phase adjuster 20 is set to adjust the electrical lengths of the impedance converter 23 and the impedance converter 24. Thus, the design of the phase adjuster 20 becomes easy.

[0104] The three-way Doherty amplifier circuit has been described as an example, but it may also be a two-way Doherty amplifier circuit without the peak amplifier 14 and the impedance converter. In addition, it may also be an N-way Doherty amplifier circuit where N is 4 or more. In this case, only N - 1 peak amplifiers need to be provided.

[0105] The embodiments disclosed herein should be considered as illustrative in all respects and not restrictive. The scope of the present disclosure is shown not by the above meaning but by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Claims

1. A Doherty amplifier circuit, comprising: An allocation node allocates an input signal to be input into a first signal and a second signal; a main amplifier having a first GaN HEMT, the main amplifier amplifying the first signal and outputting the amplified first signal as a third signal; a first peak amplifier having a second GaN HEMT, the first peak amplifier amplifying the second signal and outputting the amplified second signal as a fourth signal; and a synthesis node, synthesizing the third signal and the fourth signal, and outputting the synthesized signal as an output signal to an output terminal, The first electrical length is shorter than the second electrical length, wherein The first electrical length is the sum of the electrical length between the distribution node and the main amplifier and the electrical length between the main amplifier and the synthesis node, and the second electrical length is the sum of the electrical length between the distribution node and the first peak amplifier and the electrical length between the first peak amplifier and the synthesis node.

2. The Doherty amplifier circuit according to claim 1, wherein: A difference between the second electrical length and the first electrical length, converted into a phase at a center frequency of an operating frequency band, is greater than or equal to 2° and less than or equal to 20°.

3. The Doherty amplifier circuit according to claim 2, wherein: When the input power of the input signal is the power for the main amplifier and the first peak amplifier to operate, the difference between the change in phase when the center frequency signal passes through the main amplifier and the change in phase when the center frequency signal passes through the first peak amplifier, and the value obtained by converting the difference between the second electrical length and the first electrical length into a phase at the center frequency, is less than 2°.

4. The Doherty amplifier circuit according to claim 1, comprising: a second peak amplifier, the second peak amplifier having a third GaN HEMT, the second peak amplifier amplifying the fifth signal and outputting the amplified signal as a sixth signal; The distribution node distributes the input signal into the first signal, the second signal, and the fifth signal, The synthesis node synthesizes the third signal, the fourth signal, and the sixth signal, and outputs the synthesized signal as the output signal to the output terminal. The input power of the input signal for the second peak amplifier to be turned on is greater than the input power of the input signal for the first peak amplifier to be turned on, The third electrical length is longer than the second electrical length, wherein The third electrical length is a sum of an electrical length between the distribution node and the second peak amplifier and an electrical length between the second peak amplifier and the combining node.

5. The Doherty amplifier circuit according to claim 4, wherein: The difference between the second electrical length and the first electrical length is converted into a phase of 2° or more and 20° or less at the center frequency of the operating frequency band, A difference between the third electrical length and the second electrical length, converted into a phase at the center frequency, is greater than or equal to 2° and less than or equal to 20°.

6. The Doherty amplifier circuit according to claim 5, wherein: The difference between the phase change amount when the center frequency signal passes through the main amplifier and the phase change amount when the center frequency signal passes through the first peak amplifier and the value obtained by converting the difference between the second electrical length and the first electrical length into the phase at the center frequency is less than 2°, The difference between the phase change when the center frequency signal passes through the first peak amplifier and the phase change when the center frequency signal passes through the second peak amplifier, and the value of the phase at the center frequency converted from the difference between the third electrical length and the second electrical length, is less than 2°.

7. The Doherty amplifier circuit according to any one of claims 4 to 6, comprising: A first impedance converter connected between the first peak amplifier and the synthesis node; A second impedance converter connected between the second peak amplifier and the synthesis node; A first phase adjuster connected between the distribution node and the main amplifier; a second phase adjuster connected between the distribution node and the first peak amplifier; as well as A third phase adjuster is connected between the distribution node and the second peak amplifier. The electrical length of the second phase adjuster is converted into a phase of a signal of a center frequency of the operating frequency band of not less than 2° and not more than 20°, The electrical length of the third phase adjuster is converted into a phase of the signal of the center frequency of not less than 4° and not more than 40°.

8. The Doherty amplifier circuit according to claim 7, wherein: No impedance transformer is provided between the main amplifier and the synthesis node, The electrical length of the first phase adjuster is converted into a phase of a signal of the center frequency of not less than 67.5° and not more than 112.5°.

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