Doherty amplifier circuit

Abstract

The present disclosure provides a Doherty amplifier circuit capable of improving characteristics. A Doherty amplifier circuit is provided with: a divider for dividing an input signal into a first signal, a second signal, and a third signal, and dividing the power of the second signal to be greater than the power of the third signal; a main amplifier (10) which amplifies the first signal and outputs the amplified signal as a fourth signal; a first peak amplifier (12) which amplifies the second signal and outputs the amplified signal as a fifth signal; a second peak amplifier (14) which amplifies the third signal and outputs the amplified signal as a sixth signal; and a synthesizer that synthesizes the fourth signal, the fifth signal, and the sixth signal, and outputs the synthesized signal as an output signal to an output terminal, the input power of the input signal for conduction of the first peak amplifier being smaller than the input power of the input signal for conduction of the second peak amplifier.

Description

Technical Field

[0001] The present invention relates to a Doherty amplifier circuit. Background Art

[0002] There is known an N (N is 3 or more) - way Doherty amplifier circuit that uses a main amplifier and two or more peak amplifiers (for example, Patent Documents 1 and 2).

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: U.S. Patent No. 8022760 Specification

[0006] Patent Document 2: U.S. Patent No. 10601375 Specification

[0007] In a Doherty amplifier circuit, it is required to increase the gain of the amplified modulated wave. Summary of the Invention

[0008] An object of the present disclosure is to improve characteristics.

[0009] One embodiment of the present disclosure is a Doherty amplifier circuit including: a distributor that distributes an input input signal into a first signal, a second signal, and a third signal, and distributes the power of the second signal to be greater than the power of the third signal; a main amplifier that amplifies the first signal and outputs the amplified signal as a fourth signal; a first peak amplifier that amplifies the second signal and outputs the amplified signal as a fifth signal; a second peak amplifier that amplifies the third signal and outputs the amplified signal as a sixth signal; and a combiner that combines the fourth signal, the fifth signal, and the sixth signal and outputs the combined signal as an output signal to an output terminal, and the input power of the input signal for turning on the first peak amplifier is less than the input power of the input signal for turning on the second peak amplifier.

[0010] Advantages of the Invention

[0011] According to the present disclosure, characteristics can be improved. Brief Description of the Drawings

[0012] Figure 1 is a block diagram of the Doherty amplifier circuit of Example 1.

[0013] Figure 2 is a top view of the semiconductor device in Example 1.

[0014] Figure 3It is a schematic diagram showing the probability relative to Pout, the Pout of each amplifier relative to Pin, the gain of each amplifier relative to Pin, and the overall gain relative to Pin in Example 1 and Comparative Example 1.

[0015] Figure 4 It is a Smith chart showing the load impedance in Example 1.

[0016] Figure 5 It is a Smith chart showing the load impedance in Modified Example 1 of Example 1.

[0017] Figure 6 It is a top view of the semiconductor device in Example 2.

[0018] Figure 7 It is a schematic diagram showing the probability relative to Pout, the Pout of each amplifier relative to Pin, the gain of each amplifier relative to Pin, and the overall gain relative to Pin in Example 2 and Example 1.

[0019] Explanation of Reference Numerals

[0020] 10: Main amplifier;

[0021] 12 (First peak amplifier), 14 (Second peak amplifier): Peak amplifiers;

[0022] 16: Divider;

[0023] 18: Combiner;

[0024] 20a, 20b, 20c: Semiconductor chips;

[0025] 21a, 21b, 21c: Substrates;

[0026] 22a, 22b, 22c, 23a, 23b, 23c: Pads;

[0027] 24a, 24b, 24c: Capacitive components;

[0028] 25: Dielectric substrate;

[0029] 26: Electrode;

[0030] 27a, 27b, 27c, 28a, 28b, 28c: Leads;

[0031] 30, 31, 32, 33, 34, 35: Matching circuits;

[0032] 36, 37, 38, 39: Bias circuits;

[0033] 46, 47, 48: Bonding wires;

[0034] 50: Package;

[0035] 51: Base;

[0036] 52, 54: Impedance;

[0037] 56: Circle;

[0038] 100: Doherty amplifier circuit;

[0039] S1 (first signal), S2 (second signal), S3 (third signal), S4 (fourth signal), S5 (fifth signal), S6 (sixth signal): Signals;

[0040] Sin: Input signal;

[0041] Sout: Output signal;

[0042] Tin: Input terminal;

[0043] Tout: Output terminal;

[0044] D1 (first distance), D2 (second distance), D4: Distances;

[0045] D5: Diameter. Detailed implementation manners

[0046] [Description of the embodiments of the present disclosure]

[0047] First, the content of the embodiments of the present disclosure will be listed for description.

[0048] (1) One embodiment of the present disclosure is a Doherty amplifier circuit, which includes: a distributor that distributes an input input signal into a first signal, a second signal, and a third signal, and distributes the power of the second signal to be greater than the power of the third signal; a main amplifier that amplifies the first signal and outputs the amplified signal as a fourth signal; a first peak amplifier that amplifies the second signal and outputs the amplified signal as a fifth signal; a second peak amplifier that amplifies the third signal and outputs the amplified signal as a sixth signal; and a synthesizer that synthesizes the fourth signal, the fifth signal, and the sixth signal and outputs the synthesized signal as an output signal to an output terminal, and the input power of the input signal for turning on the first peak amplifier is less than the input power of the input signal for turning on the second peak amplifier. Thus, in the range of power with a high probability of modulation wave, the overall gain will increase. Therefore, the gain of the modulation wave can be increased and the characteristics can be improved.

[0049] (2) In the above (1), it is also possible that when the main amplifier and the first peak amplifier are operating and the second peak amplifier is not operating, the first distance between the first position and the second position is shorter than the second distance, where the first position is the position on the Smith chart of the impedance at the center frequency of the operating frequency band when looking from the first peak amplifier towards the synthesizer, the second position is the position on the Smith chart of the impedance at the center frequency when looking from the first peak amplifier towards the synthesizer where the gain of the first peak amplifier becomes maximum, and the second distance is the distance between the position on the Smith chart of the impedance at the center frequency when looking from the main amplifier towards the synthesizer and the position on the Smith chart of the impedance at the center frequency when looking from the main amplifier towards the synthesizer where the gain of the main amplifier becomes maximum. Thereby, the characteristics can be further improved.

[0050] (3) In the above (2), it is also possible that the first position on the Smith chart is located within a circle centered at the second position and having a diameter equal to the distance between the second position and the third position, where the third position is the position on the Smith chart of the impedance at the center frequency when looking from the first peak amplifier towards the synthesizer where the efficiency of the first peak amplifier becomes maximum. Thereby, the characteristics can be further improved.

[0051] (4) In the above (2) or (3), it is also possible that when the main amplifier, the first peak amplifier, and the second peak amplifier are operating, the third distance between the fourth position and the second position is less than or equal to the first distance, where the fourth position is the position on the Smith chart of the impedance at the center frequency when looking from the first peak amplifier towards the synthesizer. Thereby, the characteristics can be further improved.

[0052] (5) In any one of the above (1) to (4), it is also possible that when the same bias voltage is supplied to the first peak amplifier and the second peak amplifier, the saturation power of the first peak amplifier is greater than the saturation power of the second peak amplifier. Thereby, the characteristics can be further improved.

[0053] (6) In any one of the above (1) to (4), it is also possible that when the same bias voltage is supplied to the first peak amplifier and the second peak amplifier, the saturation power of the first peak amplifier is equal to the saturation power of the second peak amplifier. Thereby, amplifiers with the same structure can be used.

[0054] [Details of the Embodiments of the Present Disclosure]

[0055] Hereinafter, a specific example of a Doherty amplifier circuit according to an embodiment of the present disclosure will be described with reference to the accompanying drawings. It should be noted that the present disclosure is not limited to these examples, but is shown by the claims, and is intended to include all changes within the meaning and scope equivalent to the claims.

[0056] As the Doherty amplifier circuit, a high-output high-frequency amplifier circuit for a mobile communication base station will be described as an example. In this case, the frequency of the high-frequency signal is, for example, 0.5 GHz or more and 10 GHz or less. Figure 1 It is a block diagram of the Doherty amplifier circuit of Embodiment 1.

[0057] As Figure 1 shown, in the Doherty amplifier circuit 100, a main amplifier 10, a peak amplifier 12 (first peak amplifier), and a peak amplifier 14 (second peak amplifier) are connected in parallel between a distributor 16 and a combiner 18. Thus, the Doherty amplifier circuit 100 is a three-way amplifier circuit. The Doherty amplifier circuit may also be an N-way Doherty amplifier circuit having three or more peak amplifiers.

[0058] A high-frequency signal serving as an input signal Sin is input to an input terminal Tin. The distributor 16 distributes the input signal Sin input to the input terminal Tin into a signal S1 (first signal), a signal S2 (second signal), and a signal S3 (third signal). The distributor 16 is, for example, a Wilkinson type distributor.

[0059] The path for the signal S1 to be input includes a matching circuit 30, a bias circuit 36, the main amplifier 10, a bias circuit 39, and a matching circuit 33. The path for the signal S2 to be input includes a matching circuit 31, a bias circuit 37, the peak amplifier 12, and a matching circuit 34. The path for the signal S3 to be input includes a matching circuit 32, a bias circuit 38, the peak amplifier 14, and a matching circuit 35.

[0060] The matching circuits 30 to 32 match the impedance when looking at the matching circuits 30 to 32 from the distributor 16 with the impedance when looking at the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 from the matching circuits 30 to 32, respectively. The bias circuits 36 to 38 supply gate bias voltages VG1 to VG3 to the gates G of the main amplifier 10, the peak amplifier 12, and the peak amplifier 14, respectively, to suppress leakage of the signals S1 to S3 to the bias terminals.

[0061] The main amplifier 10, the peak amplifier 12, and the peak amplifier 14 amplify the signal S1, the signal S2, and the signal S3 respectively, and output the amplified signal S4 (the fourth signal), the signal S5 (the fifth signal), and the signal S6 (the sixth signal) respectively. The bias circuit 39 supplies a drain bias voltage VD to the drain D of the main amplifier 10 to suppress the leakage of the signal S4 to the bias terminal. The matching circuits 33 to 35 match the impedances when looking from the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 to the matching circuits 33 to 35 respectively with the impedances when looking from the matching circuits 33 to 35 to the synthesizer 18 respectively. The synthesizer 18 synthesizes the signals S4 to S6 and outputs the synthesized signal as the output signal Sout to the output terminal Tout.

[0062] The main amplifier 10, the peak amplifier 12, and the peak amplifier 14 each include transistors Q1 to Q3. The transistors Q1 to Q3 are, for example, FETs (Field Effect Transistors), for example, GaN HEMTs (Gallium Nitride High Electron Mobility Transistors) or LDMOSs (Laterally Diffused Metal Oxide Semiconductors). The sources S of the transistors Q1 to Q3 are grounded, the signals S1 to S3 are respectively input to their gates G, and the signals S4 to S6 are respectively output from their drains D.

[0063] Figure 2 It is a top view of the semiconductor device in Embodiment 1. Figure 2 The cover of the package 50 is not shown in the figure. The thickness direction of the base 51 of the package 50 is set as the Z direction, the direction from the leads 27a to 27c to the leads 28a to 28c is set as the X direction (the second direction intersecting the first direction), and the direction orthogonal to the X direction and the Z direction is set as the Y direction (the first direction).

[0064] As Figure 2 shown, in the semiconductor device 102, the package 50 has a base 51 whose upper surface is at least conductive. The base 51 is, for example, a conductive substrate such as a laminated substrate of copper and molybdenum. A reference potential such as a ground potential is supplied to the base 51. The semiconductor chips 20a to 20c and the capacitive components 24a to 24c are mounted on the base 51.

[0065] On the negative (−) side in the X direction of the base 51, leads 27a to 27c are provided with an insulating layer (not shown) interposed therebetween. On the positive (+) side in the X direction of the base 51, leads 28a to 28c are provided with an insulating layer (not shown) interposed therebetween. The leads 27a to 27c and the leads 28a to 28c are, for example, metal layers or metal plates such as copper. Signals S1 to S3 are respectively input to the leads 27a to 27c, and signals S4 to S6 are respectively output from the leads 28a to 28c.

[0066] The semiconductor chip 20a includes a substrate 21a, a transistor Q1, pads 22a and 23a provided on the upper surface of the substrate 21a, and an electrode (not shown) provided on the lower surface of the substrate 21a. The pads 22a, 23a, and the lower surface electrode are electrically connected to the gate G, drain D, and source S of the transistor Q1, respectively. The semiconductor chip 20b includes a substrate 21b, a transistor Q2, pads 22b and 23b provided on the upper surface of the substrate 21b, and an electrode provided on the lower surface of the substrate 21b. The pads 22b, 23b, and the lower surface electrode are electrically connected to the gate G, drain D, and source S of the transistor Q2, respectively. The semiconductor chip 20c includes a substrate 21c, a transistor Q3, pads 22c and 23c provided on the upper surface of the substrate 21c, and an electrode provided on the lower surface of the substrate 21c. The pads 22c, 23c, and the lower surface electrode are electrically connected to the gate G, drain D, and source S of the transistor Q3, respectively.

[0067] The substrates 21a to 21c are semiconductor substrates. When the transistors Q1 to Q3 are GaN HEMTs, the substrates 21a to 21c are, for example, silicon carbide (SiC) substrates, sapphire substrates, or gallium nitride (GaN) substrates. When the transistors Q1 to Q3 are LDMOSs, the substrates 21a to 21c are, for example, silicon (Si) substrates. The pads 22a to 22c, the pads 23a to 23c, and the lower surface electrodes are, for example, metal layers such as gold layers. The transistors Q1 to Q3 are of the same size (for example, the gate widths are the same, and the saturation power is the same when the gate bias voltage and the drain bias voltage are the same).

[0068] The capacitive components 24a to 24c include a dielectric substrate 25, an electrode 26 provided on the upper surface of the dielectric substrate 25, and an electrode provided on the lower surface of the dielectric substrate 25. A capacitor is formed with the electrode 26 and the lower surface electrode of the dielectric substrate 25 interposed therebetween. The dielectric substrate 25 is, for example, an alumina substrate or a barium titanate substrate. The electrode 26 is, for example, a metal layer such as a gold layer.

[0069] Bond wires 46 electrically connect leads 27a to 27c to electrodes 26 of capacitive components 24a to 24c, respectively. Bond wire 47 electrically connects electrodes 26 of capacitive components 24a to 24c to pads 22a to 22c, respectively. Bond wire 48 electrically connects pads 23a to 23c to leads 28a to 28c, respectively. Bond wires 46 to 48 are metal wires such as gold wires or aluminum wires, for example.

[0070] Bond wire 46 and bond wire 47 function as inductors, and capacitive components 24a to 24c function as capacitors. Bond wire 46, bond wire 47, and capacitive components 24a to 24c correspond to matching circuits 30 to 32 of the T-type LCL circuit.

[0071] Figure 3 It is a schematic diagram showing the probability relative to Pout, the Pout of each amplifier relative to Pin, the gain of each amplifier relative to Pin, and the overall gain relative to Pin in Example 1 and Comparative Example 1.

[0072] The probability is the probability of the modulated wave signal of the high-frequency signal for mobile communication amplified by the Doherty amplifier circuit 100. That is, the probability is the probability that the Doherty amplifier circuit 100 outputs a certain output power Pout. Each Pout is the output power Pout of the main amplifier 10, the peak amplifier 12, and the peak amplifier 14. Each gain is the power gain of the main amplifier 10, the peak amplifier 12, and the peak amplifier 14, respectively. The overall gain is the power gain of the output power Pout of the output signal Sout relative to the input power Pin of the input signal Sin. Note that Pin and Pout are expressed in dB. The gain of the main amplifier 10 below the power P1 is greater than the gain of the peak amplifier 12 above the power P1 and below the power P2. That is, the slope of Pout of the main amplifier 10 below the power P1 relative to the input power Pin is greater than the slope of Pout of the peak amplifier 12 above the power P1 and below the power P2 relative to the input power Pin. However, Figure 3 It is a schematic diagram that shows the slope of Pout of the main amplifier 10 below the power P1 relative to the input power Pin to be smaller than the slope of Pout of the peak amplifier 12 above the power P1 and below the power P2 relative to the input power Pin. The dashed line represents Comparative Example 1, and the solid line represents Example 1.

[0073] [Description of Comparative Example 1]

[0074] In Comparative Example 1, the distribution ratio of the distributor 16 is the same for signal S2 and signal S3. As Figure 3As such, in Comparative Example 1, when the output power Pout is the power P0, the probability of the modulation wave is the highest. That is, when the signal of the output modulation wave is output, the time when the output power Pout is the power P0 is the longest. The main amplifier 10 is a class A amplifier or a class AB amplifier, and the peak amplifiers 12 and 14 are class C amplifiers. The input power Pin for turning on the peak amplifier 12 is greater than the input power Pin for turning on the main amplifier 10, and the input power Pin for turning on the peak amplifier 14 is greater than the input power Pin for turning on the peak amplifier 12. In order to operate in this way, it can be achieved by making the gate bias voltage VG2 of the transistor Q2 more negative than the gate bias voltage VG1 of the transistor Q1 and making the gate bias voltage VG3 of the transistor Q3 more negative than the gate bias voltage VG2 of the transistor Q2.

[0075] When the input power Pin of the input signal Sin increases and the input power Pin exceeds the power P0, before reaching the power P1, the main amplifier 10 operates, but the peak amplifiers 12 and 14 do not operate. When the input power Pin is below the power P1, as the input power Pin increases, the output power Pout of the main amplifier 10 linearly increases. Therefore, when the input power Pin is below the power P1, each gain and the overall gain are substantially constant.

[0076] When the input power Pin is above the power P1 and below the power P2b, the main amplifier 10 and the peak amplifier 12 operate, but the peak amplifier 14 does not operate. In this range, the main amplifier 10 saturates. Therefore, the gain of the main amplifier 10 decreases. Along with this, the overall gain also decreases. Since the peak amplifier 12 operates in class C, the gain of the peak amplifier 12 between the power P1 and the power P2b is lower than the gain of the main amplifier 10 below the power P1. In addition, the saturation power of the peak amplifier 12 is less than the saturation power of the main amplifier 10.

[0077] When the input power Pin is above the power P2b and below the power P3b, the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 all operate. In this range, not only the main amplifier 10 saturates, but the peak amplifier 12 also saturates. Therefore, the gain of the peak amplifier 12 decreases. Along with this, the overall gain also decreases. Since the operating point of the peak amplifier 14 is more negative than the operating point of the peak amplifier 12, the gain of the peak amplifier 14 between the power P2b and the power P3b is lower than the gain of the peak amplifier 12 between the power P1 and the power P2b. In addition, the saturation power of the peak amplifier 14 is less than the saturation power of the peak amplifier 12.

[0078] When the input power Pin is equal to or higher than the power P3b, not only the main amplifier 10 and the peak amplifier 12 are saturated, but also the peak amplifier 14 is saturated. Therefore, the gain of the peak amplifier 14 decreases. Along with this, the overall gain also decreases.

[0079] The product of the probability and the overall gain corresponds to the gain of the modulation wave. To increase the gain of the modulation wave, increase the overall gain at the Pout with a high probability.

[0080] [Description of Embodiment 1]

[0081] In Embodiment 1, the power of the signal S2 is distributed to be larger than the power of the signal S3. That is, when the amplitude of the power of the signal S2 is set to A2 (in W) and the amplitude of the power of the signal S3 is set to A3 (in W), A2 > A3. For example, it is set to A2:A3 = 2:1.

[0082] As Figure 3 In this way, when the input power Pin is equal to or lower than P1, each Pout, each gain, and the overall gain are the same as those in Comparative Example 1. When the input power Pin is higher than P1, not only the main amplifier 10 operates, but also the peak amplifier 12 operates. Since the distribution ratio A2 / A3 of the signal S2 by the distributor 16 is greater than 1, the Pout of the peak amplifier 12 rises sharply compared with Comparative Example 1. The gain of the peak amplifier 12 with respect to the input power Pin of the input signal Sin is greater than that in Comparative Example 1. Therefore, the overall gain is greater than the overall gain in Comparative Example 1. The peak amplifier 12 saturates when the input power Pin is the power P2a. The power P2a is less than the power P2b in Comparative Example 1.

[0083] When the input power Pin becomes equal to or higher than the power P2a, the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 all operate. The peak amplifier 12 saturates, so the gain of the peak amplifier 12 decreases, and thus the overall gain also decreases. Since the distribution ratio A3 / A2 of the signal S3 by the distributor 16 is less than 1, the Pout of the peak amplifier 14 rises slowly compared with Comparative Example 1. The gain of the peak amplifier 14 with respect to the input power Pin of the input signal Sin is less than that in Comparative Example 1. Therefore, the overall gain is less than the overall gain in Comparative Example 1. The peak amplifier 14 saturates when the input power Pin is the power P3a. The power P3a is greater than the power P3b in Comparative Example 1.

[0084] As described above, in Embodiment 1, compared with Comparative Example 1, when the input power Pin is between the power P1 and the power P2a (or the power P2b), the overall gain becomes larger, and when the input power Pin is equal to or higher than the power P2a (or the power P2b), the overall gain becomes smaller.

[0085] The gain of the modulation wave is the gain obtained by multiplying the probability of the modulation wave by the overall gain. In Example 1, the distributor 16 distributes the power of signal S2 to be greater than the power of signal S3. Thus, within the range of power P1 to power P2a with a high probability, the overall gain is greater than that of Comparative Example 1. Therefore, compared with Comparative Example 1, the gain of the modulation wave can be increased and the characteristics are improved.

[0086] From the viewpoint of increasing the gain of the modulation wave, the ratio A2 / A3 of the amplitude A2 of the power of signal S2 to the amplitude A3 of the power of signal S3 can be set to 1.2 or more, can be set to 1.5 or more, and can be set to 2 or more. When the amplitude A3 of signal S3 is too small, the gain decreases when the input power Pin is large. From this viewpoint, the ratio A2 / A3 can be set to 10 or less and can be set to 5 or less.

[0087] Figure 4 It is a Smith chart showing the load impedance in Example 1. The upper half of the Smith chart is shown. It should be noted that each load impedance is an imaginary value used to explain the load impedance of each amplifier. The load impedance Z10 of the main amplifier 10, the load impedance Z12 of the peak amplifier 12, and the load impedance Z14 of the peak amplifier 14 are the impedances when looking from the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 to the matching circuits 33 to 35 (i.e., the synthesizer 18) respectively in Figure 1

[0088] In Figure 4 the gain-matched impedance 52 is the impedance at which the gain (power gain) becomes maximum at the center frequency of the operating frequency band when load pull measurements are performed on the main amplifier 10, the peak amplifier 12, and the peak amplifier 14. The efficiency-matched impedance 54 is the impedance at which the drain efficiency becomes maximum at the center frequency of the operating frequency band when load pull measurements are performed on the main amplifier 10, the peak amplifier 12, and the peak amplifier 14.

[0089] It should be noted that in Figure 4 the gain-matched impedances 52 of the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 are the same as each other, but they can also be different from each other. The efficiency-matched impedances 54 of the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 are the same as each other, but they can also be different from each other.

[0090] ​The load impedances Z10a, Z10b, and Z10c are the load impedances at the center frequencies of the operating frequency bands of the main amplifier 10 when the input power Pin is the power P1, the power P2, and the power P3, respectively. The load impedances Z12b and Z12c are the load impedances at the center frequencies of the operating frequency bands of the peak amplifier 12 when the input power Pin is the power P2 and the power P3, respectively. The load impedance Z14c is the load impedance at the center frequency of the operating frequency band of the peak amplifier 14 when the input power Pin is the power P3.

[0091] When the input power Pin is the power P1, the load impedance Z10a is near the impedance 54 for efficiency matching. When the input power Pin is the power P2, the load impedances Z10b and Z12b are between the impedance 54 for efficiency matching and the impedance 52 for gain matching. When the input power Pin is the power P3, the load impedances Z10c, Z12c, and Z14c are near the load impedance 52 for gain matching. Thus, at the power P1, the efficiency of the Doherty amplifier circuit 100 can be increased. At the power P2, the efficiency and gain of the Doherty amplifier circuit 100 can be made appropriate. At the power P3, the gain of the Doherty amplifier circuit 100 can be increased.

[0092] [Modified Example 1 of Example 1]

[0093] Figure 5 is a Smith chart showing the load impedance in Modified Example 1 of Example 1. As Figure 5 shown, in Modified Example 1 of Example 1, compared with Example 1, the load impedance Z12b of the peak amplifier 12 when the input power Pin is the power P2 is closer to the impedance 52 for gain matching. Other configurations are the same as those in Example 1, and the description thereof is omitted.

[0094] In Modified Example 1 of Example 1, when the input power Pin is the power P2 (i.e., when the main amplifier 10 and the peak amplifier 12 are operating and the peak amplifier 14 is not operating), the first distance D1 is set as the distance between the first position and the second position, where the first position is the position on the Smith chart of the load impedance Z12b and the second position is the position on the Smith chart of the impedance 52 for gain matching. The second distance D2 is set as the distance between the position on the Smith chart of the load impedance Z10b and the position on the Smith chart of the impedance 52 for gain matching. At this time, the distance D1 is shorter than the distance D2. Thus, the gain of the peak amplifier 12 at the power P2 is increased, Figure 3 and the overall gain at the power P2a in

[0095] From the viewpoint of increasing the gain of the peak amplifier 12 at power P2, the distance D1 can be set to be less than or equal to 0.8 times the distance D2, can be set to be less than or equal to 0.6 times the distance D2, and can be set to be less than or equal to 0.4 times the distance D2.

[0096] At power P2, the distance between the position of the impedance 52 that matches the gain of the peak amplifier 12 on the Smith chart and the third position, where the third position is the position of the impedance 54 that matches the efficiency of the peak amplifier 12 on the Smith chart, is set as D4. On the Smith chart, a circle 56 with a diameter D5 equal to the distance D4 is drawn with the impedance 52 as the center. At this time, the load impedance Z12b is located inside the circle 56. Thereby, at power P2, the gain of the peak amplifier 12 can be increased, and the characteristics are further improved.

[0097] From the viewpoint of increasing the gain of the peak amplifier 12 at power P2, the diameter D5 of the circle 56 can be set to be less than or equal to 0.8 times the distance D4, can be set to be less than or equal to 0.6 times the distance D4, and can be set to be less than or equal to 0.4 times the distance D4.

[0098] When the input power Pin is power P3 (i.e., when the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 are operating), the third distance D3 ( Figure 5 which is approximately 0) is set as the distance between the fourth position and the second position, where the fourth position is the position of the load impedance Z12c of the peak amplifier 12 on the Smith chart, and the second position is the position of the impedance 52 that matches the gain on the Smith chart. At this time, the third distance D3 is less than or equal to the first distance D1. Thereby, at power P2 and power P3, the gain of the peak amplifier 12 can be increased, and the characteristics can be further improved.

[0099] From the viewpoint of increasing the gain of the peak amplifier 12 at power P3, the third distance D3 can be set to be less than or equal to 0.8 times the first distance D1, can be set to be less than or equal to 0.6 times the first distance D1, and can be set to be less than or equal to 0.4 times the first distance D1.

[0100] Alternatively, as in Embodiment 1 and its Variant 1, when the same bias voltages (gate bias voltage and drain bias voltage) are supplied to peak amplifier 12 and peak amplifier 14, the saturation power of peak amplifier 12 is equal to the saturation power of peak amplifier 14. Thus, amplifiers with the same structure (e.g., semiconductor chips) can be used as peak amplifier 12 and peak amplifier 14. It should be noted that the equality (or approximate equality) of the saturation power of peak amplifier 12 and the saturation power of peak amplifier 14 allows for differences within the manufacturing error range. For example, the difference between the saturation power of peak amplifier 12 and the saturation power of peak amplifier 14 can be set to 1 dBm or less, and can be set to 0.5 dBm or less. It should be noted that the saturation power may not be the power at which the output power is completely saturated. For example, the saturation power can also be reduced by about 1 dBm to 3 dBm from the power at which the output power is completely saturated. When comparing the saturation powers of different amplifiers, the power obtained by reducing a certain value from the power at which the output power is completely saturated can also be used for comparison.

[0101] [Embodiment 2]

[0102] Figure 6 is a top view of the semiconductor device in Embodiment 2. As Figure 6 shown, in the semiconductor device 104 of Embodiment 2, transistor Q2 is larger than transistor Q3. That is, transistor Q2 is larger than transistor Q3 (e.g., larger gate width, larger saturation power when the gate bias voltage and drain bias voltage are the same).

[0103] Figure 7 is a schematic diagram showing the probability with respect to Pout, the Pout of each amplifier with respect to Pin, the gain of each amplifier with respect to Pin, and the overall gain with respect to Pin in Embodiment 2 and Embodiment 1. The dashed line represents Embodiment 1, and the solid line represents Embodiment 2.

[0104] Let the saturation powers of transistor Q2 and transistor Q3 when the same gate bias voltage and drain bias voltage are supplied to transistor Q2 and transistor Q3 be Ps2 and Ps3 (in W), respectively. At this time, let the ratio Ps2 / Ps3 of Ps2 (in W) with respect to Ps3 be approximately equal to the ratio A2 / A3. At this time, when the input power Pin is greater than the power P1, the gain of peak amplifier 12 in Embodiment 2 and Embodiment 1 is approximately the same. The peak amplifier 12 of Embodiment 1 saturates at a power smaller than power P2 ( Figure 3 power P2a), while the peak amplifier 12 of Embodiment 2 saturates at power P2 ( Figure 3Before the power P2b), it was not saturated. Therefore, the gain of the peak amplifier 12 does not decrease before reaching the power P2. Near the power P2, before reaching an input power Pin larger than that in Embodiment 1, the overall gain of Embodiment 2 does not decrease.

[0105] When the input power Pin is greater than the power P2, the gain of the peak amplifier 14 is substantially the same in Embodiment 2 and Embodiment 1. The peak amplifier 14 of Embodiment 1 saturates at a power greater than the power P3, while the peak amplifier 14 of Embodiment 2 saturates at the power P3. Therefore, the gain of the peak amplifier 14 decreases at a power P3 smaller than that in Embodiment 1. Near the power P3, the overall gain of Embodiment 2 is less than the overall gain of Embodiment 1.

[0106] In Embodiment 2, when the same bias voltages (gate bias voltage and drain bias voltage) are supplied to the peak amplifier 12 and the peak amplifier 14, the saturation power of the peak amplifier 12 is made greater than the saturation power of the peak amplifier 14. Thereby, near P2 where the probability of the modulation wave is high, the overall gain is greater than that in Embodiment 1. Therefore, compared with Embodiment 1, the gain of the modulation wave can be increased, and the characteristics can be further improved.

[0107] From the viewpoint of increasing the gain of the modulation wave, the saturation power Ps2 (denoted by W) of the peak amplifier 12 with respect to the saturation power Ps3 (denoted by W) of the peak amplifier 14 can be set to 1.2 times or more, can be set to 1.5 times or more, can be set to 2 times or more. When the saturation power Ps3 of the peak amplifier 14 is too small, the gain decreases when the input power Pin is large. From this viewpoint, the saturation power Ps2 with respect to the saturation power Ps3 can be set to 10 times or less, can be set to 5 times or less. The ratio of the saturation powers Ps2 / Ps3 can be set to 0.5 times or more and 2 times or less of the distribution ratio A2 / A3 of the distributor 16, can be set to 0.8 times or more and 1.25 times or less of the distribution ratio A2 / A3 of the distributor 16.

[0108] The three-way Doherty amplifier circuit has been described as an example, but in the case of an N-way Doherty amplifier circuit, N - 1 peak amplifiers can be provided. In Figure 4 it has been described that when the same gate bias voltage and drain bias voltage are supplied to the main amplifier 10, the peak amplifier 12, and the peak amplifier 14, the saturation powers of the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 are the same, but the saturation powers of the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 can also be different.

[0109] It should be considered that the embodiments disclosed herein are illustrative in all respects and not restrictive. The scope of the present disclosure is not shown by the above meanings, but is shown by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Claims

1. A Doherty amplifier circuit, comprising: a distributor, which distributes an input signal into a first signal, a second signal and a third signal, and distributes power of the second signal to be greater than power of the third signal; a main amplifier, amplifying the first signal and outputting the amplified signal as a fourth signal; a first peak amplifier, amplifying the second signal, and outputting the amplified signal as a fifth signal; a second peak amplifier, amplifying the third signal, and outputting the amplified signal as a sixth signal; as well as a synthesizer that synthesizes the fourth signal, the fifth signal, and the sixth signal, and outputs the synthesized signal as an output signal to an output terminal, An input power of the input signal for turning on the first peak amplifier is less than an input power for turning on the second peak amplifier.

2. The Doherty amplifier circuit according to claim 1, wherein: When the main amplifier and the first peak amplifier are operating and the second peak amplifier is not operating, A first distance between the first position and the second position is shorter than a second distance, Among them, the first position is the position on the Smith chart of the impedance at the center frequency of the operating frequency band when looking from the first peak amplifier to the synthesizer, the second position is the position on the Smith chart of the impedance at the center frequency when looking from the first peak amplifier to the synthesizer where the gain of the first peak amplifier becomes maximum, and the second distance is the distance between the position on the Smith chart of the impedance at the center frequency when looking from the main amplifier to the synthesizer and the position on the Smith chart of the impedance at the center frequency when looking from the main amplifier to the synthesizer where the gain of the main amplifier becomes maximum.

3. The Doherty amplifier circuit according to claim 2, wherein: The first position on the Smith chart is located within a circle having the second position as the center and a distance between the second position and a third position as the diameter, wherein the third position is a position on the Smith chart of the impedance at the center frequency when looking from the first peak amplifier toward the synthesizer at which the efficiency of the first peak amplifier becomes maximum.

4. The Doherty amplifier circuit according to claim 2 or 3, wherein: When the main amplifier, the first peak amplifier and the second peak amplifier are operating, a third distance between a fourth position and the second position is less than or equal to the first distance, wherein the fourth position is a position on the Smith chart of the impedance at the center frequency when looking from the first peak amplifier toward the synthesizer.

5. The Doherty amplifier circuit according to any one of claims 1 to 3, wherein: When the same bias voltage is supplied to the first peak amplifier and the second peak amplifier, the saturation power of the first peak amplifier is greater than the saturation power of the second peak amplifier.

6. The Doherty amplifier circuit according to any one of claims 1 to 3, wherein: When the same bias voltage is supplied to the first peak amplifier and the second peak amplifier, the saturation power of the first peak amplifier is equal to the saturation power of the second peak amplifier.

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