Rail-to-rail input stage circuit for a constant transconductance operational amplifier and method of operation thereof

Abstract

The application belongs to the technical field of integrated circuits, and discloses a rail-to-rail input stage circuit for a constant transconductance operational amplifier and a working method thereof; wherein the rail-to-rail input stage circuit for the constant transconductance operational amplifier comprises a double-source follower circuit, a complementary differential pair circuit and a tail current source; wherein the double-source follower circuit comprises PMOS tubes M5, M6, M9 and M10 and NMOS tubes M7, M8, M11 and M12, the PMOS tubes M5 and M6 and the NMOS tubes M7 and M8 are used as a double-source follower; the complementary differential pair circuit comprises an NMOS differential pair composed of NMOS tubes M1 and M2 and a PMOS differential pair composed of PMOS tubes M3 and M4, the gates of the NMOS differential pair and the PMOS differential pair are respectively connected to the output end of the double-source follower. The technical scheme disclosed by the application has the advantages of relatively simple structure, good transconductance stability and high efficiency.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to a rail-to-rail input stage circuit for a constant transconductance operational amplifier and its operating method. Background Technology

[0002] In modern electronic systems, operational amplifiers are widely used in signal processing, data conversion, and amplification. Applications such as wide-input single-ended to differential conversion and analog input drivers require the operational amplifier's input stage to maintain constant transconductance across the rail-to-rail common-mode input range to ensure signal stability and gain consistency. However, existing rail-to-rail op-amp input stage technologies still have many limitations, restricting their performance in practical applications.

[0003] Currently, traditional rail-to-rail operational amplifier input stages typically employ a parallel NMOS and PMOS differential pair structure. While this structure can achieve a large common-mode input range, its transconductance fluctuates significantly with changes in common-mode voltage, leading to signal distortion and affecting overall circuit performance. Furthermore, existing transconductance stability optimization techniques, although able to alleviate this problem to some extent, still suffer from drawbacks such as complex structure, high process requirements, and low transconductance efficiency. For example, while a circuit structure using a triple current mirror technique can compensate for transconductance near the power rail, its circuit design is complex and requires extremely high accuracy in the compensation current, increasing design and manufacturing difficulty. While level-shifting techniques using single-source followers can adjust the input level, the differential pairs in the input stage need to operate alternately, which not only reduces transconductance efficiency but also increases chip area requirements. Terminology explanation: NMOS stands for N-channel metal-oxide-semiconductor field-effect transistor; PMOS stands for P-channel metal-oxide-semiconductor field-effect transistor.

[0004] In summary, existing technologies still have some shortcomings, and there is an urgent need to develop an operational amplifier input stage structure that can achieve constant transconductance within the rail-to-rail input range without increasing circuit complexity and chip area, in order to solve the technical problems of large transconductance fluctuations, complex design, and low transconductance efficiency in existing technical solutions. Summary of the Invention

[0005] The purpose of this invention is to provide a rail-to-rail input stage circuit for a constant transconductance operational amplifier and its operating method, thereby solving one or more of the aforementioned technical problems. Specifically, the technical solution disclosed in this invention is a rail-to-rail input stage circuit with a simple structure, good transconductance stability, and high efficiency, and has broad application prospects.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] This invention provides a rail-to-rail input stage circuit for a constant transconductance operational amplifier, comprising: a dual-source follower circuit, a complementary differential pair circuit, and a tail current source; wherein,

[0008] The dual-source follower circuit includes PMOS transistors M5, M6, M9, and M10, and NMOS transistors M7, M8, M11, and M12; wherein, PMOS transistors M5 and M6 and NMOS transistors M7 and M8 are used as dual-source followers; PMOS transistors M9 and M10 and NMOS transistors M11 and M12 are always turned on, used as current source loads to provide bias for the dual-source follower and to adjust the common-mode voltage of the input complementary differential pair circuit;

[0009] The complementary differential pair circuit includes an NMOS differential pair composed of NMOS transistors M1 and M2 and a PMOS differential pair composed of PMOS transistors M3 and M4; wherein the gates of the NMOS differential pair and the PMOS differential pair are respectively connected to the output terminal of the dual-source follower.

[0010] The tail current source includes tail current sources M13 and M14; wherein, the sources of NMOS transistors M1 and M2 are connected to the drain of tail current source M14, the sources of PMOS transistors M3 and M4 are connected to the drain of tail current source M13, the gates of tail current sources M13 and M14 are both used to connect to the bias circuit, the source of tail current source M13 is used to connect to the power supply terminal, and the source of tail current source M14 is used to connect to the ground terminal.

[0011] A further improvement of the present invention is that,

[0012] In the dual-source follower circuit, the gates of PMOS transistors M5 and M6 and NMOS transistors M7 and M8 are used to receive the common-mode voltage input signal. The source of PMOS transistor M5 is connected to the output node b, the source of PMOS transistor M6 is connected to the output node d, the source of NMOS transistor M7 is connected to the output node a, and the source of NMOS transistor M8 is connected to the output node c.

[0013] A further improvement of the present invention is that,

[0014] In the dual-source follower circuit, the drain of PMOS transistor M9 is connected to output node b, the drain of PMOS transistor M10 is connected to output node d, the drain of NMOS transistor M11 is connected to output node a, and the drain of NMOS transistor M12 is connected to output node c. The gates of PMOS transistors M9 and M10 and NMOS transistors M11 and M12 are all used to connect to the bias circuit. The sources of PMOS transistors M9 and M10 are used to connect to the power supply terminal, and the sources of NMOS transistors M11 and M12 are used to connect to the ground terminal.

[0015] A further improvement of the present invention is that,

[0016] In the complementary differential pair circuit, the gate of NMOS transistor M1 is connected to output node b, the gate of NMOS transistor M2 is connected to output node d, the gate of PMOS transistor M3 is connected to output node a, and the gate of PMOS transistor M4 is connected to output node c; the drain of NMOS transistor M1 is connected to output node N1, the drain of NMOS transistor M2 is connected to output node N2, the drain of PMOS transistor M3 is connected to output node P1, and the drain of PMOS transistor M4 is connected to output node P2.

[0017] A further improvement of the present invention is that,

[0018] It also includes: a bias circuit; the bias circuit is connected to the gates of the tail current sources M13 and M14, and is used to maintain the tail current of the NMOS differential pair and the PMOS differential pair constant by using a certain bias.

[0019] The present invention provides a method for operating a rail-to-rail input stage circuit for a constant transconductance operational amplifier, comprising the following steps:

[0020] Input common-mode voltage data into the dual-source follower circuit, perform level shifting processing, and output the processed common-mode voltage data;

[0021] The processed common-mode voltage data is input to the complementary differential pair circuit to ensure that the complementary differential pair operates in the saturation region in a voltage range close to the power rail.

[0022] A further improvement of the present invention is that the NMOS differential pair and the PMOS differential pair are always on.

[0023] A further improvement of this invention is that, during the constant conduction process of the NMOS differential pair and the PMOS differential pair,

[0024] when V DD -(| V GS3,4 |+| V ov13 |)< V in <V DD , V in near V DD When PMOS transistors M5 and M6 are turned off, PMOS transistors M9 and M10 are turned on, and NMOS transistors M1 and M2 are turned on. NMOS transistors M7 and M8 are normally turned on, and the gate-source voltages of NMOS transistors M7 and M8 are controlled to shift the input common-mode voltage, and PMOS transistors M3 and M4 are turned on, ultimately achieving simultaneous conduction of the NMOS differential pair and the PMOS differential pair; where, V DD Indicates the power supply voltage. V in Indicates the common-mode voltage input signal. V GS3,4 This represents the gate-source voltage of PMOS transistors M3 and M4. V ov13 This represents the overdrive voltage of the tail current source M13.

[0025] A further improvement of this invention is that, during the constant conduction process of the NMOS differential pair and the PMOS differential pair,

[0026] when V SS < V in < V GS1,2 + V ov14 , V in near V SS When PMOS transistors M5 and M6 are normally turned on, the gate-source voltages of PMOS transistors M5 and M6 are controlled to shift the input common-mode voltage, and NMOS transistors M1 and M2 are turned on; NMOS transistors M7 and M8 are turned off, NMOS transistors M11 and M12 are controlled to be turned on, and PMOS transistors M3 and M4 are turned on, ultimately achieving simultaneous conduction of the NMOS differential pair and the PMOS differential pair; where, V SS Indicates the grounding terminal voltage. V GS1,2 This represents the gate-source voltage of NMOS transistors M1 and M2. V ov14 This represents the overdrive voltage of the tail current source M14.

[0027] A further improvement of the present invention is that, during the operation of the rail-to-rail input stage circuit, the total transconductance of the input stage is equal to the sum of the transconductance of the NMOS differential pair and the transconductance of the PMOS differential pair.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] The rail-to-rail input stage circuit for a constant transconductance operational amplifier disclosed in this invention utilizes PMOS and NMOS differential pairs to form complementary differential pairs, aiming to expand the common-mode input range of the circuit. A dual-source follower circuit is used to adjust the common-mode input level, thereby adjusting the input stage transconductance. This design offers advantages such as relatively simple structure, good transconductance stability, and high efficiency, and has broad application prospects. Specifically, the circuit structure employing triple current mirror technology involves current matching control, resulting in a relatively complex circuit structure. This invention uses a dual-source follower circuit to reduce structural complexity. While the level shifting technology using a single-source follower can adjust the input level, its input stage differential pairs need to work alternately, which not only reduces transconductance efficiency but also increases chip area. This invention uses a dual-source follower circuit, allowing the complementary differential pairs to work simultaneously, improving transconductance efficiency and reducing chip area.

[0030] In this invention, a dual-source follower is introduced to control the input common-mode voltage of the complementary differential pair. The dual-source follower consists of PMOS transistors M5 and M6 and NMOS transistors M7 and M8, which work together to perform a level-shifting operation on the input common-mode voltage. For example, when the input common-mode voltage of the NMOS differential pair is low, the dual-source follower raises it to ensure that the NMOS differential pair operates in the saturation region. Conversely, when the input common-mode voltage of the PMOS differential pair is high, the dual-source follower lowers it, similarly ensuring that the PMOS differential pair operates stably.

[0031] In this invention, the voltage processed by the dual-source follower is transmitted to the gates (points a, b, c, d) of the complementary differential pair. In this way, no matter how the input common-mode voltage changes, the complementary differential pair can always operate stably in the saturation region, thereby ensuring the performance of the circuit.

[0032] In this invention, a stable bias circuit is used to maintain the constant tail current of the differential pair. Through precise control of the bias circuit, the tail current of the differential pair can be kept constant in the rail-to-rail input range, thereby enabling the input stage transconductance of the circuit (i.e. the sum of the transconductances of the complementary differential pairs) to also remain constant throughout the entire input range.

[0033] In summary, the improved techniques employed in this invention effectively eliminate transconductance ripple and significantly reduce signal distortion. Compared to traditional solutions, this invention eliminates the need for precise current matching between NMOS and PMOS differential pairs, simplifying circuit design. The cooperative operation of complementary differential pairs avoids efficiency losses caused by alternating operation, improving transconductance efficiency. Simultaneously, this design reduces chip area, significantly enhancing the circuit's transconductance efficiency and overall performance. In conclusion, this invention, through the introduction of complementary differential pairs, dual-source followers, and stable bias circuitry, achieves constant transconductance within the rail-to-rail input range, eliminating transconductance ripple, reducing signal distortion, and improving the circuit's transconductance efficiency and overall performance. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of a rail-to-rail input stage circuit for a constant transconductance operational amplifier in an embodiment of the present invention.

[0036] Figure 2 This is a schematic diagram of the input stage transconductance simulation verification results of the rail-to-rail input stage circuit for a constant transconductance operational amplifier according to an embodiment of the present invention;

[0037] Figure 3 This is a schematic diagram showing the comparison of the input-level transconductance curves of the method of the present invention and existing methods in an embodiment of the present invention. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention; obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0039] Based on the technical solutions disclosed in the embodiments of this invention, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this invention. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices.

[0040] Please see Figure 1 This invention provides a rail-to-rail input stage circuit for a constant transconductance operational amplifier, the implementation circuit of which includes: a dual-source follower circuit, a complementary differential pair circuit, and a tail current source; wherein,

[0041] The dual-source follower circuit includes PMOS transistors M5, M6, M9, and M10, and NMOS transistors M7, M8, M11, and M12. PMOS transistors M5 and M6, and NMOS transistors M7 and M8 serve as dual-source followers. The gates of PMOS transistors M5 and M6, and NMOS transistors M7 and M8, are used to receive the common-mode voltage input signal. The sources of PMOS transistors M5 and M6 are output to nodes b and d, respectively, and the sources of NMOS transistors M7 and M8 are output to nodes a and c, respectively. The output terminals (a, b, c, d) are connected to the gates of the complementary differential pair, respectively. Simultaneously, PMOS transistors M9 and M10, and NMOS transistors M11 and M12 are constantly conducting, serving both as the current source load providing bias for the dual-source follower and regulating the input common-mode voltage of the complementary differential pair transistors to ensure that both pairs operate in the saturation region close to the power rail voltage range. Furthermore, a stable bias circuit maintains the operating points of transistors M13 and M14, further stabilizing the tail current of the complementary differential pair transistors and thus maintaining constant transconductance. To further explain, the common-mode voltage is input from the gates of PMOS transistors M5 and M6 and NMOS transistors M7 and M8, and output from the sources; the output points of the dual-source follower are points a, b, c, and d. The drain of PMOS transistor M9 is connected to the source (node ​​b) of PMOS transistor M5, the drain of PMOS transistor M10 is connected to the source (node ​​d) of PMOS transistor M6, the drain of NMOS transistor M11 is connected to the source (node ​​a) of NMOS transistor M7, and the drain of NMOS transistor M12 is connected to the source (node ​​c) of NMOS transistor M8.

[0042] The complementary differential pair circuit includes an NMOS differential pair composed of NMOS transistors M1 and M2, and a PMOS differential pair composed of PMOS transistors M3 and M4. The sources of the NMOS differential pairs are connected to the drain of the tail current source M14, and their gates are connected to the shifted common-mode levels at nodes b and d, respectively. The sources of the PMOS differential pairs are connected to the drain of the tail current source M13, and their gates are connected to the shifted common-mode levels at nodes a and c, respectively. Further explanation: the sources of NMOS transistors M1 and M2 are connected to the drain of the tail current source M14, and the sources of PMOS transistors M3 and M4 are connected to the drain of the tail current source M13. The gates of NMOS transistors M1 and M2 are connected to points b and d, and the gates of PMOS transistors M3 and M4 are connected to points a and c. The drains of NMOS transistors M1 and M2 are connected to output nodes N1 and N2, respectively; the drains of PMOS transistors M3 and M4 are connected to output nodes P1 and P2, respectively, serving as the outputs of the complementary differential pair. M13 and M14 are tail current sources, and their gates are both connected to the bias circuit. The source of M13 is connected to the power supply, and the source of M14 is grounded. By using appropriate bias to maintain the tail current of the differential pair constant, the total transconductance of the input stage can be kept basically constant.

[0043] In the technical solution disclosed in this invention, PMOS differential pairs and NMOS differential pairs together constitute complementary differential pairs, thereby expanding the common-mode input range. This invention employs a dual-source follower (illustratively, composed of PMOS transistors M5 and M6 and NMOS transistors M7 and M8) to control the input common-mode voltage of the complementary differential pairs. The input common-mode voltage undergoes a level-shifting operation via the dual-source follower; that is, when the input common-mode voltage of the NMOS differential pair is low, it is raised through level shifting; when the input common-mode voltage of the PMOS differential pair is high, it is lowered through level shifting. Subsequently, the processed voltage is transmitted to the gates (points a, b, c, and d) of the complementary differential pairs, ensuring that the complementary differential pairs always operate stably in the saturation region within a voltage range close to the power rail. In this operating state, the input stage transconductance is the sum of the transconductances of the complementary differential pairs. By using a stable bias circuit to maintain a constant tail current of the differential pairs, constant transconductance can be achieved within the rail-to-rail input range. The technical means adopted in the embodiments of the present invention can effectively eliminate transconductance fluctuations, significantly reduce signal distortion, and eliminate the need for precise matching of the currents of NMOS differential pairs and PMOS differential pairs. In addition, the complementary differential pairs work together, avoiding the efficiency loss caused by alternating operation, resulting in high transconductance efficiency, reducing chip area and significantly improving the transconductance efficiency and overall performance of the circuit.

[0044] In one embodiment of the present invention, the specific working principle of the technical solution is as follows:

[0045] when V DD -(| VGS3,4 |+| V ov13 |)< V in < V DD ,Right now V in near V DD At this time, M5 and 6 are cut off. It is necessary to control the gate voltage of M9 and 10 to make them conduct, raising the potential at points b and d, thus turning on M1 and 2. In addition, M7 and 8 conduct normally, and their... V GS A potential shift is applied to the input common-mode voltage, lowering the potential at points a and c, thus turning on M3 and M4. This causes both the NMOS and PMOS differential pairs to conduct simultaneously. Explained... V DD Indicates the power supply voltage. V in Indicates the common-mode voltage input signal. V GS3,4 This represents the gate-source voltage of M3 and M4. V ov13 This indicates the overdrive voltage of M13.

[0046] when V SS < V in < V GS1,2 + V ov14 ,Right now V in near V SS At that time, M5 and M6 are normally conducting, controlling their... V GS The input common-mode voltage is shifted, raising the potential at points b and d, thus turning on M1 and 2. Meanwhile, M7 and 8 are turned off, controlling the gate voltage of M11 and 12 to turn them on, raising the potential at points a and c, thus turning on M3 and 4. Therefore, the NMOS differential pair and the PMOS differential pair are simultaneously turned on. Explained... V SS Indicates the grounding terminal voltage; V GS1,2 This represents the gate-source voltages of M1 and M2; V ov14 This indicates the overdrive voltage of M14.

[0047] when V GS1,2 + V ov14 <V in < V DD -(| V GS3,4 |+| V ov13 |), V in In the intermediate range, both the NMOS differential pair and the PMOS differential pair are turned on simultaneously.

[0048] therefore, V in At any range, the input differential pair transistors are always on, and the total transconductance of the input stage is equal to the sum of the transconductance of the NMOS differential pair and the transconductance of the PMOS differential pair.

[0049] The dual-source follower level shifting technique proposed in this invention eliminates the need for precise matching of the currents of the NMOS and PMOS differential pairs, and allows the NMOS and PMOS differential pairs to operate simultaneously across the entire power supply voltage range, improving transconductance efficiency and avoiding alternating operation errors. Not only is its operating principle simple and the number of components small, but compared to traditional input-stage transconductance optimization techniques, it achieves a smaller input-stage transconductance change rate with lower power consumption and smaller footprint.

[0050] The operating method of the circuit of the present invention includes the following steps:

[0051] Step 1: Use the gates of PMOS transistors M5 and M6 and NMOS transistors M7 and M8 to input common-mode voltage data. This common-mode voltage will serve as the basis input signal for subsequent circuit processing to control the input common-mode voltage of the complementary differential pair.

[0052] Step 2: After the common-mode voltage is input from the gates of M5 to M8, it undergoes level shifting through a dual-source follower (composed of PMOS transistors M5 and M6 and NMOS transistors M7 and M8). The common-mode voltage is output from the sources of M5 to M8, and the output points of the dual-source follower are points a, b, c, and d.

[0053] Step 3: The common-mode level, shifted by the dual-source follower, is connected to the complementary differential pair circuit. This ensures the complementary differential pair operates in the saturation region near the power rail voltage range, extending the common-mode input range. The complementary differential pair circuit consists of an NMOS differential pair composed of NMOS transistors M1 and M2, and a PMOS differential pair composed of PMOS transistors M3 and M4. The gates of NMOS transistors M1 and M2 are connected to points b and d, respectively, while the gates of PMOS transistors M3 and M4 are connected to points a and c, respectively. The complementary differential pairs work together, and the total transconductance of the input stage equals the sum of the transconductances of the NMOS and PMOS differential pairs. Using a stable bias circuit to maintain a constant tail current of the differential pair ensures a constant total transconductance across the rail-to-rail input range.

[0054] Step 4: The processed signals are output through the drain terminals (N1, N2, P1, P2) of NMOS transistors M1 and M2 and PMOS transistors M3 and M4, for subsequent signal processing or other circuit module applications.

[0055] The input stage area, power consumption, and transconductance rate of change in this invention and existing implementations are compared, as shown in Table 1. Table 1 presents simulation results obtained from circuit design using 0.18 µm CMOS (Complementary Metal Oxide Semiconductor) technology and a 1.8 V power supply.

[0056] Table 1. Comparison of parameters between the present invention and existing technologies

[0057]

[0058] Table 1 compares the performance indicators of static power consumption, input stage area, and transconductance rate of change in the present invention and the conventional structure. For the three parameters of area, power consumption, and transconductance rate of change, a figure of merit (FOM) is set to comprehensively evaluate the circuit performance. The FOM value is equal to the product of the input stage area, power consumption, and transconductance rate of change. The lower the FOM value, the better the overall performance of the circuit.

[0059] Compared to existing structures employing triple current mirroring and level shifting techniques, the circuit structure provided by this invention is simpler, achieving a smaller input stage transconductance change rate of only 0.95% with lower power consumption and footprint, and its FOM value is also significantly lower than similar designs. This invention simplifies the circuit structure, reduces chip area, lowers production costs, and meets the requirements of applications with stringent stability and anti-interference performance.

[0060] Please see Figure 2 All transistors in the constant transconductance rail-to-rail input stage circuit of the present invention are manufactured using the same process. Circuit simulation was performed using a 0.18 µm CMOS process at a power supply voltage of 1.8 V. The total transconductance curve of the input stage of the constant transconductance rail-to-rail input stage circuit of the present invention is shown below. Figure 2 As shown, the total transconductance of the input stage remains basically stable with the change of common-mode input voltage in the range of 0~1.8V.

[0061] Please see Figure 3 Based on 0.18 μm CMOS technology, the transconductance of the operational amplifier input stage is optimized using triple current mirror technology, level shifting technology, and the dual-source follower level shifting technology described in this paper. Figure 3As shown, the total transconductance of the operational amplifier input stage in traditional rail-to-rail implementations is halved when the common-mode input level is close to the power supply voltage and ground. The triple current mirror technique is affected by non-ideal factors in actual circuits, impacting current compensation. The level shifting technique using a single-source follower suffers from deviations due to the alternating operation of PMOS and NMOS differential pairs. This invention discloses a novel rail-to-rail input stage circuit for a constant transconductance operational amplifier, overcoming the poor transconductance stability of existing operational amplifier input stage transconductance optimization methods. Through input voltage shifting technology based on a dual-source follower, it not only reduces circuit complexity but also achieves a smaller input stage transconductance change rate with lower power consumption and area.

[0062] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A rail-to-rail input stage circuit for a constant transconductance operational amplifier, characterized in that, include: Dual-source follower circuit, complementary differential pair circuit, and tail current source; among them, The dual-source follower circuit includes PMOS transistors M5, M6, M9, and M10, and NMOS transistors M7, M8, M11, and M12; wherein, PMOS transistors M5 and M6 and NMOS transistors M7 and M8 are used as dual-source followers; PMOS transistors M9 and M10 and NMOS transistors M11 and M12 are always turned on, used as current source loads to provide bias for the dual-source follower and to adjust the common-mode voltage of the input complementary differential pair circuit; The complementary differential pair circuit includes an NMOS differential pair composed of NMOS transistors M1 and M2 and a PMOS differential pair composed of PMOS transistors M3 and M4; wherein the gates of the NMOS differential pair and the PMOS differential pair are respectively connected to the output terminal of the dual-source follower. The tail current source includes tail current sources M13 and M14; wherein, the sources of NMOS transistors M1 and M2 are connected to the drain of tail current source M14, the sources of PMOS transistors M3 and M4 are connected to the drain of tail current source M13, the gates of tail current sources M13 and M14 are both used to connect to the bias circuit, the source of tail current source M13 is used to connect to the power supply terminal, and the source of tail current source M14 is used to connect to the ground terminal. In the dual-source follower circuit, the gates of PMOS transistors M5 and M6 and NMOS transistors M7 and M8 are used to receive the common-mode voltage input signal. The source of PMOS transistor M5 is connected to the output node b, the source of PMOS transistor M6 is connected to the output node d, the source of NMOS transistor M7 is connected to the output node a, and the source of NMOS transistor M8 is connected to the output node c. In the dual-source follower circuit, the drain of PMOS transistor M9 is connected to output node b, the drain of PMOS transistor M10 is connected to output node d, the drain of NMOS transistor M11 is connected to output node a, and the drain of NMOS transistor M12 is connected to output node c; the gates of PMOS transistors M9 and M10 and NMOS transistors M11 and M12 are all used to connect to the bias circuit; the sources of PMOS transistors M9 and M10 are used to connect to the power supply terminal, and the sources of NMOS transistors M11 and M12 are used to connect to the ground terminal. In the complementary differential pair circuit, the gate of NMOS transistor M1 is connected to output node b, the gate of NMOS transistor M2 is connected to output node d, the gate of PMOS transistor M3 is connected to output node a, and the gate of PMOS transistor M4 is connected to output node c; the drain of NMOS transistor M1 is connected to output node N1, the drain of NMOS transistor M2 is connected to output node N2, the drain of PMOS transistor M3 is connected to output node P1, and the drain of PMOS transistor M4 is connected to output node P2. It also includes: a bias circuit; the bias circuit is connected to the gates of the tail current sources M13 and M14, and is used to maintain the tail current of the NMOS differential pair and the PMOS differential pair constant by using a certain bias.

2. A method of operating the rail-to-rail input stage circuit for a constant transconductance operational amplifier as described in claim 1, characterized in that, Includes the following steps: Input common-mode voltage data into the dual-source follower circuit, perform level shifting processing, and output the processed common-mode voltage data; The processed common-mode voltage data is input to the complementary differential pair circuit to ensure that the complementary differential pair operates in the saturation region in a voltage range close to the power rail.

3. The operating method of a rail-to-rail input stage circuit for a constant transconductance operational amplifier according to claim 2, characterized in that, The NMOS differential pair and the PMOS differential pair are always on.

4. The operating method of a rail-to-rail input stage circuit for a constant transconductance operational amplifier according to claim 3, characterized in that, During the constant conduction process of NMOS differential pairs and PMOS differential pairs when V DD -(| V GS3,4 |+| V ov13 |)< V in < V DD , V in near V DD When PMOS transistors M5 and M6 are turned off, PMOS transistors M9 and M10 are turned on, and NMOS transistors M1 and M2 are turned on. NMOS transistors M7 and M8 are normally turned on, and the gate-source voltages of NMOS transistors M7 and M8 are controlled to shift the input common-mode voltage, and PMOS transistors M3 and M4 are turned on, ultimately achieving simultaneous conduction of the NMOS differential pair and the PMOS differential pair; where, V DD Indicates the power supply voltage. V in Indicates the common-mode voltage input signal. V GS3,4 This represents the gate-source voltage of PMOS transistors M3 and M4. V ov13 This represents the overdrive voltage of the tail current source M13.

5. The operating method of a rail-to-rail input stage circuit for a constant transconductance operational amplifier according to claim 3, characterized in that, During the constant conduction process of NMOS differential pairs and PMOS differential pairs when V SS < V in < V GS1,2 + V ov14 , V in near V SS When PMOS transistors M5 and M6 are normally turned on, the gate-source voltages of PMOS transistors M5 and M6 are controlled to shift the input common-mode voltage, and NMOS transistors M1 and M2 are turned on; NMOS transistors M7 and M8 are turned off, NMOS transistors M11 and M12 are controlled to be turned on, and PMOS transistors M3 and M4 are turned on, ultimately achieving simultaneous conduction of the NMOS differential pair and the PMOS differential pair; where, V SS Indicates the grounding terminal voltage. V GS1,2 This represents the gate-source voltage of NMOS transistors M1 and M2. V ov14 This represents the overdrive voltage of the tail current source M14.

6. The method of operating a rail-to-rail input stage circuit for a constant transconductance operational amplifier according to claim 2, characterized in that, During the operation of the rail-to-rail input stage circuit, the total transconductance of the input stage is equal to the sum of the transconductance of the NMOS differential pair and the transconductance of the PMOS differential pair.

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