W-band reflection type attenuator

Abstract

The invention discloses a W-band reflective attenuator, which comprises a first single-ended attenuator, a second single-ended attenuator, an input inductor and an output inductor, and is characterized in that the first single-ended attenuator and the second single-ended attenuator form a differential structure; the first single-ended attenuator comprises a first orthogonal coupler, a first load network and a second load network; the second single-ended attenuator comprises a second orthogonal coupler, a third load network and a fourth load network; the first load network, the second load network, the third load network and the fourth load network comprise adjustable capacitors, series resistors and numerical control switch arrays, the first ends of the adjustable capacitors are connected with input signals, and the second ends of the adjustable capacitors are connected with the ground; the first end of the series resistor is connected with an input signal and is connected with the first end of the adjustable capacitor, and the second end of the series resistor is connected with the numerical control switch array; the numerical control switch array comprises a plurality of control switch branches which are connected in parallel. According to the invention, attenuation control of a plurality of gears can be realized through combined control of a plurality of parallel control switch branches.

Description

Technical Field

[0001] The present invention relates to the technical field of millimeter-wave transceivers, and in particular to a W-band reflective attenuator applicable to millimeter-wave transceivers. Background Art

[0002] Millimeter-wave gain control modules based on CMOS (Complementary Metal Oxide Semiconductor) technology are widely used in transceiver systems within this frequency band, such as amplitude control in phased array systems and self-interference cancellation technology in full-duplex systems. According to the angle of whether additional power supply is required, they can be divided into two types: active attenuators and passive attenuators. Passive attenuators have become a common solution for gain control in low-power applications in this frequency band due to their advantages such as zero DC power consumption and low loss.

[0003] When the operating frequency reaches the W-band (75 GHz - 110 GHz), traditional multi-bit cascaded switched passive attenuators have problems such as large insertion loss and decreased attenuation accuracy, and no longer meet the application requirements. Currently, the passive attenuator topologies for applications in this frequency band mainly include four types: distributed, differential Π-type, coupled line type, and reflective attenuators.

[0004] In the current design of W-band reflective attenuators, only a simple resistor model is used for theoretical analysis of amplitude attenuation, without considering the influence of parasitic capacitance introduced by the reflective load network on circuit performance, and lacking the modeling calculation of the output phase error index. At the operating frequency of the W-band, when switching different attenuation levels, the output phase of the attenuator will also change greatly. Due to the lack of appropriate phase compensation measures, the output relative phase error of this module is relatively large, which will introduce unnecessary phase fluctuations to the transceiver system, greatly limiting the performance and application scenarios of the reflective attenuator.

[0005] Therefore, how to reduce the output relative phase error of the W-band reflective attenuator and solve the problem of large output relative phase error. Summary of the Invention

[0006] The purpose of the present invention is to provide a W-band reflective attenuator to reduce the output relative phase error of the W-band reflective attenuator.

[0007] To achieve the above purpose, the present invention provides the following technical solutions:

[0008] On one aspect of the present invention, a W-band reflective attenuator is provided, which includes: a first single-ended attenuator, a second single-ended attenuator, an input inductor, and an output inductor. The input inductor is respectively connected to the input ends of the first single-ended attenuator and the second single-ended attenuator, the output inductor is respectively connected to the output ends of the first single-ended attenuator and the second single-ended attenuator, and the first single-ended attenuator and the second single-ended attenuator are constructed into a differential structure;

[0009] The first single-ended attenuator includes a first quadrature coupler, a first load network, and a second load network; the input end of the first quadrature coupler is connected to the input inductor, the through end of the first quadrature coupler is connected to the first load network, the coupled end of the first quadrature coupler is connected to the second load network, and the isolated end of the first quadrature coupler is connected to the output inductor;

[0010] The second single-ended attenuator includes a second quadrature coupler, a third load network, and a fourth load network; the input end of the second quadrature coupler is connected to the input inductor, the through end of the second quadrature coupler is connected to the third load network, the coupled end of the second quadrature coupler is connected to the fourth load network, and the isolated end of the second quadrature coupler is connected to the output inductor;

[0011] The first, second, third, and fourth load networks include an adjustable capacitor, a series resistor, and a numerically controlled switch array. The first end of the adjustable capacitor is connected to the input signal, and its second end is grounded; the first end of the series resistor is connected to the input signal and is connected to the first end of the adjustable capacitor, and the second end of the series resistor is connected to the numerically controlled switch array; the numerically controlled switch array includes multiple parallel control switch branches.

[0012] According to an embodiment of the present invention, each of the control switch branches includes an RC circuit and a switch S connected in series.

[0013] According to an embodiment of the present invention, each of the control switch branches includes a first and a second NMOS field-effect transistor connected in series.

[0014] According to an embodiment of the present invention, the multiple parallel control switch branches are combined to form a sub-control switch array corresponding to multiple attenuation levels.

[0015] The n attenuation levels correspond to the width ratios of the NMOS field-effect transistors used in different control switch branches from low to high, where the nth level is twice that of the (n - 1)th level.

[0016] According to an embodiment of the present invention, the drain of the first NMOS field-effect transistor is connected to the series resistor, the source is connected to the drain of the second NMOS field-effect transistor, and the source of the second NMOS field-effect transistor is grounded; the gates of the first and second field-effect transistors are connected.

[0017] According to an embodiment of the present invention, the first, second, third, and fourth load networks use the number of control switch branches in multiple parallel connections as the number of bits of the binary code of the digital control signal. When the bit in the digital control signal is at a high level, the switch of the control switch branch corresponding to the bit is closed; when the bit in the digital control signal is at a low level, the switch of the control switch branch corresponding to the bit is opened.

[0018] According to an embodiment of the present invention, the first, second, third, and fourth load networks further include a first switched-capacitor circuit connected in parallel with the multiple parallel control switch branches. The first switched-capacitor circuit includes a first capacitor and a first switch connected in series in sequence. The input end of the first capacitor is connected to the series resistor, the output end is connected to the input end of the first switch, and the output end of the first switch is grounded.

[0019] According to an embodiment of the present invention, the isolation ends of the first and second quadrature couplers are connected to a second switched-capacitor circuit. The second switched-capacitor circuit includes a second capacitor and a second switch connected in series in sequence. The input end of the second capacitor is connected to the isolation end, the output end of the second capacitor is connected to the input end of the second switch, and the output end of the second switch is grounded; alternatively, the isolation ends of the first and second quadrature couplers are connected to a variable inductor, and the variable inductor is grounded.

[0020] Advantageous Effects

[0021] The present invention provides a W-band reflective attenuator, which has the following advantageous effects compared with the prior art:

[0022] 1. By introducing a series resistor in the load network, better dB linear attenuation accuracy of the series resistor is achieved.

[0023] 2. By introducing a variable capacitor C p in the load network, the parasitic capacitance of each branch can be reduced, the contribution of the parasitic capacitance to the imaginary part of the port impedance can be reduced, and thus a smaller total equivalent capacitance C total can be obtained, so as to use C p for phase compensation, and the phase fluctuation caused by the parasitic capacitance can be further reduced.

[0024] 3. Different attenuation gears can be correspondingly formed by the horizontal combination of different numbers of control switch branches of the W-band reflective attenuator.

[0025] 4. The switch array implemented by the parallel NMOS transistor stacking technology, each parallel switch branch is composed of two NMOS transistors of the same size connected in series and the digital signals controlling the two NMOS transistors are the same, which can reduce the contribution of the parasitic capacitance to the imaginary part of the port impedance and further reduce the phase fluctuation caused by the parasitic capacitance. Description of the Drawings

[0026] The accompanying drawings described herein are used to provide a further understanding of the present invention and form a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0027] Figure 1 It is a schematic structural diagram of a W-band reflective attenuator in an embodiment of the present invention;

[0028] Figure 2 It is a schematic structural diagram of a single-ended attenuator in an embodiment of the present invention;

[0029] Figure 3 It is a circuit diagram of a W-band reflective attenuator in an embodiment of the present invention;

[0030] Figure 4 It is a schematic diagram of a quadrature coupler in an embodiment of the present invention;

[0031] Figure 5 It is an equivalent circuit schematic diagram of a quadrature coupler in an embodiment of the present invention;

[0032] Figure 6 It is an equivalent circuit schematic diagram of a load network in an embodiment of the present invention;

[0033] Figure 7 It is a circuit schematic diagram of a load network implemented by NMOS in an embodiment of the present invention;

[0034] Figure 8 It is a circuit schematic diagram of a load network for implementing multi-step attenuation by NMOS in an embodiment of the present invention;

[0035] Figure 9 It is a circuit schematic diagram of a load network of a parallel switched-capacitor circuit in an embodiment of the present invention;

[0036] Figure 10 It is a circuit schematic diagram of a single-ended attenuator connected to a switched-capacitor circuit in an embodiment of the present invention. Detailed Embodiments

[0037] In order to clearly describe the technical solutions in the embodiments of the present invention, in the embodiments of the present invention, terms such as "first" and "second" are used to distinguish identical or similar items with basically the same functions and effects. For example, the first threshold and the second threshold are only used to distinguish different thresholds and do not limit their sequence. Those skilled in the art can understand that terms such as "first" and "second" do not limit the quantity and execution order, and terms such as "first" and "second" do not necessarily mean different.

[0038] It should be noted that in the present invention, words such as "exemplary" or "for example" are used to represent examples, illustrations or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the present invention should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of words such as "exemplary" or "for example" is intended to present relevant concepts in a specific manner.

[0039] In the present invention, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the association relationship of associated objects and indicates that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone, where A and B may be singular or plural. The character " / " generally represents an "or" relationship between the front and rear associated objects. The following at least one (item) or its similar expression refers to any combination of these items, including any combination of single item (item) or plural items (items). For example, at least one (item) of a, b or c may represent: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b and c may be single or multiple.

[0040] Aiming at the problem of relatively large output relative phase error commonly existing in W-band reflective attenuators, the present invention proposes a solution from the aspect of design optimization of the reflective load network circuit structure. By introducing parasitic capacitance in the impedance network into theoretical analysis, a W-band reflective impedance network structure based on NMOS (N-Metal-Oxide-Semiconductor) field effect transistor stacking technology is proposed, effectively reducing the output relative phase error.

[0041] The reflective attenuator includes a quadrature coupler and a reflective load network, and realizes attenuation by using the impedance mismatch between the quadrature coupler and the reflective load network. The quadrature coupler includes two coplanarly coupled metal lines and uses top-layer and sub-top-layer metals to reduce the insertion loss of the quadrature coupler itself. The reflective load network includes an RC array and a switching NMOS field effect transistor, and changes the impedance of the load network port by closing and disconnecting the switch, thereby realizing output signal attenuation.

[0042] As Figure 1As shown, a schematic structural diagram of a W-band reflective attenuator is given. The W-band reflective attenuator includes: a first single-ended attenuator P, a second single-ended attenuator N, an input inductor Lin, and an output inductor Lout. The input inductor Lin is connected to the input ends of the first single-ended attenuator and the second single-ended attenuator. The output inductor Lout is connected to the output ends of the first single-ended attenuator and the second single-ended attenuator. The first single-ended attenuator P and the second single-ended attenuator N are constructed as a differential structure.

[0043] As Figure 2 shown, a schematic structural diagram of a single-ended attenuator is given. The single-ended attenuator includes a quadrature coupler and two load networks, namely load network 1 and load network 2. The input end ① of the quadrature coupler receives a radio frequency input signal input through the input inductor. The through end ② of the quadrature coupler is connected to the first end of load network 1, and the second end of load network 1 is grounded. The coupled end ③ of the quadrature coupler is connected to the first end of load network 2, and the second end of load network 2 is grounded. The isolated end ④ of the quadrature coupler is connected to the output inductor to output a radio frequency output signal.

[0044] The first single-ended attenuator P and the second single-ended attenuator N have the same structure. As Figure 3 shown, the first single-ended attenuator P includes a first quadrature coupler H1, a first load network F1, and a second load network F2. The input end P1 of the first quadrature coupler H1 is connected to the input inductor Lin. The through end P2 of the first quadrature coupler H1 is connected to the first end of the first load network F1, and the second end of the first load network F1 is grounded. The coupled end P3 of the first quadrature coupler H1 is connected to the first end of the second load network F2, and the second end of the second load network F2 is grounded. The isolated end P4 of the first quadrature coupler H1 is connected to the output inductor Lout.

[0045] The second single-ended attenuator N includes a second quadrature coupler H2, a third load network F3, and a fourth load network F4. The input end N1 of the second quadrature coupler H2 is connected to the input inductor Lin. The through end N2 of the second quadrature coupler H2 is connected to the first end of the third load network F3, and the second end of the third load network F3 is grounded. The coupled end N3 of the second quadrature coupler H2 is connected to the first end of the fourth load network F4, and the second end of the fourth load network F4 is grounded. The isolated end N4 of the second quadrature coupler H2 is connected to the output inductor Lout.

[0046] The input ends INP and INN of the input inductor Lin are used to input a radio frequency input signal. The output ends OUTP and OUTN of the output inductor Lout are used to output a radio frequency output signal.

[0047] As Figure 4As shown, a schematic diagram of the quadrature coupler is given. The first and second quadrature couplers include four ports: ① Input port, ② Through port, ③ Coupling port, and ④ Isolated port. When the quadrature coupler is implemented specifically, it is realized by using two coupled metal lines with the same shape on different planes, and the top layer and the sub-top layer metals can be used to reduce losses.

[0048] As Figure 5 shown, a schematic diagram of the equivalent circuit principle of the quadrature coupler based on the lumped model is given. In the equivalent circuit of the quadrature coupler made of two coupled metal lines with the same shape on different planes, it includes two mutually coupled first inductor L1 and second inductor L2, two coupling capacitors C M across the first and second inductors, and four capacitors C K from each end of the first and second inductors to the ground. By adjusting the capacitors C M , C K , the values of the first and second inductors L1 and L2, and the coupling coefficient k, when the isolated port ④ is connected to the matching load network at a specific operating frequency of the quadrature coupler, the output signals of the through port ② and the coupling port ③ are orthogonal to each other in phase.

[0049] As Figure 6 shown, a schematic diagram of the equivalent circuit structure of the load network is given. The load network includes an adjustable capacitor C p , a series resistor Rs, and a numerically controlled switch array. The first end of the adjustable capacitor C p is connected to the input signal, and its second end is grounded. The first end of the series resistor Rs is connected to the input signal and is connected to the first end of the adjustable capacitor C p , and the second end of the series resistor Rs is connected to the numerically controlled switch array. The numerically controlled switch array includes multiple parallel control switch branches, and each control switch branch includes an RC circuit and a switch S connected in series in sequence, and the switch S is grounded.

[0050] The RF input signal is connected to the load network from the Input end. First, it passes through the series resistor Rs. The value of the series resistor is Rs, which is less than the characteristic impedance of the quadrature coupler. The smaller the attenuation step value, the smaller the value of the series resistor Rs. The preferred value range is 5 - 100 ohms. For example, if the characteristic impedance is 50 ohms, the value range of the series resistor Rs is 5 - 50 ohms. In some preferred embodiments, the value of the series resistor Rs is 25 ohms.

[0051] The introduction of the series resistance Rs is to achieve dB (decibel) linear attenuation by direct digital signal control; then it enters the digital control switch array composed of multiple parallel switch branches. In different switch branches, different degrees of attenuation are achieved by adjusting the value of the resistor R in the RC circuit, and the output relative phase error in different attenuation states is reduced by adjusting the value of the capacitor C. For example, in the first switch branch, there is a first RC circuit formed by the parallel connection of a first resistor R1 and a first capacitor C1. The first RC circuit is connected to the first end of the first control switch S1, and the second end of the first control switch S1 is grounded.

[0052] The phase shift φ can be regarded as the delay τ introduced by the circuit in the time domain, and the two satisfy φ = 2πfgτ. For the RC network in the digital control switch array, the delay τ is also related to the resistors and capacitors connected to the nodes and satisfies τ = RC. In theory, by reasonably adjusting the values of R and C in the parallel switch branches at different gears, their product can be maintained as a constant value. For a reflective attenuator, the real part of the port impedance of the load network should be the maximum value in the reference state. As each parallel switch branch is turned on in sequence, the real part of the port impedance gradually decreases and approaches the characteristic impedance of the quadrature coupler. R(a) represents the real part of the port impedance in the attenuation state a, and a represents the attenuation state. Therefore, R(a) should be a monotonically decreasing function of a, that is, dR / da < 0. To reduce the relative change amount Δτ of τ(a) in the attenuation interval, C(a) represents the capacitance value corresponding to the imaginary part of the port impedance in the attenuation state a, and it should be such that C(a) increases proportionally as R(a) decreases.

[0053] As Figure 6 shown, regardless of whether the switch S 1 ~S 5 is turned on or not, the capacitors C 1 ~C 5 always contribute the same to the imaginary part of the port, and they can be regarded as a total equivalent capacitor C total , where the total equivalent capacitor C total = C 1 + C 2 + C 3 + C 4 + C 5 , and the total equivalent capacitor C total is on the order of fF, and the preferred value range is 5 - 100 fF. In some preferred embodiments, the total equivalent capacitor C total is 20 fF. Therefore, a tunable capacitor C p to ground is connected in parallel at the input port (Input). Similarly, the tunable capacitor C p is also on the order of fF. Let C(a) = C total + C p (a). Then C p(a) increases as R(a) decreases, which will reduce the delay difference between different attenuation levels and ultimately achieve compensation for the output relative phase error.

[0054] Taking R(1):R(2):R(4):R(8):R(16) = 16:8:4:2:1 as an example, the following should be satisfied

[0055] C(1):C(2):C(4):C(8):C(16) = 1:2:4:8:16. Then, C p (1) can be set to 0, C(1) = C total ;

[0056] C p (2) = C total , C(2) = 2C total And so on, the capacitance values required for each attenuation level can be obtained.

[0057] As Figure 7 shown, a specific implementation of the load network is given. The load network is implemented based on the NMOS field-effect transistor stacking structure, that is, NMOS field-effect transistors are used to replace the RC circuits and switches S in each branch of Figure 6 respectively. Considering that whether the MOS switch is closed or open, it can be represented by a parallel model of the on-resistance and parasitic capacitance. When the switch is closed, it can be regarded as a small resistor in parallel with the parasitic capacitance. When the switch is open, it can be regarded as a large resistor in parallel with the parasitic capacitance. The closing and opening of the switch have little impact on the parasitic capacitance, and the imaginary part change of the port impedance can be reduced well. Therefore, Figure 7 in the shown implementation, two MOS switches with the same size are used to implement the RC circuit and the switch S respectively, forming a parallel switch branch. On the one hand, the change of the port impedance of each branch is still consistent with that of a single MOS switch. On the other hand, the stacking of MOS switches makes the parasitic capacitances in series, which can reduce the parasitic capacitance of each branch and the contribution of the parasitic capacitance to the imaginary part of the port impedance, and thus a smaller C total can be obtained to use the variable capacitor C p for phase compensation, and the phase fluctuation caused by the parasitic capacitance can be further reduced.

[0058] The variable capacitor can be a fixed capacitor, a thin-film capacitor or an electrolytic capacitor. The adjustment methods of the variable capacitor include using a manual regulator, a potentiometer, a magnetic core or a microswitch to change the distance between the electrodes, thereby changing the capacitance value.

[0059] The adjustment of the capacitance value of the variable capacitor can also be achieved electronically by a microprocessor. The variable capacitor is an adaptive capacitance module, which realizes the charging and discharging of the capacitor by a self - turning - off device during the alternating - current periodic operation. The energy stored in the capacitor is proportional to the square of the voltage applied across its terminals. By changing the terminal voltage of the variable capacitor, the energy stored in the capacitor can be changed. During the positive half - cycle of the alternating current, the first self - turning - off device is used to control the charging of the variable capacitor; during the negative half - cycle of the alternating current, the second self - turning - off device is used to control the charging of the variable capacitor.

[0060] In Figure 3 the structures of the first to fourth load networks F1 - F4 shown are the same, and they all adopt the load - network structure shown in Figure 7 to form a differential structure and the control signals of each load network are always the same. The radio - frequency input signal is connected to the load network shown in Figure 7 through the Input terminal. On the one hand, it is grounded through the variable capacitor C p . On the other hand, it first passes through the series resistor Rs and then enters the numerically - controlled switch array composed of stacked NMOS field - effect transistors. The digital control signal is a five - bit binary code CW[0]~CW[4] in total. The five - bit binary code can control Figure 7 the closing and opening of the NMOS field - effect transistors serving as switches in the 5 - way parallel switch branches shown. When the control signal is at a high level, the switch closes; when the control signal is at a low level, the switch opens. The control switch S is an NMOS field - effect transistor. When CW[0]~CW[4] are all at a low level, all control switches S are open, and the port impedance of the load network is high - impedance (open - circuit), corresponding to the reference attenuation state of the attenuator; when CW[0]~CW[4] are all at a high level, all control switches S are closed, and the port impedance of the load network is close to the characteristic impedance of the quadrature coupler, corresponding to the maximum attenuation state of the attenuator. The control switch S is implemented by an NMOS field - effect transistor.

[0061] By gating different switch branches through the binary code, the binary digital code can directly control the attenuator to achieve dB - linear attenuation. Furthermore, as shown in Table 1, the corresponding relationship between the control code and the theoretical attenuation of the attenuator of the present invention is given.

[0062] Table 1: Corresponding relationship table between the control code and the theoretical attenuation of the attenuator

[0063]

[0064]

[0065] Looking from the input end of the load network, the W-band reflective attenuator of the present invention first has a series resistor for achieving better dB linear attenuation accuracy, and then a switch array implemented by the parallel NMOS transistor stacking technology. Each parallel switch branch is composed of two NMOS transistors of the same size connected in series, and the digital signals controlling the two NMOS transistors are the same. By laterally combining different numbers of switch branches, different attenuation levels can be correspondingly formed. For example, taking the setting of 5 levels as an example, from low to high, they are 0.5 dB, 1 dB, 2 dB, 4 dB, and 8 dB. To achieve this change in attenuation levels, it should be ensured that for different attenuation levels, the NMOS transistor sizes in different parallel switch branches corresponding to that level are the same, but the numbers used are different. The ratio of the number of NMOS transistors used in the arrays composed of different switch branches corresponding to the attenuation levels from low to high should be 1:2:4:8:16. Since the parasitic capacitances introduced by the NMOS transistors used in different branches are of the same order of magnitude, the change in the imaginary part of the port impedance of the load network at different attenuation levels is reduced, thereby reducing the output relative phase error of the attenuator.

[0066] As Figure 8 shown, the equivalent circuit diagrams of the load network corresponding to different attenuation levels are given. By combining the different parallel switch branches shown in Figure 7 , different attenuation levels can be formed. For example Figure 8 the different attenuation levels corresponding to 0.5 dB, 1 dB, 2 dB, 4 dB, and 8 dB shown in

[0067] For the attenuation level of 0.5 dB, two serially connected NMOS field-effect transistors M0 are used as the parallel switch branch. The source of the first NMOS field-effect transistor of the parallel switch branch is connected to the drain of the second NMOS field-effect transistor. The gates of the two NMOS field-effect transistors M0 are interconnected as the control bit, and the binary control code CW[0] is used to control the on / off of the parallel branch at this level.

[0068] For the attenuation level of 8 dB, a sub-array is formed by combining 16 parallel branches (16 - 31) horizontally. The source of the first NMOS field-effect transistor of the switch branch is connected to the drain of the second NMOS field-effect transistor. After connecting all the gates of each row in the sub-array and then connecting the gates of each row, the binary control code CW[4] is used to control the on / off of the parallel branch at this level.

[0069] Figure 8The equivalent circuit schematic diagram of the gear division is only for illustrative purposes. In specific implementations, the required attenuation gears can be selected from Table 1 to combine the parallel branches by oneself to form the corresponding load network circuit. On the Cadence platform, the circuit and layout design simulations were carried out based on the 45nm SOI CMOS process. In the frequency band of 89 - 99GHz, the output relative phase error is less than 10°; at the center frequency point (94GHz), the output relative phase error is less than 6°.

[0070] As Figure 9 shown, as a further improvement, a parallel branch can be added to the digital control switch array in series with the series resistor Rs in the load network. The added parallel branch includes a capacitor and a switch connected in sequence. The additional switch capacitor is used to adjust the imaginary part of the port impedance of the load network. By connecting and disconnecting the switch capacitor branch, the phase compensation between different attenuation states can be realized, and the output relative phase error can be reduced.

[0071] As Figure 10 shown, as a further improvement, at the output end of the attenuator, that is, at the isolation end of the quadrature coupler, a phase compensation measure is added, and a switch capacitor branch or a variable inductor branch is added. A capacitor and a switch are connected in sequence from the isolation end, and the switch is grounded. By changing the capacitive reactance or inductance value, the output relative phase error can be reduced.

[0072] Applying the W-band reflective attenuator of the present invention can reduce the output relative phase error of the attenuator, that is, reduce the difference between the maximum output phase and the minimum output phase.

[0073] Utilize the impedance mismatch between the quadrature coupler and the load network to control the intensity of the output signal and thus achieve attenuation. However, during the attenuation gear switching process, due to the parasitic capacitance of the MOS switch tube, the closing and opening of the switch will not only affect the real part of the port impedance of the load network, but also affect the imaginary part of the port impedance, resulting in a relative phase error of the output signal between different attenuation states of the attenuator at the same operating frequency. Therefore, in the mathematical modeling process of the reflective attenuator, not only the real part of the port impedance of the load network, that is, the amplitude attenuation performance of the attenuator, should be considered. When considering the output relative phase fluctuation index, the change of the imaginary part of the port impedance should also be introduced as an important parameter into the model. Based on the above considerations, the W-band reflective attenuator of the present invention introduces parasitic capacitance into the mathematical model, proposes a scheme for reducing the output relative phase error applied to the W-band reflective attenuator, and uses MOS transistors to implement the load network.

[0074] Although the present invention has been described in connection with the various embodiments, however, in the process of implementing the claimed invention, those skilled in the art can understand and realize other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the like. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions recited in the specification. Certain measures are recited in mutually different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0075] Although the present invention has been described in connection with specific features and their embodiments, it is obvious that various modifications and combinations can be made thereto without departing from the spirit and scope of the present invention. Accordingly, the present specification and the drawings are merely illustrative of the present invention and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the present invention. Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the present invention and its equivalent technologies, the present invention is also intended to include these changes and modifications.

Claims

1. A W-band reflective attenuator, characterized in that: include: A first single-ended attenuator, a second single-ended attenuator, an input inductor, and an output inductor, wherein the input inductor is connected to the input ends of the first single-ended attenuator and the second single-ended attenuator respectively, the output inductor is connected to the output ends of the first single-ended attenuator and the second single-ended attenuator respectively, and the first single-ended attenuator and the second single-ended attenuator are constructed as a differential structure; The first single-ended attenuator includes a first orthogonal coupler, a first load network, and a second load network; the input end of the first orthogonal coupler is connected to the input inductor, the through end of the first orthogonal coupler is connected to the first load network, the coupling end of the first orthogonal coupler is connected to the second load network, and the isolation end of the first orthogonal coupler is connected to the output inductor; The second single-ended attenuator includes a second orthogonal coupler, a third load network, and a fourth load network; the input end of the second orthogonal coupler is connected to the input inductor, the through end of the second orthogonal coupler is connected to the third load network, the coupling end of the second orthogonal coupler is connected to the fourth load network, and the isolation end of the second orthogonal coupler is connected to the output inductor; The first, second, third and fourth load networks include an adjustable capacitor, a series resistor and a digitally controlled switch array. The first end of the adjustable capacitor is connected to the input signal, and the second end thereof is grounded. The first end of the series resistor is connected to the input signal and is connected to the first end of the adjustable capacitor, and the second end of the series resistor is connected to the digitally controlled switch array. The digitally controlled switch array includes multiple parallel control switch branches.

2. The W-band reflection attenuator according to claim 1, characterized in that: Each of the control switch branches includes an RC circuit and a switch S connected in series.

3. The W-band reflective attenuator according to claim 1, characterized in that: Each of the control switch branches includes a first NMOS field effect transistor and a second NMOS field effect transistor connected in series.

4. The W-band reflection attenuator according to claim 3, characterized in that: The multiple parallel control switch branches are combined to form a sub-control switch array corresponding to n attenuation gears, where n is a natural number greater than or equal to 3.

5. The W-band reflection attenuator according to claim 4, characterized in that: The n attenuation gears correspond from low to high to the width ratios of the NMOS field effect tubes used in different control switch branches, wherein the nth gear is twice the n-1th gear.

6. The W-band reflection attenuator according to claim 3 or 5, characterized in that: The drain of the first NMOS field effect tube is connected to the series resistor, the source is connected to the drain of the second NMOS field effect tube, the source of the second NMOS field effect tube is grounded; the gates of the first and second field effect tubes are connected.

7. The W-band reflection attenuator according to claim 1, characterized in that: The first, second, third and fourth load networks use the number of control switch branches connected in parallel as the number of bits of the binary code of the digital control signal. When a bit in the digital control signal is at a high level, the control switch branch corresponding to the bit is closed. When a bit in the digital control signal is at a low level, the control switch branch switch corresponding to the bit is disconnected.

8. The W-band reflective attenuator according to claim 4, characterized in that: The first, second, third and fourth load networks use the number of sub-control switch arrays corresponding to multiple attenuation gears as the number of bits of the binary code of the digital control signal. When the bit in the digital control signal is at a high level, the control switch branch switch in the sub-control switch array corresponding to the bit is closed; when the bit in the digital control signal is at a low level, the control switch branch switch in the sub-control switch array corresponding to the bit is opened.

9. The W-band reflection attenuator according to claim 1, characterized in that: The first, second, third and fourth load networks also include a first switch capacitor circuit connected in parallel with the multi-way parallel control switch branches, the first switch capacitor circuit includes a first capacitor and a first switch connected in series in sequence, the input end of the first capacitor is connected to the series resistor, the output end is connected to the input end of the first switch, and the output end of the first switch is grounded.

10. The W-band reflection attenuator according to claim 1, characterized in that: The isolation ends of the first and second orthogonal couplers are connected to a second switch capacitor circuit, which includes a second capacitor and a second switch connected in series, an input end of the second capacitor is connected to the isolation end, an output end of the second capacitor is connected to an input end of the second switch, and an output end of the second switch is grounded; or, the isolation ends of the first and second orthogonal couplers are connected to a variable inductor, and the variable inductor is grounded.

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