CML latch taking active inductor as load
By using active inductor as load in the CML latch circuit and changing the zero pole position of the circuit, the low-pass characteristic problem caused by parasitic capacitance of ordinary CML latch circuits is solved, and the effect of high integration and fast latch is achieved, while reducing power consumption and circuit area.
Patent Information
- Application Number
- CN202510169929.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-17
- Publication Date
- 2025-05-30
AI Technical Summary
In SerDes circuits, ordinary CML latch circuits are affected by parasitic capacitance, the output exhibits low-pass characteristics, limiting the transmission rate of digital signals, and traditional spiral inductors increase the circuit area and produce parasitic effects.
A CML latch with an active inductor is used to configure the zero pole position of the circuit by changing the resistance and capacitance of the active inductor circuit to achieve the passive inductor characteristics. The latch circuit is composed of three MOS differential pairs, and the active inductor formed by the source follower is used as the load.
The function of passive inductor is realized, the integration and latch speed of CML latch circuits are improved, power consumption is reduced, and circuit area is reduced.
Smart Images
Figure CN120074494A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of integrated circuits, relates to a latch, and particularly relates to a CML latch with an active inductor as a load. Background Art
[0002] In a SerDes circuit, a feed-forward equalizer and a decision feedback equalizer are required to compensate for the high-frequency part of a signal. The digital delay circuit therein can use a CML latch circuit to halve the clock rate. Affected by parasitic capacitance, the output of a common CML latch circuit exhibits low-pass characteristics, restricting the transmission rate of digital signals. Therefore, an inductor needs to be introduced at the output end to offset the influence of the load capacitance and increase the energy of the high-frequency part of the signal. Introducing a traditional spiral inductor will increase the circuit area and generate large parasitic effects, which is not conducive to integration. Compared with a passive inductor, an active inductor has a small circuit area and can provide a bias for the CML latch circuit while realizing the inductor effect. Summary of the Invention
[0003] In order to overcome the deficiencies of the above-mentioned prior art, the purpose of the present invention is to provide a CML latch with an active inductor as a load, which is used for a CML latch circuit with an active inductor as a load in a feed-forward equalizer. The zero-pole position of the circuit can be configured by changing the resistance and capacitance of the active inductor circuit to achieve the characteristics of a passive inductor.
[0004] In order to achieve the above purpose, the technical solution of the present invention is as follows:
[0005] A CML latch with an active inductor as a load includes a CML latch circuit and an active inductor. It is characterized in that the latch circuit is composed of 3 MOS differential pair transistors, and the active inductor composed of a source follower is used as the load of the CML.
[0006] The CML latch circuit includes a current source, eight transistors, and two capacitors. The differential input terminals of the digital signal are respectively connected to the two signal input terminals of the latch, and the differential clock drive signals are respectively connected to the two clock signal input terminals of the latch circuit; the active inductor circuit includes two transistors, two resistors, and two capacitors. The two source electrodes of the active inductor circuit are respectively connected to the drains of the two transistors of the latch circuit as differential output terminals. The differential input signals VIN+ / VIN- are driven by the differential clock signals CLK+ / CLK-, and the final output is the differential signal VOU+ / VOU-.
[0007] The substrates of the NMOS transistors M1 to M6 of the CML latch circuit are grounded; the sources of M1 and M2 are connected to a bias current source circuit, and the gates are used as the input terminals of the differential clock signal; the drain of M1 is connected to the sources of M3 and ; the drain of M2 is connected to the sources of M5 and M6; the gates of M3 and M4 are used as the input terminals of the differential digital signal; the drain of M3 is respectively connected to the gate of M5, the drain of M6 and the source of M7, serving as the differential signal inverting output terminal; the drain of M4 is respectively connected to the drain of M5, the gate of M6 and the source of M8, serving as the differential signal non-inverting output terminal; the differential signal output terminals are respectively connected in parallel with capacitors C3 and C4.
[0008] The bias current source circuit includes NMOS transistors M9, M10, a reference current source Iref and a bias voltage source vdd; the substrates and sources of M9 and M10 are grounded; the drain of M9 is connected to the sources of M1 and M2; the gate of M9 is connected to the gate and drain of M10, and is connected to the bias voltage source vdd through the reference current source Iref.
[0009] The active inductor circuit includes NMOS transistors M7, M8, resistor R1, resistor R2, capacitor C1, capacitor C2; the substrates of M7 and M8 are grounded, the drains are connected to the power supply vdd, the gates are respectively connected in series with resistors R1 and R2 to the power supply vdd, and capacitors C1 and C2 are respectively connected in parallel between the gates and sources; the source of M7 is connected to the drain of M3, serving as the differential signal inverting output terminal; the source of M8 is connected to the drain of M4, serving as the differential signal non-inverting output terminal.
[0010] The latch circuit uses an active inductor as the load, replacing the traditional integrated spiral inductor, realizing the function of the passive inductor, and improving the integration and latching speed of the CML latch circuit.
[0011] The latch circuit uses an active inductor as the load, replacing the bias resistor required at the load end, and reducing the power consumption.
[0012] The output impedance of the active inductor formed by the source follower is as shown in formula (1):
[0013] (1);
[0014] Where, is the transconductance of the NMOS transistor M7, is the resistance value of the resistor R1, is the sum of the capacitance C1 and the Cgs of the NMOS transistor M7; or is the transconductance of the NMOS transistor M8, is the resistance value of the resistor R2, is the sum of the capacitance C2 and the Cgs of the NMOS transistor M8; as can be seen from Equation (1), the output impedance of the active inductor can generate a pole and a zero, and this zero can be used for high-frequency compensation.
[0015] The inductance value of the described active inductor is as shown in Equation (2):
[0016] (2);
[0017] Where, is the transconductance of the NMOS transistor M7, is the resistance value of the resistor R1, is the sum of the capacitance C1 and the Cgs of the NMOS transistor M7; or is the transconductance of the NMOS transistor M8, is the resistance value of the resistor R2, is the sum of the capacitance C2 and the Cgs of the NMOS transistor M8;
[0018] In order to increase the common-mode rejection ratio of this differential circuit, during the design process of the component parameters of the active inductor circuit, it should be made such that the transconductance of the NMOS transistor M7 = the transconductance of the NMOS transistor M8 = , the resistor R1 = R2 = , the sum of the capacitance C1 and the Cgs of the NMOS transistor M7 = the sum of the capacitance C2 and the Cgs of the NMOS transistor M8 = ;
[0019] Furthermore, the transconductance in Equation (2) can be obtained from Equation (3):
[0020] (3);
[0021] Where, and are both bias quantities. When the bias parameters in the CML latch circuit are determined, the transconductance of the NMOS in the active inductor can be determined.
[0022] Furthermore, combining Equation (1) and Equation (2), it can be known that when > , the output impedance exhibits a high-pass effect, and this effect also enables the active inductor composed of a source follower to replace the passive inductor, realizing the broadening of the frequency domain and improving the latching speed of the latch;
[0023] As can be seen from Equation (2), when > , the output characteristic exhibits an inductance effect, and this effect can enable the active inductor to replace the passive inductor, improving the integration degree of the overall circuit.
[0024] Combined with Equation (1), it can be deduced that | | The output impedance can increase with the increase of frequency, and the load capacitance can be partially offset at high frequencies, thus realizing the expansion of the frequency domain bandwidth and improving the latching rate of the latch.
[0025] The output circuit of the active inductor can be equivalent to a combination of an inductor and a parallel resistor and a series resistor. The active inductor can provide bias for the CML latch circuit, replace the bias resistor of the traditional CML latch circuit, and reduce the power consumption of the circuit.
[0026] The beneficial effects of the present invention are as follows:
[0027] The CML latch is composed of differential pair MOS transistors, and the active inductor is composed of a source follower. The CML latch realizes the latching function. The active inductor replaces the bias resistor in the traditional CML latch circuit, and at the same time can replace the passive inductor to realize high-frequency compensation, reduce the power consumption of the CML latch circuit, reduce the area of the circuit, and improve the latching rate of the latch. Brief Description of the Drawings
[0028] Figure 1 Circuit diagram of a CML latch with a passive inductor as the load.
[0029] Figure 2 Circuit diagram of a CML latch with an active inductor as the load.
[0030] Figure 3 Waveform diagrams of the clock, input, and output of the CML latch circuit with a passive inductor as the load.
[0031] Figure 4 Waveform diagrams of the clock, input, and output of the CML latch circuit with an active inductor as the load. Detailed Description of the Preferred Embodiments
[0032] The present invention will be further described below in conjunction with the accompanying drawings and working principles.
[0033] As Figure 2 shown, the present invention discloses a CML latch circuit with an active inductor as the load, which includes a latch circuit and an active inductor. The latch circuit is composed of a latch pair tube formed by two differential pair MOS transistors; the active inductor is a load formed by a source follower.
[0034] For the CML latch circuit with an active inductor as the load, the differential input signals VIN+ / VIN- are driven by the differential clock signals CLK+ / CLK-, and the final output is the differential signals VOU+ / VOU-.
[0035] The CML latch circuit with an active inductor as the load includes a latch circuit and an active inductor. The latch circuit is composed of 3 MOS differential pair circuits; a source follower forms the active inductor as the load of the CML circuit.
[0036] The latch circuit includes a current source, eight transistors and two capacitors. The differential input terminals of the digital signal are respectively connected to the two signal input terminals of the latch, and the clock differential drive signals are respectively connected to the two clock signal input terminals of the latch circuit; the active inductor circuit includes two transistors, two resistors and two capacitors. The two source electrodes of the active inductor circuit are respectively connected to the drains of the two transistors of the latch circuit as the load differential output terminals.
[0037] The latch circuit uses an active inductor as the load, replacing the traditional integrated spiral inductor, realizing the function of the passive inductor, and improving the integration and latching speed of the CML latch circuit.
[0038] Furthermore, the latch circuit uses an active inductor as the load, replacing the bias resistor required at the load end, and reducing power consumption.
[0039] The CML latch circuit with an active inductor as the load according to the present invention is characterized in that: the CML latch circuit includes NMOS transistors M1 to M6, a bias current source circuit, capacitor C3 and capacitor C4.
[0040] The substrates of NMOS transistors M1 to M6 are grounded.
[0041] The source electrodes of NMOS transistor M1 and NMOS transistor M2 are connected to the bias current source, and the gates are used as the input terminals of the differential clock signal.
[0042] The drain of NMOS transistor M1 is connected to the source electrodes of NMOS transistor M3 and NMOS transistor M4.
[0043] The drain of NMOS transistor M2 is connected to the source electrodes of NMOS transistor M5 and NMOS transistor M6.
[0044] The gates of NMOS transistor M3 and NMOS transistor M4 are used as the input terminals of the digital differential signal.
[0045] The drain of NMOS transistor M3 is connected to the gate of NMOS transistor M5, the drain of NMOS transistor M6 and the source stage of NMOS transistor M7, serving as the differential signal inverting output terminal.
[0046] The drain of NMOS transistor M4 is connected to the drain of NMOS transistor M5, the gate of NMOS transistor M6 and the source stage of NMOS transistor M8, serving as the differential signal non-inverting output terminal.
[0047] The differential signal output terminals are respectively connected in parallel with capacitors C3 and C4 as the load capacitors of the subsequent stage, which can filter out high-frequency noise.
[0048] Furthermore, the bias current source circuit is implemented using a current mirror circuit, which can accurately copy the current Iref of the reference current source to the drain of M9 without being affected by process and temperature. This circuit includes NMOS transistor M9, NMOS transistor M10, bias reference current source Iref, and bias voltage source vdd.
[0049] The substrates and sources of NMOS transistor M9 and NMOS transistor M10 are grounded.
[0050] The drain of NMOS transistor M9 is connected to the sources of NMOS transistor M1 and NMOS transistor M2.
[0051] The gate of NMOS transistor M9 is connected to the gates and drains of NMOS transistor M10, and is connected to the bias voltage source vdd through the reference current source Iref.
[0052] The CML latch circuit with an active inductor as the load is characterized in that: the active inductor circuit includes NMOS transistor M7, NMOS transistor M8, resistor R1, resistor R2, capacitor C1, capacitor C2, and bias voltage source vdd.
[0053] The substrates of NMOS transistor M7 and NMOS transistor M8 are grounded, the drains are connected to the power supply vdd, the gates are respectively connected to the power supply vdd in series with resistors R1 and R2, and capacitors C1 and C2 are respectively connected in parallel between the gates and sources.
[0054] The source of NMOS transistor M7 is connected to the drain of NMOS transistor M3 as the differential signal inverting output terminal.
[0055] The source of NMOS transistor M8 is connected to the drain of NMOS transistor M4 as the differential signal non-inverting output terminal.
[0056] Furthermore, the output impedance of the active inductor formed by the source follower is:
[0057] (1)
[0058] Wherein, is the transconductance of NMOS transistor M7, is the resistance value of resistor R1, is the sum of capacitor C1 and Cgs of NMOS transistor M7; or is the transconductance of NMOS transistor M8, is the resistance value of resistor R2, It is the sum of the capacitance C2 and the Cgs of the NMOS transistor M8.
[0059] As can be seen from Equation (1), the output impedance of the active inductor can generate a pole and a zero, and this zero can be used for high-frequency compensation.
[0060] Furthermore, the equivalent circuit of the active inductor can obtain the inductance value of the active inductor as:
[0061] (2)
[0062] Wherein, is the transconductance of the NMOS transistor M7, is the resistance value of the resistor R1, is the sum of the capacitance C1 and the Cgs of the NMOS transistor M7; or is the transconductance of the NMOS transistor M8, is the resistance value of the resistor R2, is the sum of the capacitance C2 and the Cgs of the NMOS transistor M8, and the value of is close to , is the characteristic frequency.
[0063] Furthermore, in order to increase the common-mode rejection ratio of the differential circuit, during the design process of the component parameters of the active inductor circuit, it should be made such that the transconductance of the NMOS transistor M7 = the transconductance of the NMOS transistor M8 = , the resistor R1 = R2 = , the sum of the capacitance C1 and the Cgs of the NMOS transistor M7 = the sum of the capacitance C2 and the Cgs of the NMOS transistor M8 = ;
[0064] Furthermore, the transconductance in Equation (2) can be obtained from Equation (3)
[0065] (3)
[0066] Wherein, and are both bias quantities. When the bias parameters in the CML latch circuit are determined, the transconductance of the NMOS in the active inductor can be determined.
[0067] Furthermore, combining Equation (1) and Equation (2), it can be known that when > , the output impedance presents a high-pass effect, and this effect also enables the active inductor composed of a source follower to replace the passive inductor, realizing the broadening of the frequency domain and improving the latching speed of the latch.
[0068] Furthermore, based on the above design of the CML latch circuit with an active inductor as the load and the calculation of the corresponding component parameters, the simulation software Cadence was used to simulate the CML latch circuit with a passive inductor as the load ( Figure 1 as shown) and the CML latch circuit with an active inductor as the load ( Figure 2 as shown), and the results are as shown in Figure 3 and Figure 4 (CLK is the differential clock signal, VIN is the differential input signal, and VOU is the differential output signal);
[0069] From the simulation results Figure 3 and Figure 4 it can be obtained that the CML latch circuit designed in the present invention with an active inductor as the load can normally implement the latch function. And from the simulation result diagram, it can be obtained that the CML latch circuit with a passive inductor can significantly compensate the rising edge and falling edge of the signal, that is, adding an inductor at the load end can achieve the compensation of the gain of the high-frequency part of the signal. At the same time, the CML latch circuit using an active inductor as the load can also significantly compensate the rising edge and falling edge of the signal, that is, the CML latch circuit designed in the present invention with an active inductor as the load can replace the passive inductor to achieve the compensation of the energy of the high-frequency part of the signal, and at the same time replace the bias resistor in the CML latch circuit to reduce the circuit power consumption. Furthermore, by comparing the size of the passive inductor with the size of the active inductor composed of CMOS, it can be known that the CML latch circuit described in the present invention with an active inductor as the load is more conducive to integration.
[0070] Use differential pair MOS transistors to form a CML latch, and use a source follower to form an active inductor. The CML latch completes the latch function; the active inductor realizes the function of the passive inductor, compensates the energy of the high-frequency part of the signal, improves the latch rate of the latch, reduces the circuit area, and at the same time replaces the bias resistor in the traditional CML latch circuit to reduce the power consumption of the CML latch.
Claims
1. A CML latch with an active inductor as a load, comprising a CML latch circuit and an active inductor, characterized in that: The latch circuit is composed of three MOS differential pairs, and an active inductor composed of a source follower is used as the load of the CML.
2. A CML latch with an active inductor as a load according to claim 1, characterized in that: The CML latch circuit includes a current source, eight transistors and two capacitors. The differential input end of the digital signal is connected to the two signal input ends of the latch respectively, and the differential clock drive signal is connected to the two clock signal input ends of the latch circuit respectively; the active inductor circuit includes two transistors, two resistors and two capacitors. The two sources of the active inductor circuit are connected to the drains of the two transistors of the latch circuit as differential output ends. The differential input signal VIN+ / VIN- is driven by the differential clock signal CLK+ / CLK-, and the final output is the differential signal VOU+ / VOU-.
3. A CML latch with an active inductor as a load according to claim 2, characterized in that: The substrates of the NMOS transistors M1-M6 of the CML latch circuit are grounded; the sources of M1 and M2 are connected to the bias current source circuit, and the gates serve as the input terminals of the differential clock signal; the drain of M1 is connected to the sources of M3 and; the drain of M2 is connected to the sources of M5 and M6; the gates of M3 and M4 serve as the input terminals of the differential digital signal; the drain of M3 is respectively connected to the gate of M5, the drain of M6 and the source of M7 as the inverting output terminal of the differential signal; the drain of M4 is respectively connected to the drain of M5, the gate of M6 and the source of M8 as the in-phase output terminal of the differential signal; the output terminals of the differential signal are respectively connected in parallel with capacitors C3 and C4.
4. A CML latch with an active inductor as a load according to claim 3, characterized in that: The bias current source circuit comprises NMOS transistors M9, M10, a reference current source Iref and a bias voltage source vdd; the substrate and source of M9 and M10 are grounded; the drain of M9 is connected to the source of M1 and M2; The gate of M9 is connected to the gate and drain of M10 and is connected to a bias voltage source vdd through a reference current source Iref.
5. A CML latch with an active inductor as a load according to claim 2, characterized in that: The active inductor circuit comprises NMOS transistors M7, M8, resistors R1, R2, capacitors C1 and C2; the substrates of M7 and M8 are grounded, the drains are connected to the power supply vdd, the gates are respectively connected in series with resistors R1 and R2 and are connected to the power supply vdd, and capacitors C1 and C2 are respectively connected in parallel between the gate and the source; the source of M7 is connected to the drain of M3 as the inverting output terminal of the differential signal; the source of M8 is connected to the drain of M4 as the in-phase output terminal of the differential signal.
6. A CML latch with an active inductor as a load according to claim 1, characterized in that: The output impedance of the active inductor formed by the source follower is shown in formula (1): （1）； in, is the transconductance of the NMOS transistor M7, is the resistance value of resistor R1, is the sum of the capacitor C1 and the Cgs of the NMOS transistor M7; or is the transconductance of the NMOS transistor M8, is the resistance value of resistor R2, is the sum of capacitor C2 and Cgs of NMOS transistor M8; From formula (1), it can be seen that the output impedance of the active inductor can produce a pole and a zero point, and the zero point can be used for high-frequency compensation; The inductance value of the active inductor is shown in formula (2): （2）； in, is the transconductance of the NMOS transistor M7, is the resistance value of resistor R1, is the sum of the capacitor C1 and the Cgs of the NMOS transistor M7; or is the transconductance of the NMOS transistor M8, is the resistance value of resistor R2, is the sum of capacitor C2 and Cgs of NMOS transistor M8; From formula (2), we can see that when > When , the output characteristic shows an inductance effect, which can make active inductance replace passive inductance and improve the integration of the overall circuit. Combining with formula (1), we can get | |The output impedance can increase with the frequency, which can partially offset the load capacitance at high frequencies.
7. A CML latch with an active inductor as a load according to claim 1, characterized in that: The transconductance in equation (2) is : （3） in, and are all bias values. When the bias parameters in the CML latch circuit are determined, the transconductance of the NMOS in the active inductor is That can be determined.
8. The CML latch with active inductance as load according to claim 1, characterized in that: The output circuit of the active inductor is equivalent to a combination of an inductor, a parallel resistor and a series resistor.