Level shifter and operating method thereof

Abstract

The invention discloses a level shifter and an operation method thereof. The level shifter includes: a low voltage domain configured to output a first pulse current and a second pulse current that are non-overlapping based on opposite edges of a logic input signal; and a high voltage domain including a latch and a current mirroring circuit, the current mirroring circuit configured to mirror non-overlapping first and second pulse currents such that the latch is set when the first pulse current is active and reset when the second pulse current is active. The current mirroring circuit includes a first mirroring path for a first pulse current and a second mirroring path for a second pulse current. The level shifter has a common-mode-gradient current added to the first pulse current and the second pulse current that are not overlapping. The first mirroring path and the second mirroring path are cross-coupled such that the common mode gradient current is reduced or cancelled before the non-overlapping first and second pulse currents are input to the latch.

Description

Technical Field

[0001] The present invention relates to a level shifter and a method of operating a level shifter having a low voltage domain and a high voltage domain. Background Art

[0002] In multi-voltage domain applications, level conversion is required to propagate a signal from one voltage level to another. In cases of higher switching requirements (e.g., >50V / ns), especially for wide bandgap applications, traditional level shifter designs have limited capabilities in terms of fast dv / dt switching. In low voltage (e.g., 3V or lower) applications, traditional level shifters provide good speed and current consumption performance. However, in high voltage (e.g., 3V to 120V or higher) applications, the speed of traditional level shifter designs is limited because high voltage devices have large parasitic capacitances and channel resistances. To improve the propagation delay time, current signal driving has been introduced. Due to high speed dV / dt requirements, e.g., GaN requires dV / dt >50V / ns, noise injection errors are common for traditional level shifter designs. To ensure stable signal propagation during voltage rise or fall, a large DC bias current is typically applied, which increases current consumption. Additionally, due to geometric (layout) limitations of the device with respect to the applied voltage, device parasitics also increase. For example, for a 150V NMOS device, a high speed transition of >50V / ns requires tens of milliamperes (mA) of current to charge the parasitic capacitance. For power-sensitive applications such as battery applications, tens of mA of current is problematic for level shifter designs.

[0003] Therefore, an improved level shifter design is needed. Summary of the Invention

[0004] According to an embodiment of a level shifter, the level shifter includes: a low voltage domain configured to output non-overlapping first and second pulse currents based on opposite edges of a logic input signal; and a high voltage domain including a latch and a current mirror circuit configured to mirror the non-overlapping first and second current pulses such that the latch is set when the first pulse current is valid and reset when the second pulse current is valid, wherein the current mirror circuit includes a first mirror path for the first pulse current and a second mirror path for the second pulse current, wherein the level shifter has a common mode ramp current added to the non-overlapping first and second pulse currents, and wherein the first and second mirror paths are cross-coupled such that the common mode ramp current is reduced or cancelled before the non-overlapping first and second pulse currents are input to the latch.

[0005] According to an embodiment of a method of operating a level shifter having a high voltage domain and a low voltage domain, the method includes: applying a logic input signal to the low voltage domain such that the low voltage domain outputs non-overlapping first and second pulse currents based on opposite edges of the logic input signal; mirroring the first pulse current via a first mirror path in the high voltage domain and mirroring the second pulse current via a second mirror path in the high voltage domain such that a latch in the high voltage domain is set when the first pulse current is valid and reset when the second pulse current is valid, wherein the first mirror path and the second mirror path are cross-coupled; and reducing or canceling a common mode ramp current added to the non-overlapping first and second pulse currents before the non-overlapping first and second pulse currents are input to the latch.

[0006] Those skilled in the art will recognize other features and advantages upon reading the following detailed description and viewing the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The elements in the drawings are not necessarily to scale relative to each other. Like reference numerals represent corresponding like components. The features of the various embodiments shown may be combined unless they are mutually exclusive. Embodiments are depicted in the drawings and described in detail in the following description.

[0008] Figure 1 A circuit schematic showing an embodiment of a level shifter having a cross-coupled current mirror circuit for reducing or canceling common mode ramp current is shown. DETAILED DESCRIPTION

[0009] The embodiments described herein provide a level shifter for fast switching applications (e.g., dV / dt > 50 V / ns). The level shifter uses pulse currents to effect signal conversion from one voltage level to another. The pulse current levels can be controlled by current limiting resistors, which reduces the static current consumption of the level shifter. To overcome the input signal being overridden by parasitic charging caused by rising or falling voltage levels, common mode signal cancellation can be introduced. In this case, the parasitic charging currents generated on the set / reset paths of the level shifter latch during voltage transitions are canceled by complementary signals. The remaining signal current from the set / reset paths of the latch propagates correctly. The latch is implemented in a high voltage domain (e.g., 3 V to 120 V or higher) and is used to capture the input steady state from the low voltage domain of the level shifter.

[0010] Next, exemplary embodiments of the level shifter are described with reference to the drawings.

[0011] Figure 1Shows an embodiment of the level converter 100. The level converter 100 includes a low-voltage (e.g., 5V or lower, 3V or lower, etc.) domain 102, and the low-voltage domain 102 is configured to output non-overlapping first (e.g., set) pulse current I based on the opposite edge of the logic input signal IN SET and second (e.g., reset) pulse current I RST . For example, the rising edge of the logic input signal IN can be used to generate the set (first) pulse current I SET , and the falling edge of the logic input signal IN can be used to generate the reset (second) pulse current I RST . The non-overlapping first pulse current I SET and second pulse current I RST have widths that depend on the technology, e.g., based on the reverse recovery time of high-voltage pMOS devices. For example, both the non-overlapping first pulse current I SET and second pulse current I RST can have a pulse width greater than 15 ns.

[0012] The level converter 100 can be implemented using any semiconductor technology with high-voltage capabilities, which has a designated high-voltage (e.g., 3V to 120V or higher) domain 104 isolated from the low-voltage domain 102, such as high-voltage Si (silicon) technology. For example, the level converter 100 can be used with a driver such as a three-phase motor driver, where the high-voltage domain 104 can be part of any pre-driver stage or final driver stage.

[0013] The high-voltage domain 104 of the level converter 100 includes a latch 106 and a current mirror circuit. The current mirror circuit is configured to mirror the non-overlapping first pulse current I SET and second pulse current I RST , such that the latch 106 is set when the first pulse current I SET is valid and reset when the second pulse current I RST is valid. The current mirror circuit includes a first mirror path 108 for the first pulse current I SET and a second mirror path 110 for the second pulse current I RST .

[0014] The level converter 100 also has a common-mode ramp current I SET added to the non-overlapping first pulse current I RST and second pulse current I SLEW . Due to parasitic capacitances within the level converter 100 such as metal wiring capacitance, device (p- or n-) well capacitance, isolation capacitance, etc., when the first pulse current I SET or second pulse current I RSTWhen there is a transition (from low level to high level or from high level to low level), a common-mode slew current I will appear. SLEW .

[0015] If the common-mode slew current I is not mitigated, SLEW then the magnitude of the non-overlapping first pulse current I SET and the second pulse current I RST will have to be increased such that the pulse currents I SET and I RST are strong enough to trigger (set or reset) the latch 106. More specifically, for example, in the case where the level shifter 100 is configured to provide bootstrap control to a buck regulator, due to the high voltage slew, e.g., from 3V to 120V or higher, there may be large capacitances on both the set current path and the reset current path. The parasitic capacitances are charged and discharged during each set / reset pulse current transition to set the high voltage circuitry. At relatively high speeds (e.g., 20MHz to 1000MHz), if the first pulse current I SET and the second pulse current I RST are small, then the common-mode slew current I SLEW is large and dominant, leading to a malfunction.

[0016] To mitigate this issue, the first mirror path 108 and the second mirror path 110 included in the high voltage domain 104 of the level shifter 100 are cross-coupled such that the common-mode slew current I SET and the second pulse current I RST are reduced or canceled before being input to the latch 106. Thus, only the first (set) pulse current I SLEW and the second (reset) pulse current I SET remain, which reduces the current consumption of the two mirror paths 108, 110 in the high voltage domain 104. Otherwise, higher currents would be required for the pulse currents I RST SET such that the signal is not overridden or controlled by the common-mode slew current I RST SLEW . The mirror paths 108, 110 in the high voltage domain 104 ideally match for effective common-mode cancellation, but there may be some mismatches, meaning that not all of the common-mode current can be canceled.

[0017] In one embodiment, the non-overlapping first pulse current I SET and the second pulse current I RST are generated by the same resistor R LIMIT in the low voltage domain 102.​Control. According to this embodiment, the low-voltage domain 102 of the level shifter 100 includes a pulse generator 112 configured to generate a first pulse Set_Pulse based on the rising edge or falling edge of the logic input signal IN, and generate a second pulse Reset_Pulse based on the other of the rising edge or falling edge of the logic input signal IN. The set current or reset current for triggering the latch 106 in the high-voltage domain 104 flows only when the corresponding pulse I SET 、I RST is valid in the low-voltage domain 102, thereby reducing the static current consumption. The transient current is determined by the widths of the corresponding pulse currents I SET 、I RST .

[0018] The first inverter 114 coupled between the voltage rail VDDL and the reference rail VSSL of the low-voltage domain 102 has an input controlled by the first pulse Set_Pulse. The second inverter 116 coupled between the voltage rail VDDL and the reference rail VSSL of the low-voltage domain 102 has an input controlled by the second pulse Reset_Pulse. The first nMOS transistor device NMH0 has a gate coupled to the output of the first inverter 114, a drain that transmits the first pulse current I SET to the first mirror path 108 of the current mirror circuit in the high-voltage domain 104, and a source. The second nMOS transistor device NMH1 has a gate coupled to the output of the second inverter 116, a drain that transmits the second pulse current I RST to the second mirror path 110 of the current mirror circuit in the high-voltage domain 104, and a source.

[0019] The same resistor R LIMIT couples the source of the first nMOS transistor device NMH0 and the source of the second nMOS transistor device NMH1 to the reference rail VSSL of the low-voltage domain 102. Therefore, the non-overlapping first pulse current I SET 、second pulse current I RST should have the same amplitude, which reduces the current mismatch compared to using two independent current sources. Using two independent current sources would instead result in two paths from the power supply (VDDL) to the ground (VSSL) and increase the current mismatch.

[0020] In one embodiment, the first mirror path 108 and the second mirror path 110 of the current mirror circuit are symmetric. Individually or in combination, both the first mirror path 108 and the second mirror path 110 of the current mirror circuit may include nMOS ('NM') and pMOS ('PM') transistor devices NM10 to NM15, NM20 to NM25, PM10 to PM15, PM20 to PM25, wherein the nMOS and pMOS transistor devices NM10 to NM15, PM10 to PM15 of the first mirror path 108 and the nMOS and pMOS transistor devices NM20 to NM25, PM20 to PM25 of the second mirror path 110 have matching transconductances.

[0021] For example, the first mirror path 108 of the current mirror circuit may include a plurality of first pMOS transistor devices PM10 to PM13, each first pMOS transistor device having a source coupled to the first voltage rail VDDH of the high voltage domain 104, a gate driven by the first pulse current I SET and the common mode slope current I SLEW and a drain. Similarly, the second mirror path 110 of the current mirror circuit may include a plurality of second pMOS transistor devices PM20 to PM25, each second pMOS transistor device having a source coupled to the first voltage rail VDDH of the high voltage domain 104, a gate driven by the second pulse current I RST and the common mode slope current I SLEW and a drain.

[0022] The drain of the first pMOS transistor device PM10, which is the first of the first pMOS transistor devices PM10 to PM13, may be coupled to the node 118 of the first mirror path 108 into which the first pulse current I SET and the common mode slope current I SLEW flow. The drain of the first pMOS transistor device PM20, which is the first of the second pMOS transistor devices PM20 to PM25, may be coupled to the node 120 of the second mirror path 110 into which the second pulse current I RST and the common mode slope current I SLEW flow. The first pMOS transistor devices PM10, PM20 of both the mirror paths 108, 110 are the main devices of the respective mirror paths 108, 110, wherein the current of each first pMOS transistor device PM10, PM20 is set by the respective pulse currents I SET and I RST in the low voltage domain 102 and is shared by the resistor R LIMITControl. For example, the size of the first pMOS transistor device PM10 among the first pMOS transistor devices PM10 to PM13 can be designed to support the first pulse current I SET plus the common-mode ramp current I SLEW , and the size of the first pMOS transistor device PM20 among the second pMOS transistor devices PM20 to PM25 can be designed to support the second pulse current I RST plus the common-mode ramp current I SLEW .

[0023] The drain of the second pMOS transistor device PM13 among the first pMOS transistor devices PM10 to PM13 can be cross-coupled to the second pulse current I RST and the common-mode ramp current I SLEW flowing into the node 120 of the second mirror path 110. Similarly, the drain of the second pMOS transistor device PM23 among the second pMOS transistor devices PM20 to PM25 can be cross-coupled to the first pulse current I SET and the common-mode ramp current I SLEW flowing into the node 118 of the first mirror path 108. Each branch PM10 to PM13, PM20 to PM23 of the current mirror circuit provides one Nth of the current (I SET +I SLEW )(I RST +I SLEW ) flowing through the main device. In Figure 1 , the mirror cross-coupled pMOS device pair PM13 and PM23 reduces the common-mode current by half.

[0024] Whenever the latch 106 is set or reset, the common-mode ramp current I SLEW charges or discharges both sides. However, the first mirror path 108 and the second mirror path 110 of the current mirror circuit included in the high-voltage domain 104 of the level shifter 100 are cross-coupled via, for example, the second pMOS transistor device PM13 among the first pMOS transistor devices PM10 to PM13 and the second pMOS transistor device PM23 among the second pMOS transistor devices PM20 to PM23. Therefore, before the non-overlapping first pulse current I SET and the second pulse current I RST are input to the latch 106, the common-mode ramp current I SLEW is reduced or canceled.

[0025] The first mirror path 108 of the current mirror circuit can include being configured to reduce or cancel the common-mode ramp current I SET from the first pulse current I SLEWA plurality of first nMOS transistor devices NM10 to NM11. The second mirror path 110 of the current mirror circuit may include a plurality of second nMOS transistor devices NM20 to NM21 configured to reduce or cancel the common-mode ramp current I RST from the second pulse current I SLEW .

[0026] For example, each of the first nMOS transistor devices NM10, NM11 may have a source coupled to the second voltage rail VSSH of the high voltage domain 104, a gate driven by the drain of the third pMOS transistor device PM11 among the first pMOS transistor devices PM10 to PM13, and a drain. Each of the second nMOS transistor devices NM20, NM21 may similarly have a source coupled to the second voltage rail VSSH of the high voltage domain 104, a gate driven by the drain of the third pMOS transistor device PM21 among the second pMOS transistor devices PM20 to PM23, and a drain.

[0027] The drain of the first nMOS transistor device NM10 among the first nMOS transistor devices NM10 to NM11 may be coupled to the drain of the third pMOS transistor device PM11 among the first pMOS transistor devices PM10 to PM13. The drain of the second nMOS transistor device NM11 among the first nMOS transistor devices NM10 to NM11 may be cross-coupled to the drain of the fourth pMOS transistor device PM22 among the second pMOS transistor devices PM20 to PM23. The drain of the first nMOS transistor device NM20 among the second nMOS transistor devices NM20 to NM21 may be coupled to the drain of the third pMOS transistor device PM21 among the second pMOS transistor devices PM20 to PM23. The drain of the second nMOS transistor device NM21 among the second nMOS transistor devices NM20 to NM21 may be cross-coupled to the drain of the fourth pMOS transistor device PM12 among the first pMOS transistor devices PM10 to PM13. In Figure 1 , the mirror cross-coupled pair of nMOS devices NM11 and NM21 cancels the common-mode current of the pMOS device PM12 or the pMOS device PM22. Figure 1 There is no common-mode current at the nMOS devices NM12 and NM22 in

[0028] As described above, the low voltage domain 102 may include a first nMOS transistor device NMH0 that transmits the first pulse current I SET to the first mirror path 108 of the current mirror circuit and a second nMOS transistor device that transmits the second pulse current I RSTThe second nMOS transistor device NMH1 transmitted to the second mirror path 110 of the current mirror circuit. The sizes of the first nMOS transistor device NMH0 and the second nMOS transistor device NMH1 in the low voltage domain 102 are designed to support the first pulse current and the second pulse current respectively. The transistor size ratios of each of the first pMOS transistor device PM10 among the first pMOS transistor devices PM10 to PM13, the second pMOS transistor device PM13 among the first pMOS transistor devices PM10 to PM13, the first pMOS transistor device PM20 among the second pMOS transistor devices PM20 to PM23, and the second pMOS transistor device PM23 among the second pMOS transistor devices PM20 to PM23 are all 1 / 2. The transistor size ratios of the third pMOS transistor device PM11 among the first pMOS transistor devices PM10 to PM13, the fourth pMOS transistor device PM12 among the first pMOS transistor devices PM10 to PM13, the third pMOS transistor device PM21 among the second pMOS transistor devices PM20 to PM23, and the fourth pMOS transistor device PM22 among the second pMOS transistor devices PM20 to PM23 are all 1 / 4.

[0029] The first mirror path 108 of the current mirror circuit may further include a plurality of third pMOS transistor devices PM14 to PM15, each third pMOS transistor device having a source, a gate, and a drain coupled to the first voltage rail VDDH of the high voltage domain 104. Similarly, the second mirror path 110 of the current mirror circuit may include a plurality of fourth pMOS transistor devices PM24 to PM25, each fourth pMOS transistor device having a source, a gate, and a drain coupled to the first voltage rail VDDH of the high voltage domain 104. The drain and the gate of the first pMOS transistor device PM14 among the third pMOS transistor devices PM14 to PM15 may be coupled together. The drain of the second pMOS transistor device PM15 among the third pMOS transistor devices PM14 to PM15 may be coupled to the first input node 122 and the first output node 124 of the latch 106. The drain and the gate of the first pMOS transistor device PM24 among the fourth pMOS transistor devices PM24 to PM25 may be coupled together. The drain of the second pMOS transistor device PM25 among the fourth pMOS transistor devices PM24 to PM25 may be coupled to the second input node 126 and the second output node 128 of the latch 106. In the case where the level shifter 100 is used with a driver such as a three-phase motor driver, the logic input signal IN input to the low voltage domain 102 may originate from a controller for the driver, and the outputs OH, OHb (inverted) of the latch 106 may be gate drive signals. For example, the high voltage domain may be a pre-driver stage or a final driver stage.

[0030] The first mirror path 108 of the current mirror circuit may further include a plurality of third nMOS transistor devices NM12 to NM15. Each third nMOS transistor device has a source coupled to the second voltage rail VSSH of the high voltage domain 104, a gate driven by the fourth pMOS transistor device PM12 among the first pMOS transistor devices PM10 to PM13, and a drain. The second mirror path 110 of the current mirror circuit may similarly include a plurality of fourth nMOS transistor devices NM22 to NM25. Each fourth nMOS transistor device has a source coupled to the second voltage rail VSSH of the high voltage domain 104, a gate driven by the fourth pMOS transistor device PM22 among the second pMOS transistor devices PM20 to PM23, and a drain. The drain of the first nMOS transistor device NM12 among the third nMOS transistor devices NM12 to NM15 may be coupled to the drain of the fourth pMOS transistor device PM12 among the first pMOS transistor devices PM10 to PM13. The drain of the second nMOS transistor device NM14 among the third nMOS transistor devices NM12 to NM15 may be coupled to the drain of the first pMOS transistor device PM14 among the third pMOS transistor devices PM14 to PM15. The drain of the third nMOS transistor device NM15 among the third nMOS transistor devices NM12 to NM15 may be coupled to the second output node 128 and the second input node 126 of the latch 106. The drain of the first nMOS transistor device NM22 among the fourth nMOS transistor devices NM22 to NM25 may be coupled to the drain of the fourth pMOS transistor device PM22 among the second pMOS transistor devices PM20 to PM23. The drain of the second nMOS transistor device NM24 among the fourth nMOS transistor devices NM22 to NM25 may be coupled to the drain of the first pMOS transistor device PM24 among the fourth pMOS transistor devices PM24 to PM25. The drain of the third nMOS transistor device NM25 among the fourth nMOS transistor devices NM22 to NM25 may be coupled to the first output node 124 and the first input node 122 of the latch 106.

[0031] Transistor sizing determines whether the common - mode slope current I SLEW is completely canceled or only partially canceled. As Figure 1 shown, the transistor ratios may not be the same (1 / 2 and 1 / 4). For Figure 1 the ratios 1 / 2 and 1 / 4 shown, the common - mode slope current I SLEW is completely canceled (if there is no mismatch). However, different ratios are still valid. If there is a mismatch, then the common - mode slope current I SLEW will not be completely canceled, but Figure 1The transistor sizing ratios 1 / 2 and 1 / 4 shown in SLEW are closest to the ideal case (no mismatch). The transistor sizing ratio 1 / 3 will reduce the common-mode slew current I SLEW , but some portion of the common-mode slew current I SET will be injected into the non-overlapping first (set) pulse current I RST and the second (reset) pulse current I SET , which means that higher pulse currents I RST and I SLEW must be generated accordingly to cover I

[0032] For example, such as from 2 to 4 and from 4 to 8. Figure 1 At node 130 in SET , and during the rising or falling transition of the first pulse current I

[0033] The current I(NM12) in the nMOS device NM12 is given by:

[0034] = I(PM12) - I(NM21) SET = (1 / 2 * I SLEW ) - (1 / 2 * I RST ) SLEW = 1 / 2 * I

[0035] - 1 / 2 * I SET - 1 / 2 * I RST (1)

[0036] where I(PM12) is the current in the pMOS device PM12, and I(NM21) is the current in the nMOS device NM12.

[0037] At node 132 in Figure 1 , and during the rising or falling transition of the second pulse current I RST , the current I(NM22) in the nMOS device NM22 is given by:

[0038] = I(PM22) - I(NM11)

[0039] = (1 / 2 * I RST ) - (1 / 2 * I SLEW ) SET = 1 / 2 * I SLEW )

[0040] - 1 / 2 * I RST - 1 / 2 * I SET (2)

[0041] Wherein, I(PM22) is the current in the pMOS device PM22, and I(NM11) is the current in the nMOS device NM11.

[0042] For the ideal case without mismatch, no common-mode slope current I appears at the set input 122 or the reset input 126 of the latch 106. SLEW .

[0043] In the differential mode, current balance is achieved through symmetric set and reset paths. The non-overlapping first pulse current I SET and the second pulse current I RST are defined by the threshold voltages of the first nMOS transistor device NMH0 and the second nMOS transistor device NMH1 and the common resistor R integrated in the low voltage domain 102. LIMIT The sizes of the pMOS devices PM10 and PM20 in the high voltage domain 104 are designed to support (I SET +I SLEW ) or (I RST +I SLEW ). The non-overlapping first pulse current I SET and the second pulse current I RST are greater than the set / reset path mismatch. The cross-coupled device pairs PM13 to PM23, NM11 to NM21, PM15 to PM25, and NM15 to NM25 protect the set event and the reset event.

[0044] When the first (set) pulse current I SET is valid and the second (reset) pulse current I RST is invalid (zero), the pMOS device PM13 pulls up the node 120, the pMOS device PM20 is turned off, the nMOS device NM11 pulls down the node 132, and the nMOS device NM22 is turned off. The current at the set input 122 of the latch 106 is given by:

[0045] I(PM15)+I(NM25)

[0046] =I SET -I RST

[0047] ≈I SET (3)

[0048] Wherein, I(PM15) is the current in the pMOS device PM15, and I(NM25) is the current in the nMOS device NM25. The current at the reset input 126 of the latch 106 is given by:

[0049] I(PM25)+I(NM15)

[0050] = -I SET +I RST

[0051] ≈ -I SET (4)

[0052] Wherein, I(PM25) is the current in the pMOS device PM25, and I(NM15) is the current in the nMOS device NM15.

[0053] When the first (set) pulse current I SET is invalid (zero) and the second (reset) pulse current I RST is valid, the pMOS device PM23 pulls up node 118, the pMOS device PM10 is turned off, the nMOS device NM21 pulls down node 130, and the nMOS device NM12 is turned off. The current at the reset input 126 of the latch 106 is given by:

[0054] I(PM25) + I(NM15)

[0055] = I RST -I SET

[0056] ≈ I RST (5)

[0057] The current at the set input 122 of the latch 106 is given by:

[0058] I(PM15) + I(NM25)

[0059] = -I RST +I SET

[0060] ≈ -I RST . (6)

[0061] A method of operating the level shifter 100 may include: applying a logic input signal IN to the low voltage domain 102 such that the low voltage domain 102 outputs non-overlapping first and second pulse currents I SET and I RST based on opposite edges of the logic input signal IN; mirroring the first pulse current I SET via a first mirror path 108 in the high voltage domain 104 and mirroring the second pulse current I RST via a second mirror path 110 in the high voltage domain 104 such that the latch 106 in the high voltage domain 104 is set when the first pulse current I SET is valid and reset when the second pulse current I RST is valid; and during the non-overlapping first pulse current ISET and a second pulse current I RST to reduce or cancel the common-mode ramp current I added to the non-overlapping first pulse current I SET and the second pulse current I RST before being input to the latch 106. SLEW The method further includes controlling the non-overlapping first pulse current I LIMIT and the second pulse current I SET through the same resistor R in the low voltage domain 102. RST .

[0062] Although the present disclosure is not limited thereto, the following numbered examples illustrate one or more aspects of the disclosure.

[0063] Example 1. A level shifter, comprising: a low voltage domain configured to output a non-overlapping first pulse current and a second pulse current based on opposite edges of a logic input signal; and a high voltage domain including a latch and a current mirror circuit, the current mirror circuit being configured to mirror the non-overlapping first pulse current and the second pulse current such that the latch is set when the first pulse current is valid and reset when the second pulse current is valid, wherein the current mirror circuit includes a first mirror path for the first pulse current and a second mirror path for the second pulse current, wherein the level shifter has a common-mode ramp current added to the non-overlapping first pulse current and the second pulse current, and wherein the first mirror path and the second mirror path are cross-coupled such that the common-mode ramp current is reduced or cancelled before the non-overlapping first pulse current and the second pulse current are input to the latch.

[0064] Example 2. The level shifter according to Example 1, wherein the non-overlapping first pulse current and the second pulse current are controlled by the same resistor in the low voltage domain.

[0065] Example 3. The level shifter according to Example 2, wherein the low voltage domain includes: a pulse generator configured to generate a first pulse based on a rising edge or a falling edge of a logic input signal and generate a second pulse based on the other of the rising edge or the falling edge of the logic input signal; a first inverter coupled between a voltage rail and a reference rail of the low voltage domain and having an input controlled by the first pulse; a second inverter coupled between the voltage rail and the reference rail of the low voltage domain and having an input controlled by the second pulse; a first nMOS transistor device having a gate coupled to the output of the first inverter, a drain delivering a first pulse current to a first mirror path of a current mirror circuit, and a source; and a second nMOS transistor device having a gate coupled to the output of the second inverter, a drain delivering a second pulse current to a second mirror path of the current mirror circuit, and a source, wherein a resistor couples the sources of the first nMOS transistor device and the second nMOS transistor device to the reference rail of the low voltage domain.

[0066] Example 4. The level shifter according to any one of Examples 1 to 3, wherein the first mirror path and the second mirror path of the current mirror circuit are symmetric.

[0067] Example 5. The level shifter according to any one of Examples 1 to 4, wherein both the first mirror path and the second mirror path of the current mirror circuit include nMOS and pMOS transistor devices, and wherein the nMOS and pMOS transistor devices of the first mirror path and the nMOS and pMOS transistor devices of the second mirror path have matching transconductances.

[0068] Example 6. The level shifter according to any one of Examples 1 to 5, wherein: the first mirror path of the current mirror circuit includes a plurality of first pMOS transistor devices, each first pMOS transistor device having a source coupled to the first voltage rail of the high voltage domain, a gate driven by the first pulse current and the common mode ramp current, and a drain; the second mirror path of the current mirror circuit includes a plurality of second pMOS transistor devices, each second pMOS transistor device having a source coupled to the first voltage rail of the high voltage domain, a gate driven by the second pulse current and the common mode ramp current, and a drain; the drain of the first pMOS transistor device among the first pMOS transistor devices is coupled to the node of the first mirror path where the first pulse current and the common mode ramp current flow in; the drain of the first pMOS transistor device among the second pMOS transistor devices is coupled to the node of the second mirror path where the second pulse current and the common mode ramp current flow in; the drain of the second pMOS transistor device among the first pMOS transistor devices is coupled to the node of the second mirror path where the second pulse current and the common mode ramp current flow in; and the drain of the second pMOS transistor device among the second pMOS transistor devices is coupled to the node of the first mirror path where the first pulse current and the common mode ramp current flow in.

[0069] Example 7. The level shifter according to Example 6, wherein: the first pMOS transistor device among the first pMOS transistor devices is sized to support the first pulse current plus the common mode ramp current, and the first pMOS transistor device among the second pMOS transistor devices is sized to support the second pulse current plus the common mode ramp current.

[0070] Example 8. The level shifter according to Example 6 or Example 7, wherein: the first mirror path of the current mirror circuit includes a plurality of first nMOS transistor devices configured to reduce or cancel the common mode ramp current from the first pulse current; and the second mirror path of the current mirror circuit includes a plurality of second nMOS transistor devices configured to reduce or cancel the common mode ramp current from the second pulse current.

[0071] Example 9. The level shifter according to any one of Examples 6 to 8, wherein: the first mirror path of the current mirror circuit includes a plurality of first nMOS transistor devices, each first nMOS transistor device having a source coupled to the second voltage rail of the high voltage domain, a gate driven by the drain of the third pMOS transistor device in the first pMOS transistor devices, and a drain; the second mirror path of the current mirror circuit includes a plurality of second nMOS transistor devices, each second nMOS transistor device having a source coupled to the second voltage rail of the high voltage domain, a gate driven by the drain of the third pMOS transistor device in the second pMOS transistor devices, and a drain; the drain of the first nMOS transistor device in the first nMOS transistor devices is coupled to the drain of the third pMOS transistor device in the first pMOS transistor devices; the drain of the second nMOS transistor device in the first nMOS transistor devices is coupled to the drain of the fourth pMOS transistor device in the second pMOS transistor devices; the drain of the first nMOS transistor device in the second nMOS transistor devices is coupled to the drain of the third pMOS transistor device in the second pMOS transistor devices; and the drain of the second nMOS transistor device in the second nMOS transistor devices is coupled to the drain of the fourth pMOS transistor device in the first pMOS transistor devices.

[0072] Example 10. The level shifter according to Example 9, wherein: the low voltage domain: includes a first nMOS transistor device configured to deliver a first pulse current to the first mirror path of the current mirror circuit; and a second nMOS transistor device configured to deliver a second pulse current to the second mirror path of the current mirror circuit; the sizes of the first nMOS transistor device and the second nMOS transistor device in the low voltage domain are designed to support the first pulse current and the second pulse current respectively; the transistor size ratio of each of the first pMOS transistor device in the first pMOS transistor devices, the second pMOS transistor device in the first pMOS transistor devices, the first pMOS transistor device in the second pMOS transistor devices, and the second pMOS transistor device in the second pMOS transistor devices is 1 / 2; and the transistor size ratio of each of the third pMOS transistor device in the first pMOS transistor devices, the fourth pMOS transistor device in the first pMOS transistor devices, the third pMOS transistor device in the second pMOS transistor devices, and the fourth pMOS transistor device in the second pMOS transistor devices is 1 / 4.

[0073] Example 11. The level shifter according to Example 9 or Example 10, wherein: the first mirror path of the current mirror circuit includes a plurality of third pMOS transistor devices, each of the third pMOS transistor devices having a source, a gate, and a drain coupled to the first voltage rail of the high voltage domain; the second mirror path of the current mirror circuit includes a plurality of fourth pMOS transistor devices, each of the fourth pMOS transistor devices having a source, a gate, and a drain coupled to the first voltage rail of the high voltage domain; the drain and the gate of the first pMOS transistor device among the third pMOS transistor devices are coupled together; the drain of the second pMOS transistor device among the third pMOS transistor devices is coupled to the first input node and the first output node of the latch; the drain and the gate of the first pMOS transistor device among the fourth pMOS transistor devices are coupled together; the drain of the second pMOS transistor device among the fourth pMOS transistor devices is coupled to the second input node and the second output node of the latch.

[0074] Example 12. The level shifter according to Example 11, wherein: the first mirror path of the current mirror circuit includes a plurality of third nMOS transistor devices, each of the third nMOS transistor devices having a source coupled to the second voltage rail of the high voltage domain, a gate driven by the fourth pMOS transistor device among the first pMOS transistor devices, and a drain; the second mirror path of the current mirror circuit includes a plurality of fourth nMOS transistor devices, each of the fourth nMOS transistor devices having a source coupled to the second voltage rail of the high voltage domain, a gate driven by the drain of the fourth pMOS transistor device among the second pMOS transistor devices, and a drain; the drain of the first nMOS transistor device among the third nMOS transistor devices is coupled to the drain of the fourth pMOS transistor device among the first pMOS transistor devices; the drain of the second nMOS transistor device among the third nMOS transistor devices is coupled to the drain of the first pMOS transistor device among the third pMOS transistor devices; the drain of the third nMOS transistor device among the third nMOS transistor devices is coupled to the second output node and the second input node of the latch; the drain of the first nMOS transistor device among the fourth nMOS transistor devices is coupled to the drain of the fourth pMOS transistor device among the second pMOS transistor devices; the drain of the second nMOS transistor device among the fourth nMOS transistor devices is coupled to the drain of the first pMOS transistor device among the fourth pMOS transistor devices; and the drain of the third nMOS transistor device among the fourth nMOS transistor devices is coupled to the first output node and the first input node of the latch.

[0075] Example 13. The level shifter according to any one of Examples 1 to 12, wherein both the non-overlapping first pulse current and the second pulse current have a pulse width greater than 15 ns.

[0076] Example 14. A buck regulator including the level shifter according to Example 1, wherein the level shifter is configured to provide bootstrap control to the buck regulator.

[0077] Example 15. A method of operating a level shifter having a low voltage domain and a high voltage domain, the method including: applying a logic input signal to the low voltage domain such that the low voltage domain outputs non-overlapping first and second pulse currents based on opposite edges of the logic input signal; mirroring the first pulse current via a first mirror path in the high voltage domain and the second pulse current via a second mirror path in the high voltage domain such that a latch in the high voltage domain is set when the first pulse current is valid and reset when the second pulse current is valid, wherein the first mirror path and the second mirror path are cross-coupled; and reducing or canceling a common mode ramp current added to the non-overlapping first and second pulse currents before the non-overlapping first and second pulse currents are input to the latch.

[0078] Example 16. The method according to Example 15, further including: controlling the non-overlapping first and second pulse currents through the same resistor in the low voltage domain.

[0079] Terms such as "first", "second", etc. are used to describe various elements, regions, sections, etc., and are not intended to be restrictive. Throughout the specification, like reference numerals refer to like elements.

[0080] As used herein, the terms "having", "containing", "including", "comprising", etc. are open terms indicating the presence of the stated element or feature, but do not exclude additional elements or features. Unless the context clearly indicates otherwise, the articles "a", "an", "the" are intended to include the plural and the singular.

[0081] Unless otherwise clearly indicated, the expression "and / or" should be interpreted to include all possible combinations of conjunction and disjunction. For example, the expression "A and / or B" should be interpreted to mean only A, only B, or both A and B. The expression "at least one of..." should be interpreted in the same manner as "and / or" unless otherwise clearly indicated. For example, the expression "at least one of A and B" should be interpreted to mean only A, only B, or both A and B.

[0082] It should be understood that, unless otherwise specifically indicated, the features of the various embodiments described herein may be combined with each other.

[0083] Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will understand that various alternative and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Accordingly, the present invention is intended to be limited only by its claims and their equivalents.

Claims

1. A level converter, comprising: a low voltage domain configured to output non-overlapping first pulse current and second pulse current based on opposite edges of a logic input signal; as well as a high voltage domain including a latch and a current mirror circuit, the current mirror circuit being configured to mirror the non-overlapping first pulse current and second pulse current such that the latch is set when the first pulse current is valid and reset when the second pulse current is valid, The current mirror circuit includes a first mirror path for the first pulse current and a second mirror path for the second pulse current. wherein the level converter has a common mode slope current added to the non-overlapping first pulse current and second pulse current, The first mirror path and the second mirror path are cross-coupled so as to reduce or offset the common-mode slope current before the non-overlapping first pulse current and the second pulse current are input into the latch.

2. The level converter according to claim 1, wherein: The non-overlapping first pulse current and second pulse current are controlled by a same resistor in the low voltage domain.

3. The level converter according to claim 2, wherein: The low voltage domain includes: a pulse generator configured to generate a first pulse based on a rising edge or a falling edge of the logic input signal, and to generate a second pulse based on the other of the rising edge or the falling edge of the logic input signal; a first inverter coupled between a voltage rail of the low voltage domain and a reference rail and having an input controlled by the first pulse; a second inverter coupled between the voltage rail of the low voltage domain and the reference rail and having an input controlled by the second pulse; a first nMOS transistor device having a gate coupled to the output of the first inverter, a drain delivering the first pulse current to a first mirror path of the current mirror circuit, and a source; and a second nMOS transistor device having a gate coupled to the output of the second inverter, a drain for delivering the second pulse current to a second mirror path of the current mirror circuit, and a source, The resistor couples a source of the first nMOS transistor device and a source of the second nMOS transistor device to the reference rail of the low voltage domain.

4. The level converter according to claim 1, wherein: The first mirror path and the second mirror path of the current mirror circuit are symmetrical.

5. The level converter according to claim 1, wherein: The first mirror path and the second mirror path of the current mirror circuit both include nMOS transistor devices and pMOS transistor devices, and wherein the nMOS transistor devices and pMOS transistor devices of the first mirror path and the nMOS transistor devices and pMOS transistor devices of the second mirror path have matched transconductances.

6. The level converter according to claim 1, wherein: The first mirror path of the current mirror circuit includes a plurality of first pMOS transistor devices, each of which has a source coupled to a first voltage rail of the high voltage domain, a gate driven by the first pulse current and the common-mode slope current, and a drain; The second mirror path of the current mirror circuit includes a plurality of second pMOS transistor devices, each second pMOS transistor device having a source coupled to the first voltage rail of the high voltage domain, a gate driven by the second pulse current and the common-mode slope current, and a drain; A drain of a first pMOS transistor device among the plurality of first pMOS transistor devices is coupled to a node of the first mirror path into which the first pulse current and the common-mode slope current flow; A drain of a first pMOS transistor device among the plurality of second pMOS transistor devices is coupled to a node of the second mirror path into which the second pulse current and the common-mode slope current flow; A drain of a second pMOS transistor device among the plurality of first pMOS transistor devices is coupled to a node of the second mirror path into which the second pulse current and the common-mode slope current flow; and A drain of a second pMOS transistor device among the plurality of second pMOS transistor devices is coupled to a node of the first mirror path into which the first pulse current and the common-mode slope current flow.

7. The level converter according to claim 6, wherein: A first pMOS transistor device of the plurality of first pMOS transistor devices is sized to support the first pulse current plus the common-mode slope current; and A first pMOS transistor device of the plurality of second pMOS transistor devices is sized to support the second pulse current plus the common-mode slope current.

8. The level converter according to claim 6, wherein: The first mirror path of the current mirror circuit includes a plurality of first nMOS transistor devices configured to reduce or cancel the common-mode slope current from the first pulse current; and The second mirror path of the current mirror circuit includes a plurality of second nMOS transistor devices configured to reduce or cancel the common-mode slope current from the second pulse current.

9. The level converter according to claim 6, wherein: The first mirror path of the current mirror circuit includes a plurality of first nMOS transistor devices, each first nMOS transistor device having a source coupled to a second voltage rail of the high voltage domain, a gate driven by a drain of a third pMOS transistor device of the plurality of first pMOS transistor devices, and a drain; the second mirror path of the current mirror circuit comprising a plurality of second nMOS transistor devices, each second nMOS transistor device having a source coupled to the second voltage rail of the high voltage domain, a gate driven by a drain of a third pMOS transistor device of the plurality of second pMOS transistor devices, and a drain; a drain of a first nMOS transistor device of the plurality of first nMOS transistor devices coupled to a drain of a third pMOS transistor device of the plurality of first pMOS transistor devices; a drain of a second nMOS transistor device of the plurality of first nMOS transistor devices coupled to a drain of a fourth pMOS transistor device of the plurality of second pMOS transistor devices; a drain of a first nMOS transistor device of the plurality of second nMOS transistor devices coupled to a drain of a third pMOS transistor device of the plurality of second pMOS transistor devices; and A drain of a second nMOS transistor device of the plurality of second nMOS transistor devices is coupled to a drain of a fourth pMOS transistor device of the plurality of first pMOS transistor devices.

10. The level converter according to claim 9, wherein: The low voltage domain includes: a first nMOS transistor device configured to deliver the first pulse current to the first mirror path of the current mirror circuit; and a second nMOS transistor device configured to deliver the second pulse current to the second mirror path of the current mirror circuit; The first nMOS transistor device and the second nMOS transistor device of the low voltage domain are sized to support a first pulse current and a second pulse current, respectively; A transistor size ratio of each of a first pMOS transistor device of the plurality of first pMOS transistor devices, a second pMOS transistor device of the plurality of first pMOS transistor devices, a first pMOS transistor device of the plurality of second pMOS transistor devices, and a second pMOS transistor device of the plurality of second pMOS transistor devices is 1 / 2; and A transistor size ratio of each of the third pMOS transistor device among the plurality of first pMOS transistor devices, the fourth pMOS transistor device among the plurality of first pMOS transistor devices, the third pMOS transistor device among the plurality of second pMOS transistor devices, and the fourth pMOS transistor device among the plurality of second pMOS transistor devices is 1 / 4.

11. The level shifter according to claim 9, wherein: The first mirror path of the current mirror circuit includes a plurality of third pMOS transistor devices, each third pMOS transistor device having a source, a gate, and a drain coupled to the first voltage rail of the high voltage domain; The second mirror path of the current mirror circuit includes a plurality of fourth pMOS transistor devices, each fourth pMOS transistor device having a source, a gate, and a drain coupled to the first voltage rail of the high voltage domain; A drain and a gate of a first pMOS transistor device among the plurality of third pMOS transistor devices are coupled together; A drain of a second pMOS transistor device of the plurality of third pMOS transistor devices is coupled to a first input node and a first output node of the latch; A drain and a gate of a first pMOS transistor device among the plurality of fourth pMOS transistor devices are coupled together; A drain of a second pMOS transistor device of the plurality of fourth pMOS transistor devices is coupled to the second input node and the second output node of the latch.

12. The level shifter according to claim 11, wherein: the first mirror path of the current mirror circuit comprising a plurality of third nMOS transistor devices, each third nMOS transistor device having a source coupled to the second voltage rail of the high voltage domain, a gate driven by a fourth pMOS transistor device of the plurality of first pMOS transistor devices, and a drain; the second mirror path of the current mirror circuit comprising a plurality of fourth nMOS transistor devices, each fourth nMOS transistor device having a source coupled to the second voltage rail of the high voltage domain, a gate driven by a drain of a fourth pMOS transistor device of the plurality of second pMOS transistor devices, and a drain; a drain of a first nMOS transistor device of the plurality of third nMOS transistor devices coupled to a drain of a fourth pMOS transistor device of the plurality of first pMOS transistor devices; a drain of a second nMOS transistor device of the plurality of third nMOS transistor devices coupled to a drain of a first pMOS transistor device of the plurality of third pMOS transistor devices; A drain of a third nMOS transistor device of the plurality of third nMOS transistor devices is coupled to the second output node and the second input node of the latch; a drain of a first nMOS transistor device of the plurality of fourth nMOS transistor devices coupled to a drain of a fourth pMOS transistor device of the plurality of second pMOS transistor devices; a drain of a second nMOS transistor device of the plurality of fourth nMOS transistor devices coupled to a drain of a first pMOS transistor device of the plurality of fourth pMOS transistor devices; and A drain of a third nMOS transistor device of the plurality of fourth nMOS transistor devices is coupled to the first output node and the first input node of the latch.

13. The level converter according to claim 1, wherein: The non-overlapping first pulse current and the second pulse current both have a pulse width greater than 15 ns.

14. A buck regulator comprising the level converter according to claim 1, wherein: The level shifter is configured to provide bootstrap control to the buck regulator.

15. A method of operating a level shifter having a low voltage domain and a high voltage domain, the method comprising: applying a logic input signal to the low voltage domain so that the low voltage domain outputs a non-overlapping first pulse current and a second pulse current based on opposite edges of the logic input signal; mirroring the first pulse current via a first mirror path in the high voltage domain and mirroring the second pulse current via a second mirror path in the high voltage domain, so that a latch in the high voltage domain is set when the first pulse current is valid and reset when the second pulse current is valid, wherein the first mirror path and the second mirror path are cross-coupled; as well as A common mode slope current added to the non-overlapping first pulse current and second pulse current is reduced or offset before the non-overlapping first pulse current and second pulse current are input to the latch.

16. The method according to claim 15, further comprising: The non-overlapping first pulse current and second pulse current are controlled by a same resistor in the low voltage domain.

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