Output port circuit and integrated chip

Abstract

The invention discloses an output port circuit and an integrated chip, and belongs to the technical field of integrated circuits, the output port circuit comprises a NAND gate, a NOR gate, an inverter, a first control transistor, a first switch transistor, a control unit, a second control transistor, a fourth control transistor and a fifth control transistor, the drain electrode of the second control transistor is connected with the drain electrode of the first switch transistor, the substrate end of the second control transistor is connected with a second node, the second node is connected with the source electrodes of the fourth control transistor and the fifth control transistor, and the drain electrode of the fifth control transistor is connected with the grid electrode of the fourth control transistor and connected to the first node. By adding the control unit, the second control transistor, the fourth control transistor and the fifth control transistor, electric leakage is avoided through the control unit, the fourth control transistor and the fifth control transistor while it is guaranteed that the logic function of the circuit is the same as that of a conventional circuit.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly relates to an output port circuit and an integrated chip. Background Art

[0002] The output port circuit of a conventional integrated circuit is as Figure 1 shown. Din is an input signal, and Enable is an enable control signal. In some application environments, the output port Out is powered on first. At this time, the power supply voltage VDD is not yet powered on, and the voltage at the power supply voltage VDD is still equal to 0V. Since the doping type of the drain end of the first PMOS transistor P1 is P-type and the doping type of the substrate end is N-type, there is a parasitic diode between the drain end and the substrate end of the first PMOS transistor P1. The P end of the diode is connected to the drain end of the first PMOS transistor P1, and the N end of the diode is connected to the substrate end of the first PMOS transistor P1. Therefore, the output port Out will sink current to VDD through the parasitic diode from the drain end to the substrate end of the first PMOS transistor P1, resulting in reverse leakage.

[0003] It should be noted that the information disclosed in the background art part of this invention is only intended to deepen the understanding of the general background technology of the present invention, and should not be regarded as an admission or any form of implication that this information constitutes the prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of the present invention is to provide an output port circuit and an integrated chip to solve the problem of reverse leakage of the output port circuit.

[0005] To solve the above technical problems, the present invention provides an output port circuit, including: a NAND gate, a NOR gate, an inverter, a first control transistor, a first switching transistor, a control unit, a second control transistor, a fourth control transistor, and a fifth control transistor;

[0006] The first input terminal and the second input terminal of the NOR gate are respectively connected to an input signal and an enable control signal. The first input terminal of the NAND gate is connected to the enable control signal through an inverter, and the second input terminal of the NAND gate is connected to the input signal. The output terminal of the NOR gate is connected to the gate of the first switching transistor. The source of the first switching transistor is grounded, and the drain is connected to the output port. The output terminal of the NAND gate is connected to the gate of the first control transistor, and the source of the first control transistor is connected to the power supply voltage;

[0007] One end of the control unit is connected to the output end of the inverter, and the other end is used to connect to the second control transistor to control the conduction of the second control transistor. The drain of the first control transistor is connected to the first node, the source of the second control transistor is connected to the first node, the drain of the second control transistor is connected to the drain of the first switching transistor, the body terminal of the second control transistor is connected to the second node, the second node is respectively connected to the sources of the fourth control transistor and the fifth control transistor, the drain of the fifth control transistor is interconnected with the gate of the fourth control transistor and connected to the first node, and the drain of the fourth control transistor is interconnected with the gate of the fifth control transistor and connected to the output port.

[0008] Preferably, the control unit includes a second switching transistor and a third control transistor. The gate of the second switching transistor is connected to the output end of the inverter, the gate of the second switching transistor and the gate of the third control transistor are interconnected, the drain of the second switching transistor and the drain of the third control transistor are connected and interconnected with the gate of the second control transistor, and the source of the third control transistor is connected to the drain of the first switching transistor.

[0009] Preferably, the second switching transistor and the third control transistor have opposite polarities.

[0010] Preferably, the second switching transistor is an NMOS transistor and the third control transistor is a PMOS transistor.

[0011] Preferably, the fourth control transistor and the fifth control transistor have the same polarity.

[0012] Preferably, both the fourth control transistor and the fifth control transistor are PMOS transistors.

[0013] On the other hand, the present invention also provides an integrated chip, including a NAND gate, a NOR gate, an inverter, a first control transistor, a first switching transistor, a control unit, a second control transistor, a fourth control transistor, and a fifth control transistor;

[0014] The first input terminal and the second input terminal of the NOR gate are respectively connected to an input signal and an enable control signal. The first input terminal of the NAND gate is connected to the enable control signal through an inverter, the second input terminal of the NAND gate is connected to the input signal, the output terminal of the NOR gate is connected to the gate of the first switching transistor, the source of the first switching transistor is grounded and the drain is connected to the output port, the output terminal of the NAND gate is connected to the gate of the first control transistor, and the source of the first control transistor is connected to the power supply voltage;

[0015] One end of the control unit is connected to the output end of the inverter, and the other end is used to connect to the second control transistor to control the conduction of the second control transistor. The drain of the first control transistor is connected to the first node. The source of the second control transistor is connected to the first node. The drain of the second control transistor is connected to the drain of the first switching transistor. The body terminal of the second control transistor is connected to the second node. The second node is respectively connected to the sources of the fourth control transistor and the fifth control transistor. The drain of the fifth control transistor is interconnected with the gate of the fourth control transistor and connected to the first node. The drain of the fourth control transistor is interconnected with the gate of the fifth control transistor and connected to the output port.

[0016] Preferably, the control unit includes a second switching transistor and a third control transistor. The gate of the second switching transistor is connected to the output end of the inverter. The gate of the second switching transistor is interconnected with the gate of the third control transistor. The drain of the second switching transistor is connected to the drain of the third control transistor and interconnected with the gate of the second control transistor. The source of the third control transistor is connected to the drain of the first switching transistor.

[0017] Preferably, the second switching transistor is an NMOS transistor and the third control transistor is a PMOS transistor.

[0018] Preferably, both the fourth control transistor and the fifth control transistor are PMOS transistors.

[0019] In the output port circuit provided by the present invention, one end of the control unit is connected to the output end of the inverter INV, and the other end is used to connect to the second control transistor P2 to control the conduction of the second control transistor P2. The drain of the first control transistor P1 is connected to the first node. The source of the second control transistor P2 is connected to the first node Net1. The drain of the second control transistor P2 is connected to the drain of the first switching transistor N1. The body terminal of the second control transistor P2 is connected to the second node Net2. The second node Net2 is respectively connected to the sources of the fourth control transistor P4 and the fifth control transistor P5. The drain of the fifth control transistor P5 is interconnected with the gate of the fourth control transistor P4 and connected to the first node Net1. The drain of the fourth control transistor P4 is interconnected with the gate of the fifth control transistor P5 and connected to the output port Out. By adding a control unit, a second control transistor, a fourth control transistor, and a fifth control transistor, while ensuring that the logic function of the circuit of the present disclosure is the same as that of the conventional circuit, leakage is also avoided through the control unit, the fourth control transistor, and the fifth control transistor.

[0020] The integrated chip provided by the present invention and the output port circuit provided by the present invention belong to the same inventive concept. Therefore, the output port circuit provided by the present invention has at least all the advantages of the integrated chip provided by the present invention, which will not be elaborated here. Further, the output port Out cannot leak electricity to the power supply voltage VDD through the fourth control transistor P4 and the fifth control transistor P5, nor can it leak electricity to Gnd via the control unit and the first switching transistor N1. There is no leakage path between the output port Out and VDD and Gnd, so the occurrence of reverse leakage is avoided. Description of the Drawings

[0021] Figure 1 is a circuit diagram of the output port circuit of a conventional integrated circuit;

[0022] Figure 2 is a circuit diagram of the output port circuit provided by an embodiment of the present invention. Detailed Embodiments

[0023] The output port circuit and the integrated chip proposed by the present invention will be further described in detail below with reference to the drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention. It should be understood that the drawings in the specification do not necessarily show the specific structure of the present invention in proportion, and the illustrative features used to explain certain principles of the present invention in the drawings of the specification will also adopt a slightly simplified drawing method. The specific design features of the present invention disclosed herein, such as specific dimensions, directions, positions, and shapes, will be partially determined by the specific application and use environment. Also, in the embodiments described below, sometimes the same reference numerals are used commonly between different drawings to represent the same part or parts having the same function, and the repeated description thereof is omitted. In this specification, similar reference numerals and letters are used to represent similar items. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0024] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, "a plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0025] In the description of this specification, the description referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0026] The inventors' research found that, for the conventional output circuit as Figure 1 shown, when the enable control signal Enable is 1, the output terminal of the NOR gate (i.e., the gate voltage of the first NMOS transistor N1) is 0, the first NMOS transistor N1 is cut off, the output terminal of the NAND gate (the gate voltage of the first PMOS transistor P1) is VDD, and the first PMOS transistor P1 is also cut off, and the output port Out is in a high-impedance state; when Enable is 0, the output terminals of the NOR gate and the NAND gate (i.e., the gate of the first PMOS transistor P1 and the gate of the first NMOS transistor N1) are equal to the inverse of the input signal Din. If the input signal Din is 1, then the gates of both the first PMOS transistor P1 and the first NMOS transistor N1 are 0, the first NMOS transistor N1 is cut off, the first PMOS transistor P1 is turned on, and the output port Out outputs VDD. If the input signal Din is 0, then the gates of both the first PMOS transistor P1 and the first NMOS transistor N1 are 1, the first NMOS transistor N1 is turned on, the first PMOS transistor P1 is cut off, and the output port Out outputs 0. In the Figure 1 circuit, a situation where the output port Out is powered on first, resulting in reverse leakage, will occur.

[0027] Based on this, the core idea of the present invention is that by adding a control unit, a second control transistor, a fourth control transistor, and a fifth control transistor, while ensuring that the logic function of the circuit of the present disclosure is the same as that of the conventional circuit, leakage is also avoided through the control unit and the fourth and fifth control transistors.

[0028] Specifically, please refer to Figure 2 , which is a schematic diagram of an embodiment of the present invention. An output port circuit includes: a NAND gate, a NOR gate, an inverter INV, a first control transistor P1, a first switching transistor N1, a control unit, a second control transistor P2, a fourth control transistor P4, and a fifth control transistor P5.

[0029] The first input terminal and the second input terminal of the NOR gate are respectively connected to the input signal Din and the enable control signal Enable. The first input terminal of the NAND gate is connected to the enable control signal Enable through an inverter INV. The second input terminal of the NAND gate is connected to the input signal Din. The output terminal of the NOR gate is connected to the gate of the first switching transistor N1. The source of the first switching transistor N1 is grounded to Gnd, and the drain is connected to the output port Out. The output terminal of the NAND gate is connected to the gate of the first control transistor P1. The source of the first control transistor P1 is connected to the power supply voltage VDD.

[0030] One end of the control unit is connected to the output terminal of the inverter INV, and the other end is used to connect to the second control transistor P2 to control the second control transistor P2 to conduct. The drain of the first control transistor P1 is connected to the first node Net1. The source of the second control transistor P2 is connected to the first node Net1. The drain of the second control transistor P2 is connected to the drain of the first switching transistor N1. The substrate end of the second control transistor P2 is connected to the second node Net2. The second node Net2 is respectively connected to the sources of the fourth control transistor P4 and the fifth control transistor P5. The drain of the fifth control transistor P5 is interconnected with the gate of the fourth control transistor P4 and connected to the first node Net1. The drain of the fourth control transistor P4 is interconnected with the gate of the fifth control transistor P5 and connected to the output port Out.

[0031] When the output port Out is first powered up to a high level, but the power supply voltage VDD has not been powered up yet, since the voltage of the output port Out is relatively high and the power supply voltage VDD is equal to 0, the output voltages of the inverter INV, the NAND gate, and the NOR gate are all 0. The gate voltage of the first switching transistor N1 is equal to 0, and the first switching transistor N1 is turned off. The output port Out cannot leak current to its source grounded end Gnd through the first switching transistor N1, and the control unit is disconnected, so that the output port Out cannot leak current from the control unit either. Further, there is a parasitic diode between the drain and the substrate end of the fourth control transistor P4. The P electrode and the N electrode of this parasitic diode are respectively connected to the drain and the substrate end of the fourth control transistor P4. The output port Out will charge Net2 (i.e., the substrate end of the second control transistor P2) through this parasitic diode until the voltage of Net2 is equal to V Out -V dio , where V dio is the forward conduction voltage drop of the parasitic diode. At this time, the gate voltage of the second control transistor P2 is equal to the voltage of the output port Out, and the voltage at the substrate end of the second control transistor P2, that is, the second node Net2, is equal to VOut -V dio Therefore, the second control transistor P2 is turned off, so the output port Out cannot leak through the second control transistor P2. Additionally, the gate voltage of the fifth control transistor P5 is also the voltage of the output port Out, and the voltage at the second node Net2 is equal to -V Out -V dio Therefore, the fifth control transistor P5 is also turned off. Thus, the output port Out also cannot leak through the fourth control transistor P4 and the fifth control transistor P5. Based on the above analysis, it can be seen that the output port Out cannot leak to the power supply voltage VDD through the fourth control transistor P4 and the fifth control transistor P5, nor can it leak to Gnd via the control unit and the first switching transistor N1. There is no leakage path between the output port Out and VDD and Gnd, thus avoiding the occurrence of reverse leakage

[0032] Specifically, the control unit includes a second switching transistor N2 and a third control transistor P3. The gate of the second switching transistor N2 is connected to the output terminal of the inverter INV. The gates of the second switching transistor N2 and the third control transistor P3 are interconnected. The drains of the second switching transistor N2 and the third control transistor P3 are interconnected and connected to the gate of the second control transistor P2. The source of the third control transistor P3 is connected to the drain of the first switching transistor N1, that is, connected to the output port Out. The substrate end and the source of the second switching transistor N2 are commonly connected to the ground Gnd

[0033] By setting the second control transistor P2 to be turned on through the control unit, when the output port Out is powered on but the power supply voltage VDD has not been powered on, the second control transistor P2 is turned off. When the output port Out is powered on to a high level first and the power supply voltage VDD has not been powered on, the third control transistor P3 is turned on. The gate voltage of the second control transistor P2 is equal to the voltage of the output port Out, and the second switching transistor N2 is turned off. The output port Out cannot leak through the control unit, and the second control transistor P2 is also turned off

[0034] In one embodiment, the second switching transistor N2 and the third control transistor P3 have opposite polarities. The second switching transistor N2 is an NMOS transistor, and the third control transistor P3 is a PMOS transistor. The fourth control transistor P4 and the fifth control transistor P5 have the same polarity. Both the fourth control transistor P4 and the fifth control transistor P5 are PMOS transistors

[0035] When the enable control signal Enable = 1, that is, when the enable control signal Enable outputs a high level, the output terminal of the NOR gate (i.e., the gate voltage of the first switching transistor N1) is 0, the output terminal of the inverter INV is 0, the first switching transistor N1 is turned off, the output terminal of the NAND gate (the gate voltage of the first control transistor P1) is at a high level or the power supply voltage VDD. At this time, the first control transistor P1 is also turned off, the second switching transistor N2 is turned off, and the output port Out is in a high-impedance state.

[0036] Conversely, when the enable control signal Enable = 0, that is, when the enable control signal Enable outputs a low level, the output terminal of the inverter INV is 1, the second switching transistor N2 is turned on, the third control transistor P3 is turned off, and the gate voltage of the second control transistor P2 is equal to 0.

[0037] At this time, if the enable control signal Enable = 0 and the input signal Din = 1, the gate voltage of the first switching transistor N1 is 0, the first switching transistor N1 is turned off, the gate voltage of the first control transistor P1 is 0, the first control transistor P1 is turned on, and the drain voltage of the first control transistor P1, that is, at the first node Net1, will be the power supply voltage VDD. The drain of the fifth control transistor P5 is connected to the first node Net1, the substrate end of the fifth control transistor P5 is connected to the second node Net2. There is a parasitic diode between the substrate end and the drain of the fifth control transistor P5. The P electrode of this parasitic diode is connected to the drain of the fifth control transistor P5, and the N electrode is connected to the substrate end of the fifth control transistor P5. The P electrode and the N electrode of this parasitic diode are respectively connected to the first node Net1 and the second node Net2. The voltage of the first node Net1 is equal to the power supply voltage VDD. Therefore, this parasitic diode is forward-conducted and charges the second node Net2 until the voltage of the second node Net2 is equal to VDD - V dio , where V dio is the forward conduction voltage drop of this parasitic diode. Since the gate voltage of the second control transistor P2 is 0, the second control transistor P2 is also turned on, and the output port Out will output a high level.

[0038] If the enable control signal Enable = 0 and the input signal Din = 0, the gate voltages of the first switching transistor N1 and the first control transistor P1 will both be equal to the power supply voltage VDD. The first switching transistor N1 is turned on, and the first control transistor P1 is turned off. At this time, regardless of whether the second control transistor P2 is turned on or not, the output port Out will output 0.

[0039] The transistors used in all embodiments of this application can be thin film transistors, field effect transistors, or other devices with the same characteristics. According to their functions in the circuit, the transistors used in the embodiments of this application are mainly CMOS transistors (Complementary Metal Oxide Semiconductor). Except that the back gate end of the second control transistor P2 is connected to the second node Net2, the back gate ends of the remaining MOS transistors are interconnected with their source electrodes, which will not be elaborated here one by one.

[0040] Based on the same inventive concept, the present disclosure also provides an integrated chip, including: a NAND gate NAND, a NOR gate NOR, an inverter INV, a first control transistor P1, a first switching transistor N1, a control unit, a second control transistor P2, a fourth control transistor P4, and a fifth control transistor P5.

[0041] The first input terminal and the second input terminal of the NOR gate NOR are respectively connected to the input signal Din and the enable control signal Enable. The first input terminal of the NAND gate NAND is connected to the enable control signal Enable through the inverter INV. The second input terminal of the NAND gate NAND is connected to the input signal Din. The output terminal of the NAND gate NAND is connected to the gate of the first control transistor P1. The output terminal of the NOR gate NOR is connected to the gate of the first switching transistor N1. The source electrode of the first switching transistor N1 is grounded to Gnd, and the drain electrode is connected to the output port Out. The output terminal of the NAND gate NAND is connected to the gate of the first control transistor P1. The source electrode of the first control transistor P1 is connected to the power supply voltage VDD.

[0042] One end of the control unit is connected to the output terminal of the inverter INV, and the other end is used to connect to the second control transistor P2 to control the conduction of the second control transistor P2. The drain electrode of the first control transistor P1 is connected to the first node. The source electrode of the second control transistor P2 is connected to the first node Net1. The drain electrode of the second control transistor P2 is connected to the drain electrode of the first switching transistor N1. The back gate end of the second control transistor P2 is connected to the second node Net2. The second node Net2 is respectively connected to the source electrodes of the fourth control transistor P4 and the fifth control transistor P5. The drain electrode of the fifth control transistor P5 is interconnected with the gate of the fourth control transistor P4 and connected to the first node Net1. The drain electrode of the fourth control transistor P4 is interconnected with the gate of the fifth control transistor P5 and connected to the output port Out.

[0043] When the output port Out is first powered up to a high level, but the power supply voltage VDD is not yet powered up, since the voltage of the output port Out is relatively high and the power supply voltage VDD is equal to 0, the output voltages of the inverter INV, the NAND gate NAND, and the NOR gate NOR are all 0. The gate voltage of the first switching transistor N1 is equal to 0, and the first switching transistor N1 is turned off. The output port Out cannot leak current to its source grounded terminal Gnd through the first switching transistor N1, and the control unit is disconnected, so that the output port Out cannot leak current from the control unit either. Further, there is a parasitic diode between the drain and the substrate terminal of the fourth control transistor P4. The P electrode and the N electrode of this parasitic diode are connected to the drain and the substrate terminal of the fourth control transistor respectively. The output port Out will charge Net2 (i.e., the substrate terminal of the second control transistor P2) through this parasitic diode until the voltage of Net2 is equal to V Out -V dio , where V dio is the forward conduction voltage drop of the parasitic diode. At this time, the gate voltage of the second control transistor P2 is equal to the voltage of the output port Out, and the voltage at the substrate terminal of the second control transistor P2, that is, the second node Net2, is equal to V Out- V dio . Therefore, the second control transistor P2 is turned off, so the output port Out cannot leak current through the second control transistor P2. In addition, the gate voltage of the fifth control transistor P5 is also the voltage of the output port Out, and the voltage at the second node Net2 is equal to V Out -V dio . Therefore, the fifth control transistor P5 is also turned off. Therefore, the output port Out cannot leak current through the fourth control transistor P4 and the fifth control transistor P5 either. Based on the above analysis, it can be seen that the output port Out cannot leak current to the power supply voltage VDD through the fourth control transistor P4 and the fifth control transistor P5, nor can it leak current to Gnd through the control unit and the first switching transistor N1. There is no leakage path between the output port Out and VDD and Gnd, so the occurrence of reverse leakage is avoided.

[0044] Specifically, the control unit includes a second switching transistor N2 and a third control transistor P3. The gate of the second switching transistor N2 is connected to the output terminal of the inverter INV. The gates of the second switching transistor N2 and the third control transistor P3 are interconnected. The drain of the second switching transistor N2 is interconnected with the gate of the second control transistor P2. The source of the third control transistor P3 is connected to the drain of the first switching transistor N1. By setting the second control transistor P2 to conduct, when the output port Out is powered on but the power supply voltage VDD is not yet powered on, the second control transistor P2 is cut off. When the output port Out is first powered on to a high level and the power supply voltage VDD is not yet powered on, the third control transistor P3 conducts. The gate voltage of the second control transistor P2 is equal to the voltage of the output port Out, and the second switching transistor N2 is cut off. The output port Out cannot leak electricity through the control unit, and the second control transistor P2 is also cut off.

[0045] In an embodiment, the polarities of the second switching transistor N2 and the third control transistor P3 are opposite. The second switching transistor N2 is an NMOS transistor, and the third control transistor P3 is a PMOS transistor. The polarities of the fourth control transistor and the fifth control transistor are the same. Both the fourth control transistor and the fifth control transistor are PMOS transistors.

[0046] In summary, in the output port circuit and the integrated chip provided in the embodiments of the present invention, by adding a control unit, a second control transistor, a fourth control transistor, and a fifth control transistor, while ensuring that the logic function of the circuit of the present disclosure is the same as that of the conventional circuit, leakage is also avoided through the control unit, the fourth control transistor, and the fifth control transistor, thereby being able to solve the reverse leakage problem of the conventional output port circuit.

[0047] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. An output port circuit, characterized in that, comprising: a NAND gate, a NOR gate, an inverter, a first control transistor, a first switching transistor, a control unit, a second control transistor, a fourth control transistor, and a fifth control transistor; The first input terminal and the second input terminal of the NOR gate are respectively connected to an input signal and an enable control signal. The first input terminal of the NAND gate is connected to the enable control signal through an inverter. The second input terminal of the NAND gate is connected to the input signal. The output terminal of the NOR gate is connected to the gate of the first switching transistor. The source of the first switching transistor is grounded, and the drain is connected to the output port. The output terminal of the NAND gate is connected to the gate of the first control transistor, and the source of the first control transistor is connected to the power supply voltage; One end of the control unit is connected to the output terminal of the inverter, and the other end is used to connect to the second control transistor to control the second control transistor to conduct. The drain of the first control transistor is connected to a first node. The source of the second control transistor is connected to the first node. The drain of the second control transistor is connected to the drain of the first switching transistor. The substrate terminal of the second control transistor is connected to a second node. The second node is respectively connected to the sources of the fourth control transistor and the fifth control transistor. The drain of the fifth control transistor is interconnected with the gate of the fourth control transistor and connected to the first node. The drain of the fourth control transistor is interconnected with the gate of the fifth control transistor and connected to the output port.

2. The output port circuit according to claim 1, characterized in that, The control unit includes a second switching transistor and a third control transistor. The gate of the second switching transistor is connected to the output terminal of the inverter. The gate of the second switching transistor is interconnected with the gate of the third control transistor. The drain of the second switching transistor is interconnected with the drain of the third control transistor and connected to the gate of the second control transistor. The source of the third control transistor is connected to the drain of the first switching transistor.

3. The output port circuit according to claim 2, characterized in that, The second switching transistor and the third control transistor have opposite polarities.

4. The output port circuit according to claim 2, characterized in that, The second switching transistor is an NMOS transistor, and the third control transistor is a PMOS transistor.

5. The output port circuit according to claim 1, characterized in that, The fourth control transistor and the fifth control transistor have the same polarity.

6. The output port circuit according to claim 5, characterized in that, Both the fourth control transistor and the fifth control transistor are PMOS transistors.

7. An integrated chip, characterized in that, comprising a NAND gate, a NOR gate, an inverter, a first control transistor, a first switching transistor, a control unit, a second control transistor, a fourth control transistor, and a fifth control transistor; The first input terminal and the second input terminal of the NOR gate are respectively connected to an input signal and an enable control signal. The first input terminal of the NAND gate is connected to the enable control signal through an inverter. The second input terminal of the NAND gate is connected to the input signal. The output terminal of the NOR gate is connected to the gate of the first switching transistor. The source of the first switching transistor is grounded, and the drain is connected to the output port. The output terminal of the NAND gate is connected to the gate of the first control transistor. The source of the first control transistor is connected to the power supply voltage. One end of the control unit is connected to the output terminal of the inverter, and the other end is used to connect to the second control transistor to control the conduction of the second control transistor. The drain of the first control transistor is connected to the first node. The source of the second control transistor is connected to the first node. The drain of the second control transistor is connected to the drain of the first switching transistor. The substrate terminal of the second control transistor is connected to the second node. The second node is respectively connected to the sources of the fourth control transistor and the fifth control transistor. The drain of the fifth control transistor is interconnected with the gate of the fourth control transistor and connected to the first node. The drain of the fourth control transistor is interconnected with the gate of the fifth control transistor and connected to the output port.

8. The integrated chip according to claim 7, wherein, the control unit includes a second switching transistor and a third control transistor. The gate of the second switching transistor is connected to the output terminal of the inverter. The gate of the second switching transistor and the gate of the third control transistor are interconnected. The drain of the second switching transistor and the drain of the third control transistor are connected and interconnected with the gate of the second control transistor. The source of the third control transistor is connected to the drain of the first switching transistor.

9. The integrated chip according to claim 8, wherein, the second switching transistor is an NMOS transistor, and the third control transistor is a PMOS transistor.

10. The integrated chip according to claim 8, wherein, both the fourth control transistor and the fifth control transistor are PMOS transistors.

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