Phase-locked loop applied to multi-frequency-point output wide frequency range

Abstract

The invention discloses a phase-locked loop applied to a multi-frequency-point output wide frequency range, and the phase-locked loop comprises a phase frequency detector which is used for carrying out the frequency and phase detection of an input signal and a frequency division signal, and outputting a pull-up control signal and a pull-down control signal of a charge pump according to a detection result; the charge pump is used for subtracting the pull-up current from the pull-down current; the low-pass filter is used for integrating and converting the difference between the pull-up current and the pull-down current into the control voltage of the voltage-controlled oscillator; the voltage-controlled oscillator is used for outputting a clock signal according to the control voltage; and the frequency divider is used for carrying out frequency division processing on the clock signal to obtain a frequency division signal and inputting the frequency division signal into the phase frequency detector. The pulse signals with different widths are output to control the charge pump switch to generate the pull-up current and the pull-down current, and the difference between the two currents is converted into the control voltage of the voltage-controlled oscillator through integration of the low-pass filter, so that the frequency of the voltage-controlled oscillator is modulated, and finally the locking state of the phase-locked loop is realized.

Description

Technical Field

[0001] This application relates to the field of integrated circuit manufacturing technology, and particularly to a phase-locked loop applied to wide frequency range with multi-frequency output. Background Art

[0002] With the continuous development of semiconductor technology, the power consumption of integrated circuits is getting lower and lower, and the speed is getting faster and faster. At the same time, digital, analog, and radio frequency circuits can be integrated on the same chip to realize a system on chip (SoC). And the clock signal used to drive the SoC, CPU or other mixed signal systems needs to meet very high requirements to ensure the normal operation of the circuit. Common frequency synthesis technologies include direct frequency synthesis, phase-locked loop (PLL) frequency synthesis, direct digital synthesis, etc. Among them, the phase-locked loop technology, as the most common frequency synthesis technology, has the advantages of high output frequency, wide tuning range, good stability, strong noise suppression ability, etc. The phase-locked loop is a typical negative feedback control loop. The clock signal with good phase noise performance input externally is divided by a prescaler and then compared with the clock signal fed back by the loop, and the corresponding control signal is output to adjust the phase-locked loop circuit, so that the phase difference between the two input signals of the frequency discriminator and phase discriminator does not change with time. At this time, the output signal of the voltage-controlled oscillator can be used as the clock of the system after a series of processes, so it is widely used in various electronic systems.

[0003] A stable clock signal is crucial for the chip. For digital circuits, whether it is synchronous timing or asynchronous timing, the correct processing of digital information, including arithmetic operations, transmission, and storage, needs to be guaranteed by a stable clock. In modern communication systems, high-performance clocks are everywhere. In wireless communication transmitting and receiving systems, a clock generation circuit called a frequency synthesizer (FS) is required to generate an accurate clock signal, which will be used as the local oscillator signal of the mixer to realize the "shift" of the spectrum. And in wired communication systems such as optical fiber communication and some communication systems using metal wires as carriers, digital signals are also modulated to a certain frequency. Accurate clock generation and clock recovery circuits are crucial components. Under the action of the high-frequency clock provided by the phase-locked loop, serial data transceiver of 100 Gb / s for a single channel has been realized at present. Therefore, the research and design of high-performance phase-locked loop chips are of great significance. Summary of the Invention

[0004] In view of the above-mentioned disadvantages of the prior art, this application provides a phase-locked loop applied to wide frequency range with multi-frequency output, which is used to solve at least one defect in the prior art.

[0005] To achieve the above and other objects, the present application provides a phase-locked loop applied to a wide frequency range of multi-frequency output. The phase-locked loop includes:

[0006] A frequency discriminator and phase detector, configured to detect the frequency and phase of an input signal and a divided signal, and output a pull-up control signal and a pull-down control signal of a charge pump according to the detection results;

[0007] A charge pump, connected to the frequency discriminator and phase detector, configured to generate a pull-up current according to the pull-up control signal and a pull-down current according to the pull-down control signal, and subtract the pull-up current from the pull-down current;

[0008] A low-pass filter, connected to the output end of the charge pump, configured to integrate the difference between the pull-up current and the pull-down current to convert it into a control voltage of the voltage-controlled oscillator;

[0009] A voltage-controlled oscillator, connected to the low-pass filter, configured to output a clock signal according to the control voltage;

[0010] A frequency divider, connected to the voltage-controlled oscillator, configured to perform frequency division processing on the clock signal to obtain a divided signal, and input the divided signal into the frequency discriminator and phase detector.

[0011] In an embodiment of the present invention, the low-pass filter includes a first filter and a second filter; when the input signal is a high-frequency signal, the first filter integrates the difference between the pull-up current and the pull-down current to convert it into a control voltage of the voltage-controlled oscillator; when the input signal is a low-frequency signal, the second filter integrates the difference between the pull-up current and the pull-down current to convert it into a control voltage of the voltage-controlled oscillator.

[0012] In an embodiment of the present invention, the first filter includes: a second capacitor, a third capacitor, a first resistor, and a second resistor;

[0013] One end of the first resistor is connected to one end of the second resistor to form a first connection node, and the first connection node is connected to the output end of the charge pump; the other end of the second resistor is respectively connected to the upper plate of the third capacitor and the input end of the voltage-controlled oscillator; the lower plate of the third capacitor is grounded; the other end of the first resistor is connected to the upper plate of the second capacitor, and the lower plate of the second capacitor is respectively grounded.

[0014] In an embodiment of the present invention, the second filter includes: a first capacitor, a second capacitor, a third capacitor, a first resistor, and a second resistor;

[0015] One end of the first resistor is connected to one end of the second resistor to form a first connection node, and the first connection node is connected to the output end of the charge pump; the other end of the second resistor is respectively connected to the upper plate of the third capacitor and the input end of the voltage-controlled oscillator; the lower plate of the third capacitor is grounded; the other end of the first resistor is connected to the upper plate of the second capacitor to form a second connection node, the second connection node is connected to the upper plate of the first capacitor, and the lower plates of the first capacitor and the second capacitor are respectively grounded.

[0016] In an embodiment of the present invention, the low-pass filter further includes: a switch;

[0017] The upper plate of the first capacitor is connected to one end of the switch, and the second connection node is connected to the other end of the switch; the switch includes an enable end, and when the signal received by the enable end is enabled, the switch conducts.

[0018] In an embodiment of the present invention, the frequency divider includes a first frequency divider and a second frequency divider. The first frequency divider outputs a first divided frequency signal, and the second frequency divider outputs a second divided frequency signal;

[0019] When the input signal is a high-frequency signal, the first frequency divider divides the clock signal to obtain a first divided frequency signal and inputs the first divided frequency signal into the frequency discriminator and phase discriminator;

[0020] When the input signal is a low-frequency signal, the first frequency divider and the second frequency divider divide the clock signal to obtain a second divided frequency signal and input the second divided frequency signal into the frequency discriminator and phase discriminator.

[0021] In an embodiment of the present invention, the first frequency divider includes:

[0022] A first input end, connected to the output end of the voltage-controlled oscillator;

[0023] A first control end, receiving a first control signal

[0024] A second control end, receiving a second control signal;

[0025] A first output end, outputting a first divided frequency signal according to the first control signal and the second control signal;

[0026] The control unit includes:

[0027] A second input end, connected to the first output end of the first frequency division unit;

[0028] A third control end, receiving a third control signal;

[0029] A second output terminal, connected to one of the input terminals of the frequency discriminator and phase detector, outputs a first divided-frequency signal according to the third control signal and inputs the first divided-frequency signal into the frequency discriminator and phase detector.

[0030] In an embodiment of the present invention, the second frequency divider includes:

[0031] A third input terminal, connected to the first output terminal of the first frequency division unit;

[0032] A fourth control terminal, receiving a fourth control signal;

[0033] A fifth control terminal, receiving a fifth control signal;

[0034] A third output terminal, outputting a third divided-frequency signal according to the third control signal and the fourth control signal;

[0035] The control unit further includes:

[0036] A fourth input terminal, connected to the third output terminal of the second frequency division unit;

[0037] The second output terminal outputs a second divided-frequency signal according to the third control signal, and the second divided-frequency signal is the product of the first divided-frequency signal and the third divided-frequency signal.

[0038] Advantages of the present application:

[0039] A phase-locked loop applied to multi-frequency output with a wide frequency range in the present application includes: a frequency discriminator and phase detector, configured to detect the frequency and phase of an input signal and a divided-frequency signal, and output a pull-up control signal and a pull-down control signal of a charge pump according to the detection results; a charge pump, connected to the frequency discriminator and phase detector, configured to generate a pull-up current according to the pull-up control signal and generate a pull-down current according to the pull-down control signal, and subtract the pull-up current from the pull-down current; a low-pass filter, connected to the output terminal of the charge pump, configured to integrate the difference between the pull-up current and the pull-down current into a control voltage of the voltage-controlled oscillator; a voltage-controlled oscillator, connected to the low-pass filter, configured to output a clock signal according to the control voltage; a frequency divider, connected to the voltage-controlled oscillator, configured to perform frequency division processing on the clock signal to obtain a divided-frequency signal, and input the divided-frequency signal into the frequency discriminator and phase detector. In the present application, pulse signals with different widths are output to control the charge pump switch to generate a pull-up current (Iup) and a pull-down current (Idown), and the difference between the two currents is integrated by the low-pass filter and converted into a control voltage of the voltage-controlled oscillator, thereby modulating the frequency of the VCO, and finally realizing the locked state of the phase-locked loop.

[0040] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. Description of the Drawings

[0041] The drawings herein are incorporated into and form a part of this specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts. In the drawings:

[0042] Figure 1 is a schematic block diagram of a phase-locked loop applied to a multi-frequency output wide-frequency range according to an embodiment of the present application;

[0043] Figure 2 is a circuit diagram of a low-pass filter according to an embodiment of the present application;

[0044] Figure 3 is a circuit diagram of a frequency divider according to an embodiment of the present application;

[0045] Figure 4 (a) is a simulation diagram of the input and feedback signals applied under a clock frequency input of 90 MHz, Figure 4 (b) is a simulation diagram of the output of the charge pump, Figure 4 (c) is a simulation diagram of the voltage output of the VCO;

[0046] Figure 5 (a) is a simulation diagram of the input and feedback signals applied under a clock frequency input of 7.5 MHz, Figure 5 (b) is a simulation diagram of the output of the charge pump, Figure 5 (c) is a simulation diagram of the voltage output of the VCO. Detailed Embodiments

[0047] The following illustrates the embodiments of the present application through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0048] It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present application in a schematic manner. Therefore, only the components related to the present application are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0049] Although terms such as "first", "second", "A", and "B" may be used herein to describe various elements, these elements should not be limited by these terms and are only used to distinguish one element from another. For example, without departing from the scope of the following technology, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element. The term "and / or" includes combinations of multiple related items or any item among multiple related items.

[0050] As used herein, unless the context otherwise indicates, the singular forms are also intended to include the plural forms. It will be understood that the term "comprising" means the presence of the described features, quantities, steps, operations, elements, or combinations thereof, but does not exclude the presence or addition of one or more other features, quantities, steps, operations, elements, components, or combinations thereof.

[0051] Before the detailed description, it is intended to clarify that the division of components in this specification is only based on the main functions of each component. That is, two or more components described below may be combined into one component, or may be divided into two or more components according to more detailed functions. In addition to the main functions of the components, each component described below may also perform some or all of the functions of other components, and some of the main functions of each component may be specifically performed by other components.

[0052] The phase-locked loop circuit is a negative feedback system. The basic phase-locked loop includes three essential circuit modules: a phase detector (PD), a loop filter (LPF), and a voltage-controlled oscillator (VCO). The phase detector compares the input reference clock signal and the clock signal fed back by the voltage-controlled oscillator, and the output signal is a measure of the phase difference between the two. This phase difference is filtered through a filter to remove the high-frequency components in the signal, and the output signal is used as the control signal for the voltage-controlled oscillator to change the oscillation frequency of the voltage-controlled oscillator, so that the phase difference between the output signal of the voltage-controlled oscillator and the reference clock is reduced, achieving the locking function. The charge pump type phase-locked loop has been widely studied and applied due to its wide capture range and small locking error.

[0053] Compared with the basic phase-locked loop structure, because it requires a certain frequency capture ability, based on this, the present application provides a phase-locked loop applied to a wide frequency range of multi-frequency point output, such as Figure 1 As shown, the phase-locked loop applied to a wide frequency range of multi-frequency point output includes:

[0054] A Phase Frequency Detector (PFD) is used to detect the frequency and phase of an input signal and a divided signal, and outputs a pull-up control signal and a pull-down control signal for a charge pump according to the detection results.

[0055] The charge pump is connected to the Phase Frequency Detector, and is used to generate a pull-up current according to the pull-up control signal and a pull-down current according to the pull-down control signal, and to subtract the pull-up current from the pull-down current.

[0056] The low-pass filter is connected to the output terminal of the charge pump, and is used to integrate the difference between the pull-up current and the pull-down current into a control voltage for a voltage-controlled oscillator.

[0057] The voltage-controlled oscillator is connected to the low-pass filter, and is used to output a clock signal according to the control voltage.

[0058] The frequency divider is connected to the voltage-controlled oscillator, and is used to divide the clock signal to obtain a divided signal, and input the divided signal into the Phase Frequency Detector.

[0059] In this application, the phase detector in the basic phase-locked loop is replaced by a Phase Frequency Detector (PFD), a charge pump is added between the Phase Frequency Detector and the low-pass filter, and a frequency divider is added to the feedback loop between the Phase Frequency Detector and the voltage-controlled oscillator. According to different division ratios, clock signals of multiple frequency points are output. The working principle of the charge pump phase-locked loop is the same as that of the basic phase-locked loop. When the loop starts, if there is a frequency difference between the input reference clock and the feedback clock, the Phase Frequency Detector realizes the frequency detection function. When the frequencies of the two are the same, the Phase Frequency Detector realizes the phase detection function. Whether it is frequency detection or phase detection, different-width pulse signals are output to control the charge pump switch to generate a pull-up current (Iup) and a pull-down current (Idown). The difference between the two currents is integrated by the low-pass filter into a control voltage for the voltage-controlled oscillator, so as to modulate the frequency of the VCO, and finally realize the locked state of the phase-locked loop.

[0060] In an embodiment, the low-pass filter includes a first filter and a second filter; when the input signal is a high-frequency signal, the first filter integrates the difference between the pull-up current and the pull-down current into a control voltage for the voltage-controlled oscillator; when the input signal is a low-frequency signal, the second filter integrates the difference between the pull-up current and the pull-down current into a control voltage for the voltage-controlled oscillator.

[0061] Please refer to Figure 2 , the first filter includes: a second capacitor C2, a third capacitor C3, a first resistor R1, and a second resistor R2.

[0062] One end of the first resistor R1 is connected to one end of the second resistor R2 to form a first connection node, and the first connection node is connected to the output end of the charge pump; the other end of the second resistor R2 is respectively connected to the upper plate of the third capacitor C3 and the input end of the voltage-controlled oscillator; the lower plate of the third capacitor C3 is grounded; the other end of the first resistor R1 is connected to the upper plate of the second capacitor C2, and the lower plate of the second capacitor C2 is respectively grounded.

[0063] When the input signal is a high-frequency signal, the first filter includes the first resistor R1, the second resistor R2, the second capacitor C2 and the third capacitor C3. One end of the first resistor R1 is connected to one end of the second resistor R2 and the output of the charge pump. The upper plate of the second capacitor C2 is connected to the first resistor R1. One end of the first resistor R1 is connected to the upper plate of the second capacitor C2. The lower plate of the second capacitor C2 is grounded. One end of the second resistor R2 is connected to the output of the charge pump and one end of the first resistor R1, and the other end is connected to the bias module in the voltage-controlled oscillator and the upper plate of the third capacitor C3. The upper plate of the third capacitor C3 is connected to one end of the second resistor R2 and the bias circuit module in the voltage-controlled oscillator. The lower plate of the third capacitor C3 is grounded. The first resistor R1 and the second capacitor C2 are connected in series, and the second resistor R2 and the third capacitor C3 are connected in series, and the two are connected in parallel to form a second-order low-pass filter.

[0064] Please refer to Figure 2 , the second filter includes: the first capacitor C1, the second capacitor C2, the third capacitor C3, the first resistor R1, the second resistor R2; one end of the first resistor R1 is connected to one end of the second resistor R2 to form a first connection node, and the first connection node is connected to the output end of the charge pump; the other end of the second resistor R2 is respectively connected to the upper plate of the third capacitor C3 and the input end of the voltage-controlled oscillator; the lower plate of the third capacitor C3 is grounded; the other end of the first resistor R1 is connected to the upper plate of the second capacitor to form a second connection node, the second connection node is connected to the upper plate of the first capacitor C1, and the lower plates of the first capacitor C1 and the second capacitor C2 are respectively grounded.

[0065] In an embodiment, the low-pass filter further includes: a switch;

[0066] The upper plate of the first capacitor is connected to one end of the switch, and the second connection node is connected to the other end of the switch; the switch includes an enable end OE, and when the signal received by the enable end is enabled, the switch conducts.

[0067] When the input signal is a low-frequency signal and the frequency detection circuit detects a low clock frequency, the enable terminal of the switch in the low-pass filter circuit is enabled, connecting the large capacitor C1 into the low-pass filter circuit. The lower plate of the first capacitor C1 is grounded, the upper plate of the first capacitor C1 is connected to the transmission signal terminal of the switch, the upper plate of the second capacitor C2 is connected to the other transmission terminal of the switch and one end of the first resistor R1, the lower plate of the second capacitor C2 is grounded, one end of the first resistor R1 is connected to the upper plate of the second capacitor C2 and one end of the switch transmission terminal, and the other end is connected to one end of the second resistor R2 and the output terminal of the charge pump. One end of the second resistor R2 is connected to the output of the charge pump and one end of the first resistor R1, and the other end is connected to the upper plate of the second capacitor C2 and the bias module in the voltage-controlled oscillator. The upper plate of the second capacitor C2 is connected to one end of the second resistor R2 and the bias module in the voltage-controlled oscillator, and the lower plate of the second capacitor C2 is grounded. The low-pass filter connects the large capacitor C1 and the second capacitor C2 in parallel and then in series with the first resistor R1. The second resistor R2 is in series with the third capacitor C3, and the two are then in parallel. The purpose of connecting the first capacitor C1 in parallel is to ensure that the voltage stably output by the charge pump under the low-frequency clock input enables the bias module in the voltage-controlled oscillator to work properly.

[0068] Please refer to Figure 3 , the frequency divider includes a first frequency divider and a second frequency divider. The first frequency divider outputs a first divided frequency signal, and the second frequency divider outputs a second divided frequency signal;

[0069] When the input signal is a high-frequency signal, the clock signal is frequency-divided by the first frequency divider to obtain a first divided frequency signal, and the first divided frequency signal is input into the frequency discriminator and phase detector;

[0070] When the input signal is a low-frequency signal, the clock signal is frequency-divided by the first frequency divider and the second frequency divider to obtain a second divided frequency signal, and the second divided frequency signal is input into the frequency discriminator and phase detector.

[0071] Please refer to Figure 3 , the first frequency divider includes:

[0072] A first input terminal Vcp1, connected to the output terminal of the voltage-controlled oscillator;

[0073] A first control terminal X1, receiving a first control signal

[0074] A second control terminal X2, receiving a second control signal;

[0075] A first output terminal, outputting a first divided frequency signal according to the first control signal and the second control signal;

[0076] The control unit includes:

[0077] A second input terminal A, connected to the first output terminal of the first frequency division unit;

[0078] A third control terminal S3, which receives a third control signal;

[0079] A second output terminal Vback, which is connected to one of the input terminals of the frequency discriminator and phase detector, outputs a first divided-frequency signal according to the third control signal and inputs the first divided-frequency signal to the frequency discriminator and phase detector.

[0080] Please refer to Figure 3 , the second frequency divider includes:

[0081] A third input terminal Vcp2, which is connected to the first output terminal of the first frequency division unit;

[0082] A fourth control terminal S1, which receives a fourth control signal;

[0083] A fifth control terminal S2, which receives a fifth control signal;

[0084] A third output terminal, which outputs a third divided-frequency signal according to the third control signal and the fourth control signal;

[0085] The control unit further includes:

[0086] A fourth input terminal B, which is connected to the third output terminal of the second frequency division unit;

[0087] The second output terminal outputs a second divided-frequency signal according to the third control signal, and the second divided-frequency signal is the product of the first divided-frequency signal and the third divided-frequency signal.

[0088] The frequency divider mainly consists of two stages of frequency dividers, namely the first frequency divider and the second frequency divider. The first frequency divider can achieve frequency division by 6, 7, and 8. Vcp1 is the output timing signal of the voltage-controlled oscillator, connected to the first input terminal of the first frequency divider. The first control terminal X1 and the second control terminal X2 are the control signals of the first frequency divider, that is, the first control signal and the second control signal. GND is the ground signal, and VS1 is the power supply signal. When the first control signal X1 = 0, the second control signal X2 = 0 or the first control signal X1 = 1, the second control signal X2 = 1, frequency division by 7 is achieved; when the first control signal X1 = 0, the second control signal X2 = 1, frequency division by 8 is achieved; when the first control signal X1 = 1, the second control signal X2 = 0, frequency division by 6 is achieved. The second frequency divider can achieve frequency division by 2, 4, 8, and 16. Vcp2 is the output of the first frequency divider and also the input of the second frequency divider, connected to the third input terminal of the second frequency divider. The fourth control terminal S1 and the fifth control terminal S2 are the control terminals of the second frequency divider, respectively outputting the fourth control signal and the fifth control signal. GND is the ground signal, and VS1 is the power supply signal. When the fourth control signal S1 = 0, the fifth control signal S2 = 0, frequency division by 2 can be achieved; when the fourth control signal S1 = 0, the fifth control signal S2 = 1, frequency division by 4 can be achieved; when the fourth control signal S1 = 1, the fifth control signal S2 = 0, frequency division by 8 can be achieved; when the fourth control signal S1 = 1, the fifth control signal S2 = 1, frequency division by 16 can be achieved. In the PLL circuit at a high clock input frequency, the third control signal S3 in the control unit is 0, and the signal output from the third output terminal Vback is the signal of Vcp2, that is, the frequency divider only uses the first-stage frequency division. According to different configurations of the control signals X1 and X2, frequency division by 6, 7, and 8 can be achieved, and the circuit defaults to frequency division by 6. Under the same port configuration, in the PLL circuit at a low clock input frequency, the third control signal S3 of the control unit mux is 0 in the initial stage and then jumps to 1. In the initial stage, the frequency divider only selects the first frequency divider to achieve frequency division by 6, 7, and 8. When the third control signal S3 of the control unit mux jumps to 1, the PLL circuit uses two-stage frequency dividers. The permutations and combinations of the two cascaded frequency dividers can achieve frequency division by 12, 24, 48, 96, 14, 28, 56, 112, 16, 32, 64, and 128. By default, the first frequency divider of the circuit achieves frequency division by 6, and the second frequency divider achieves frequency division by 2 in the initial stage. After the third control signal of the control unit mux jumps to 1, the fifth control signal S2 of the second frequency divider also jumps from 0 to 1, and the second frequency divider achieves frequency division by 4, and the overall PLL circuit achieves frequency division by 24.

[0089] Different from the common operational amplifier connected in negative feedback, the phase-locked loop compares the phase rather than the voltage or current signal at the input end. Its output frequency fout can accurately track the reference frequency fin or output at a certain multiple. The output clock satisfies fout = α·fin in terms of frequency, where α is the frequency multiplication factor. When the phase-locked loop circuit starts with a high-frequency input of 90 MHz, the frequency discriminator and phase detector, and the charge pump work. The switch in the low-pass filter is turned off, and the large capacitor is not connected. The difference between the pull-up and pull-down currents of the charge pump is integrated through the low-pass filter and converted into the control voltage of the voltage-controlled oscillator, thereby modulating the frequency of the voltage-controlled oscillator. In the case of a high-frequency clock signal input, only the first frequency divider is used in the frequency divider, and 6-divider, 7-divider, and 8-divider can be achieved. That is, according to different circuit configurations, the voltage-controlled oscillator can output frequencies of 540 MHz, 630 MHz, and 720 MHz. The circuit is default set to 6-divider, that is, the output is 540 MHz. The simulation results of the input signal, feedback signal, charge pump output, and VCO output of the phase-locked loop circuit are as Figure 4 shown. Figure 4 (a) shows the input and feedback signals applied under a clock frequency input of 90 MHz. It can be seen that they are of the same frequency and in phase in the stable state; Figure 4 (b) shows the output of the charge pump. In the stable state, it is 1.07529 V. The MOS transistor in the bias circuit of the voltage-controlled oscillator can work at the normal static operating point with this voltage value; Figure 4 (c) shows the voltage output of the voltage-controlled oscillator. It can be seen that it can normally output a clock frequency of 540 MHz at 6-divider.

[0090] When the phase-locked loop circuit starts with a low-frequency input of 7.5 MHz, the frequency discriminator and phase detector, and the charge pump work. The switch in the low-pass filter is turned off, and the large capacitor is connected. The difference between the pull-up and pull-down currents of the charge pump is integrated through the low-pass filter and converted into the control voltage of the voltage-controlled oscillator, thereby modulating the frequency of the voltage-controlled oscillator. When a low-frequency clock signal is input, the frequency divider uses two cascaded stages. Multiple frequency points of 12-divider, 24-divider, 48-divider, 96-divider, 14-divider, 28-divider, 56-divider, 112-divider, 16-divider, 32-divider, 64-divider, and 128-divider can be achieved under different configurations. That is, according to different circuit configurations, the voltage-controlled oscillator can output a minimum frequency of 90 MHz and a maximum output frequency of 960 MHz. The circuit is default set to achieve 6-divider in the first stage and 4-divider in the second stage, and the output of the VCO is 180 MHz. The simulation results of the input and feedback signals, charge pump output, and voltage-controlled oscillator output of the phase-locked loop circuit are as Figure 5 shown. Figure 5 (a) shows the input and feedback signals applied under a clock frequency input of 7.5 MHz. It can be seen that they are of the same frequency and in phase in the stable state; Figure 5(b) is the output of the charge pump. In the initial state, the output of the charge pump is 497.5 mV. This output voltage in the bias circuit of the voltage-controlled oscillator easily makes the NMOS transistor in a critical operating state, resulting in unstable output of the voltage-controlled oscillator. Therefore, when the 7.5 MHz clock frequency is input, the switch in the low-pass filter conducts to connect the large capacitor C1 into the circuit, making the charge pump output 664.06 mV, enabling the normal operation of the voltage-controlled oscillator. At the same time, the mux circuit in the frequency divider selects a two-stage cascaded frequency divider, defaulting to a 24-frequency division, that is, the voltage-controlled oscillator outputs a clock frequency of 180 MHz, and the simulation results are as Figure 5 shown in (c).

[0091] Based on the traditional charge pump phase-locked loop circuit, the present invention proposes a PLL circuit with a wide frequency range. The circuit uses a second-order low-pass filter. A large capacitor C1 of the nF level is connected in parallel through a switch at the upper plate node A of the capacitor C2. At low-frequency input, this large capacitor can be connected into the circuit, so that the output voltage of the charge pump of the circuit can pass through the low-pass filter without being too low to prevent the bias circuit in the voltage-controlled oscillator from working properly. And a switch is connected to select not to connect the large capacitor at high clock frequency input. At high clock frequency input, the charge pump can also output quickly and stably. Compared with the traditional single-stage frequency divider, the present invention uses two-stage frequency dividers in series. Through the control unit, the two-stage frequency dividers are cascaded, enabling the circuit to achieve multi-frequency point output. When the PLL circuit is input with a high clock frequency, the switch control signal in the low-pass filter is turned off, and Vback of the control unit of the frequency divider selects the output of Vcp2 under the switch control signal S3, and the circuit realizes 6-frequency division, 7-frequency division, and 8-frequency division; when the PLL circuit is input with a low clock frequency, the switch control signal in the low-pass filter is turned off at the initial stage and then always on. At the initial stage, the large capacitor C1 is not connected into the circuit, and the output voltage of the charge pump is too low, which easily causes unstable output of the circuit. Connecting the large capacitor C1 into the PLL circuit enables the circuit to output stably at the charge pump output and the output voltage enables the bias circuit to work properly in the bias circuit module of the voltage-controlled oscillator (VCO). Vback in the control unit of the frequency divider selects the output of Vcp2 at the initial stage under the switch control signal S3 and then selects the B port output, that is, selects the output of the first frequency divider at the initial stage, realizing 6-frequency division, 7-frequency division, and 8-frequency division. After a period of time, it selects the cascaded output of the two-stage frequency divider. According to different configurations of the two-stage frequency divider, 12-frequency division, 24-frequency division, 48-frequency division, 96-frequency division, 14-frequency division, 28-frequency division, 56-frequency division, 112-frequency division, 16-frequency division, 32-frequency division, 64-frequency division, and 128-frequency division can be realized, achieving multiple frequency point outputs. Compared with the traditional charge pump phase-locked loop circuit, the PLL circuit of the present invention can output multiple frequency points and has a wide frequency range of applications.

[0092] The above embodiments are only used to exemplarily illustrate the principles and effects of the present application, rather than to limit the present application. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present application should still be covered by the claims of the present application.

Claims

1. A phase-locked loop for multi-frequency output with a wide frequency range, characterized in that: The phase-locked loop comprises: A frequency and phase detector, used to detect the frequency and phase of the input signal and the frequency-divided signal, and output a pull-up control signal and a pull-down control signal of the charge pump according to the detection result; A charge pump connected to the frequency detector and phase detector, used to generate a pull-up current according to the pull-up control signal and a pull-down current according to the pull-down control signal, and to make a difference between the pull-up current and the pull-down current; A low-pass filter connected to the output end of the charge pump, and used for integrating the difference between the pull-up current and the pull-down current and converting it into a control voltage of the voltage-controlled oscillator; a voltage-controlled oscillator, connected to the low-pass filter, and configured to output a clock signal according to the control voltage; The frequency divider is connected to the voltage-controlled oscillator and is used for performing frequency division processing on the clock signal to obtain a frequency division signal, and inputting the frequency division signal into the frequency and phase detector.

2. The phase-locked loop for multi-frequency output with a wide frequency range according to claim 1, characterized in that: The low-pass filter includes a first filter and a second filter; when the input signal is a high-frequency signal, the first filter integrates the difference between the pull-up current and the pull-down current and converts it into a control voltage of the voltage-controlled oscillator; when the input signal is a low-frequency signal, the second filter integrates the difference between the pull-up current and the pull-down current and converts it into a control voltage of the voltage-controlled oscillator.

3. The phase-locked loop for multi-frequency output with a wide frequency range according to claim 2, characterized in that: The first filter comprises: a second capacitor, a third capacitor, a first resistor, and a second resistor; One end of the first resistor is connected to one end of the second resistor to form a first connection node, and the first connection node is connected to the output end of the charge pump; the other end of the second resistor is respectively connected to the upper plate of the third capacitor and the input end of the voltage-controlled oscillator; the lower plate of the third capacitor is grounded; the other end of the first resistor is connected to the upper plate of the second capacitor, and the lower plates of the second capacitor are respectively grounded.

4. The phase-locked loop for multi-frequency output with a wide frequency range according to claim 2, characterized in that: The second filter comprises: a first capacitor, a second capacitor, a third capacitor, a first resistor, and a second resistor; One end of the first resistor is connected to one end of the second resistor to form a first connection node, and the first connection node is connected to the output end of the charge pump; the other end of the second resistor is respectively connected to the upper plate of the third capacitor and the input end of the voltage-controlled oscillator; the lower plate of the third capacitor is grounded; the other end of the first resistor is connected to the upper plate of the second capacitor to form a second connection node, the second connection node is connected to the upper plate of the first capacitor, and the lower plate of the first capacitor and the lower plate of the second capacitor are respectively grounded.

5. The phase-locked loop for multi-frequency output with a wide frequency range according to claim 4, characterized in that: The low-pass filter further comprises: a switch; The upper plate of the first capacitor is connected to one end of the switch, and the second connection node is connected to the other end of the switch; the switch includes an enable end, and when the signal received by the enable end is enabled, the switch is turned on.

6. The phase-locked loop for multi-frequency output with a wide frequency range according to claim 1, characterized in that: The frequency divider comprises a first frequency divider and a second frequency divider, the first frequency divider outputs a first frequency divided signal, and the second frequency divider outputs a second frequency divided signal; When the input signal is a high-frequency signal, the clock signal is frequency-divided by a first frequency divider to obtain a first frequency-divided signal, and the first frequency-divided signal is input into the frequency and phase detector; When the input signal is a low-frequency signal, the clock signal is frequency-divided by the first frequency divider and the second frequency divider to obtain a second frequency-divided signal, and the second frequency-divided signal is input into the frequency and phase detector.

7. The phase-locked loop for multi-frequency output with a wide frequency range according to claim 6, characterized in that: The first frequency divider comprises: A first input terminal connected to the output terminal of the voltage-controlled oscillator; A first control terminal receives a first control signal A second control terminal receives a second control signal; A first output terminal, outputting a first frequency-divided signal according to the first control signal and the second control signal; Control unit, comprising: A second input terminal connected to the first output terminal of the first frequency dividing unit; A third control terminal receives a third control signal; The second output terminal is connected to one of the input terminals of the phase frequency detector, outputs a first frequency-divided signal according to the third control signal, and inputs the first frequency-divided signal to the phase frequency detector.

8. The phase-locked loop for multi-frequency output in a wide frequency range according to claim 7, characterized in that: The second frequency divider comprises: A third input terminal connected to the first output terminal of the first frequency dividing unit; A fourth control terminal, receiving a fourth control signal; A fifth control terminal, receiving a fifth control signal; A third output terminal, outputting a third frequency-divided signal according to the third control signal and the fourth control signal; The control unit also includes: a fourth input terminal connected to the third output terminal of the second frequency dividing unit; The second output terminal outputs a second frequency-divided signal according to the third control signal, where the second frequency-divided signal is a product of the first frequency-divided signal and the third frequency-divided signal.

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