Charge sampling phase-locked loop with wide locking range and control method thereof
By introducing a pulse width sampling frequency lock module into the charge sampling phase-locking loop, the signal period output by the control voltage-controlled oscillator is twice the preset pulse width square wave signal, solving the problem of limited locking range of the charge sampling phase-locking loop, achieving the effect of wide locking range and low noise.
Patent Information
- Application Number
- CN202510008740.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-03
- Publication Date
- 2025-05-30
AI Technical Summary
The locking range of the existing charge sampling phase lock loop is limited, and a wider locking range cannot be achieved, resulting in the gain of the charge sampling phase detector cannot reach the maximum value and the phase noise cannot reach the optimal level.
The charge sampling phase lock loop is adopted that includes a pulse width sampling frequency lock module and a charge sampling phase lock module. The pulse width sampling frequency lock is realized through the crystal oscillator, the sampling and holding unit and the comparison and logic unit. The signal period output by the control voltage-controlled oscillator is twice the pulse width of the input buffer output signal.
A wide locking range and low noise charge sampling phase-locking loop is realized, ensuring a wide tuning range and reducing the overall power consumption of the phase-locking loop, maximizing the gain of the charge sampling phase detector, and suppressing the contribution of in-band phase noise.
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Figure CN120074507A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical fields of frequency synthesis and phase locking, and in particular to a charge sampling phase-locked loop with a wide locking range and a control method therefor. Background Art
[0002] The charge sampling phase-locked loop uses the method of charge sampling to detect the phase difference, and adjusts the frequency of the voltage-controlled oscillator to keep the phase of the output signal synchronized with the reference signal. However, the locking range of the charge sampling phase-locked loop in the prior art is relatively limited, usually only covering a frequency range of several megahertz (MHz). To achieve a wider locking range, it is necessary to use a traditional charge pump phase-locked loop with a dead zone for frequency locking. This kind of phase-locked loop cannot lock the output frequency exactly at twice the frequency of the reference clock, resulting in the gain of the charge sampling phase detector not reaching the maximum value, and the phase noise (PN) not being optimal either. Another non-divide-by-N wide-frequency locking loop using unequal-delay sampling cannot achieve high-precision frequency locking due to a time error of plus or minus one-quarter of an oscillator period in the sampling timestamp, so it is not applicable to the charge sampling phase-locked loop. Summary of the Invention
[0003] To solve the above technical problems, the purpose of the present invention is to provide a charge sampling phase-locked loop with a wide locking range and low noise and a control method therefor.
[0004] To achieve the above object, one aspect of the embodiments of the present application proposes a charge sampling phase-locked loop with a wide locking range, which includes a pulse width sampling frequency locking module and a charge sampling phase-locking module. The pulse width sampling frequency locking module includes a crystal oscillator, a sample and hold unit, and a comparison and logic unit. The charge sampling phase-locking module includes an input buffer, a charge sampling phase detector, and a voltage-controlled oscillator. The crystal oscillator is connected to the input buffer. The input buffer, the sample and hold unit, and the voltage-controlled oscillator are all connected to the charge sampling phase detector. The sample and hold unit and the voltage-controlled oscillator are both connected to the comparison and logic unit. The crystal oscillator is used to output a first sine wave signal. The voltage-controlled oscillator is used to output a second sine wave signal. The input buffer is used to convert the first sine wave signal into a preset pulse width square wave signal. The charge sampling phase detector is used to sample the second sine wave signal according to the preset pulse width square wave signal to obtain a voltage difference signal. The voltage difference signal is used to control the voltage-controlled oscillator with a first control accuracy so that the voltage-controlled oscillator is phase-locked with the preset pulse width square wave signal. The sample and hold unit is used to sample the second sine wave signal according to the preset pulse width square wave signal to obtain a sampled voltage. The comparison and logic unit is used to output a first control signal according to the sampled voltage. The first control signal is used to control the voltage-controlled oscillator with a second control accuracy so that the period of the signal output by the voltage-controlled oscillator is twice the period of the preset pulse width square wave signal.
[0005] In some embodiments, the charge sampling phase-locking module further includes a loop filter. The charge sampling phase detector and the voltage-controlled oscillator are both connected to the loop filter. The loop filter is used to obtain a second control signal for controlling the frequency of the voltage-controlled oscillator according to the voltage difference signal, and further make the waveform phase of the second sine wave signal equal to the phase of the preset pulse width square wave signal according to the second control signal.
[0006] In some embodiments, the sample and hold unit includes a first delay unit and a second delay unit. The charge sampling phase detector, the comparison and logic unit, and the input buffer are all connected to the first delay unit. The charge sampling phase detector, the comparison and logic unit, and the input buffer are all connected to the second delay unit. The first delay unit and the second delay unit are used to delay the preset pulse width square wave signal to obtain a square wave delay signal.
[0007] To achieve the above object, another aspect of the embodiments of the present application proposes a control method for a charge sampling phase-locked loop with a wide locking range, including the following steps:
[0008] Output a first sine wave signal through a crystal oscillator;
[0009] Output a second sine wave signal through a voltage-controlled oscillator;
[0010] Convert the first sine wave signal into a preset pulse-width square wave signal through an input buffer;
[0011] Sample the second sine wave signal according to the preset pulse-width square wave signal through a charge sampling phase detector to obtain a voltage difference signal, and the voltage difference signal is used to control the voltage-controlled oscillator with a first control accuracy so that the voltage-controlled oscillator is phase-locked with the preset pulse-width square wave signal;
[0012] Sample the second sine wave signal according to the preset pulse-width square wave signal through a sample and hold unit to obtain a sampled voltage;
[0013] Output a first control signal according to the sampled voltage through a comparison and logic unit, and the first control signal is used to control the voltage-controlled oscillator with a second control accuracy so that the period of the signal output by the voltage-controlled oscillator is twice the period of the preset pulse-width square wave signal.
[0014] In some embodiments, the step of sampling the second sine wave signal according to the preset pulse-width square wave signal through a charge sampling phase detector to obtain a voltage difference signal is specifically:
[0015] Convert the phase difference between the second sine wave signal and the preset pulse-width square wave signal into the voltage difference signal through capacitor integration.
[0016] In some embodiments, the control method further includes:
[0017] Obtain a second control signal for controlling the frequency of the voltage-controlled oscillator according to the voltage difference signal through a loop filter, and then make the waveform phase of the second sine wave signal equal to the phase of the preset pulse-width square wave signal according to the second control signal.
[0018] In some embodiments, the second sine wave signal includes a second positive-phase sine wave signal and a second anti-phase sine wave signal, and the sampled voltage includes a first rising-edge sampled voltage, a first falling-edge sampled voltage, and a second rising-edge sampled voltage. The step of sampling the second sine wave signal according to the preset pulse-width square wave signal through a sample and hold unit to obtain a sampled voltage specifically includes:
[0019] Sample the second positive-phase sine wave signal output by the voltage-controlled oscillator at the rising edge of the preset pulse-width square wave signal to obtain the first rising-edge sampled voltage;
[0020] Sample the second positive-phase sine wave signal output by the voltage-controlled oscillator at the falling edge of the preset pulse-width square wave signal to obtain the first falling-edge sampled voltage;
[0021] Sample the second inverted sine wave signal output by the voltage-controlled oscillator at the rising edge of the preset pulse width square wave signal to obtain the second rising edge sampling voltage.
[0022] In some embodiments, the control method further includes:
[0023] Delay the preset pulse width square wave signal through a first delay unit and a second delay unit to obtain a square wave delay signal.
[0024] In some embodiments, the control method further includes a step of sampling the second non-inverted sine wave signal by the sample and hold unit according to the square wave delay signal to obtain a third rising edge sampling voltage. Specifically:
[0025] Sample the second non-inverted sine wave signal output by the voltage-controlled oscillator at the rising edge of the square wave delay signal to obtain the third rising edge sampling voltage.
[0026] In some embodiments, the output of the first control signal by the comparison and logic unit according to the sampling voltage specifically includes:
[0027] Compare the first rising edge sampling voltage and the third rising edge sampling voltage to obtain the edge region relationship of the rising edge of the square wave signal corresponding to the second sine wave signal;
[0028] Compare the first rising edge sampling voltage and the second rising edge sampling voltage to obtain the voltage amplitude relationship between the sampling voltage and the common mode voltage of the voltage-controlled oscillator;
[0029] Determine the region of the rising edge of the square wave signal corresponding to the second sine wave signal according to the edge region relationship and the voltage amplitude relationship;
[0030] Compare the first rising edge sampling voltage and the first falling edge sampling voltage, and then obtain the correlation relationship between the frequency of the voltage-controlled oscillator and the pulse width of the square wave signal according to the comparison result and the region;
[0031] Output the first control signal according to the correlation relationship.
[0032] The beneficial effects of the present invention are as follows: A charge sampling phase-locked loop with a wide locking range and its control method according to the present invention includes a pulse width sampling frequency locking module and a charge sampling phase locking module. The pulse width sampling frequency locking module includes a crystal oscillator, a sample and hold unit, and a comparison and logic unit. The charge sampling phase locking module includes an input buffer, a charge sampling phase detector, and a voltage-controlled oscillator. On the one hand, the present invention introduces a pulse width sampling frequency locking module into the traditional charge sampling phase-locked loop, which can achieve the locking of the output signal frequency without using the high-power and narrow-bandwidth current-mode frequency divider in the traditional phase-locked loop, thereby ensuring a wide tuning range and reducing the overall power consumption of the phase-locked loop. On the other hand, by controlling the signal period output by the voltage-controlled oscillator through the pulse width sampling frequency locking module to be exactly twice the pulse width of the output signal of the input buffer, the gain of the charge sampling phase detector can be maximized, thereby effectively suppressing the contribution of the charge sampling phase detector to the in-band phase noise of the phase-locked loop output signal. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following introduces the drawings required to be used in the embodiments of the present invention. It should be understood that the drawings introduced below only facilitate the clear expression of some embodiments of the technical solutions in the present invention. For those skilled in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0034] Figure 1 FIG. is a structural block diagram of a charge sampling phase-locked loop with a wide locking range provided by an embodiment of the present invention;
[0035] Figure 2 FIG. is a circuit schematic diagram of a charge sampling phase detector provided by an embodiment of the present invention;
[0036] Figure 3 FIG. is another structural block diagram of a charge sampling phase-locked loop with a wide locking range provided by an embodiment of the present invention;
[0037] Figure 4 FIG. is a circuit schematic diagram of a charge sampling phase-locked loop with a wide locking range provided by an embodiment of the present invention;
[0038] Figure 5 FIG. is a step flow chart of a control method for a charge sampling phase-locked loop with a wide locking range provided by an embodiment of the present invention;
[0039] Figure 6 FIG. is a schematic diagram of a pulse width sampling principle provided by an embodiment of the present invention.
[0040] Reference numerals: R01, first resistor; R02, second resistor; Q01, first transistor; Q02, second transistor; C01, first capacitor; C02, second capacitor. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0041] In order to make the objectives, technical solutions and advantages of the present application clearer and more understandable, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application. When the following description involves the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the embodiments of the present application. They are only examples of devices and methods consistent with some aspects of the embodiments of the present application detailed in the appended claims.
[0042] It can be understood that the terms "first", "second", etc. used in the present application can be used in this article to describe various concepts, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of the present application, the first information can also be referred to as the second information. Similarly, the second information can also be referred to as the first information. Depending on the context, the words "if", "when" as used herein can be interpreted as "when...", "when...", or "in response to determining".
[0043] The terms "at least one", "multiple", "each", "any one", etc. used in the present application, at least one includes one, two or more than two, multiple includes two or more than two, each refers to each of the corresponding multiple, and any one refers to any one of the multiple.
[0044] The charge sampling phase-locked loop uses the charge sampling method to detect the phase difference, and adjusts the frequency of the voltage-controlled oscillator to keep the phase of the output signal synchronized with the reference signal. However, the locking range of the charge sampling phase-locked loop in the prior art is relatively limited, usually only covering a frequency range of a few megahertz (MHz). To achieve a wider locking range, a traditional charge pump phase-locked loop with a dead zone must be used for frequency locking. This phase-locked loop cannot lock the output frequency exactly at twice the frequency of the reference clock, resulting in the gain of the charge sampling phase detector not reaching the maximum value, and the phase noise (PN) not being optimal either. Another non-divider wide-frequency frequency-locked loop using unequal delay sampling cannot achieve high-precision frequency locking due to the time error of plus or minus one-quarter of the oscillator period in the sampling timestamp, so it is not applicable to the charge sampling phase-locked loop.
[0045] To this end, an embodiment of the present invention proposes a charge sampling phase-locked loop with a wide locking range, which includes a pulse width sampling frequency locking module and a charge sampling phase locking module. The pulse width sampling frequency locking module includes a crystal oscillator, a sample and hold unit, and a comparison and logic unit. The charge sampling phase locking module includes an input buffer, a charge sampling phase detector, and a voltage-controlled oscillator. On the one hand, the present invention introduces a pulse width sampling frequency locking module into the traditional charge sampling phase-locked loop, which can achieve the locking of the output signal phase without using the high-power and narrow-bandwidth current-mode frequency divider in the traditional phase-locked loop, thereby ensuring a wide tuning range and reducing the overall power consumption of the phase-locked loop. On the other hand, by controlling the signal period output by the voltage-controlled oscillator through the pulse width sampling frequency locking module to be exactly twice the pulse width of the output signal of the input buffer, the gain of the charge sampling phase detector can be maximized, thereby effectively suppressing the contribution of the charge sampling phase detector to the in-band phase noise of the phase-locked loop output signal.
[0046] Referring to Figure 1 , Figure 1 FIG. is a structural block diagram of a charge sampling phase-locked loop with a wide locking range provided by an embodiment of the present invention. An embodiment of the present invention proposes a charge sampling phase-locked loop with a wide locking range, which includes a pulse width sampling frequency locking module and a charge sampling phase locking module. The pulse width sampling frequency locking module includes a crystal oscillator, a sample and hold unit, and a comparison and logic unit. The charge sampling phase locking module includes an input buffer, a charge sampling phase detector, and a voltage-controlled oscillator. The crystal oscillator is connected to the input buffer. The input buffer, the sample and hold unit, and the voltage-controlled oscillator are all connected to the charge sampling phase detector. The sample and hold unit and the voltage-controlled oscillator are both connected to the comparison and logic unit. The crystal oscillator is used to output a first sine wave signal. The voltage-controlled oscillator is used to output a second sine wave signal. The input buffer is used to convert the first sine wave signal into a preset pulse width square wave signal. The charge sampling phase detector is used to sample the second sine wave signal according to the preset pulse width square wave signal to obtain a voltage difference signal. The voltage difference signal is used to control the voltage-controlled oscillator with a first control accuracy so that the voltage-controlled oscillator is phase-locked with the preset pulse width square wave signal. The sample and hold unit is used to sample the second sine wave signal according to the preset pulse width square wave signal to obtain a sampled voltage. The comparison and logic unit is used to output a first control signal according to the sampled voltage. The first control signal is used to control the voltage-controlled oscillator with a second control accuracy so that the period of the signal output by the voltage-controlled oscillator is twice the period of the preset pulse width square wave signal.
[0047] Specifically, the crystal oscillator is used to generate a stable and accurate first sine wave signal. Through its own mechanical vibration characteristics, it converts the vibration frequency into an electrical signal frequency, thereby outputting a sine wave signal with a stable frequency.
[0048] An input buffer for converting a first sine wave signal from a crystal oscillator into a square wave signal with a specific pulse width (i.e., a preset pulse width square wave signal) through a digital time converter. Since the square wave signal has distinct rising and falling edges, converting the first sine wave signal into a preset pulse width square wave signal facilitates digital processing or serves as a reference signal to simplify the processing of subsequent circuits.
[0049] A charge sampling phase detector for sampling a second sine wave signal output by a voltage controlled oscillator using the preset pulse width square wave signal output by the input buffer to obtain a voltage difference signal.
[0050] A sample and hold unit for sampling the second sine wave signal output by the voltage controlled oscillator using the preset pulse width square wave signal output by the input buffer to obtain a sampled voltage. Among them, the second sine wave signal is a differential signal (including a second positive phase sine wave signal and a second inverted phase sine wave signal with opposite phases), and the sample and hold unit samples the differential signal according to the rising and falling edges of the preset pulse width square wave signal to obtain multiple sampled voltages.
[0051] A comparison and logic unit for receiving the multiple sampled voltages output by the sample and hold unit and comparing these sampled voltages to obtain the magnitude relationship between the current voltage controlled oscillator frequency and the preset pulse width square wave signal, thereby generating a first control signal for controlling the voltage controlled oscillator with a second control precision (i.e., coarse control). Specifically, the first control signal output by the comparison and logic unit adjusts the coarse tuning input of the voltage controlled oscillator so that the waveform period of its output signal is adjusted to be close to twice the period of the preset pulse width square wave signal generated by the input buffer, thereby achieving the frequency locking function.
[0052] The voltage controlled oscillator has two inputs, one voltage input for precise frequency modulation and one multi-bit digital input for coarse frequency modulation. The charge sampling phase locked module is a negative feedback that generates a second control signal for controlling the voltage controlled oscillator with a first control precision (i.e., precise control) to make the output phase of the voltage controlled oscillator equal to that of the crystal oscillator, achieving phase locking; the pulse width sampling frequency locking module generates a multi-bit digital signal (i.e., the first control signal) with a second control precision (i.e., coarse control) to control the voltage controlled oscillator so that the output signal period of the voltage controlled oscillator is twice that of the crystal oscillator, achieving frequency locking.
[0053] It should be noted that as Figure 2 shown is the circuit schematic diagram of the charge sampling phase detector. The output swing of the voltage controlled oscillator is set to A VCO and the frequency of the voltage controlled oscillator is set to ω VCO and the ratio of the output frequency of the voltage controlled oscillator to the frequency of the crystal oscillator is set to N, and the transconductance of the first transistor Q01 and the second transistor Q02 is set to G MThe resistance values of the first resistor R01 and the second resistor R02 are set to R D The pulse width of the square wave signal is set to T P , then the gain K of the charge sampling phase detector PD is calculated by the following formula:
[0054]
[0055] As can be seen from the above formula, when the frequency ω of the voltage-controlled oscillator VCO is exactly twice the pulse width T of the square wave signal P , the gain and noise of the charge sampling phase detector reach the theoretical optimal values. Therefore, in the embodiments of the present invention, by controlling the signal period output by the voltage-controlled oscillator to be exactly twice the pulse width of the output signal of the input buffer, the gain of the charge sampling phase detector is maximized, thereby suppressing the contribution of the charge sampling phase detector to the in-band phase noise of the phase-locked loop output signal.
[0056] Referring to Figure 3 , Figure 3 , which is another structural block diagram of the charge sampling phase-locked loop with a wide locking range provided by the embodiments of the present invention. Further, as an optional implementation manner, the charge sampling phase-locked module further includes a loop filter. The charge sampling phase detector and the voltage-controlled oscillator are both connected to the loop filter. The loop filter is used to obtain a second control signal for controlling the frequency of the voltage-controlled oscillator according to the voltage difference signal, and further make the waveform phase of the second sine wave signal equal to the phase of the preset pulse width square wave signal according to the second control signal.
[0057] Specifically, as shown in Figure 2 , the charge sampling phase detector samples the second sine wave output by the voltage-controlled oscillator using the preset pulse width square wave signal, converts the phase difference between the center time of the preset pulse width square wave signal and the zero-crossing point of the second sine wave signal into a charge difference sampled by the first capacitor C01 and the second capacitor C01, and further generates a voltage difference signal. This voltage difference signal is processed by the loop filter to generate a second control signal for controlling the frequency of the voltage-controlled oscillator.
[0058] Referring to Figure 4 , Figure 4 , which is the circuit schematic diagram of the charge sampling phase-locked loop with a wide locking range provided by the embodiments of the present invention. Further, as an optional implementation manner, the sample and hold unit includes a first delay unit and a second delay unit. The charge sampling phase detector, the comparison and logic unit, and the input buffer are all connected to the first delay unit. The charge sampling phase detector, the comparison and logic unit, and the input buffer are all connected to the second delay unit. The first delay unit and the second delay unit are used to delay the preset pulse width square wave signal to obtain a square wave delay signal.
[0059] Specifically, the first delay unit and the second delay unit are used to delay the preset pulse-width square wave signal output by the input buffer for a certain period of time, and output a new square wave delay signal. The second sine wave signal output by the voltage-controlled oscillator is resampled at different time points through the square wave delay signal to obtain more information about the voltage-controlled oscillator.
[0060] The structure and working principle of the charge sampling phase-locked loop with a wide locking range according to the embodiments of the present invention are described above. It can be recognized that, compared with the traditional charge sampling phase-locked loop, on the one hand, the pulse-width sampling frequency-locking module is introduced into the traditional charge sampling phase-locked loop in the present invention, which can achieve the locking of the phase of the output signal without using the high-power consumption and narrow-bandwidth current-mode frequency divider in the traditional phase-locked loop, thereby ensuring a wide tuning range and reducing the overall power consumption of the phase-locked loop; on the other hand, by controlling the signal period output by the voltage-controlled oscillator to be exactly twice the pulse width of the output signal of the input buffer through the pulse-width sampling frequency-locking module, the gain of the charge sampling phase detector can be maximized, thereby effectively suppressing the contribution of the charge sampling phase detector to the in-band phase noise of the phase-locked loop output signal.
[0061] Referring to Figure 5 Embodiments of the present invention provide a control method for a charge sampling phase-locked loop with a wide locking range, which is used to control through the charge sampling phase-locked loop with a wide locking range as described above, and includes the following steps S101 to S106:
[0062] S101. Output a first sine wave signal through a crystal oscillator;
[0063] S102. Output a second sine wave signal through a voltage-controlled oscillator;
[0064] S103. Convert the first sine wave signal into a preset pulse-width square wave signal through an input buffer;
[0065] Specifically, in the charge sampling phase-locked loop, the input buffer converts the first sine wave signal from an off-chip reference crystal oscillator into a preset pulse-width square wave signal with a specific pulse width through a digital time converter.
[0066] S104. Sample the second sine wave signal according to the preset pulse-width square wave signal through a charge sampling phase detector to obtain a voltage difference signal, and the voltage difference signal is used to control the voltage-controlled oscillator with a first control accuracy to lock the voltage-controlled oscillator with the preset pulse-width square wave signal;
[0067] Further as an optional implementation manner, the step of sampling the second sine wave signal according to the preset pulse-width square wave signal through a charge sampling phase detector to obtain a voltage difference signal may specifically be the following step S1041:
[0068] S1041. Convert the phase difference between the second sine wave signal and the preset pulse-width square wave signal into a voltage difference signal through capacitor integration.
[0069] Further as an optional implementation manner, the control method may further include the following step S114:
[0070] S114. Obtain a second control signal for controlling the frequency of the voltage-controlled oscillator according to the voltage difference signal through a loop filter, and further make the waveform phase of the second sine wave signal equal to the phase of the preset pulse-width square wave signal according to the second control signal.
[0071] Specifically, the charge sampling phase detector converts the phase difference between the second sine wave signal and the preset pulse-width square wave signal into a voltage difference through capacitor integration, and then filters the voltage difference through a loop filter to obtain a second control signal for controlling the output frequency of the voltage-controlled oscillator, so that the voltage-controlled oscillator outputs a phase equal to that of the crystal oscillator to achieve phase locking.
[0072] S105. Sample the second sine wave signal according to the preset pulse-width square wave signal through a sample-and-hold unit to obtain a sampled voltage;
[0073] Further as an optional implementation manner, the second sine wave signal includes a second positive-phase sine wave signal and a second anti-phase sine wave signal, and the sampled voltage includes a first rising-edge sampled voltage, a first falling-edge sampled voltage, and a second rising-edge sampled voltage. The step of sampling the second sine wave signal according to the preset pulse-width square wave signal through a sample-and-hold unit to obtain a sampled voltage can be further divided into the following steps S1051 to S1053:
[0074] S1051. Sample the second positive-phase sine wave signal output by the voltage-controlled oscillator at the rising edge of the preset pulse-width square wave signal to obtain a first rising-edge sampled voltage;
[0075] S1052. Sample the second positive-phase sine wave signal output by the voltage-controlled oscillator at the falling edge of the preset pulse-width square wave signal to obtain a first falling-edge sampled voltage;
[0076] S1053. Sample the second anti-phase sine wave signal output by the voltage-controlled oscillator at the rising edge of the preset pulse-width square wave signal to obtain a second rising-edge sampled voltage.
[0077] Specifically, the second sine wave signal output by the voltage-controlled oscillator is a differential signal, including a second positive-phase sine wave signal and a second inverted-phase sine wave signal with opposite phases. First, the rising edge and falling edge of the pulse-width clock signal (i.e., the preset pulse-width square wave signal) are used to sample the second positive-phase sine wave signal output by the voltage-controlled oscillator, obtaining a first rising-edge sampling voltage and a first falling-edge sampling voltage. Also, the rising edge and falling edge of the pulse-width clock signal (i.e., the preset pulse-width square wave signal) are used to sample the second inverted-phase sine wave signal output by the voltage-controlled oscillator, obtaining a second rising-edge sampling voltage and a second falling-edge sampling voltage.
[0078] Further as an optional implementation manner, the control method may further include the following step S115:
[0079] S115. Delay the preset pulse-width square wave signal through a first delay unit and a second delay unit to obtain a square wave delay signal.
[0080] Further as an optional implementation manner, the control method further includes the step of sampling the second positive-phase sine wave signal by a sample-and-hold unit according to the square wave delay signal to obtain a third rising-edge sampling voltage. This step may specifically be the following step S1054:
[0081] S1054. Sample the second positive-phase sine wave signal output by the voltage-controlled oscillator at the rising edge of the square wave delay signal to obtain a third rising-edge sampling voltage.
[0082] Specifically, the pulse-width clock signal (i.e., the preset pulse-width square wave signal) is sent into a delay unit, and the delay unit will output a new clock signal that is delayed relative to the original clock signal, i.e., the square wave delay signal. Using the rising edge of this square wave delay signal, sample the second positive-phase sine wave signal output by the voltage-controlled oscillator again to obtain a third rising-edge sampling voltage. Further, use the rising edge of this square wave delay signal to sample the second inverted-phase sine wave signal to obtain a fourth rising-edge sampling voltage.
[0083] S106. Output a first control signal through a comparison and logic unit according to the sampling voltage. The first control signal is used to control the voltage-controlled oscillator with a second control accuracy so that the period of the signal output by the voltage-controlled oscillator is twice the period of the preset pulse-width square wave signal.
[0084] Further as an optional implementation manner, the step of outputting a first control signal through a comparison and logic unit according to the sampling voltage may specifically be divided into the following steps S1061 to S1065:
[0085] S1061. Compare the first rising-edge sampling voltage and the third rising-edge sampling voltage to obtain the edge region relationship between the rising edge of the square wave signal and the second sine wave signal;
[0086] Specifically, because of the time delay, the third rising-edge sampling voltage lags slightly behind the first rising-edge sampling voltage in time. Therefore, by comparing the first rising-edge sampling voltage and the third rising-edge sampling voltage, it can be determined whether the rising edge of the pulse-width clock signal (i.e., the preset pulse-width square-wave signal) is in the rising region or the falling region of the sine wave.
[0087] S1062. Compare the first rising-edge sampling voltage and the second rising-edge sampling voltage to obtain the voltage amplitude relationship corresponding to the sampling voltage and the common-mode voltage of the voltage-controlled oscillator.
[0088] Specifically, by comparing the first rising-edge sampling voltage and the second rising-edge sampling voltage, the magnitude relationship between the sampling voltage and the oscillator common-mode voltage (i.e., the average value of the two differential signals) can be understood.
[0089] S1063. Determine the region of the rising edge of the square-wave signal in the second sine-wave signal according to the edge-region relationship and the voltage amplitude relationship.
[0090] S1064. Compare the first rising-edge sampling voltage and the first falling-edge sampling voltage, and then obtain the correlation relationship between the frequency of the voltage-controlled oscillator and the pulse width of the square-wave signal according to the comparison result and the region.
[0091] S1065. Output the first control signal according to the correlation relationship.
[0092] Specifically, as Figure 6 shown in the schematic diagram of the pulse-width sampling principle, combining the edge-region relationship and the voltage amplitude relationship obtained from the foregoing comparison, it can be determined which region among regions 1-4 in Figure 6 the rising edge of the pulse-width clock signal (i.e., the preset pulse-width square-wave signal) is in. After determining the region, by comparing the first rising-edge sampling voltage and the first falling-edge sampling voltage, the correlation relationship between the current frequency of the voltage-controlled oscillator and the pulse width of the pulse-width clock signal (i.e., the preset pulse-width square-wave signal) can be inferred, so as to generate the first control signal for roughly controlling (i.e., the second control accuracy) the period of the voltage-controlled oscillator. Through this first control signal, the signal period output by the voltage-controlled oscillator is exactly twice the width of the narrow-pulse lock clock pulse.
[0093] It should be recognized that embodiments of the present invention can be implemented or carried out by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer-readable memory. The above methods can be implemented in a computer program using standard programming techniques—including a non-transitory computer-readable storage medium configured with the computer program, where the storage medium so configured causes the computer to operate in a specific and predefined manner—according to the methods and drawings described in the specific embodiments. Each program can be implemented in a high-level procedural or object-oriented programming language to communicate with the computer system. However, if desired, the program can be implemented in assembly or machine language. In any case, the language can be a compiled or interpreted language. Additionally, for this purpose the program is capable of running on a programmed application-specific integrated circuit.
[0094] In addition, the operations of the processes described herein can be performed in any suitable order, unless otherwise indicated herein or otherwise clearly contradicted by the context. The processes described herein (or variations and / or combinations thereof) can be performed under the control of one or more computer systems configured with executable instructions and can be implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) collectively executed on one or more processors, by hardware, or by a combination thereof. The above computer programs include a plurality of instructions executable by one or more processors.
[0095] Furthermore, the above methods can be implemented in any type of computing platform operably connected, including but not limited to personal computers, minicomputers, mainframes, workstations, network or distributed computing environments, separate or integrated computer platforms, or communicating with charged particle tools or other imaging devices, etc. Aspects of the present invention can be implemented in machine-readable code stored on a non-transitory storage medium or device, whether removable or integrated into the computing platform, such as a hard disk, optical read and / or write storage medium, RAM, ROM, etc., such that it can be read by a programmable computer and, when the storage medium or device is read by the computer, can be used to configure and operate the computer to perform the processes described herein. Additionally, the machine-readable code, or portions thereof, can be transmitted via a wired or wireless network. When such media include instructions or programs that implement the above-described steps in conjunction with a microprocessor or other data processor, the inventions described herein include these and other different types of non-transitory computer-readable storage media. When programmed according to the methods and techniques described in the present invention, the present invention also includes the computer itself.
[0096] A computer program can be applied to input data to perform the functions described herein, thereby transforming the input data to generate output data stored in a non-volatile memory. The output information can also be applied to one or more output devices such as a display. In a preferred embodiment of the present invention, the transformed data represents physical and tangible objects, including specific visual depictions of physical and tangible objects generated on a display.
[0097] In the foregoing description of the present specification, descriptions with reference to the terms "one embodiment / implementation", "another embodiment / implementation", or "certain embodiments / implementations", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.
[0098] Although the embodiments of the present invention have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the claims and their equivalents.
[0099] The above has specifically described the preferred embodiments of the present invention, but the present invention is not limited to the embodiments. Those skilled in the art can also make various equivalent deformations or substitutions without departing from the spirit of the present invention, and these equivalent deformations or substitutions are all included within the scope defined by the claims of this application.
Claims
1. A charge sampling phase-locked loop with a wide locking range, characterized in that: The invention comprises a pulse width sampling frequency locking module and a charge sampling phase locking module, wherein the pulse width sampling frequency locking module comprises a crystal oscillator, a sampling and holding unit and a comparison and logic unit, wherein the charge sampling phase locking module comprises an input buffer, a charge sampling phase detector and a voltage controlled oscillator, wherein the crystal oscillator is connected to the input buffer, wherein the input buffer, the sampling and holding unit and the voltage controlled oscillator are all connected to the charge sampling phase detector, wherein the sampling and holding unit and the voltage controlled oscillator are all connected to the comparison and logic unit, wherein the crystal oscillator is used to output a first sinusoidal wave signal, wherein the voltage controlled oscillator is used to output a second sinusoidal wave signal, wherein the input buffer is used to convert the first sinusoidal wave signal into a pre-set signal. Assume a pulse width square wave signal, the charge sampling phase detector is used to sample the second sinusoidal wave signal according to the preset pulse width square wave signal to obtain a voltage difference signal, the voltage difference signal is used to control the voltage controlled oscillator with a first control accuracy, so that the voltage controlled oscillator is phase-locked with the preset pulse width square wave signal, the sampling and holding unit is used to sample the second sinusoidal wave signal according to the preset pulse width square wave signal to obtain a sampling voltage, the comparison and logic unit is used to output a first control signal according to the sampling voltage, and the first control signal is used to control the voltage controlled oscillator with a second control accuracy, so that the period of the output signal of the voltage controlled oscillator is twice the period of the preset pulse width square wave signal.
2. A charge sampling phase-locked loop with a wide locking range according to claim 1, characterized in that: The charge sampling phase-locked module also includes a loop filter, the charge sampling phase detector and the voltage-controlled oscillator are both connected to the loop filter, and the loop filter is used to obtain a second control signal for controlling the frequency of the voltage-controlled oscillator according to the voltage difference signal, and then make the waveform phase of the second sinusoidal wave signal equal to the phase of the preset pulse width square wave signal according to the second control signal.
3. A charge sampling phase-locked loop with a wide locking range according to claim 1, characterized in that: The sampling and holding unit includes a first delay unit and a second delay unit, the charge sampling phase detector, the comparison and logic unit and the input buffer are all connected to the first delay unit, the charge sampling phase detector, the comparison and logic unit and the input buffer are all connected to the second delay unit, and the first delay unit and the second delay unit are used to delay the preset pulse width square wave signal to obtain a square wave delayed signal.
4. A control method for a charge sampling phase-locked loop with a wide locking range, used for controlling a charge sampling phase-locked loop with a wide locking range as claimed in any one of claims 1 to 3, characterized in that: The following steps are involved: Outputting a first sine wave signal through a crystal oscillator; outputting a second sinusoidal wave signal through a voltage-controlled oscillator; Converting the first sine wave signal into a square wave signal with a preset pulse width through an input buffer; The second sine wave signal is sampled by a charge sampling phase detector according to the preset pulse width square wave signal to obtain a voltage difference signal, wherein the voltage difference signal is used to control the voltage controlled oscillator with a first control accuracy so that the voltage controlled oscillator is phase-locked with the preset pulse width square wave signal; The second sine wave signal is sampled according to the preset pulse width square wave signal by a sampling and holding unit to obtain a sampled voltage; A first control signal is output according to the sampling voltage through a comparison and logic unit, and the first control signal is used to control the voltage-controlled oscillator with a second control accuracy so that the period of the output signal of the voltage-controlled oscillator is twice the period of the preset pulse width square wave signal.
5. The control method of a charge sampling phase-locked loop with a wide locking range according to claim 4, characterized in that: The second sine wave signal is sampled by the charge sampling phase detector according to the preset pulse width square wave signal to obtain a voltage difference signal, specifically: The phase difference between the second sinusoidal wave signal and the preset pulse width square wave signal is converted into the voltage difference signal through capacitor integration.
6. The control method of a charge sampling phase-locked loop with a wide locking range according to claim 4, characterized in that: The control method further comprises: A second control signal for controlling the frequency of the voltage-controlled oscillator is obtained through a loop filter according to the voltage difference signal, and then the waveform phase of the second sinusoidal wave signal is made equal to the phase of the preset pulse width square wave signal according to the second control signal.
7. The control method of a charge sampling phase-locked loop with a wide locking range according to claim 4, characterized in that: The second sinusoidal wave signal includes a second positive phase sinusoidal wave signal and a second anti-phase sinusoidal wave signal, the sampling voltage includes a first rising edge sampling voltage, a first falling edge sampling voltage and a second rising edge sampling voltage, and the sampling and holding unit samples the second sinusoidal wave signal according to the preset pulse width square wave signal to obtain the sampling voltage, specifically including: Sampling the second positive phase sine wave signal output by the voltage controlled oscillator at the rising edge of the preset pulse width square wave signal to obtain the first rising edge sampling voltage; Sampling the second positive phase sinusoidal wave signal output by the voltage controlled oscillator at the falling edge of the preset pulse width square wave signal to obtain the first falling edge sampling voltage; The second inverted sinusoidal wave signal output by the voltage-controlled oscillator is sampled at the rising edge of the preset pulse width square wave signal to obtain the second rising edge sampling voltage.
8. The control method of a charge sampling phase-locked loop with a wide locking range according to claim 7, characterized in that: The control method further comprises: The preset pulse width square wave signal is delayed by the first delay unit and the second delay unit to obtain a square wave delayed signal.
9. The control method of a charge sampling phase-locked loop with a wide locking range according to claim 8, characterized in that: The control method further includes the step of sampling the second positive phase sine wave signal according to the square wave delay signal by the sampling and holding unit to obtain a third rising edge sampling voltage, specifically: The second positive phase sinusoidal wave signal output by the voltage controlled oscillator is sampled at the rising edge of the square wave delay signal to obtain the third rising edge sampling voltage.
10. The control method of a charge sampling phase-locked loop with a wide locking range according to claim 9, characterized in that: Outputting a first control signal according to the sampled voltage through a comparison and logic unit specifically includes: Comparing the first rising edge sampling voltage with the third rising edge sampling voltage to obtain an edge region relationship between the rising edge of the square wave signal and the second sinusoidal wave signal; Comparing the first rising edge sampling voltage with the second rising edge sampling voltage to obtain a voltage amplitude relationship between the sampling voltage and the common mode voltage of the voltage controlled oscillator; Determine, according to the edge region relationship and the voltage amplitude relationship, a region where the rising edge of the square wave signal corresponds to the second sine wave signal; Comparing the first rising edge sampling voltage with the first falling edge sampling voltage, and then obtaining a correlation relationship between the frequency of the voltage-controlled oscillator and the pulse width of the square wave signal according to the comparison result and the region; The first control signal is output according to the association relationship.