Digital phase-locked loop and clock circuit

Abstract

The invention provides a digital phase-locked loop and a clock circuit wherein the digital phase-locked loop adopts a cascade phase-locked loop structure and comprises a plurality of phase-locked loops; each phase-locked loop at least comprises a time-to-voltage converter, an analog-to-digital conversion module, a filter and a ring oscillator; each non-first phase-locked loop in the plurality of phase-locked loops further comprises a digital-to-analog conversion module; each non-first phase-locked loop is used for outputting an output signal after noise elimination based on an input signal of a first input end and an input signal of a second input end of each time-to-voltage converter and a noise quantization signal of a previous phase-locked loop. Through the time-to-voltage converter, the digital-to-analog conversion module and the analog-to-digital conversion module, phase noise of a previous phase-locked loop can be eliminated in a voltage domain, an output signal after noise elimination is obtained, meanwhile, the phase noise elimination gain is high in robustness under PVT change, no controller is needed for correction, and the phase noise elimination precision is high. And the quantization noise introduced in the whole noise elimination process is extremely low.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and more particularly, to a digital phase-locked loop and a clock circuit. Background Art

[0002] Phase-locked loops (PLLs) are widely used in modern System on Chip (SoC) designs. Compared with analog PLLs based on inductance-capacitance oscillators, digital PLLs based on ring oscillators have smaller areas and better scalability. However, the worse phase noise performance of ring oscillators also limits the application of this type of PLL, especially in scenarios where PLLs are increasingly required to output with low jitter performance.

[0003] In the prior art, a feedforward noise cancellation technique can be introduced into the digital PLL to suppress the phase noise of the oscillator. Specifically, a time-to-digital converter, a parameter β controller, a threshold controller, a register, and a digitally controlled delay link are set in the digital PLL. By comparing with the input reference signal, the time-to-digital converter quantifies the time error caused by the PLL phase noise into a digital code, and this digital code further controls the delay of the delay link through the parameter β to eliminate the time error caused by the PLL phase noise in the time domain, and finally obtain a low-jitter PLL output.

[0004] However, this processing method requires background calibration methods such as a parameter β controller and a threshold controller to maintain its robustness under process, temperature, and voltage variations. The introduction of a parameter β controller and a threshold controller increases the design difficulty of the digital PLL, resulting in a higher design cost, and too much background calibration is not conducive to the actual application of the circuit. Summary of the Invention

[0005] The purpose of this application is to provide a digital phase-locked loop and a clock circuit to solve the problems of poor robustness and complex and cumbersome calibration steps in the prior art.

[0006] To achieve the above object, the technical solutions adopted in the embodiments of this application are as follows: In a first aspect, an embodiment of this application provides a digital phase-locked loop, and the digital phase-locked loop includes: a plurality of phase-locked loops; Each of the phase-locked loops at least includes: a time-to-voltage converter, an analog-to-digital conversion module, a filter, and a ring oscillator; Each non-first phase-locked loop among the plurality of phase-locked loops further includes: a digital-to-analog conversion module; The first input terminal of the time-voltage converter of the first phase-locked loop is used to access the reference signal. The second input terminal of the time-voltage converter of the first phase-locked loop is used to access the processed signal of the first phase-locked loop. Each output terminal of the time-voltage converter of the first phase-locked loop is connected to each input terminal of the analog-to-digital conversion module of the first phase-locked loop in a one-to-one correspondence. The output terminal of the analog-to-digital conversion module of the first phase-locked loop is connected to the second input terminal of the digital-to-analog conversion module of the next phase-locked loop and the input terminal of the filter of the first phase-locked loop. The output terminal of the filter of the first phase-locked loop is connected to the input terminal of the ring oscillator of the first phase-locked loop. The output terminal of the ring oscillator of the first phase-locked loop is used to output the processed signal of the first phase-locked loop; The first input terminal of the time-voltage converter of each non-first phase-locked loop is used to access the processed signal of the previous phase-locked loop, and the second input terminal of the time-voltage converter of each non-first phase-locked loop is used to access the processed signal of each non-first phase-locked loop. Each output terminal of the time-voltage converter of each non-first phase-locked loop is respectively connected to each input terminal of the digital-to-analog conversion module of each phase-locked loop in a one-to-one correspondence. Each output terminal of the digital-to-analog conversion module of each non-first phase-locked loop is respectively connected to each input terminal of the analog-to-digital conversion module of each non-first phase-locked loop in a one-to-one correspondence; The output terminal of the analog-to-digital conversion module of each phase-locked loop except the last phase-locked loop among each non-first phase-locked loop is connected to the second input terminal of the digital-to-analog conversion module of the next phase-locked loop and the input terminal of the filter of each phase-locked loop except the last phase-locked loop among each non-first phase-locked loop. The output terminal of the analog-to-digital conversion module of the last phase-locked loop is connected to the input terminal of the filter of the last phase-locked loop among each non-first phase-locked loop; The output terminal of the filter of each non-first phase-locked loop is connected to the input terminal of the ring oscillator of each non-first phase-locked loop. The output terminal of the ring oscillator of each non-first phase-locked loop is used to output the processed signal of each non-first phase-locked loop; Each phase-locked loop except the last phase-locked loop is used to generate and output a noise quantization signal to the analog-to-digital conversion module of the next phase-locked loop based on the input signals of the first input terminal and the second input terminal of each time-voltage converter, and output a processed signal to the second input terminal of each time-voltage converter according to the noise quantization signal; Each non-first phase-locked loop is used to output an output signal after noise cancellation based on the input signals of the first input terminal and the second input terminal of each time-voltage converter and the noise quantization signal of the previous phase-locked loop.

[0007] Optionally, the output end of each of the time-voltage converters includes a first output end and a second output end. Each of the time-voltage converters is configured to generate time difference information of the input signals of the first input end and the second input end according to the time information of the input signals of the first input end and the second input end, and output a first voltage through the first output end and a second voltage through the second output end according to the time difference information; The analog-to-digital conversion module of the first phase-locked loop is configured to determine the noise quantization signals of the input signals of the first input end and the second input end based on the first voltage and the second voltage; The digital-to-analog conversion modules of non-first phase-locked loops are configured to generate voltage signals with the phase noise of the output of the previous phase-locked loop eliminated based on the first voltage, the second voltage, and the noise quantization signal of the previous phase-locked loop; The analog-to-digital conversion modules of non-first phase-locked loops are configured to generate the noise quantization signals of non-first phase-locked loops based on the voltage signals with the phase noise of the output of the previous phase-locked loop eliminated; Each filter and each ring oscillator of each of the phase-locked loops are configured to output the processed signals of each phase-locked loop based on the noise quantization signals output by the analog-to-digital conversion modules of each phase-locked loop.

[0008] Optionally, the analog-to-digital conversion module of the first phase-locked loop includes: a first digital-to-analog converter, a second digital-to-analog converter, and a comparison processing module; The input end of the first digital-to-analog converter is connected to the first output end of the time-voltage converter, and the input end of the second digital-to-analog converter is connected to the second output end of the time-voltage converter; The first digital-to-analog converter is configured to perform digital-to-analog conversion on the first voltage from the first output end, obtain a first voltage signal, and output the first voltage signal to the comparison processing module; the second digital-to-analog converter is configured to perform digital-to-analog conversion on the second voltage from the second output end, obtain a second voltage signal, and output the second voltage signal to the comparison processing module; the comparison processing module is configured to perform differential processing on the first voltage signal and the second voltage signal and output the noise quantization signal.

[0009] Optionally, each of the phase-locked loops further includes: a frequency divider; The input end of the frequency divider is connected to the output end of the ring oscillator, and the output end of the frequency divider is connected to the second input end of the time-voltage converter.

[0010] Optionally, the analog-to-digital conversion module of each non-first phase-locked loop includes: a comparator; The input end of the comparator is connected to the first output end and the second output end of the digital-to-analog conversion module.

[0011] Optionally, the digital-to-analog conversion module includes: a first conversion module and a control module; A first input end of the first conversion module is connected to a first output end of the time-voltage converter, a second input end of the first conversion module is connected to a second output end of the time-voltage converter, a first output end of the first conversion module is connected to a first input end of the analog-to-digital conversion module, and a second output end of the first conversion module is connected to a second input end of the analog-to-digital conversion module; A control end of the first conversion module is connected to a first output end of the control module; A first input end of the control module is connected to an output end of the analog-to-digital conversion module of the previous phase-locked loop.

[0012] Optionally, the digital-to-analog conversion module further includes: a second conversion module; A first input end of the second conversion module is connected to the first output end of the time-voltage converter and the first output end of the first conversion module, a second input end of the second conversion module is connected to the second output end of the time-voltage converter and the second output end of the first conversion module, a first output end of the second conversion module is connected to the first input end of the analog-to-digital conversion module, and a second output end of the second conversion module is connected to the second input end of the analog-to-digital conversion module; A control end of the second conversion module is connected to a second output end of the control module, and a second input end of the control module is connected to an output end of the ring oscillator.

[0013] Optionally, the first conversion module includes: a third digital-to-analog converter and a fourth digital-to-analog converter; the second conversion module includes: a fifth digital-to-analog converter and a sixth digital-to-analog converter; An input end of the third digital-to-analog converter is connected to the first output end of the time-voltage converter, and an input end of the fourth digital-to-analog converter is connected to the second output end of the time-voltage converter; An output end of the third digital-to-analog converter is connected to an input end of the fifth digital-to-analog converter, and an output end of the fourth digital-to-analog converter is connected to an input end of the sixth digital-to-analog converter; A control end of the third digital-to-analog converter and a control end of the fourth digital-to-analog converter are connected to a first output end of the control module, and a control end of the fifth digital-to-analog converter and a control end of the sixth digital-to-analog converter are connected to a second output end of the control module.

[0014] Optionally, the third digital-to-analog converter and the fourth digital-to-analog converter are 7b capacitive digital-to-analog converters respectively, and the fifth digital-to-analog converter and the sixth digital-to-analog converter are 9b capacitive digital-to-analog converters respectively; or, the third digital-to-analog converter and the fourth digital-to-analog converter are 9b capacitive digital-to-analog converters respectively, and the fifth digital-to-analog converter and the sixth digital-to-analog converter are 7b capacitive digital-to-analog converters respectively.

[0015] In a second aspect, another embodiment of the present application provides a clock circuit, which includes: the digital phase-locked loop according to any one of the first aspect.

[0016] The beneficial effects of the present application are as follows: By arranging multiple phase-locked loops in the digital phase-locked loop, and arranging a time-voltage converter, an analog-to-digital conversion module, a filter, and a ring oscillator in the first phase-locked loop, and arranging a time-voltage converter, a digital-to-analog conversion module, an analog-to-digital conversion module, a filter, and a ring oscillator in each non-first phase-locked loop, so that each phase-locked loop except the last one can convert the time error caused by phase noise into a voltage difference based on the input signal input to the time-voltage converter, thereby generating and outputting a noise quantization signal to the next phase-locked loop, so that each non-first phase-locked loop can eliminate the phase noise of the previous phase-locked loop in the voltage domain based on the input signal input to the time-voltage converter and the noise quantization signal of the previous phase-locked loop, and obtain an output signal after noise cancellation, avoiding the introduction of additional unnecessary quantization noise and ensuring the suppression effect of phase noise. At the same time, by determining and eliminating the differences of the input signals through the time-voltage converter, the digital-to-analog conversion module, and the analog-to-digital conversion module, the phase noise cancellation gain of the digital phase-locked loop is robust under PVT variations, without the need for any controller for calibration, and also has the advantage of extremely small quantization noise introduced during the entire noise cancellation process, further improving the stability of the digital phase-locked loop provided by the embodiments of the present application. Description of the Drawings

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0018] Figure 1 It is a schematic structural diagram of a digital phase-locked loop in the prior art; Figure 2 It is a schematic structural diagram of a digital phase-locked loop provided by an embodiment of the present application; Figure 3 It is another schematic structural diagram of a digital phase-locked loop provided by an embodiment of the present application; Figure 4 It is a schematic diagram of a principle for noise cancellation in the digital phase-locked loop provided by an embodiment of the present application; Figure 5 It is a schematic diagram of a structure of the analog-to-digital conversion module of the first phase-locked loop in the digital phase-locked loop provided by an embodiment of the present application; Figure 6 It is another schematic diagram of a structure of the digital phase-locked loop provided by an embodiment of the present application; Figure 7 It is a schematic diagram of a structure of each non-first phase-locked loop in the digital phase-locked loop provided by an embodiment of the present application; Figure 8 It is another schematic diagram of a structure of each non-first phase-locked loop in the digital phase-locked loop provided by an embodiment of the present application; Figure 9 It is yet another schematic diagram of a structure of each non-first phase-locked loop in the digital phase-locked loop provided by an embodiment of the present application; Figure 10 It is another schematic diagram of a structure of each non-first phase-locked loop in the digital phase-locked loop provided by an embodiment of the present application; Figure 11 It is yet another schematic diagram of a structure of the digital phase-locked loop provided by an embodiment of the present application; Figure 12 It is a schematic diagram of a simulation result of the digital phase-locked loop provided by an embodiment of the present application under the condition of circuit mismatch; Figure 13 It is a schematic diagram of a phase noise test of the second-stage phase-locked loop in the digital phase-locked loop provided by an embodiment of the present application; Figure 14 It is a schematic diagram of a test of the output jitter of the second-stage phase-locked loop in the digital phase-locked loop provided by an embodiment of the present application with respect to changes in power supply voltage and temperature; Figure 15 It is a schematic diagram of the test results of the output jitter of different chips in the digital phase-locked loop provided by an embodiment of the present application. Detailed implementation manners

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It should be understood that the accompanying drawings in the present application only serve the purposes of illustration and description, and are not used to limit the protection scope of the present application. Additionally, it should be understood that the schematic drawings are not drawn to actual scale. The flowcharts used in the present application illustrate the operations implemented according to some embodiments of the present application. It should be understood that the operations in the flowchart may not be implemented in sequence, and steps without a logical context relationship may be reversed in order or implemented simultaneously. In addition, those skilled in the art may add one or more other operations to the flowchart or remove one or more operations from the flowchart under the guidance of the content of the present application.

[0020] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all embodiments. The components of the embodiments of the present application usually described and illustrated in the accompanying drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but merely represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative efforts fall within the scope of protection of the present application.

[0021] It should be noted that the term "including" will be used in the embodiments of the present application to indicate the presence of the subsequently stated features, but does not exclude the addition of other features.

[0022] In the prior art, a phase noise feedforward cancellation technique (feedforward noise cancellation) can be introduced into a digital phase-locked loop to suppress the phase noise of an oscillator. Specifically, Figure 1 is a schematic structural diagram of a digital phase-locked loop in the prior art. Refer to Figure 1 As shown, in the prior art, by setting a time-to-digital converter, a parameter β controller, a threshold controller, a register, and a digitally controlled delay link in the digital phase-locked loop, and by comparing with an input reference signal, the time-to-digital converter quantifies the time error caused by the phase noise of the phase-locked loop into a digital code, and this digital code further controls the delay of the delay link through the parameter β to eliminate the time error caused by the phase noise of the phase-locked loop in the time domain, and finally obtain a phase-locked loop output with low jitter.

[0023] However, this processing method in the prior art requires a parameter β controller and a threshold controller to maintain its optimal performance. First, to ensure that the quantization process of the time-to-digital converter introduces the lowest quantization noise, the threshold controller needs to continuously adjust the time threshold of the time-to-digital converter in the background through the statistical characteristics of the output of the time-to-digital converter. Second, to ensure the most ideal phase noise cancellation gain under the influence of process, power supply voltage, and temperature (PVT) variations, the parameter β controller needs to continuously adjust the value of β in the background according to the correlation between the parameter β and the output of the time-to-digital converter. That is, the introduction of the parameter β controller and the threshold controller increases the design difficulty of applying this digital phase-locked loop, and in the application of this digital phase-locked loop, complex background calibration of parameters such as the phase noise cancellation gain is also required to cope with the phase noise deterioration caused by PVT variations in actual applications.

[0024] Therefore, this processing method increases the design difficulty of the digital phase-locked loop, resulting in a relatively high design cost, and excessive background calibration is not conducive to the actual application of the circuit.

[0025] Based on the above problems, the present application proposes a digital phase-locked loop. By setting multiple phase-locked loops in the digital phase-locked loop, and setting a time-voltage converter, an analog-to-digital conversion module, a filter, and a ring oscillator in the first phase-locked loop, and setting a time-voltage converter, a digital-to-analog conversion module, an analog-to-digital conversion module, a filter, and a ring oscillator in each non-first phase-locked loop, so that each phase-locked loop except the last one can generate and output a noise quantization signal to the next phase-locked loop based on the input signal input to the time-voltage converter. Thus, each non-first phase-locked loop can eliminate the phase noise of the previous phase-locked loop based on the input signal input to the time-voltage converter and the noise quantization signal of the previous phase-locked loop, and obtain an output signal after noise cancellation, so that its phase noise cancellation gain has strong robustness under PVT (Process, Voltage, Temperature) variations, without any controller for correction, ensuring the suppression effect of phase noise.

[0026] The following will describe in detail the digital phase-locked loop provided by the embodiments of the present application in combination with multiple embodiments.

[0027] Figure 2 FIG. is a schematic structural diagram of the digital phase-locked loop provided by the embodiments of the present application. Referring to Figure 2 as shown, the digital phase-locked loop includes: multiple phase-locked loops.

[0028] Each phase-locked loop at least includes: a time-voltage converter, an analog-to-digital conversion module, a filter, a ring oscillator; each non-first phase-locked loop among the multiple phase-locked loops further includes: a digital-to-analog conversion module.

[0029] Among them, the time-voltage converter is used to achieve linear time-to-voltage conversion by controlling the internal charge pump to discharge from the load capacitor. The analog-to-digital conversion module is used to quantize the voltage output by each time-voltage converter, thereby realizing the quantization of noise. The digital-to-analog conversion module is used to eliminate the voltage amount caused by the phase noise output by the previous phase-locked loop in the voltage output by the time-voltage converter according to the quantization result output by the analog-to-digital conversion module of the previous phase-locked loop.

[0030] Among them, the filter can be a digital loop filter, which is used to smooth the output signal of the analog-to-digital conversion module and generate a control signal based on this signal to adjust the frequency of the ring oscillator to ensure the stability and accuracy of the obtained processed signal.

[0031] Exemplarily, Figure 2 taking the digital phase-locked loop including three-stage phase-locked loops as an example for illustration. Referring to Figure 2 as shown, each phase-locked loop at least includes: a time-voltage converter, an analog-to-digital conversion module, a filter, and a ring oscillator, and both the second-stage phase-locked loop and the third-stage phase-locked loop further include a digital-to-analog conversion module.

[0032] The first input terminal of the time-voltage converter of the first phase-locked loop is used to receive a reference signal S REF , and the second input terminal of the time-voltage converter of the first phase-locked loop is used to receive the processed signal of the first phase-locked loop S OUT,PLL1 , each output terminal of the time-voltage converter of the first phase-locked loop is connected to each input terminal of the analog-to-digital conversion module of the first phase-locked loop in one-to-one correspondence. The output terminal of the analog-to-digital conversion module of the first phase-locked loop is connected to the second input terminal of the digital-to-analog conversion module of the next phase-locked loop and the input terminal of the filter of the first phase-locked loop. The output terminal of the filter of the first phase-locked loop is connected to the input terminal of the ring oscillator of the first phase-locked loop. The output terminal of the ring oscillator of the first phase-locked loop is used to output the processed signal of the first phase-locked loop S OUT,PLL1 .

[0033] The first input terminal of the time-voltage converter of each non-first phase-locked loop is used to receive the processed signal of the previous phase-locked loop, and the second input terminal of the time-voltage converter of each non-first phase-locked loop is used to receive the processed signal of each non-first phase-locked loop. Each output terminal of the time-voltage converter of each non-first phase-locked loop is respectively connected to each input terminal of the digital-to-analog conversion module of each phase-locked loop in one-to-one correspondence. Each output terminal of the digital-to-analog conversion module of each non-first phase-locked loop is respectively connected to each input terminal of the analog-to-digital conversion module of each non-first phase-locked loop in one-to-one correspondence

[0034] The output terminal of the analog-to-digital conversion module of each phase-locked loop except the last phase-locked loop among each non-first phase-locked loop is connected to the second input terminal of the digital-to-analog conversion module of the next phase-locked loop and the input terminal of the filter of each phase-locked loop except the last phase-locked loop among each non-first phase-locked loop. The output terminal of the analog-to-digital conversion module of the last phase-locked loop is connected to the input terminal of the filter of the last phase-locked loop among each non-first phase-locked loop

[0035] The output terminal of the filter of each non-first phase-locked loop is connected to the input terminal of the ring oscillator of each non-first phase-locked loop. The output terminal of the ring oscillator of each non-first phase-locked loop is used to output the processed signal of each non-first phase-locked loop

[0036] Exemplarily, continuing to refer to Figure 2 as shown, the first input terminal of the time-voltage converter of the first phase-locked loop is used to receive a reference signal S REF , and the second input terminal of the time-voltage converter of the first phase-locked loop is used to receive the processed signal of the first phase-locked loop S OUT,PLL1, each output terminal of the time-voltage converter of the first phase-locked loop is connected to each input terminal of the analog-to-digital conversion module of the first phase-locked loop in a one-to-one correspondence. The output terminal of the analog-to-digital conversion module of the first phase-locked loop is connected to the second input terminal of the digital-to-analog conversion module of the second-stage phase-locked loop and the input terminal of the filter of the first phase-locked loop. The output terminal of the analog-to-digital conversion module of the first phase-locked loop outputs the noise quantization signal of the first phase-locked loop to the digital-to-analog conversion module of the second-stage phase-locked loop D ADC1 , the output terminal of the filter of the first phase-locked loop is connected to the input terminal of the ring oscillator of the first phase-locked loop. The output terminal of the ring oscillator of the first phase-locked loop is connected to the second input terminal of the time-voltage converter of the first phase-locked loop and the first input terminal of the time-voltage converter of the second-stage phase-locked loop, and is used to output the processed signal of the first phase-locked loop S OUT,PLL1 .

[0037] Exemplarily, continue to refer to Figure 2 shown, the first input terminal of the time-voltage converter of the second-stage phase-locked loop is used to access the processed signal of the first phase-locked loop S OUT,PLL1 , the second input terminal of the time-voltage converter of the second-stage phase-locked loop is used to access the processed signal of the second-stage phase-locked loop S OUT,PLL2 .

[0038] Exemplarily, continue to refer to Figure 2 shown, each output terminal of the time-voltage converter of the second-stage phase-locked loop is respectively connected to each input terminal of the digital-to-analog conversion module of the second-stage phase-locked loop in a one-to-one correspondence. Each output terminal of the digital-to-analog conversion module of the second-stage phase-locked loop is respectively connected to each input terminal of the analog-to-digital conversion module of the second-stage phase-locked loop in a one-to-one correspondence. The output terminal of the analog-to-digital conversion module of the second-stage phase-locked loop is connected to the second input terminal of the digital-to-analog conversion module of the third-stage phase-locked loop and the input terminal of the filter of the second-stage phase-locked loop. The output terminal of the analog-to-digital conversion module of the second-stage phase-locked loop outputs the noise quantization signal of the second-stage phase-locked loop to the digital-to-analog conversion module of the third-stage phase-locked loop D ADC2 , the output terminal of the filter of the second-stage phase-locked loop is connected to the input terminal of the ring oscillator of the second-stage phase-locked loop. The output terminal of the ring oscillator of the second-stage phase-locked loop is connected to the second input terminal of the time-voltage converter of the second-stage phase-locked loop and the first input terminal of the time-voltage converter of the third-stage phase-locked loop, and is used to output the processed signal of the second-stage phase-locked loop S OUT,PLL2 .

[0039] Exemplarily, continue to refer to Figure 2 shown, the first input terminal of the time-voltage converter of the third-stage phase-locked loop is used to access the processed signal of the second-stage phase-locked loop SOUT,PLL2 The second input terminal of the time-voltage converter of the third-level phase-locked loop is used to connect to the processed signal of the third-level phase-locked loop. S OUT,PLL3 .

[0040] Exemplarily, continue to refer to Figure 2 As shown, each output terminal of the time-voltage converter of the third-level phase-locked loop is respectively and correspondingly connected to each input terminal of the digital-to-analog conversion module of the third-level phase-locked loop. Each output terminal of the digital-to-analog conversion module of the third-level phase-locked loop is respectively and correspondingly connected to each input terminal of the analog-to-digital conversion module of the third-level phase-locked loop. The output terminal of the analog-to-digital conversion module of the third-level phase-locked loop is connected to the input terminal of the filter of the third-level phase-locked loop. The output terminal of the filter of the third-level phase-locked loop is connected to the input terminal of the ring oscillator of the second-level phase-locked loop. The output terminal of the ring oscillator of the third-level phase-locked loop is connected to the second input terminal of the time-voltage converter of the third-level phase-locked loop, and is used to output the processed signal of the third-level phase-locked loop. S OUT,PLL3 , that is, the output signal after noise cancellation.

[0041] Each phase-locked loop except the last one is used to generate a noise quantization signal based on the input signal at the first input terminal and the input signal at the second input terminal of each time-voltage converter, and output it to the analog-to-digital conversion module of the next phase-locked loop, and output a processed signal to the second input terminal of each time-voltage converter according to the noise quantization signal.

[0042] Each non-first phase-locked loop is used to output an output signal after noise cancellation based on the input signal at the first input terminal and the input signal at the second input terminal of each time-voltage converter and the noise quantization signal of the previous phase-locked loop.

[0043] Exemplarily, continue to refer to Figure 2 As shown, continue to take the three-level phase-locked loop as an example. The first phase-locked loop is used to generate a noise quantization signal of the first phase-locked loop based on the reference signal at the first input terminal of the input time-voltage converter S REF and the input signal at the second input terminal S OUT,PLL1 , and output it to the filter of the first phase-locked loop and the analog-to-digital conversion module of the second-level phase-locked loop. D ADC1 At the same time, the filter and the ring oscillator of the first phase-locked loop are based on the noise quantization signal of the first phase-locked loop D ADC1 , obtain and output a processed signal of the first phase-locked loop to the time-voltage converter of the second-level phase-locked loop. S OUT,PLL1 .

[0044] Exemplarily, continue to refer toFigure 2 As shown, continuing with the example of a three-stage phase-locked loop, the second-stage phase-locked loop is based on the input signal at the first input terminal of the input time-voltage converter S OUT,PLL1 and the input signal at the second input terminal S OUT,PLL2 as well as the noise quantization signal of the first phase-locked loop D ADC1 , generates and outputs the noise quantization signal of the second-stage phase-locked loop to the filter of the second-stage phase-locked loop and the analog-to-digital conversion module of the third-stage phase-locked loop D ADC2 . Meanwhile, the filter of the second-stage phase-locked loop and the ring oscillator obtain and output the processed signal of the second-stage phase-locked loop to the time-voltage converter of the third-stage phase-locked loop based on the noise quantization signal of the second-stage phase-locked loop S OUT,PLL2 .

[0045] Exemplarily, continuing to refer to Figure 2 as shown, continuing with the example of a three-stage phase-locked loop, the third-stage phase-locked loop, as the last phase-locked loop, after obtaining the noise quantization signal of the second-stage phase-locked loop D ADC2 and the processed signal of the second-stage phase-locked loop S OUT,PLL2 , based on the noise quantization signal of the second-stage phase-locked loop D ADC2 , the processed signal of the third-stage phase-locked loop S OUT,PLL3 and the processed signal of the second-stage phase-locked loop S OUT,PLL2 , through the time-voltage converter, analog-to-digital conversion module, filter and ring oscillator, eliminates phase noise, thereby obtaining the output signal after noise cancellation S OUT,PLL3 .

[0046] It can be understood that when the digital phase-locked loop provided by the embodiments of the present application includes multiple phase-locked loops, the noise information in the signal can be quantized in sequence by each phase-locked loop except the last one with different precisions, and the phase noise can be feed-forward filtered by the next phase-locked loop based on the noise quantization signal of the previous phase-locked loop. Thus, after each phase-locked loop processes, the final output signal of the digital phase-locked loop, that is, the output signal after noise cancellation, can be obtained, making the phase noise cancellation gain robust under PVT variations and without any controller for correction.

[0047] Among them, the number of phase-locked loops can be set according to the noise cancellation precision or the number of noise cancellation times.

[0048] Optionally, when the digital phase-locked loop provided by the embodiments of the present application is a two-stage phase-locked loop, the noise information in the signal can be quantified by the first phase-locked loop, and the phase noise can be fed forward and filtered by the second phase-locked loop based on the noise quantization signal of the first phase-locked loop, so that the output signal after noise cancellation can be obtained through the second phase-locked loop.

[0049] Optionally, the time-to-voltage converters in each phase-locked loop can be the same time-to-voltage converter, that is, a time-to-voltage converter with the same conversion gain, and the analog-to-digital conversion module in the first phase-locked loop and the digital-to-analog conversion modules in each non-first phase-locked loop can be correspondingly set. For example, the minimum voltage adjustment unit corresponding to the analog-to-digital conversion module in the first phase-locked loop can be the same as the minimum voltage adjustment unit corresponding to the digital-to-analog conversion modules in each non-first phase-locked loop.

[0050] Exemplarily, the design parameters of the analog-to-digital conversion module and the digital-to-analog conversion module in each phase-locked loop can also be related to the phase noise cancellation gain.

[0051] In this embodiment, by setting multiple phase-locked loops in the digital phase-locked loop, and setting a time-to-voltage converter, an analog-to-digital conversion module, a filter, and a ring oscillator in the first phase-locked loop, and setting a time-to-voltage converter, a digital-to-analog conversion module, an analog-to-digital conversion module, a filter, and a ring oscillator in each non-first phase-locked loop, so that each phase-locked loop except the last one can convert the time error caused by phase noise into a voltage difference based on the input signal input to the time-to-voltage converter, thereby generating and outputting a noise quantization signal to the next phase-locked loop, so that each non-first phase-locked loop can eliminate the phase noise of the previous phase-locked loop in the voltage domain based on the input signal input to the time-to-voltage converter and the noise quantization signal of the previous phase-locked loop, and obtain the output signal after noise cancellation, avoiding the introduction of additional unnecessary quantization noise and ensuring the suppression effect of phase noise. At the same time, by determining and eliminating the differences of the input signals through the time-to-voltage converter, the digital-to-analog conversion module, and the analog-to-digital conversion module, the phase noise cancellation gain of the digital phase-locked loop has strong robustness under PVT variations, without any controller for correction, and also has the advantage that the quantization noise introduced in the whole noise cancellation process is extremely small, further improving the stability of the digital phase-locked loop provided by the embodiments of the present application.

[0052] In a possible implementation manner, the output end of each time-to-voltage converter includes a first output end and a second output end. Each time-to-voltage converter is configured to generate time difference information of the input signal of the first input end and the input signal of the second input end according to the time information of the input signal of the first input end and the input signal of the second input end, and output a first voltage through the first output end and output a second voltage through the second output end according to the time difference information.

[0053] Optionally,Figure 3 Another structural diagram of a digital phase-locked loop provided in an embodiment of the present application is shown in FIG. Figure 4 A schematic diagram of the principle of noise elimination in a digital phase-locked loop provided in an embodiment of the present application, referring to Figure 3 as well as Figure 4 As shown, taking the digital phase-locked loop as a two-stage phase-locked loop as an example, in the first phase-locked loop, the first input terminal of the time-to-voltage converter of the first phase-locked loop is used to access the reference signal S REF The second input terminal of the time voltage converter of the first phase-locked loop is used to access the processed signal of the first phase-locked loop S OUT,PLL1 , the first phase-locked loop time-to-voltage converter is used to convert S OUT,PLL1 The rising edge arrival time ( t OUT,PLL1 )and S REF The rising edge arrival time ( t REF ) comparison, the first phase-locked loop time voltage converter discharges the load capacitor by controlling the internal charge pump, S OUT,PLL1 The time error caused by phase noise ( t REF – t OUT,PLL1 = Δ t ER1 ) is converted into a voltage difference ( V CLK,REF – V OUT,PLL1 = ΔV ER1 ), to achieve linear time-to-voltage conversion, where the conversion gain is K TVC .

[0054] The analog-to-digital conversion module of the first phase-locked loop is used to determine the noise quantization signal of the input signal of the first input terminal and the input signal of the second input terminal based on the first voltage and the second voltage.

[0055] Optionally, refer to Figure 3 as well as Figure 4 As shown, the analog-to-digital conversion module of the first phase-locked loop is used to determine the voltage difference information according to the first voltage and the second voltage. ΔV ER1 , and the voltage difference information ΔV ER1 Convert to get the noise quantization signal D ADC , where the total quantization gain of the analog-to-digital conversion module isK ADC 。

[0056] The digital-to-analog conversion modules of non-first PLLs are configured to generate voltage signals with the phase noise of the output of the previous PLL eliminated, based on the first voltage, the second voltage, and the noise quantization signals of the previous PLL; the analog-to-digital conversion modules of non-first PLLs are configured to generate the noise quantization signals of non-first PLLs based on the voltage signals with the phase noise of the output of the previous PLL eliminated.

[0057] Optionally, continuing to refer to Figure 3 and Figure 4 shown, in the second-stage PLL, the time-to-voltage converter of the second-stage PLL is configured to obtain a conversion voltage ( S OUT,PLL1 ) according to the arrival time of the rising edge of t OUT,PLL1 ), and obtain a conversion voltage ( V OUT,PLL1 ) according to the arrival time of the rising edge of the processed signal S OUT,PLL2 of the second-stage PLL ( t OUT,PLL1 ). The digital-to-analog conversion module of the second-stage PLL is configured to eliminate V OUT,PLL2 from the conversion voltage ( D ADC ) according to the noise quantization signal V OUT,PLL1 of the first PLL, to obtain a voltage ( ΔV ER1 ) with the phase noise of the first PLL eliminated, that is, the voltage signal with the phase noise of the output of the previous PLL of the second-stage PLL eliminated. V FFNC

[0058] The analog-to-digital conversion module of the second-stage PLL is configured to compare the voltage signal with the phase noise of the output of the previous PLL of the second-stage PLL eliminated ( V FFNC ) with the conversion voltage ( S OUT,PLL2 ) of the processed signal V OUT,PLL2 of the second-stage PLL, so as to implement the function of phase discrimination in the second-stage PLL. Among them, the total quantization gain of the digital-to-analog conversion module is K DAC .

[0059] It can be understood that, continuing to refer to Figure 3 and Figure 4 shown, the total quantization gain of the analog-to-digital conversion module of the first PLLK ADC It can be represented by the following formula (1): (1) Where, Δ U1 is the minimum voltage regulation unit of the analog-to-digital conversion module. Due to the adoption of the charge pump and CDAC, the conversion gain of the time-to-voltage converter in the first phase-locked loop K TVC and the total quantization gain of the analog-to-digital conversion module K ADC are relatively robust under PVT variations, and since the analog-to-digital conversion module can obtain a very small Δ U1 , the quantization noise introduced in this quantization process is also very small, and there is no need for an additional complex calibrator like a time-to-digital converter.

[0060] It can be understood that continuing to refer to Figure 3 and Figure 4 as shown, the total quantization gain K DAC of the digital-to-analog conversion module of the second-stage phase-locked loop can be represented by the following formula (2): (2) Where, Δ U2 is the minimum voltage regulation unit of the digital-to-analog conversion module.

[0061] It can be understood that continuing to refer to Figure 3 and Figure 4 as shown, when the conversion gains K TVC of the time-to-voltage converters in the two-stage phase-locked loop are equal, the phase noise cancellation gain G V-FFNC of the digital phase-locked loop provided by the embodiment of the present application can be represented by the following formula (3): (3) That is to say, when there is a corresponding relationship between the design parameters of the analog-to-digital conversion module of the first phase-locked loop and the digital-to-analog conversion module of the second-stage phase-locked loop, for example: the minimum voltage regulation unit Δ U1 of the analog-to-digital conversion module of the first phase-locked loop and the minimum voltage regulation unit Δ U2 of the digital-to-analog conversion module of the second-stage phase-locked loop are equal, an ideal phase noise cancellation gain equal to 1 G V-FFNC, and this gain does not require any calibration, avoiding the introduction of additional unnecessary quantization noise, ensuring the suppression effect of phase noise, and at the same time making the phase noise cancellation gain of the digital phase-locked loop robust under PVT (Process, Voltage, Temperature) variations.

[0062] Each filter of each phase-locked loop and each ring oscillator are used to output an output signal after noise cancellation based on the noise quantization signal output by the analog-to-digital conversion module of each phase-locked loop.

[0063] Optionally, continue to refer to Figure 3 and Figure 4 As shown, after the filter smoothes the noise quantization signal output by the analog-to-digital conversion module of each phase-locked loop, by adjusting the frequency of the ring oscillator, it can ensure that the phase difference between the output signal and the reference signal remains within a small range, thereby reducing phase noise, enabling the ring oscillator of the first phase-locked loop to output the processed signal of the first phase-locked loop, and enabling the ring oscillator of the second-stage phase-locked loop to output the output signal after noise cancellation.

[0064] In a possible implementation manner, Figure 5 This is a schematic structural diagram of the analog-to-digital conversion module of the first phase-locked loop in the digital phase-locked loop provided by the embodiments of the present application. Refer to Figure 5 As shown, the analog-to-digital conversion module of the first phase-locked loop includes: a first digital-to-analog converter, a second digital-to-analog converter, and a comparison processing module.

[0065] The input end of the first digital-to-analog converter is connected to the first output end of the time-voltage converter, and the input end of the second digital-to-analog converter is connected to the second output end of the time-voltage converter.

[0066] Optionally, the analog-to-digital conversion module can be a 7-bit successive approximation analog-to-digital converter (abbreviated as 7b-SAR-ADC), a 5-bit successive approximation analog-to-digital converter (abbreviated as 5b-SAR-ADC), an 8-bit successive approximation analog-to-digital converter (abbreviated as 8b-SAR-ADC), or other successive approximation analog-to-digital converters (abbreviated as SAR-ADC). Exemplarily, the analog-to-digital conversion module includes a first digital-to-analog converter, a second digital-to-analog converter, and a comparison processing module. Among them, the first digital-to-analog converter and the second digital-to-analog converter can be the same digital-to-analog converter. For example, both can be 7-bit capacitive digital-to-analog converters (abbreviated as 7b-CDAC), which are used to implement digital-to-analog conversion using a capacitor array and have a resolution of 7 bits.

[0067] The first digital-to-analog converter is used to perform digital-to-analog conversion on the first voltage from the first output terminal, obtain and output a first voltage signal to the comparison and processing module; the second digital-to-analog converter is used to perform digital-to-analog conversion on the second voltage from the second output terminal, obtain and output a second voltage signal to the comparison and processing module; the comparison and processing module is used to perform differential processing on the first voltage signal and the second voltage signal and output a noise quantization signal.

[0068] Optionally, the comparison and processing module may include a comparator, a successive approximation register (SAR), a control logic circuit, and a clock, which are used to perform differential comparison on the first voltage signal and the second voltage signal, and convert the analog signal into a digital signal for output.

[0069] In a possible implementation manner, the first phase-locked loop may further include: a first compensation capacitor and a second compensation capacitor.

[0070] One end of the first compensation capacitor is connected to the first output terminal of the time-voltage converter, and the other end of the first compensation capacitor is connected to the input terminal of the first digital-to-analog converter. One end of the second compensation capacitor is connected to the second output terminal of the time-voltage converter, and the other end of the second compensation capacitor is connected to the input terminal of the second digital-to-analog converter.

[0071] Optionally, the first compensation capacitor and the second compensation capacitor are used to compensate for the load capacitance in other phase-locked loops in the digital phase-locked loop provided in the embodiments of the present application in the first phase-locked loop, so that the load capacitances between the phase-locked loops are kept consistent, thereby improving the gain and phase response stability of the digital phase-locked loop provided in the embodiments of the present application, thereby improving the locking performance and anti-noise ability of the digital phase-locked loop, and also reducing the power consumption of the digital phase-locked loop provided in the embodiments of the present application.

[0072] In a possible implementation manner, Figure 6 is another structural schematic diagram of the digital phase-locked loop provided in the embodiments of the present application. Refer to Figure 6 as shown, each phase-locked loop further includes: a frequency divider.

[0073] The input terminal of the frequency divider is connected to the output terminal of the ring oscillator, and the output terminal of the first frequency divider is connected to the second input terminal of the time-voltage converter.

[0074] It should be understood that different frequency division methods may be adopted for each phase-locked loop in the digital phase-locked loop provided in the embodiments of the present application, and the structures in each phase-locked loop can be adaptively adjusted according to different frequency division methods.

[0075] Optionally, the frequency divider can be an integer frequency divider with retiming, which can divide the input signal by a preset integer multiple to ensure the stability of the signal, reduce oscillations or errors caused by signal instability. At the same time, it can also ensure the synchronization and accuracy of data transmission.

[0076] Optionally, the frequency divider can also be a fractional frequency divider, which is used to divide a higher-frequency signal to obtain the required lower-frequency signal, so that the output frequency of the output signal of the digital phase-locked loop provided by the embodiments of the present application is closer to the expected value, improving the quality of signal transmission, reducing phase noise, ensuring the stability and reliability of the signal, and improving the anti-interference ability, thus ensuring the reliability of signal synchronization.

[0077] The structure of the analog-to-digital conversion module of the first phase-locked loop is described above by way of example. The following is an exemplary description of the structure of the analog-to-digital conversion modules of each non-first phase-locked loop.

[0078] In a possible implementation manner, Figure 7 is a schematic structural diagram of each non-first phase-locked loop in the digital phase-locked loop provided by the embodiments of the present application. Referring to Figure 7 as shown, on the basis of Figure 3 , the analog-to-digital conversion module of each non-first phase-locked loop includes: a comparator.

[0079] The input end of the comparator is connected to the first output end and the second output end of the digital-to-analog conversion module.

[0080] Optionally, Figure 7 taking a two-stage phase-locked loop as an example for illustration. Referring to Figure 7 as shown, the comparator is used to quantize the signal output by the digital-to-analog conversion module to obtain a quantization result ( D CMP ), so that the filter can adjust the output frequency of the ring oscillator based on the quantization result ( D CMP ) to eliminate the phase noise of the phase-locked loop output.

[0081] In a possible implementation manner, Figure 8 is another schematic structural diagram of each non-first phase-locked loop in the digital phase-locked loop provided by the embodiments of the present application. Referring to Figure 8 as shown, the digital-to-analog conversion module includes: a first conversion module and a control module.

[0082] The first input terminal of the first conversion module is connected to the first output terminal of the time-voltage converter, the second input terminal of the first conversion module is connected to the second output terminal of the time-voltage converter, the first output terminal of the first conversion module is connected to the first input terminal of the analog-to-digital conversion module, and the second output terminal of the first conversion module is connected to the second input terminal of the analog-to-digital conversion module; the control terminal of the first conversion module is connected to the first output terminal of the control module; the first input terminal of the control module is connected to the output terminal of the analog-to-digital conversion module of the previous phase-locked loop.

[0083] Optionally, the first conversion module may include multiple digital-to-analog converters. For example, it may include a 7-bit capacitive digital-to-analog converter (7b Capacitive Digital-to-Analog Converter, abbreviated as 7b-CDAC), which is used to implement digital-to-analog conversion using a capacitor array and has a resolution of 7 bits.

[0084] Optionally, the first conversion module may further include multiple 9-bit capacitive digital-to-analog converters (9b Capacitive Digital-to-Analog Converter, abbreviated as 9b-CDAC), which are used to implement digital-to-analog conversion using a capacitor array and have a resolution of 9 bits.

[0085] Optionally, Figure 8 Taking a two-stage phase-locked loop as an example for illustration, referring to Figure 8 as shown, the control module is used to generate different noise cancellation digital codes based on the noise quantization signal output by the analog-to-digital conversion module of the previous phase-locked loop ( D FFNC ), so as to cancel different types of noise, so that the first conversion module can cancel the phase noise output by the previous phase-locked loop.

[0086] In a possible implementation manner, Figure 9 This is another structural schematic diagram of each non-first phase-locked loop in the digital phase-locked loop provided by the embodiments of the present application. Referring to Figure 9 as shown, on the basis of Figure 8 , the digital-to-analog conversion module further includes: a second conversion module.

[0087] The first input terminal of the second conversion module is connected to the first output terminal of the time-voltage converter and the first output terminal of the first conversion module, the second input terminal of the second conversion module is connected to the second output terminal of the time-voltage converter and the second output terminal of the first conversion module, the first output terminal of the second conversion module is connected to the first input terminal of the analog-to-digital conversion module, and the second output terminal of the second conversion module is connected to the second input terminal of the analog-to-digital conversion module; the control terminal of the second conversion module is connected to the second output terminal of the control module, and the second input terminal of the control module is connected to the output terminal of the ring oscillator.

[0088] Optionally, when the frequency divider is a fractional frequency divider, a second conversion module can be added to the digital-to-analog conversion module to eliminate the quantization noise generated by the fractional frequency divider through the second conversion module.

[0089] Optionally, Figure 9 Taking a two-stage phase-locked loop as an example for illustration, referring to Figure 9 as shown, the control module is used to generate different quantization noise cancellation digital codes ( D QNC ) based on the processed signals output by the ring oscillators of each phase-locked loop to eliminate the voltage error caused by the quantization noise brought by fractional frequency division.

[0090] Optionally, the second conversion module can include multiple digital-to-analog converters. For example, it can include a 9b capacitive digital-to-analog converter (9b Capacitive Digital-to-Analog Converter, abbreviated as 9b-CDAC) for implementing digital-to-analog conversion using a capacitor array and having a resolution of 9 bits.

[0091] Optionally, the second conversion module can also include multiple 7b capacitive digital-to-analog converters (7b Capacitive Digital-to-Analog Converter, abbreviated as 7b-CDAC) for implementing digital-to-analog conversion using a capacitor array and having a resolution of 7 bits.

[0092] In a possible implementation manner, Figure 10 is another structural schematic diagram of each non-first phase-locked loop in the digital phase-locked loop provided by the embodiments of the present application. Referring to Figure 10 as shown, on the basis of Figure 9 , the first conversion module includes: a third digital-to-analog converter and a fourth digital-to-analog converter; the second conversion module includes: a fifth digital-to-analog converter and a sixth digital-to-analog converter.

[0093] The input end of the third digital-to-analog converter is connected to the first output end of the time-voltage converter, and the input end of the fourth digital-to-analog converter is connected to the second output end of the time-voltage converter; the output end of the third digital-to-analog converter is connected to the input end of the fifth digital-to-analog converter, and the output end of the fourth digital-to-analog converter is connected to the input end of the sixth digital-to-analog converter; the control end of the third digital-to-analog converter and the control end of the fourth digital-to-analog converter are connected to the first output end of the control module, and the control end of the fifth digital-to-analog converter and the control end of the sixth digital-to-analog converter are connected to the second output end of the control module.

[0094] Optionally, the third digital-to-analog converter and the fourth digital-to-analog converter are respectively 7b capacitive digital-to-analog converters (7b Capacitive Digital-to-Analog Converter, abbreviated as 7b-CDAC), and the fifth digital-to-analog converter and the sixth digital-to-analog converter are respectively 9b capacitive digital-to-analog converters (9b Capacitive Digital-to-Analog Converter, abbreviated as 9b-CDAC); alternatively, the third digital-to-analog converter and the fourth digital-to-analog converter are respectively 9b capacitive digital-to-analog converters (9b Capacitive Digital-to-Analog Converter, abbreviated as 9b-CDAC), and the fifth digital-to-analog converter and the sixth digital-to-analog converter are respectively 7b capacitive digital-to-analog converters (7b Capacitive Digital-to-Analog Converter, abbreviated as 7b-CDAC).

[0095] The following takes a digital phase-locked loop including two cascaded phase-locked loops, where the first-stage phase-locked loop adopts an integer frequency division method and the second-stage phase-locked loop adopts a fractional frequency division method to provide an overall description of the principle of the digital phase-locked loop provided by the embodiments of the present application.

[0096] Figure 11 For another structural schematic diagram of the digital phase-locked loop provided by the embodiments of the present application, refer to Figure 11 As shown, in a fractional frequency division digital phase-locked loop based on a ring oscillator designed using a 28nm CMOS process, the first-stage phase-locked loop is an integer phase-locked loop, including a time-to-voltage converter, an analog-to-digital conversion module composed of a 7b successive approximation analog-to-digital converter (7b-SAR-ADC), multiple compensation capacitors, a filter composed of a digital loop filter, and a digitally controlled ring oscillator and an integer frequency divider with retiming. The second-stage phase-locked loop is a fractional phase-locked loop, including a time-to-voltage converter, a digital-to-analog conversion module composed of two 7b capacitive digital-to-analog converters (7b-CDAC2) and two 9b capacitive digital-to-analog converters (9b-CDAC), a comparator, a digital loop filter, a digitally controlled ring oscillator, and a fractional frequency divider. Among them, the output of the second-stage phase-locked loop is the final output of the entire digital phase-locked loop.

[0097] Continue to refer to Figure 11 As shown, in the first-stage phase-locked loop, by comparing with a reference signal ( S REF ), the time error caused by the phase noise of the output signal ( S OUT,PLL1 ) of the first-stage phase-locked loop is converted into a voltage difference ( V SAM+,PLL1 –V SAM–,PLL1 )。This voltage difference is then quantized by the analog-to-digital conversion module 7b-SAR-ADC to obtain a digital quantization result ( D ADC ). D ADC Subsequently, the output frequency of the oscillator is adjusted by a digital loop filter to eliminate the phase noise output by the first-stage phase-locked loop. At the same time, D ADC it is sent to the second-stage phase-locked loop to achieve feedforward cancellation of phase noise in the voltage domain.

[0098] In the second-stage phase-locked loop, by comparing with S OUT,PLL1 , the time error caused by the phase noise of the output of the second-stage phase-locked loop ( S OUT,PLL2 ) is first converted into a voltage difference by a time-to-voltage converter ( V SAM+,PLL2 – V SAM–,PLL2 ). Subsequently, according to D ADC and the quantization noise digital code output by the fractional divider ( D QN ), the CDAC control module in the digital-to-analog conversion module outputs a phase noise cancellation digital code ( D FFNC ) and a quantization noise cancellation digital code ( D QNC ) to control the 7b-CDAC2 in the first conversion module and the 9b-CDAC in the second conversion module respectively, so as to eliminate respectively V SAM+,PLL2 – V SAM–,PLL2 the voltage errors caused by the phase noise output by the first-stage phase-locked loop and the quantization noise brought by the fractional division of the second-stage phase-locked loop. After all the above processes are completed, this voltage difference is finally quantized by a comparator to obtain a digital quantization result ( D CMP ). D CMP Subsequently, the output frequency of the oscillator is adjusted by a digital loop filter to eliminate the phase noise output by the second-stage phase-locked loop to obtain the final output result.

[0099] Among them, the minimum voltage adjustment unit of the digital-to-analog converter in the analog-to-digital conversion module in the first-stage phase-locked loop and the minimum voltage adjustment units of each digital-to-analog converter in the digital-to-analog conversion module in the second-stage phase-locked loop can be adjusted to make the phase noise cancellation gain of the digital phase-locked loop provided by the embodiments of the present application be 1.

[0100] Exemplarily, the minimum voltage adjustment units of the 7b capacitive digital-to-analog converters in the analog-to-digital conversion module of the first-level phase-locked loop can be set to the same voltage adjustment units as those of the 7b capacitive digital-to-analog converters in the digital-to-analog conversion module of the second-level phase-locked loop, and the capacitance values of the compensation capacitors in the first-level phase-locked loop can be set to the same capacitance values as those of the 9b capacitive digital-to-analog converters in the digital-to-analog conversion module of the second-level phase-locked loop, so as to ensure the conversion gain of the time-to-voltage converter of the first-level phase-locked loop K TVC1 and the conversion gain of the time-to-voltage converter of the second-level phase-locked loop K TVC2 are equal, so that the phase noise cancellation gain does not require any calibration under PVT variations. At this time, the phase noise cancellation gain of the digital phase-locked loop provided by the embodiments of the present application G V-FFNC can be expressed by the following formula (4): (4) It should be understood that the digital phase-locked loop provided by the embodiments of the present application includes the voltage-domain phase noise feedforward cancellation technology provided by the present application. The verification results of the voltage-domain phase noise feedforward cancellation technology provided by the present application are described below by way of example.

[0101] Figure 12 is a schematic diagram of a simulation result of the digital phase-locked loop provided by the embodiments of the present application under circuit mismatch. Referring to Figure 12 as shown, the change in the phase noise cancellation gain will affect the root mean square jitter ( J PLL2 ) output by the second-level phase-locked loop. However, according to 100 Monte Carlo simulation results, the 3σ offset is 6%. According to simulation and calculation, the deterioration of the root mean square jitter output by the second-level phase-locked loop caused by a gain error less than 10% can be ignored. Therefore, the digital phase-locked loop provided by the embodiments of the present application can still maintain strong robustness in the presence of circuit mismatch.

[0102] The test results of the digital phase-locked loop provided by the embodiments of the present application are as follows: During the test, the reference input ( S REF ) of this digital phase-locked loop is provided by a crystal oscillator with an output frequency of 200 MHz. The output frequency of the first-level integer phase-locked loop is 1 GHz, and the output frequency of the second-level phase-locked loop is a fractional frequency close to 5.5 GHz.

[0103] Figure 13 is a schematic diagram of a phase noise test of the second-level phase-locked loop in the digital phase-locked loop provided by the embodiments of the present application, Figure 14A schematic diagram showing the test of the output jitter of the second-stage phase-locked loop in the digital phase-locked loop provided by the embodiments of the present application varying with the power supply voltage and temperature. Figure 15 A schematic diagram showing the test results of the output jitter of different chips in the digital phase-locked loop provided by the embodiments of the present application. Refer to Figure 13 、 Figure 14 and Figure 15 As shown, when the voltage-domain phase noise feedforward cancellation technology provided by the embodiments of the present application is not adopted, the root mean square jitter of the output of the second-stage phase-locked loop is 576 fs; when the voltage-domain phase noise feedforward cancellation technology provided by the embodiments of the present application is adopted, the root mean square jitter of the output of the second-stage phase-locked loop drops to 291 fs. This test result shows that the digital phase-locked loop provided by the embodiments of the present application significantly improves the phase noise of the phase-locked loop output, and the digital phase-locked loop provided by the embodiments of the present application does not require gain calibration.

[0104] According to Figure 14 the measurement results shown in, when the power supply voltage ( V DD ) varies (±5%) and the temperature varies (-20~100 °C), the change in the root mean square jitter of the output of the second-stage phase-locked loop is measured to be less than 7.5%. The root mean square jitter of the output of a total of 8 phase-locked loop chips is tested. According to Figure 15 the test results shown in, the jitter change of the 8 tested chips is less than 10%. Figure 14 and Figure 15 These two test results show that the digital phase-locked loop provided by the embodiments of the present application is very robust under PVT variations and meets the design purpose of the digital phase-locked loop provided by the embodiments of the present application.

[0105] Based on the same inventive concept, the embodiments of the present application provide a clock circuit, which includes: the above digital phase-locked loop.

[0106] Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the above-described systems and devices can refer to the corresponding processes in the method embodiments, which will not be elaborated in the present application. In several embodiments provided by the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. The device embodiments described above are only illustrative. For example, the division of modules is only a logical function division, and there can be other division methods in actual implementation. For another example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point, the displayed or discussed mutual coupling or direct coupling or communication connection can be through some communication interfaces, and the indirect coupling or communication connection of devices or modules can be in an electrical, mechanical or other form.

[0107] In addition, each functional unit in various embodiments of the present application may be integrated into one processing unit, may exist physically alone for each unit, or two or more units may be integrated into one unit. If the function is implemented in the form of a software functional unit and sold or used as an independent product, it may be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, may be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs that can store program codes.

[0108] The above are only specific implementation manners of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed in the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application.

Claims

1. A digital phase-locked loop, characterized in that: include: Multiple phase-locked loops; Each of the phase-locked loops at least includes: a time-to-voltage converter, an analog-to-digital conversion module, a filter, and a ring oscillator; Each non-first phase-locked loop among the plurality of phase-locked loops further includes: a digital-to-analog conversion module; The first input end of the time-to-voltage converter of the first phase-locked loop is used to access the reference signal, the second input end of the time-to-voltage converter of the first phase-locked loop is used to access the processed signal of the first phase-locked loop, each output end of the time-to-voltage converter of the first phase-locked loop is connected to each input end of the analog-to-digital conversion module of the first phase-locked loop in a one-to-one correspondence, the output end of the analog-to-digital conversion module of the first phase-locked loop is connected to the second input end of the digital-to-analog conversion module of the next phase-locked loop and the input end of the filter of the first phase-locked loop, the output end of the filter of the first phase-locked loop is connected to the input end of the ring oscillator of the first phase-locked loop, and the output end of the ring oscillator of the first phase-locked loop is used to output the processed signal of the first phase-locked loop; The first input end of the time voltage converter of each non-first phase-locked loop is used to access the processed signal of the previous phase-locked loop, and the second input end of the time voltage converter of each non-first phase-locked loop is used to access the processed signal of each non-first phase-locked loop, each output end of the time voltage converter of each non-first phase-locked loop is respectively connected to each input end of the digital-to-analog conversion module of each phase-locked loop in a one-to-one correspondence, and each output end of the digital-to-analog conversion module of each non-first phase-locked loop is respectively connected to each input end of the analog-to-digital conversion module of each non-first phase-locked loop in a one-to-one correspondence; The output end of the analog-to-digital conversion module of each non-first phase-locked loop except the last phase-locked loop is connected to the second input end of the digital-to-analog conversion module of the next phase-locked loop and the input end of the filter of each phase-locked loop except the last phase-locked loop in each non-first phase-locked loop, and the output end of the analog-to-digital conversion module of the last phase-locked loop is connected to the input end of the filter of the phase-locked loop of the last phase-locked loop in each non-first phase-locked loop; The output end of the filter of each non-first phase-locked loop is connected to the input end of the ring oscillator of each non-first phase-locked loop, and the output end of the ring oscillator of each non-first phase-locked loop is used to output the processed signal of each non-first phase-locked loop; Each phase-locked loop except the last phase-locked loop is used to generate and output a noise quantization signal to an analog-to-digital conversion module of a next phase-locked loop based on an input signal input to a first input terminal of each time-to-voltage converter and an input signal input to a second input terminal, and output a processed signal to a second input terminal of each time-to-voltage converter according to the noise quantization signal; Each non-first phase-locked loop is used to output a noise-eliminated output signal based on an input signal of a first input terminal and an input signal of a second input terminal of each time-to-voltage converter and a noise quantization signal of a previous phase-locked loop.

2. The digital phase-locked loop according to claim 1, characterized in that: The output end of each of the time-to-voltage converters includes a first output end and a second output end, and each of the time-to-voltage converters is used to generate time difference information of the input signal of the first input end and the input signal of the second input end according to time information of the input signal of the first input end and the input signal of the second input end, and output a first voltage through the first output end and output a second voltage through the second output end according to the time difference information; The analog-to-digital conversion module of the first phase-locked loop is used to determine a noise quantization signal of an input signal of the first input terminal and an input signal of the second input terminal based on a first voltage and a second voltage; The digital-to-analog conversion module of each non-first phase-locked loop is used to generate a voltage signal after the output phase noise of the preceding phase-locked loop of each non-first phase-locked loop is eliminated based on the first voltage, the second voltage and the noise quantization signal of the preceding phase-locked loop; The analog-to-digital conversion modules of each non-first phase-locked loop are used to generate noise quantization signals of each non-first phase-locked loop based on the voltage signal after the phase noise of the previous phase-locked loop is eliminated; Each of the filters and each of the ring oscillators of each of the phase-locked loops are used to output a processed signal of each phase-locked loop based on a noise quantization signal output by an analog-to-digital conversion module of each phase-locked loop.

3. The digital phase-locked loop according to claim 2, characterized in that: The analog-to-digital conversion module of the first phase-locked loop includes: a first digital-to-analog converter, a second digital-to-analog converter and a comparison processing module; The input end of the first digital-to-analog converter is connected to the first output end of the time-to-voltage converter, and the input end of the second digital-to-analog converter is connected to the second output end of the time-to-voltage converter; The first digital-to-analog converter is used to perform digital-to-analog conversion on the first voltage from the first output terminal to obtain and output a first voltage signal to the comparison processing module; the second digital-to-analog converter is used to perform digital-to-analog conversion on the second voltage from the second output terminal to obtain and output a second voltage signal to the comparison processing module; the comparison processing module is used to perform differential processing on the first voltage signal and the second voltage signal and output the noise quantization signal.

4. The digital phase-locked loop according to claim 2, characterized in that: Each of the phase-locked loops further includes: a frequency divider; The input end of the frequency divider is connected to the output end of the ring oscillator, and the output end of the frequency divider is connected to the second input end of the time-to-voltage converter.

5. The digital phase-locked loop according to claim 2, characterized in that: The analog-to-digital conversion modules of each non-first phase-locked loop include: a comparator; The input end of the comparator is connected to the first output end and the second output end of the digital-to-analog conversion module.

6. The digital phase-locked loop according to claim 2, characterized in that: The digital-to-analog conversion module includes: a first conversion module and a control module; The first input end of the first conversion module is connected to the first output end of the time-to-voltage converter, the second input end of the first conversion module is connected to the second output end of the time-to-voltage converter, the first output end of the first conversion module is connected to the first input end of the analog-to-digital conversion module, and the second output end of the first conversion module is connected to the second input end of the analog-to-digital conversion module; The control end of the first conversion module is connected to the first output end of the control module; The first input terminal of the control module is connected to the output terminal of the analog-to-digital conversion module of the previous phase-locked loop.

7. The digital phase-locked loop according to claim 6, characterized in that: The digital-to-analog conversion module further includes: a second conversion module; The first input end of the second conversion module is connected to the first output end of the time-to-voltage converter and the first output end of the first conversion module, the second input end of the second conversion module is connected to the second output end of the time-to-voltage converter and the second output end of the first conversion module, the first output end of the second conversion module is connected to the first input end of the analog-to-digital conversion module, and the second output end of the second conversion module is connected to the second input end of the analog-to-digital conversion module; The control end of the second conversion module is connected to the second output end of the control module, and the second input end of the control module is connected to the output end of the ring oscillator.

8. The digital phase-locked loop according to claim 7, characterized in that: The first conversion module includes: a third digital-to-analog converter and a fourth digital-to-analog converter; the second conversion module includes: a fifth digital-to-analog converter and a sixth digital-to-analog converter; The input end of the third digital-to-analog converter is connected to the first output end of the time-to-voltage converter, and the input end of the fourth digital-to-analog converter is connected to the second output end of the time-to-voltage converter; The output end of the third digital-to-analog converter is connected to the input end of the fifth digital-to-analog converter, and the output end of the fourth digital-to-analog converter is connected to the input end of the sixth digital-to-analog converter; The control end of the third digital-to-analog converter and the control end of the fourth digital-to-analog converter are connected to the first output end of the control module, and the control end of the fifth digital-to-analog converter and the control end of the sixth digital-to-analog converter are connected to the second output end of the control module.

9. The digital phase-locked loop according to claim 8, characterized in that: The third digital-to-analog converter and the fourth digital-to-analog converter are 7b capacitive digital-to-analog converters respectively, and the fifth digital-to-analog converter and the sixth digital-to-analog converter are 9b capacitive digital-to-analog converters respectively; or, The third digital-to-analog converter and the fourth digital-to-analog converter are respectively 9b capacitive digital-to-analog converters, and the fifth digital-to-analog converter and the sixth digital-to-analog converter are respectively 7b capacitive digital-to-analog converters.

10. A clock circuit, characterized in that: The digital phase-locked loop comprises the digital phase-locked loop as described in any one of claims 1 to 9.

Images