Continuous-time pipelined analog-to-digital converter based on multi-path interleaved time domain

Abstract

The application provides a continuous time pipeline analog-to-digital converter based on multi-path interleaving time domain, comprising a continuous time stage ADC, a time domain ADC and a digital reconfigurable filter; the continuous time stage ADC performs high-bit quantization on an input signal and outputs the input signal to the digital reconfigurable filter, and performs filtering processing on a residual signal in the input signal and outputs the residual signal to the time domain ADC; the time domain ADC is used for quantizing the residual signal passing through the continuous time stage ADC and outputting the residual signal to the digital reconfigurable filter; and the digital reconfigurable filter is used for performing digital filtering on a quantization result of the continuous time stage ADC and performing data reconstruction on a quantization code value output by the time domain ADC. The architecture not only retains the characteristics of the time domain ADC, such as super high energy efficiency and digitization, but also benefits from the continuous time ADC architecture, the resistive input impedance and the inherent anti-aliasing filtering effect, and is helpful to realize a high-speed ADC in a completely integrated wireless receiver.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and more specifically to a continuous-time pipelined analog-to-digital converter based on a multi-interleaved time domain. Background Technology

[0002] Time-domain ADCs are a promising new architecture for high speed and high energy efficiency. They are of great significance and research value for realizing high-performance and ultra-high-speed communication systems. In particular, in radio frequency receivers or zero-IF receivers, hybrid-domain ADCs, which are composed of a front-stage voltage-domain sub-ADC cascaded with a subsequent multi-channel time-domain ADC, have a higher energy efficiency ratio than pure voltage-domain ADCs.

[0003] Most ADC architectures are implemented in discrete-domain (DT) circuitry, which requires switched capacitors for sampling before subsequent signal processing. However, discrete-time (DT) ADCs require additional circuitry in fully integrated wireless receiver applications, such as anti-aliasing filters (AAF) to filter out out-of-band sideband signals, and ADC driver stage circuitry to drive a pF-level switched capacitor sampling network and suppress back kickback, thereby increasing system-level power consumption and system design complexity. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a continuous-time pipelined analog-to-digital converter based on multi-interleaved time domain, specifically comprising:

[0005] In a first aspect, the present invention provides a continuous-time pipelined analog-to-digital converter based on a multi-interleaved time domain, comprising:

[0006] Continuous-time ADC, time-domain ADC, and digital reconfigurable filters;

[0007] A continuous-time ADC performs high-level quantization on the input signal, outputs the quantization result to a digitally reconfigurable filter, filters the residual signal in the input signal, and outputs the processed signal to a time-domain ADC.

[0008] Specifically, the continuous-time ADC serves as the input of the overall ADC, performing high-order quantization of the input signal and filtering of the residual signal, while its output is connected to the input of the time-domain ADC.

[0009] A time-domain ADC quantizes the residual signal after passing through a continuous-time-domain ADC and outputs the quantized code value to a digitally reconfigurable filter.

[0010] Specifically, the input of the time-domain ADC is connected to the output of the continuous-time ADC to quantize the residual signal after the continuous-time ADC.

[0011] Digitally reconfigurable filters are used to digitally filter the quantization results of continuous-time ADCs and reconstruct the quantized code values ​​output by time-domain ADCs, thereby achieving anti-aliasing filtering effects.

[0012] Specifically, the input of the digitally reconfigurable filter is connected to the quantization result of the continuous-time stage, which is used to digitally filter the quantized code value of the continuous-time stage ADC and reconstruct the quantized code value of the subsequent time-domain ADC to achieve anti-aliasing filtering effect.

[0013] In a second aspect, the present invention also provides an electronic device comprising any of the continuous-time pipelined analog-to-digital converters based on the multi-interleaved time domain as provided in the first aspect.

[0014] The beneficial effects of this invention are:

[0015] The present invention provides a continuous-time pipelined analog-to-digital converter based on multi-interleaved time domain, comprising: a continuous-time ADC, a time-domain ADC, and a digitally reconfigurable filter; the continuous-time ADC is used to perform high-bit quantization on the input signal and output the quantization result to the digitally reconfigurable filter, and to filter the residual signal in the input signal, and output the processed signal to the time-domain ADC; the time-domain ADC is used to quantize the residual signal after passing through the continuous-time ADC, and output the obtained quantized code value to the digitally reconfigurable filter; the digitally reconfigurable filter is used to digitally filter the quantization result of the continuous-time ADC and to reconstruct the data of the quantized code value output by the time-domain ADC, thereby achieving anti-aliasing filtering effect. This architecture retains the ultra-high energy efficiency and digital characteristics of the time-domain ADC, and also benefits from the resistive input impedance and inherent anti-aliasing filtering effect of the continuous-time ADC architecture, which is of great significance for the design of high-speed ADCs and system design in fully integrated wireless receivers.

[0016] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0017] Figure 1 A schematic diagram of a continuous-time pipelined analog-to-digital converter based on multi-interleaved time domain provided by the present invention;

[0018] Figure 2 This is a schematic diagram of a delay chain array provided by the present invention;

[0019] Figure 3 A schematic diagram of a filter circuit provided by the present invention;

[0020] Figure 4 A schematic diagram of the calibration process of an IDAC circuit provided by the present invention;

[0021] Figure 5 A schematic diagram of the impulse response of a digitally reconfigurable digital filter provided by the present invention;

[0022] Figure 6 A schematic diagram illustrating the operation process of a digitally reconfigurable digital filter provided by the present invention;

[0023] Figure 7 A schematic diagram of the architecture of a high-efficiency time-domain ADC based on a ring oscillator provided by the present invention;

[0024] Figure 8 A schematic diagram of experimental results provided by the present invention;

[0025] Figure 9 This is a schematic diagram of another experimental result provided by the present invention. Detailed Implementation

[0026] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0027] To address the problems existing in the prior art, this invention proposes a continuous-time pipelined analog-to-digital converter based on multi-interleaved time domain. This ADC architecture retains the ultra-high energy efficiency and digitization characteristics of time-domain ADCs, and also benefits from the resistive input impedance and inherent anti-aliasing filtering effect of continuous-time ADC architecture. This is of great significance for the design of high-speed ADCs and system design in fully integrated wireless receivers.

[0028] Figure 1 The present invention provides a schematic diagram of a continuous-time pipelined analog-to-digital converter based on multi-interleaved time domain, comprising: a continuous-time ADC10, a time-domain ADC, and a digital reconfigurable filter.

[0029] The continuous-time ADC10 is used to perform high-level quantization on the input signal and output the quantization result to the digital reconfigurable filter. It also filters the residual signal in the input signal and outputs the processed signal to the time-domain ADC.

[0030] A time-domain ADC is used to quantize the residual signal after passing through a continuous-time ADC, and outputs the quantized code value to a digital reconfigurable filter.

[0031] Digitally reconfigurable filters are used to digitally filter the quantization results of continuous-time ADCs and reconstruct the quantized code values ​​output by time-domain ADCs, thereby achieving anti-aliasing filtering effects.

[0032] Optional, such as Figure 1As shown, the continuous-time ADC10 includes: filter circuit 101, sub-ADC, IDAC, DAC and PRBS.

[0033] The filter circuit 101 is used to amplify the signal residual and implement anti-aliasing filtering.

[0034] The sub-ADC quantizes the input signal and generates quantized code values ​​for output.

[0035] The IDAC controls the current output by the quantized code value output by the sub-ADC. The sum of the outputs of each controlled IDAC is subtracted from the input current signal at the output of the delay chain and connected to the TIA, flowing into the TIA.

[0036] DAC, or 1-bit IDAC, is used to generate a 1-bit random pulse signal based on the pseudo-random signal generated by PRBS.

[0037] PRBS is used to control a 1-bit IDAC based on the generated pseudo-random signal.

[0038] Specifically, PRBS is used to generate a "0,1" bitstream with pseudo-random properties to control 1-bit IDAC individually.

[0039] Optionally, the filter circuit 101 includes: a delay chain array, a residual amplifier, and an RC feedback unit.

[0040] The output of the delay chain array 1110 is connected to the inverting input of the residual amplifier, and the input is used to receive the external voltage V. in The RC feedback unit is connected between the output and inverting input of the residual amplifier; the non-inverting input of the residual amplifier is grounded.

[0041] For example, such as Figure 2 As shown, the delay chain array is composed of RC low-pass filters.

[0042] like Figure 2 As shown, the delay chain array includes a low-pass filter composed of N RC chips. The N RC chips are connected in parallel, with one end serving as the input signal port and the other end connected to the IDAC output, together generating a residual current signal that flows through the filter circuit 101.

[0043] Each RC low-pass filter includes a capacitor, a resistor, and a control switch.

[0044] In pipelined ADCs, generating a residual signal of appropriate amplitude requires phase delay matching between the signal passing through the main path and the IDAC output signal. However, in CT_Pipeline (continuous-time pipelined) ADCs, to avoid spectral aliasing introduced by sampling, the input signal passes directly through the main signal path without sampling, resulting in no input signal delay. This leads to phase mismatch with the IDAC output signal, resulting in a residual signal larger than the input signal amplitude. By using a delay chain array, a positive delay can be introduced into the signal path to match the phase difference and obtain the correct residual signal.

[0045] One of the major advantages of CT ADC is its inherent anti-aliasing filter. In wireless receiver system applications, CT ADC integrates the anti-aliasing filter at the front end of the ADC into the inter-stage residual amplifier inside the ADC.

[0046] For example, such as Figure 3 As shown, the low-pass filter consists of a front-end delay chain array, a TIA (transimpedance amplifier), and external feedback capacitors and resistors. To improve out-of-band rejection and make the out-of-band roll-off more pronounced, filter circuit 101 employs... Figure 3 The second-order Tow-Tomas structure shown requires a larger digitization bandwidth for the ADC due to the demands of 5G / 6G communication systems. The filter operational amplifier needs high gain at the signal bandwidth (500MHz) to achieve high linearity. Furthermore, for a second-order system, operational amplifier stability is also crucial. [The following is a possible approach:] Figure 3 The third-order feedforward operational amplifier shown (corresponding to the AMP section in the figure) requires multiple stages of cascaded operational amplifiers to achieve both high gain and a large GBW (gain-bandwidth product). Traditional cascading of two or more stages requires Miller compensation and other methods to ensure phase margin and stability, which pushes the poles inward, reducing the overall GBW. Conversely, Figure 3 The feedforward operational amplifier shown provides zeros by adding feedforward paths, forming zero-pole pairs near the poles to cancel out the effects of the poles. Thus, a multi-stage, multi-path feedforward amplifier can achieve high-frequency, high-gain at a lower unity-gain frequency.

[0047] Optionally, the selection of the filter's DC gain, cutoff frequency, and order, as well as the phase matching effect of the aforementioned delay chain array and the number of bits for coarse quantization in the continuous time stage, are all related.

[0048] Optional, the IDAC includes: a complementary current-steering IDAC array and a calibration circuit, the calibration circuit comprising a switch array and a sequential rotation control signal generation module.

[0049] The switching array is used to control the reference voltages of the complementary current steering IDAC array in a hot-swappable manner based on the control signals generated by the sequential rotation control signal generation module.

[0050] like Figure 4 As shown, the IDAC circuit includes a complementary current-rudder IDAC array and a calibration circuit. The reference voltage is obtained by voltage division by a series of resistors. The reference voltage is not directly connected to the input of the comparator (COMP). Each reference voltage is connected to the input of the comparator through a switch array consisting of several switches. The control signal of this switch array is generated by a dedicated pseudo-random control signal generation circuit, which updates the reference voltage at the input of each comparator in real time according to the cycle, realizing the effect of reference voltage rotation. This indirectly realizes the effect of sequential rotation of the IDAC circuit. The output of the comparator controls the output of the IDAC circuit, injecting or extracting current into the TIA input node, completing the difference between the signal and the first-stage coarse quantization result to generate residual current, which is amplified by the TIA and then sent to the subsequent ADC for quantization processing.

[0051] Optionally, the reconstruction logic of a digitally reconfigurable filter is represented as follows:

[0052] D out_cali (n)=D1'(n)+D2(n)-D 2_prbs (n),

[0053]

[0054] Among them, D out_cali D1'(n) represents the reconstructed output signal, where n is the index of the clock cycle. D1'(n) represents the continuous-time digital code after convergence of digital domain filtering over n clock cycles. D2(n) represents the quantized digital code of the residual signal by the time-domain ADC in the nth clock cycle. 2_prbs D1(n) represents the digital code of the PRBS generation module after convergence of digital domain filtering over n clock cycles, D1(n) represents the continuous time-level quantized digital code of the nth clock cycle, and d1(n) represents the digital code of the PRBS generation module of the nth clock cycle. This means that when a unit pulse is injected into the filter input, after passing through the filter, the subsequent time-domain ADC will respond in the current period with a system response delayed by one period. This means that when a unit pulse is injected into the filter input, after passing through the filter, the subsequent time-domain ADC will provide the system response in the current period, delayed by two periods. This means that when a unit pulse is injected into the filter input, after passing through the filter, the subsequent time-domain ADC will respond in the current period and with a delay of three periods.

[0055] For example, the signal reconstruction process of a CT Pipeline ADC is as follows: Figure 5 As shown, similar to the DT Pipeline ADC, but due to the filter, the pulse injected into the IDAC will have its observed pulse response distributed across multiple cycles (instead of just one cycle as in the DT Pipeline ADC), denoted as F(z). This invention can also design the filter as 1 / F(z) to reconstruct the input signal, but the challenge is that 1 / F(z) corresponds to a non-causal sequence in the digital domain. Therefore, this invention introduces filter A, designed as F(z), and filter B as unit 1, to restore causality. The filter tap coefficients are obtained based on... Figure 6 The cross-correlation operation shown is used to obtain the transfer function H[z]. To obtain the transfer function H[z], a random jitter sequence d[n] is added to the input u[n]. The random jitter sequence d[n] and its delay sequence are correlated with the output y[n] to obtain the cross-correlation result H[z], which is expressed as:

[0056]

[0057] Where H[z] represents the discrete z-domain expression corresponding to the linear time-invariant (LTI) system, and d[ni] represents the digital code of the PRBS generation module before the i-th clock cycle. The expression represents convolution, N represents the filter tap order, y[n] represents the response of the input signal through the linear time-invariant (LTI) system, h[ni] represents the i-th term of the linear time-invariant (LTI) system, and * represents multiplication.

[0058] Given sufficient samples, the correlation between two uncorrelated signals (the input signal sequence and the random jitter sequence) is 0. The correlation coefficient between the random jitter sequence and itself is obtained. With sufficient samples, the correlation coefficient constitutes the taps of the impulse response of H[z]. Correlation operations are then performed sequentially using its delayed sequence to obtain all the tap coefficients. Subsequently, the obtained tap coefficients are used to digitally filter the first-stage coarse quantization code value and reconstruct the subsequent code value, achieving the effects of ADC quantization and anti-aliasing filtering.

[0059] Optional, time-domain ADCs, including single-channel, high-efficiency time-domain ADCs based on ring oscillators.

[0060] For example, the subsequent time-domain ADC uses, as follows Figure 7 The high-efficiency time-domain analog-to-digital converter shown is based on a gated ring oscillator and is formed by time-domain interleaving.

[0061] Optionally, a high-efficiency time-domain analog-to-digital converter based on a gated ring oscillator specifically includes:

[0062] Voltage-to-time conversion circuit, pulse generation circuit, self-tracking sampling clock generation circuit, and time-to-digital conversion circuit;

[0063] The time-to-digital conversion circuit includes a gated ring oscillator circuit, a comparator quantization circuit, a counter quantization circuit, and a sampling and decoding circuit;

[0064] A voltage-to-time conversion circuit is used to convert a voltage signal into a step signal.

[0065] A pulse generation circuit is used to convert the step signal output by the voltage-time conversion circuit into a pulse width signal.

[0066] The self-tracking sampling clock generation circuit is used to detect the output step signal of the voltage-time conversion circuit and generate a sampling clock signal for the sampling decoding circuit.

[0067] The time-to-digital converter circuit is used to count and quantize the pulse width signal output by the pulse generation circuit to obtain the quantization result.

[0068] Further optional, the gated ring oscillator circuit includes an N-stage gated delay unit, which is cascaded to form a cross-coupled positive feedback circuit. Under the control of an external reset voltage, the internal nodes of the gated delay unit are voltage reset. A positive feedback resistor is connected to the positive feedback path of the gated delay unit. The positive feedback path of the gated delay unit and the gated inverter are controlled by a gate signal generated by a pulse generation circuit, simplifying the subsequent decoding logic and effectively reducing the delay of the gated delay unit. This improves the overall ring oscillator's oscillation frequency and time resolution, and after subsequent coarse quantization, significantly improves the ADC's energy efficiency ratio.

[0069] The present invention provides a continuous-time pipelined analog-to-digital converter based on multi-interleaved time domain, comprising: a continuous-time ADC, a time-domain ADC, and a digitally reconfigurable filter; the continuous-time ADC is used to perform high-bit quantization on the input signal and output the quantization result to the digitally reconfigurable filter, and to filter the residual signal in the input signal, and output the processed signal to the time-domain ADC; the time-domain ADC is used to quantize the residual signal after passing through the continuous-time ADC, and output the obtained quantized code value to the digitally reconfigurable filter; the digitally reconfigurable filter is used to digitally filter the quantization result of the continuous-time ADC and to reconstruct the data of the quantized code value output by the time-domain ADC, thereby achieving anti-aliasing filtering effect. This architecture retains the ultra-high energy efficiency and digital characteristics of the time-domain ADC, and also benefits from the resistive input impedance and inherent anti-aliasing filtering effect of the continuous-time ADC architecture, which is of great significance for the design of high-speed ADCs and system design in fully integrated wireless receivers.

[0070] To further demonstrate the beneficial effects of the present invention, the present invention also provides a set of experimental data, specifically as follows: Figure 8 and Figure 9 As shown, Figure 8 This is the input of the ADC in a real-world application scenario, i.e., the mixer output spectrum. It can be seen that the spectrum includes not only the 100MHz baseband signal but also other sideband frequencies and spurious signals from the mixer. Due to the interference of these sideband frequencies, the dynamic range (SFDR) is only 33.71dBc, and the NSD is -132dBFS / Hz. After quantization and filtering by this continuous-time pipelined analog-to-digital converter based on multi-interleaved time domain (e.g., ... Figure 9 As shown in the figure, the dynamic range SFDR = 58.86dBc is achieved, and the attenuation suppression of the upper sideband is more than 20dB, which achieves the effect of second-order filtering, and the NSD reaches -154dBFS / Hz.

[0071] The present invention also provides an electronic device, including the continuous-time pipelined analog-to-digital converter based on multi-interleaved time domain provided in the above embodiments.

[0072] As the electronic device embodiment is basically similar to the method embodiment, the description is relatively simple. For details and beneficial effects, please refer to the description of the method embodiment.

[0073] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0074] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A continuous-time pipelined analog-to-digital converter based on multi-interleaved time domain, characterized in that, include: Continuous-time ADC, time-domain ADC, and digital reconfigurable filters; The continuous-time ADC is used to perform high-bit quantization on the input signal, output the quantization result to the digital reconfigurable filter, filter the residual signal in the input signal, and output the processed signal to the time-domain ADC. The time-domain ADC is used to quantize the residual signal after passing through the continuous time-level ADC, and output the obtained quantized code value to the digital reconfigurable filter. The digitally reconfigurable filter is used to digitally filter the quantization result of the continuous-time ADC and reconstruct the quantized code value output by the time-domain ADC to achieve anti-aliasing filtering effect. The continuous-time ADC includes an IDAC; the IDAC includes: A complementary current-rudder IDAC array and a calibration circuit, the calibration circuit comprising a switch array and a sequential rotation control signal generation module; The switch array is used to control each reference voltage corresponding to the complementary current steering IDAC array in a hot-swappable manner based on the control signal generated by the sequential rotation control signal generation module. The reconstruction logic of the digitally reconfigurable filter is expressed as follows: ， ， ， in, Indicates the reconstructed output signal. Index representing the clock cycle, Indicates the process The continuous-time digital code obtained after digital domain filtering converges within one clock cycle. Indicates the first The time-domain ADC quantizes the residual signal into digital code over one clock cycle. The table has been passed The digital code generated by the PRBS module after convergence of digital domain filtering over one clock cycle Indicates the first Continuous time-level quantized digital code in one clock cycle Indicates the first The PRBS generates the module's digital code every clock cycle. This means that when a unit pulse is injected into the filter input, after passing through the filter, the subsequent time-domain ADC will respond in the current period with a system response delayed by one period. This means that when a unit pulse is injected into the filter input, after passing through the filter, the subsequent time-domain ADC will provide the system response in the current period, delayed by two periods. This indicates that a unit pulse is injected into the filter input, and after passing through the filter, the subsequent time-domain ADC provides a system response that is delayed by three cycles in the current cycle. The time-domain ADC includes a single-channel, high-efficiency time-domain ADC based on a ring oscillator, specifically comprising a voltage... Time conversion circuit, pulse generation circuit, self-tracking sampling clock generation circuit, and time-to-digital conversion circuit.

2. The continuous-time pipelined analog-to-digital converter based on multi-interleaved time domain according to claim 1, characterized in that, The continuous-time ADC also includes: Filter circuit, sub-ADC, DAC and PRBS; The filter circuit is used to amplify the signal residual and achieve anti-aliasing filtering; The sub-ADC is used to quantize the input signal and output quantization code value; The IDAC is used to output a current signal based on the quantization code value output by the sub-ADC; The DAC is used to generate a 1-bit random pulse signal based on the pseudo-random signal generated by the PRBS. The PRBS is used to generate a "0, 1" code stream with pseudo-random properties and to control 1 bit IDAC independently.

3. The continuous-time pipelined analog-to-digital converter based on multi-interleaved time domain according to claim 2, characterized in that, The filter circuit includes: Delay chain array, residual amplifier and RC feedback unit; The output of the delay chain array is connected to the inverting input of the residual amplifier, and the input is used to receive an external voltage V. in ; The RC feedback unit is connected across the output terminal and the inverting input terminal of the residual amplifier; The non-inverting input terminal of the residual amplifier is grounded.

4. The continuous-time pipelined analog-to-digital converter based on multi-interleaved time domain according to claim 3, characterized in that, The time-to-digital conversion circuit includes a gated ring oscillator circuit, a comparator quantization circuit, a counter quantization circuit, and a sampling decoding circuit; The voltage A time conversion circuit is used to convert a voltage signal into a step signal; The pulse generation circuit is used to convert voltage The step signal output by the time conversion circuit is converted into a pulse width signal; The self-tracking sampling clock generation circuit is used to detect voltage. The step signal output by the time conversion circuit generates a sampling clock signal for the sampling decoding circuit; The time-to-digital converter circuit is used to count and quantize the pulse width signal output by the pulse generation circuit to obtain the quantization result.

5. The continuous-time pipelined analog-to-digital converter based on multi-interleaved time domain according to claim 4, characterized in that, The DC gain of the filter, the cutoff frequency of the filter, the selection of the filter order, the phase matching effect of the delay chain array, and the number of bits of coarse quantization in the continuous time stage are all related.

6. An electronic device, characterized in that, Including the continuous-time pipelined analog-to-digital converter based on the multi-interleaved time domain as described in any one of claims 1-5.

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