Analog-to-digital conversion circuit based on VTC and TDC for RRAM storage and computing integrated chip

Abstract

The present application relates to an analog-to-digital conversion circuit based on VTC and TDC for an RRAM storage and computing integrated chip, wherein the analog-to-digital conversion circuit includes: a first comparator for comparing an input first voltage signal with a first reference signal to output a first digital signal; a charge pump for receiving the first digital signal as an enable voltage, stepping down the input first voltage signal at the enable voltage, and outputting a second voltage signal; a voltage-to-time converter for mapping the second voltage signal into a time domain signal; a time-to-digital converter for mapping the time domain signal into a second digital signal, and outputting the first digital signal and the second digital signal as a combination. The two-stage structure of the present application folds the entire input voltage range once, and optimizes the linear input range and performance of the VTC under large input voltages through a charge pump and a self-biased low-voltage common-source common-gate current mirror, thereby realizing a time domain analog-to-digital conversion circuit with a wide input range and high precision.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to an analog-to-digital conversion circuit based on VTC and TDC for an RRAM storage and computing integrated chip. Background Art

[0002] With the rapid development of artificial intelligence and large-scale model technologies, and their widespread expansion in application areas, massive amounts of data and large-scale model parameters are placing strong and efficient demands on hardware computing power. The storage units in a memory-computing architecture simultaneously store data and perform computations, breaking through the "memory wall" bottleneck created by the separation of storage and computation units in the von Neumann architecture. This is conducive to improving computing efficiency and enhancing hardware computing power. In recent years, resistive random access memory (RRAM), with its low power consumption, high speed, and non-volatility, has attracted widespread attention and demonstrated great potential in memory-computing architectures. The memristor array in an RRAM-based memory-computing chip consists of memristors and transistors. The memristors store information through their resistance values, while the transistors control the on / off state of the memristors. Based on Kirchhoff's current law, the input voltage signal is converted into a multiplication-addition current through the transconductance of the memristor array. The multiplication-addition current is then converted into a digital signal through an analog-to-digital conversion circuit. Turning on different numbers and resistance values of memristor array cells produces different amplitudes of multiplication and addition currents. Given the low precision of this current, it is typically converted into a voltage and then quantized using an analog-to-digital converter. The wide input range and high-precision conversion requirements increase the area and overhead of the analog-to-digital converter circuitry, creating a bottleneck that limits computing performance.

[0003] Based on different signal processing methods, analog-to-digital conversion circuits are categorized as voltage-domain and time-domain. Voltage-domain analog-to-digital conversion circuits discretize and quantize continuous voltage amplitudes, achieving high accuracy within a certain range. However, with advances in semiconductor technology and reductions in supply voltages, achieving high accuracy has become increasingly challenging. Time-domain analog-to-digital conversion circuits have emerged as a response to this need. Their operating principle is to convert an input voltage signal into a time quantity and then convert the time quantity into a digital output. This conversion process is primarily based on digital logic, resulting in high resolution and interference immunity. Traditional time-domain analog-to-digital conversion circuits primarily consist of a voltage-to-time converter (VTC) that converts the voltage signal into a time signal with varying pulse widths, and a time-to-digital converter (TDC) that converts the pulse width into a digital signal. The main limitation of time-domain analog-to-digital conversion circuits in wide input ranges and high precision is the nonlinearity of the VTC. This is because the resistance of the current mirror in a practical VTC is finite, resulting in a limited input linear range, which in turn limits the accuracy of time-domain conversion. Therefore, designing a time-domain analog-to-digital conversion circuit with a wide input range and high accuracy is crucial.

[0004] Currently, there is no effective solution to the problem in related technologies that the input linear range is limited, thereby limiting the accuracy of time domain conversion. Summary of the Invention

[0005] In view of this, it is necessary to provide an analog-to-digital conversion circuit based on VTC and TDC for RRAM storage and computing integrated chip and an RRAM storage and computing integrated chip to solve the problem in related technologies that the input linear range is limited, thereby limiting the accuracy of time domain conversion.

[0006] The present invention provides an analog-to-digital conversion circuit based on VTC and TDC for an RRAM storage and computing integrated chip, comprising a two-stage structure with a folded input voltage range; the first-stage structure comprises a first comparator; the second-stage structure comprises a charge pump, a voltage-to-time converter, and a time-to-digital converter;

[0007] The first comparator is connected to the charge pump and is used to compare the input first voltage signal with a first reference signal to output a first digital signal;

[0008] The charge pump is connected to the voltage-to-time converter, and is configured to receive the first digital signal as an enable voltage, step down the input first voltage signal at the enable voltage, and output a second voltage signal;

[0009] The voltage-to-time converter is connected to the time-to-digital converter and is used to map the second voltage signal into a time domain signal;

[0010] The time-to-digital converter is configured to map the time domain signal into a second digital signal, and output the first digital signal and the second digital signal as a combination.

[0011] In one embodiment, the first comparator compares the first voltage signal and the first reference signal to output the first digital signal, and the first digital signal is used as the charge pump enable voltage control; wherein, the first reference signal is half of the supply voltage, corresponding to folding the input voltage range into half.

[0012] In one embodiment, the charge pump includes an enable voltage control unit, a capacitor C1, a capacitor C2, a diode D1, and a diode D2;

[0013] The enabling voltage control unit is provided between one end of the capacitor C1 and the output end of the first comparator;

[0014] The other end of the capacitor C1 is connected to the anode of the diode D1 and the cathode of the diode D2 respectively;

[0015] The cathode of the diode D1 is connected to the positive input terminal of the first comparator;

[0016] The anode of the diode D2 is connected to one end of the capacitor C2 and the voltage-time converter respectively;

[0017] The other end of the capacitor C2 is grounded.

[0018] In one embodiment, the voltage-to-time converter includes a sample-and-hold module, a second comparator, a current mirror module, and a logic circuit;

[0019] The sampling and holding module is provided between the charge pump and the negative input terminal of the second comparator, and is used to sample and hold the second voltage signal;

[0020] The positive input terminal of the second comparator is connected to the current mirror module, and the output terminal of the second comparator is connected to the logic circuit, and is configured to receive the second voltage signal and the capacitor voltage signal generated by charging of the current mirror module, and compare the second voltage signal with the capacitor voltage signal to output a third voltage signal;

[0021] The logic circuit is used to determine the time domain signal according to the third voltage signal and the clock signal; the pulse width of the time domain signal is proportional to the amplitude of the second voltage signal.

[0022] In one embodiment, the charging current of the capacitor C3 in the voltage-to-time converter is provided by a self-biased low-voltage cascode current mirror; the self-biased low-voltage cascode current mirror biases the gate voltage of the cascode transistor through a resistor.

[0023] In one embodiment, the reference current in the voltage-to-time converter is generated by a bandgap reference circuit and a voltage-to-current circuit;

[0024] The bandgap reference circuit is connected to the voltage-to-current circuit and is used to generate a reference voltage with a low temperature coefficient;

[0025] The voltage-to-current circuit is used to convert the reference voltage into a reference current according to a preset ratio.

[0026] In one embodiment, the logic circuit is a phase detector.

[0027] In one embodiment, the time-to-digital converter includes a delay unit and a D flip-flop;

[0028] The delay unit and the D flip-flop form a delay line structure, which quantizes the pulse width of the time domain signal into digital data to output the second digital signal.

[0029] In one embodiment, the first digital signal output by the first stage structure and the second digital signal output by the second stage structure are combined by a multiplexer and an encoder and then output.

[0030] In the second aspect, an embodiment of the present application provides an RRAM storage and computing integrated chip, including an analog-to-digital conversion circuit based on VTC and TDC for the RRAM storage and computing integrated chip as described in the first aspect above; the analog-to-digital conversion circuit serves as a readout circuit of the RRAM storage and computing integrated chip.

[0031] Through this embodiment, its built-in analog-to-digital conversion circuit serves as the readout circuit of the RRAM storage and computing integrated chip; the two-stage structure of the analog-to-digital conversion circuit folds the entire input voltage range, realizing circuit structure reuse of a single VTC and a single TDC under a wide input range, which has the advantage of reducing the circuit layout area. As the readout circuit of the RRAM storage and computing integrated chip, it quantizes and outputs the resistance value of the memristor array with different numbers and different resistance values turned on.

[0032] The present invention provides an analog-to-digital conversion circuit based on VTC and TDC for an RRAM storage-computing integrated chip, wherein the analog-to-digital conversion circuit includes a first comparator, a charge pump, a voltage-to-time converter, and a time-to-digital converter; the first comparator is connected to the charge pump and is used to compare an input first voltage signal with a first reference signal to output a first digital signal; the charge pump is connected to the voltage-to-time converter and is used to receive the first digital signal as an enable voltage, step down the input first voltage signal at the enable voltage, and output a second voltage signal; the voltage-to-time converter is connected to the time-to-digital converter and is used to map the second voltage signal into a time domain signal; the time-to-digital converter is used to map the time domain signal into a second digital signal and output the first digital signal and the second digital signal as a combination. The analog-to-digital conversion circuit of the present application utilizes a two-stage structure to fold the entire input voltage range once, and optimizes the linear input range and performance of the voltage-to-time converter under large input voltages through a charge pump and a self-biased low-voltage common-source common-gate current mirror in the voltage-to-time converter, thereby solving the problem of limiting conversion accuracy due to the nonlinear characteristics of the voltage-to-time converter and realizing a time-domain analog-to-digital conversion circuit with a wide input range and high precision. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A block diagram of a VTC and TDC-based analog-to-digital conversion circuit for an RRAM storage and computing integrated chip provided in one embodiment of the present invention;

[0034] Figure 2 A circuit diagram of a charge pump provided in one embodiment of the present invention;

[0035] Figure 3A schematic block diagram of a circuit of a voltage-to-time converter provided by one embodiment of the present invention;

[0036] Figure 4 A circuit diagram of a voltage-to-time converter according to an embodiment of the present invention.

[0037] Figure numerals: 10, first comparator; 20, charge pump; 30, voltage-to-time converter; 31, reference current mirror; 32, self-biased low-voltage cascode current mirror; 33, charge and discharge control switch tube; 40, time-to-digital converter. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is described and illustrated below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. Based on the embodiments provided in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application. In addition, it can also be understood that although the efforts made in this development process may be complex and lengthy, for ordinary technicians in the field related to the contents disclosed in the present application, some changes such as design, manufacturing or production based on the technical contents disclosed in the present application are only conventional technical means and should not be understood as the contents disclosed in the present application being insufficient.

[0039] References to "embodiments" in this application mean that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it refer to independent or alternative embodiments that are mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described in this application may be combined with other embodiments unless there is a conflict.

[0040] Unless otherwise defined, the technical terms or scientific terms involved in this application should be understood by people with ordinary skills in the technical field to which this application belongs. In this application, when an element is referred to as "provided on" another element, it can be directly provided on the other element or there can also be a central element. When an element is considered to be "provided on" another element, it can be directly provided on the other element or there can also be a central element. When an element is considered to be "fixed on" another element, it can be directly fixed on the other element or there can also be a central element. The terms "first", "second", "third" and the like involved in this application are merely to distinguish similar objects and do not represent a specific ordering of objects. The terms used in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0041] See also Figure 1 The present invention provides an analog-to-digital conversion circuit based on VTC and TDC for an RRAM storage and computing integrated chip, comprising a two-stage structure with a folded input voltage range; the first-stage structure comprises a first comparator 10; the second-stage structure comprises a charge pump 20, a voltage-to-time converter 30, and a time-to-digital converter 40;

[0042] A first comparator 10 is connected to the charge pump 20 and is used to compare the input first voltage signal with a first reference signal to output a first digital signal;

[0043] The charge pump 20 is connected to the voltage-to-time converter 30 and is configured to receive the first digital signal as an enable voltage, step down the input first voltage signal at the enable voltage, and output a second voltage signal;

[0044] a voltage-to-time converter 30 , connected to the time-to-digital converter 40 , configured to map the second voltage signal into a time domain signal;

[0045] The time-to-digital converter 40 is configured to map the time domain signal into a second digital signal and output the first digital signal and the second digital signal as a combination.

[0046] Specifically, the two-stage structure of the analog-to-digital conversion circuit can fold the input voltage range. The first-stage structure includes a first comparator 10; a first voltage signal is input to the positive input terminal of the first comparator 10; a first reference signal is input to the negative input terminal of the first comparator 10; the first comparator 10 then compares the input first voltage signal with the first reference signal to output a first digital signal; the first digital signal has two functions: the first function is to serve as part of the final output of the analog-to-digital conversion circuit; the other function is to serve as the enable voltage of the charge pump 20 in the second-stage structure to control the operation of the charge pump 20. Preferably, under the conditions of a 180nm process and a power supply voltage VDD of 3.3V, based on linearity, conversion gain, and overhead factors, the input voltage range is selected to be folded in half, and the first reference signal Vref is set to half of the power supply voltage VDD, correspondingly folding the input voltage range in half. The first voltage signal is Vin.

[0047] The second-stage structure includes a charge pump 20, a voltage-to-time converter 30 (VTC), and a time-to-digital converter 40 (TDC). Enabled by a first digital signal, the charge pump 20 steps down the input first voltage signal and outputs a second voltage signal to the voltage-to-time converter 30. The voltage-to-time converter 30 maps the second voltage signal into a time-domain signal and transmits the time-domain signal to the time-to-digital converter 40. The time-to-digital converter 40 maps the time-domain signal into a second digital signal and combines the first digital signal Vout1 and the second digital signal Vout2 into the final output Vout of the analog-to-digital conversion circuit. Preferably, the number of bits of the first digital signal is 1, the number of bits of the second digital signal is 7, and the total number of bits of the output is 8. Therefore, the two-stage structure of the analog-to-digital conversion circuit reduces the requirements for the linear input performance of the VTC and the design bit number of the TDC.

[0048] In related art, a time-domain analog-to-digital conversion circuit primarily consists of a voltage-to-time converter (VTC) 30 and a time-to-digital converter (TDC) 40. The VTC converts voltage signals into time signals with varying pulse widths, while the TDC converts these signals into digital signals. The primary limitation to the wide input range and high-precision applications of time-domain analog-to-digital conversion circuits is the nonlinearity of the VTC. This is because the resistance of the current mirror in a practical VTC is finite, resulting in a limited input linear range and thus limiting the accuracy of time-domain conversion. In this embodiment, the analog-to-digital conversion circuit includes a two-stage structure for folding the input voltage range; the first stage structure includes a first comparator 10; the second stage structure includes a charge pump 20, a voltage-to-time converter 30, and a time-to-digital converter 40; the first comparator 10 is connected to the charge pump 20 and is used to compare the input first voltage signal with the first reference signal to output a first digital signal; the charge pump 20 is connected to the voltage-to-time converter 30 and is used to receive the first digital signal as an enable voltage, step down the input first voltage signal under the enable voltage, and output a second voltage signal; the voltage-to-time converter 30 is connected to the time-to-digital converter 40 and is used to map the second voltage signal into a time signal. domain signal; a time-to-digital converter 40, which is used to map the time domain signal into a second digital signal and output the first digital signal and the second digital signal as a combination. It uses a two-stage structure to fold the entire input voltage range, and realizes circuit structure multiplexing of a single VTC and a single TDC under a wide input range, which has the advantage of reducing the circuit layout area; and through the charge pump 20 and the self-biased low-voltage common-source common-gate current mirror in the voltage-to-time converter 30, the linear input range and performance of the voltage-to-time converter 30 under large input voltages are optimized, solving the problem of limiting conversion accuracy due to the nonlinear characteristics of the voltage-to-time converter 30, and realizing a wide input range and high-precision time domain analog-to-digital conversion circuit.

[0049] The following is a detailed description of each of the above circuits:

[0050] In one embodiment, Figure 2 As shown, the charge pump includes an enable voltage control unit, a capacitor C1, a capacitor C2, a diode D1 and a diode D2;

[0051] The enabling voltage control unit is arranged between one end of the capacitor C1 and the output end of the first comparator;

[0052] The other end of the capacitor C1 is connected to the anode of the diode D1 and the cathode of the diode D2 respectively;

[0053] The cathode of the diode D1 is connected to the positive input terminal of the first comparator;

[0054] The anode of the diode D2 is connected to one end of the capacitor C2 and the voltage-time converter respectively;

[0055] The other end of capacitor C2 is grounded.

[0056] Specifically, capacitor C1 is the charge pump's step-down capacitor, and capacitor C2 is the charge pump's buffer capacitor. Diodes D1 and D2 control the current flow, directing it from the input to the output. This prevents reverse current from entering the first comparator, thereby improving the stability of the analog-to-digital conversion circuit.

[0057] The charge pump outputs a stepped-down first digital signal based on the enable voltage. Its basic principle is to use the charge and discharge of the step-down capacitor to step down the input first voltage signal to the desired output voltage (i.e., output a second voltage signal). The output second voltage signal, Vout3, is the voltage of the input first voltage signal, Vin, minus the voltage of the first digital signal, Vs, using the expression: Vout3 = Vin - Vs.

[0058] The enable voltage control unit includes a single-pole double-throw switch S1, which controls the connection of the enable voltage (first digital signal). Specifically, when the input first voltage signal Vin is greater than the first reference signal Vref, the first comparator output is high. At this time, the single-pole double-throw switch S1 connects enable voltage 1, and the voltage value of enable voltage 1 is VDD / 2. Therefore, the voltage value of the input first voltage signal Vin is considered to be reduced by VDD / 2. When the input first voltage signal Vin is less than or equal to the first reference signal Vref, the first comparator output is low. At this time, the single-pole double-throw switch S1 connects enable voltage 2, and the value of enable voltage 2 is 0. Therefore, the voltage value of the input first voltage signal Vin is considered to be unchanged.

[0059] Through this embodiment, the input voltage range is folded, the maximum input voltage range is expanded, and the reliability of use is high.

[0060] In one embodiment, Figure 3 and Figure 4 As shown, the voltage-to-time converter includes a sample-and-hold module, a second comparator, a current mirror module, and a logic circuit;

[0061] A sampling and holding module is provided between the charge pump and the negative input terminal of the second comparator, and is used for sampling and holding the second voltage signal;

[0062] The positive input terminal of the second comparator is connected to the current mirror module, and the output terminal of the second comparator is connected to the logic circuit, and is used to receive the second voltage signal and the capacitor voltage signal generated by charging of the current mirror module, and compare the second voltage signal with the capacitor voltage signal to output a third voltage signal;

[0063] The logic circuit is used to determine a time domain signal according to the third voltage signal and the clock signal; the pulse width of the time domain signal is proportional to the amplitude of the second voltage signal.

[0064] Specifically, the voltage-to-time converter maps the second voltage signal into a time-domain signal. The basic principle is to simultaneously feed the second voltage signal and the capacitor voltage signal generated by the current mirror module into a second comparator for comparison, outputting a third voltage signal. The third voltage signal is then processed by a logic circuit, resulting in a time-domain signal with a pulse width proportional to the amplitude of the second voltage signal.

[0065] exist Figure 4 In the current mirror module, the current mirror module includes a reference current Iref; a reference current mirror 31 formed by MOS transistors M1 and M2; a self-biased low-voltage cascode current mirror 32 formed by resistor R1, MOS transistors M3, MOS transistors M4, MOS transistors M5, and MOS transistors M6; a charge-discharge control switch 33 formed by MOS transistors M7, MOS transistors M8, and MOS transistors M9; and a capacitor C3. The reference current Iref is connected to the self-biased low-voltage cascode current mirror 32 through the reference current mirror 31. It is typically in the uA range and is set based on factors such as power consumption. The charge and discharge of capacitor C3, along with the current output by the self-biased low-voltage cascode current mirror 32, determine the capacitor voltage signal.

[0066] Among them, the sources of MOS transistors M1 and M2 are grounded; the gate of MOS transistor M1, the drain of MOS transistor M1, and the gate of MOS transistor M2 are all connected to the reference current Iref; the drain of MOS transistor M2 is respectively connected to one end of resistor R1, the gate of MOS transistor M5, and the gate of MOS transistor M6; the other end of resistor R1 is respectively connected to the gate of MOS transistor M3, the gate of MOS transistor M4, and the drain of MOS transistor M5; the source of MOS transistor M5 is connected to the drain of MOS transistor M3; the source of MOS transistor M3 and the source of MOS transistor M4 are both connected to the power supply voltage VD D is connected; the drain of the MOS transistor M4 is connected to the source of the MOS transistor M6; the drain of the MOS transistor M6 generates a charging current IC which is fed to the source of the MOS transistor M7 and the source of the MOS transistor M8; the drain of the MOS transistor M7 is grounded; the gate of the MOS transistor M7 is connected to the clock signal CLKN; the gate of the MOS transistor M8 is connected to the clock signal CLK; the drain of the MOS transistor M8 is respectively connected to one end of the capacitor C3, the drain of the MOS transistor M9, and the positive input end of the second comparator; the other end of the capacitor C3 is grounded; the source of the MOS transistor M9 is grounded; and the gate of the MOS transistor M9 is connected to the clock signal CLK.

[0067] The clock signals CLKN and CLK are opposite at the same time. For example, when the clock signal CLK is high, the clock signal CLKN is low. When the clock signal CLK is high, MOS transistors M7 and M9 are turned on. The current generated by the self-biased low-voltage cascode current mirror 32 flows through MOS transistor M7 to ground. MOS transistor M8's gate is connected to a high level, turning it off. MOS transistor M9 is turned on, discharging capacitor C3 to zero. When the clock signal CLK is low, MOS transistor M8 is turned on, charging capacitor C3. The charging rate is determined by the ratio of the current IC of the self-biased low-voltage cascode current mirror 32 to the capacitance of capacitor C3, I / C. This is because the self-biased low-voltage cascode current mirror 32 generates a constant current to charge the capacitor. When the charging current is constant, the voltage across the capacitor has a linear relationship with time, rising at a constant rate I / C over time. Then when the capacitor voltage signal VC is greater than the negative input of the second comparator (the second voltage signal), it will cause the third voltage signal (the output of the second comparator) to jump; the clock signal CLK and the third voltage signal output by the second comparator are output through the logic circuit as a time domain signal of the phase difference between the two.

[0068] More specifically, M1, M2, and M9 are NMOS transistors, and the others are PMOS transistors. In other embodiments, MOS transistors may also be implemented using other equivalent circuits, which is not limited thereto.

[0069] Preferably, under the conditions of 180nm process and 3.3V supply voltage VDD, the second voltage signal input after charge pump voltage reduction processing meets the linear working range of the single-ended constant current type VTC. Specifically, the capacitance value of capacitor C3 is set according to the following expression:

[0070] ;

[0071] Wherein, k·Iref is the current value of the self-biased low-voltage cascode current mirror 32, k is the amplification factor of the self-biased low-voltage cascode current mirror 32 with respect to the reference current; t is the conversion time, which is related to the operating frequency of the clock signal CLK; Vvtc is the conversion voltage range in the voltage-to-time converter. The input voltage range is folded in half by the first comparator and the charge pump, and Vvtc is set to VDD / 2.

[0072] The sampling and holding module may be controlled by a clock signal CLK to maintain synchronization.

[0073] Through this embodiment, the linear input range and performance of the voltage-to-time converter under large input voltage can be further optimized through the effect of the self-biased low-voltage cascode current mirror 32 .

[0074] In one embodiment, the logic circuit is a phase detector.

[0075] Specifically, the phase detector can quickly output a time domain signal of the phase difference between the third voltage signal and the clock signal CLK, thereby reducing hardware costs.

[0076] In one embodiment, the charging current of the capacitor C3 in the voltage-to-time converter is provided by a self-biased low-voltage cascode current mirror 32 ; the self-biased low-voltage cascode current mirror 32 biases the gate voltage of the cascode transistor through a resistor.

[0077] Specifically, compared with the conventional cascode current mirror, the output voltage margin of this embodiment increases a threshold voltage, thereby improving the linearity of the output current, but the resistance is affected by PVT; that is, through this embodiment, the output voltage margin can be improved and smaller overhead can be achieved.

[0078] Preferably, considering PVT fluctuations and resistance voltage drops, the resistance value R1 refers to Vod / Iref and takes the lower limit, where Vod is the overdrive voltage of the transistor; in order to reduce the body effect, the input tube has a larger W / L; considering the area and voltage margin, the cascode transistor adopts the minimum allowable trench length.

[0079] In one embodiment, Figure 3 As shown, the reference current in the voltage-to-time converter is generated by a bandgap reference circuit and a voltage-to-current circuit;

[0080] a bandgap reference circuit connected to the voltage-to-current circuit and used for generating a reference voltage with a low temperature coefficient;

[0081] The voltage-to-current circuit is used to convert a reference voltage into a reference current according to a preset ratio.

[0082] Specifically, a bandgap reference circuit and a voltage-to-current converter form a bias circuit to generate a reference current for the reference current mirror. The bandgap reference circuit utilizes the sum of a voltage proportional to temperature and a voltage inversely proportional to temperature. The temperature coefficients of these two voltages cancel each other out, creating a temperature-independent voltage reference, typically 1.25V. The voltage-to-current converter operates on the principle of Iref = Vref / R, where R is the resistor value.

[0083] Since the reference voltage has a low temperature coefficient, the reference current converted to a low temperature coefficient according to a preset ratio can be set according to actual use requirements, which is generally at the uA level.

[0084] In one embodiment, the time-to-digital converter includes a delay unit and a D flip-flop;

[0085] The delay unit and the D flip-flop form a delay line structure, which quantizes the pulse width of the time domain signal into digital data to output a second digital signal.

[0086] Specifically, the basic principle of the time-to-digital converter is based on the time characteristics of a signal propagating in a delay line structure, and the output second digital signal is a quantized value of the pulse width of the time domain signal.

[0087] In this embodiment, the time-to-digital converter adopts a delay line structure composed of a delay unit and a D flip-flop. If the time-to-digital converter is N bits, then 2 N A basic delay unit and D flip-flop.

[0088] Through this embodiment, the time-to-digital converter can detect analog impairments and resolution limitations. It can also use the sine wave fitting method to test the effective number of bits (ENOB) of the analog-to-digital conversion circuit. The parameter design of each sub-circuit module is debugged based on the ENOB to optimize the circuit parameter design and obtain a wide input range and high-precision analog-to-digital conversion circuit.

[0089] In one embodiment, the first digital signal output by the first stage structure and the second digital signal output by the second stage structure are combined by a multiplexer and an encoder and then output.

[0090] Through this embodiment, the combined output of the first digital signal and the second digital signal can be controlled.

[0091] In addition, combined with the analog-to-digital conversion circuit based on VTC and TDC for the RRAM storage and computing integrated chip in the above-mentioned embodiment, the embodiment of the present application can provide a RRAM storage and computing integrated chip for implementation.

[0092] The RRAM storage and computing integrated chip includes any one of the analog-to-digital conversion circuits based on VTC and TDC for the RRAM storage and computing integrated chip in the above embodiments; the analog-to-digital conversion circuit serves as a readout circuit of the RRAM storage and computing integrated chip.

[0093] Through the above-mentioned RRAM storage and computing integrated chip, its built-in analog-to-digital conversion circuit serves as the readout circuit of the RRAM storage and computing integrated chip; the two-stage structure of the analog-to-digital conversion circuit folds the entire input voltage range, realizing the circuit structure reuse of a single VTC and a single TDC under a wide input range, which has the advantage of reducing the circuit layout area. As the readout circuit of the RRAM storage and computing integrated chip, it quantizes the resistance value of the memristor array with different numbers and different resistance values turned on.

[0094] The various technical features of the above-described embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the various technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0095] Those skilled in the art should recognize that the above embodiments are merely intended to illustrate the present invention and are not intended to limit the present invention. Any appropriate changes and modifications to the above embodiments fall within the scope of the present invention as long as they are within the spirit of the present invention.

Claims

1. An analog-to-digital conversion circuit based on VTC and TDC for an RRAM storage and computing integrated chip, characterized in that: A two-stage structure comprising a folded input voltage range; the first stage structure comprising a first comparator; the second stage structure comprising a charge pump, a voltage-to-time converter, and a time-to-digital converter; The first comparator is connected to the charge pump and is used to compare the input first voltage signal with a first reference signal to output a first digital signal; The charge pump is connected to the voltage-to-time converter, and is configured to receive the first digital signal as an enable voltage, step down the input first voltage signal at the enable voltage, and output a second voltage signal; The voltage-to-time converter is connected to the time-to-digital converter and is used to map the second voltage signal into a time domain signal; The time-to-digital converter is configured to map the time domain signal into a second digital signal, and output the first digital signal and the second digital signal as a combination.

2. The analog-to-digital conversion circuit based on VTC and TDC for the RRAM storage and computing integrated chip according to claim 1, characterized in that: The first comparator compares the first voltage signal and the first reference signal to output the first digital signal, and the first digital signal is used as the charge pump enable voltage control; wherein, the first reference signal is half of the supply voltage, corresponding to folding the input voltage range into half.

3. The analog-to-digital conversion circuit based on VTC and TDC for the RRAM storage and computing integrated chip according to claim 1, characterized in that: The charge pump includes an enabling voltage control unit, a capacitor C1, a capacitor C2, a diode D1 and a diode D2; The enabling voltage control unit is provided between one end of the capacitor C1 and the output end of the first comparator; The other end of the capacitor C1 is connected to the anode of the diode D1 and the cathode of the diode D2 respectively; The cathode of the diode D1 is connected to the positive input terminal of the first comparator; The anode of the diode D2 is connected to one end of the capacitor C2 and the voltage-time converter respectively; The other end of the capacitor C2 is grounded.

4. The analog-to-digital conversion circuit based on VTC and TDC for the RRAM storage and computing integrated chip according to claim 1, characterized in that: The voltage-time converter includes a sampling and holding module, a second comparator, a current mirror module and a logic circuit; The sampling and holding module is provided between the charge pump and the negative input terminal of the second comparator, and is used to sample and hold the second voltage signal; The positive input terminal of the second comparator is connected to the current mirror module, and the output terminal of the second comparator is connected to the logic circuit, and is configured to receive the second voltage signal and the capacitor voltage signal generated by charging of the current mirror module, and compare the second voltage signal with the capacitor voltage signal to output a third voltage signal; The logic circuit is used to determine the time domain signal according to the third voltage signal and the clock signal; the pulse width of the time domain signal is proportional to the amplitude of the second voltage signal.

5. The analog-to-digital conversion circuit based on VTC and TDC for the RRAM storage and computing integrated chip according to claim 4, characterized in that: The charging current of the capacitor C3 in the voltage-to-time converter is provided by a self-biased low-voltage cascode current mirror; the self-biased low-voltage cascode current mirror biases the gate voltage of the cascode transistor through a resistor.

6. The analog-to-digital conversion circuit based on VTC and TDC for the RRAM storage and computing integrated chip according to claim 4, characterized in that: The reference current in the voltage-to-time converter is generated by a bandgap reference circuit and a voltage-to-current circuit; The bandgap reference circuit is connected to the voltage-to-current circuit and is used to generate a reference voltage with a low temperature coefficient; The voltage-to-current circuit is used to convert the reference voltage into a reference current according to a preset ratio.

7. The analog-to-digital conversion circuit based on VTC and TDC for the RRAM storage and computing integrated chip according to claim 4, characterized in that: The logic circuit is a phase detector.

8. The analog-to-digital conversion circuit based on VTC and TDC for the RRAM storage and computing integrated chip according to claim 1, characterized in that: The time-to-digital converter includes a delay unit and a D flip-flop; The delay unit and the D flip-flop form a delay line structure, which quantizes the pulse width of the time domain signal into digital data to output the second digital signal.

9. The analog-to-digital conversion circuit based on VTC and TDC for the RRAM storage and computing integrated chip according to claim 1, characterized in that: The first digital signal output by the first-stage structure and the second digital signal output by the second-stage structure are combined by a multiplexer and an encoder and then output.

10. A RRAM-oriented storage and computing integrated chip, characterized in that: It comprises an analog-to-digital conversion circuit based on VTC and TDC for an RRAM storage-computing integrated chip according to any one of claims 1 to 9; the analog-to-digital conversion circuit serves as a readout circuit of the RRAM storage-computing integrated chip.

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