Video clock correction method and system based on DP signal source recovery

Abstract

The invention discloses a video clock correction method and system based on DP signal source recovery. The method comprises the following steps: acquiring an original MVID value; the clock correction module is used for calculating time T required by transmission of a frame of data according to the frame synchronization signal, calculating the period of a video clock, taking the reciprocal of the period of the video clock as the frequency of the video clock, taking the ratio of the frequency of the video clock to the frequency of the reference clock as a new MVID value, and subtracting the new MVID value from the original MVID value to obtain the MVID value; if the difference value is greater than a set threshold value, taking the new MVID value as the corrected MVID value, otherwise, taking the original MVID value as the corrected MVID value; the method has the advantages that the video clock is accurate, data processing errors are avoided, and the video clock output is stable.

Description

Technical Field

[0001] The present invention relates to the field of video clock recovery, and particularly to a method and system for correcting a video clock based on a DP signal source recovery. Background Art

[0002] In the video transmission process, only data is transmitted without transmitting the data clock. However, when the data is received and needs to be processed such as parsed and timing reconstructed, a data clock is required. Therefore, it is necessary to recover the data clock. In the current Display Port protocol, there is a same reference clock between all devices and modules. The transmission method of the data clock is that before the video source transmits data, it transmits the ratio value of the video clock and the reference clock. After receiving the data, the data clock is recovered according to this ratio value and the reference clock. The recovered clock is the video clock corresponding to the video data, that is, the data clock mentioned above.

[0003] As Figure 1 shown, in the original industry's clock recovery solution, the video clock is recovered by the value of M_VID sent by the DP (Display Port) signal source. M_VID refers to the ratio relationship between the video clock and the link clock. The recovery method is to first perform digital frequency division and then shape it through an analog PLL, and then use the shaped clock to process the data. Figure 1 In [the figure], M_VID is the ratio relationship value between the video clock and the reference clock. link_clk is the reference clock. vid_clk is the data clock. The DP signal source sends data to the DP data parsing module. The way for the DP data parsing module to parse out M_VID is that the video source (i.e., the DP signal source) will send a specific video packet. There are special digital marks at the beginning and end of this video packet. The data format between these two special digital marks is fixed, and M_VID data can be parsed out based on this. The principle of the analog module outputting the reference clock link_clk is generated by the PLL (analog phase-locked loop) oscillation configured in the register. The clock is an alternating high and low level signal. The duty cycle is the ratio of the high level / low level within one clock cycle. The ideal clock duty cycle is 50%. However, the duty cycle of the clock recovered by the digital frequency division module according to the reference clock and the ratio relationship is most likely not 50%. Therefore, it is necessary to adjust the duty cycle to 50% by the analog PLL, and finally output the recovered data clock that meets the duty cycle requirement.

[0004] The reference clock is used for data transmission between different devices, while the video clock is used for processing video data inside the device. Data between the two requires different clock domain conversion operations (converting from the reference clock domain to the video clock domain). This conversion method is to write the data into the memory (FIFO / RAM) with the reference clock and then read it out with the video clock. The time ratio of the read operation and the write operation is fixed to ensure that the memory will not be written full (continuing to write after it is full will cause data loss, and this phenomenon is called overflow). However, when the clock is not accurate enough, the phenomenon of being written full or read empty may occur. The amount of data sent by the DP signal source fluctuates, but within one frame, only the lower 8 bits of the 24-bit M_VID data will be updated in real time. Figure 1 In the existing solution shown, the M_VID is directly used to recover the video clock. Once the amount of data fluctuates greatly, due to the inaccuracy of the M_VID, the finally recovered video clock is inaccurate, and the video clock will not match the data, resulting in FIFO / ram overflow during data processing and data processing errors. In addition, some DP signal sources do not have the function of dynamically adjusting the M_VID value according to the amount of data. The M_VID value is set and sent according to the theoretically calculated amount of data, and recovering the clock to process the data according to the theoretical M_VID value during transmission may also cause data loss and data processing errors.

[0005] Chinese Patent Publication No. CN116366899A discloses a video clock generation method and device. The method includes: obtaining the clock to be adjusted and the reference clock; calculating the frequency compensation difference according to the clock to be adjusted and the reference clock; calculating the target compensation parameter according to the reference compensation parameter and the frequency compensation difference; shaping the clock to be adjusted according to the target compensation parameter to obtain the shaped clock; if the frequency difference between the shaped clock and the reference clock is within the preset frequency range, determining the shaped clock as the target video clock; if the frequency difference between the shaped clock and the reference clock is outside the preset frequency range, using the shaped clock as the new clock to be adjusted, and returning to execute the step of calculating the frequency compensation difference of this round according to the clock to be adjusted and the reference clock. It can be seen from the specification drawings of this patent document that it obtains the real-time htotal value (the htotal value is the number of pixels in a full horizontal row in the video) from the parsing module, and calculates the synchronous frequency difference according to the real-time htotal value for clock adjustment. Therefore, it adjusts the video clock for each row, with frequent adjustments, resulting in unstable output of the video clock. Secondly, the DP data parsing module outputs a fixed ratio parameter to the digital frequency divider. When the amount of data fluctuates greatly, the ratio parameter is inaccurate, resulting in clock and data mismatch and data processing errors. Summary of the Invention

[0006] The technical problem to be solved by the present invention is that the video clock output by the existing method for restoring the video clock is inaccurate, resulting in data processing errors and frequent adjustment of the video clock, which causes the instability of the video clock output.

[0007] The present invention solves the above technical problems through the following technical means: a correction method for the video clock restored based on the DP signal source, the method comprising:

[0008] S1. Obtain the original M_VID value, where the M_VID value is the proportional relationship between the video clock and the reference clock;

[0009] S2. Use the clock correction module to correct the M_VID value, and send the corrected M_VID value to the digital frequency division module. The digital frequency division module restores the video clock according to the received reference clock and the M_VID value. The process of the clock correction module correcting the M_VID value is as follows: the clock correction module calculates the time T required for transmitting one frame of data according to the frame synchronization signal, and then calculates the period of the video clock according to the time T. The reciprocal of the period of the video clock is the frequency of the video clock. The ratio of the frequency of the video clock to the frequency of the reference clock is used as the new M_VID value. The difference between the new M_VID value and the original M_VID value is calculated. If the difference is greater than the set threshold, the new M_VID value is used as the corrected M_VID value; otherwise, the original M_VID value is used as the corrected M_VID value.

[0010] The present invention calculates the time T required for transmitting one frame of data according to the frame synchronization signal, then calculates the period of the video clock according to the time T. The reciprocal of the period of the video clock is the frequency of the video clock. The ratio of the frequency of the video clock to the frequency of the reference clock is used as the new M_VID value, and the M_VID value is corrected by using the new M_VID value, avoiding data processing errors caused by inaccurate M_VID values in the case of large data fluctuations. In addition, the adjustment of the M_VID value is adjusted once for each frame of data instead of adjusting each line of the video source data, so that the adjustment frequency of the M_VID value is lower, and the finally output video clock changes more gently, and the video clock output is more stable.

[0011] Further, the S1 further includes:

[0012] Use the analog module to send the reference clock to the digital frequency division module and the clock correction module. The DP signal source sends the video source data to the DP data parsing module, and the DP data parsing module parses the original M_VID value from the video source data.

[0013] Still further, the clock correction module calculates the time T required for transmitting one frame of data according to the frame synchronization signal, including:

[0014] Start counting using the reference clock from the rising edge where the frame synchronization signal jumps from 0 to 1 until the next rising edge where the frame synchronization signal jumps from 0 to 1, then stop counting. Calculate the time T required for transmitting one frame of data as T = link_cnt * T_link_clk, where link_cnt represents the count value of the reference clock and T_link_clk represents the period of the reference clock.

[0015] Furthermore, calculating the period of the video clock according to the time T includes:

[0016] Calculate the period of the video clock using the formula T = Htotal * Vtotal * T_video_clk, where Htotal is the number of pixels in a full horizontal row of the video source data, Vtotal is the number of pixels in a full vertical column of the video source data, and T_video_clk is the period of the video clock.

[0017] Further, S2 further includes:

[0018] Use an analog PLL to adjust the duty cycle of the video clock restored by the digital frequency division module to 50%.

[0019] The present invention also provides a correction system for the video clock restored based on the DP signal source. The system includes:

[0020] A proportional relationship acquisition unit for acquiring the original M_VID value, where the M_VID value is the proportional relationship between the video clock and the reference clock;

[0021] A clock recovery and correction unit for correcting the M_VID value using a clock correction module, sending the corrected M_VID value to the digital frequency division module, and the digital frequency division module restoring the video clock according to the received reference clock and M_VID value. The process of the clock correction module correcting the M_VID value is as follows: The clock correction module calculates the time T required for transmitting one frame of data according to the frame synchronization signal, then calculates the period of the video clock according to the time T. The reciprocal of the period of the video clock is the frequency of the video clock. Take the ratio of the frequency of the video clock and the frequency of the reference clock as the new M_VID value, and subtract the new M_VID value from the original M_VID value. If the difference is greater than the set threshold, then take the new M_VID value as the corrected M_VID value; otherwise, take the original M_VID value as the corrected M_VID value.

[0022] Further, the proportional relationship acquisition unit is further used for:

[0023] Use an analog module to send the reference clock to the digital frequency division module and the clock correction module, the DP signal source sends the video source data to the DP data parsing module, and the DP data parsing module parses the original M_VID value according to the video source data.

[0024] Further, the clock correction module calculates the time T required for transmitting one frame of data according to the frame synchronization signal, including:

[0025] Starting from the edge where the frame synchronization signal jumps from 0 to 1, use the reference clock to count until the next edge where the frame synchronization signal jumps from 0 to 1, and stop counting. Calculate the time T required for transmitting one frame of data as T = link_cnt * T_link_clk, where link_cnt represents the reference clock count value and T_link_clk represents the period of the reference clock.

[0026] Further, calculating the period of the video clock according to the time T includes:

[0027] Use the formula T = Htotal * Vtotal * T_video_clk to calculate the period of the video clock, where Htotal is the number of pixels in a full horizontal row of the video source data, Vtotal is the number of pixels in a full vertical column of the video source data, and T_video_clk is the period of the video clock.

[0028] Further, the clock recovery and correction unit is further configured to:

[0029] Use an analog PLL to adjust the duty cycle of the video clock recovered by the digital frequency division module to 50%.

[0030] The advantages of the present invention are as follows:

[0031] (1) The present invention calculates the time T required for transmitting one frame of data according to the frame synchronization signal, and then calculates the period of the video clock according to the time T. The reciprocal of the period of the video clock is the frequency of the video clock. The ratio of the frequency of the video clock to the frequency of the reference clock is used as the new M_VID value, and the M_VID value is corrected using the new M_VID value, avoiding data processing errors caused by inaccurate M_VID values in the case of large data fluctuations. In addition, the adjustment of the M_VID value is performed once for one frame of data instead of for each row of the video source data, so that the adjustment frequency of the M_VID value is lower, and the finally output video clock changes more smoothly and the video clock output is more stable.

[0032] (2) The present invention can be compatible with the situation where the signal source sends an incorrect clock ratio value or the parsing module parses an incorrect clock ratio value, and can time according to the vbid identifier (i.e., the frame synchronization signal) in the data sent by the source. The correct ratio relationship is deduced according to the calculation formula, and the compatibility is good.

[0033] (3) The information such as htotal reconstructed in the patent documents described in the background art can be understood. It is work done for data transmission to other devices later. When the format requirements of the data for subsequent devices / modules are known, these operations can ensure the relative stability of the relationship between real-time data and the clock. That is, adjust the current clock and data in the direction expected by the subsequent devices / modules. However, the present invention directly detects and calculates the precise clock information of the currently transmitted video based on the special flag bits in the real-time data sent from other sources, and then processes the data according to the corrected clock, that is, restores the current clock and data to the direction of the video source. The patent documents described in the background art obtain the real-time htotal value from the parsing module (which requires certain parsing operations on the data by the parsing module) for detection and video clock recovery, while the present invention directly detects the data before it enters the parsing module, which is more direct and accurate.

[0034] (4) The present invention can implement a real-time frame rate detection function. The real-time frame rate can be calculated based on the time difference between special flag bits of two frames (the time required for one frame of video to be displayed). That is, start counting with the reference clock from the rising edge where the frame synchronization signal jumps from 0 to 1, and stop counting until the next rising edge where the frame synchronization signal jumps from 0 to 1. Calculate the time required for one frame of data transmission, and finally calculate the frequency of the video clock. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 Schematic diagram of a method for recovering the video clock of a video transmitted by an existing DP signal source;

[0036] Figure 2 Schematic diagram of a method for correcting the video clock recovered based on a DP signal source disclosed in an embodiment of the present invention;

[0037] Figure 3 Schematic diagram of video frame transmission in a method for correcting the video clock recovered based on a DP signal source disclosed in an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0039] Embodiment 1

[0040] As Figure 2 shown, Embodiment 1 of the present invention provides a method for correcting the video clock recovered based on a DP signal source. The method includes:

[0041] S1. Use the simulation module to send the reference clock to the digital frequency division module and the clock correction module, and the DP signal source to send the video source data to the DP data parsing module. The DP data parsing module parses the original M_VID value according to the video source data. The M_VID value is the proportional relationship between the video clock and the reference clock.

[0042] S2. Use the clock correction module to correct the M_VID value, and send the corrected M_VID value to the digital frequency division module. The digital frequency division module restores the video clock according to the received reference clock and M_VID value; use the analog PLL to adjust the duty cycle of the video clock restored by the digital frequency division module to 50%. The process of the clock correction module correcting the M_VID value is as follows: The clock correction module calculates the time T required for transmitting one frame of data according to the frame synchronization signal, and then calculates the period of the video clock according to the time T. The reciprocal of the period of the video clock is the frequency of the video clock. The ratio of the frequency of the video clock to the frequency of the reference clock is used as the new M_VID value. The difference between the new M_VID value and the original M_VID value is calculated. If the difference is greater than the set threshold, the new M_VID value is used as the corrected M_VID value; otherwise, the original M_VID value is used as the corrected M_VID value. The specific process of S2 is as follows:

[0043] First, the data transmission channel between different devices is called a link. When transmitting data, fixed special digits (K-code) are inserted at specific times according to the protocol regulations, and these special digits are used to distinguish the video specification information and the video content information, etc. Figure 3 The indicated ACTIVE area is the video content information, and the remaining area can be understood as the video specification information sending area. One frame of video can be understood as a picture, which has two sides, length and width. The Display Port protocol calls the number of pixels in a whole horizontal row htotal, and the number of pixels in a whole vertical column vtotal. When transmitting data between different devices, the data is transmitted in order from top to bottom and from left to right. The BS signal is the special character that needs to be inserted at the beginning of each row. The BE signal is the special character that needs to be inserted before sending the video content. Such as Figure 3, in some areas, there is only BS but no BE in one row. The data information of VBID (frame synchronization signal) is sent in each row. Among them, only VBID[0]=1 in the BS area, while VBID[0]=0 in the areas with both BS and BE. VBID[0] represents the value of the first element of the VBID signal. The present invention uses the edge where vbid[0] jumps from 0 to 1. Starting from this moment, the reference clock link_clk is used for counting until the next edge where vbid[0] jumps from 0 to 1 indicates the end of the transmission of a frame of data. The count of link_clk during this period can be used to calculate the time T required for the transmission of this frame of data, T = link_cnt * T_link_clk, where link_cnt represents the reference clock count value, and T_link_clk represents the period of the reference clock.

[0044] The time required to transmit a frame of picture can also be calculated using the formula T = Htotal * Vtotal * T_video_clk, where Htotal is the number of pixels in a full horizontal row of the video source data, Vtotal is the number of pixels in a full vertical column of the video source data, and T_video_clk is the period of the video clock. According to the above two formulas, the period T_video_clk of the video clock can be calculated, and then the frequency of the video clock can be calculated using the formula F_video_clk = 1 / T_video_clk, where F_video_clk is the frequency of the video clock. The ratio of the frequency of the video clock to the frequency of the reference clock is used as the new M_VID value. The new M_VID value is compared with the M_VID sent by the source in real time. A threshold can be set according to the size of the FIFO / ram of the data processing module. If the difference between the two M_VIDs is greater than the set threshold, the new M_VID is used to recover the clock, otherwise the M_VID sent by the source can be used.

[0045] Through the above technical solutions, the present invention calculates the time T required for the transmission of a frame of data according to the frame synchronization signal, and then calculates the period of the video clock according to the time T. The reciprocal of the period of the video clock is the frequency of the video clock. The ratio of the frequency of the video clock to the frequency of the reference clock is used as the new M_VID value, and the new M_VID value is used to correct the M_VID value, avoiding data processing errors caused by inaccurate M_VID values in the case of large data fluctuations. In addition, the adjustment of the M_VID value is adjusted once for each frame of data instead of for each row of the video source data, so the adjustment frequency of the M_VID value is lower, and the finally output video clock changes more smoothly and the video clock output is more stable.

[0046] Embodiment 2

[0047] Based on Embodiment 1, Embodiment 2 of the present invention further provides a correction system for a video clock restored based on a DP signal source, and the system includes:

[0048] A proportional relationship acquisition unit, configured to acquire an original M_VID value, where the M_VID value is the proportional relationship between the video clock and the reference clock;

[0049] A clock recovery and correction unit, configured to correct the M_VID value by using a clock correction module, send the corrected M_VID value to a digital frequency division module, and the digital frequency division module restores the video clock according to the received reference clock and the M_VID value; the process of the clock correction module correcting the M_VID value is as follows: the clock correction module calculates the time T required for transmitting one frame of data according to the frame synchronization signal, and then calculates the period of the video clock according to the time T. The reciprocal of the period of the video clock is the frequency of the video clock. The ratio of the frequency of the video clock to the frequency of the reference clock is used as the new M_VID value. The difference between the new M_VID value and the original M_VID value is calculated. If the difference is greater than the set threshold, the new M_VID value is used as the corrected M_VID value; otherwise, the original M_VID value is used as the corrected M_VID value.

[0050] Specifically, the proportional relationship acquisition unit is further configured to:

[0051] Send the reference clock to the digital frequency division module and the clock correction module by using an analog module, the DP signal source sends video source data to the DP data parsing module, and the DP data parsing module parses the original M_VID value according to the video source data.

[0052] More specifically, the clock correction module calculates the time T required for transmitting one frame of data according to the frame synchronization signal, including:

[0053] Start counting the reference clock from the rising edge where the frame synchronization signal jumps from 0 to 1 until the next rising edge where the frame synchronization signal jumps from 0 to 1, and stop counting. Calculate the time T required for transmitting one frame of data as T = link_cnt * T_link_clk, where link_cnt represents the reference clock count value and T_link_clk represents the period of the reference clock.

[0054] More specifically, calculating the period of the video clock according to the time T includes:

[0055] Use the formula T = Htotal * Vtotal * T_video_clk to calculate the period of the video clock, where Htotal is the number of pixels in a complete horizontal row in the video source data, Vtotal is the number of pixels in a complete vertical column in the video source data, and T_video_clk is the period of the video clock.

[0056] More specifically, the clock recovery and correction unit is further configured to:

[0057] Use an analog PLL to adjust the duty cycle of the video clock recovered by the digital frequency division module to 50%.

[0058] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for correcting a video clock based on DP signal source recovery, characterized in that: The method comprises: S1. Obtain the original M_VID value, where the M_VID value is the proportional relationship between the video clock and the reference clock; S2. Correct the M_VID value using the clock correction module, and send the corrected M_VID value to the digital frequency division module. The digital frequency division module recovers the video clock according to the received reference clock and the M_VID value. The process of correcting the M_VID value by the clock correction module is as follows: the clock correction module calculates the time T required for one frame of data transmission according to the frame synchronization signal, and then calculates the period of the video clock according to the time T. The reciprocal of the period of the video clock is the frequency of the video clock. The ratio of the frequency of the video clock to the frequency of the reference clock is used as the new M_VID value. The new M_VID value is subtracted from the original M_VID value. If the difference is greater than the set threshold, the new M_VID value is used as the corrected M_VID value. Otherwise, the original M_VID value is used as the corrected M_VID value.

2. The method for correcting the video clock based on DP signal source recovery according to claim 1, characterized in that: The S1 further comprises: The analog module is used to send the reference clock to the digital frequency division module and the clock correction module. The DP signal source sends the video source data to the DP data analysis module. The DP data analysis module analyzes the original M_VID value according to the video source data.

3. The method for correcting the video clock based on DP signal source recovery according to claim 2, characterized in that: The clock correction module calculates the time T required for one frame of data transmission according to the frame synchronization signal, including: Start counting with the edge when the frame synchronization signal jumps from 0 to 1 using the reference clock, and stop counting when the frame synchronization signal jumps from 0 to 1 next time, and calculate the time required for one frame of data transmission T = link_cnt*T_link_clk, where link_cnt represents the reference clock count value and T_link_clk represents the period of the reference clock.

4. The method for correcting the video clock based on DP signal source recovery according to claim 3, characterized in that: The step of calculating the period of the video clock according to the time T comprises: The period of the video clock is calculated using the formula T=Htotal*Vtotal*T_video_clk, where Htotal is the number of pixels in a whole horizontal row in the video source data, Vtotal is the number of pixels in a whole vertical column in the video source data, and T_video_clk is the period of the video clock.

5. The method for correcting the video clock based on DP signal source recovery according to claim 1, characterized in that: The S2 further includes: The duty cycle of the video clock restored by the digital frequency division module is adjusted to 50% by using an analog PLL.

6. A video clock correction system based on DP signal source recovery, characterized in that: The system comprises: A proportional relationship acquisition unit, used to acquire an original M_VID value, where the M_VID value is a proportional relationship between a video clock and a reference clock; The clock recovery and correction unit is used to correct the M_VID value by using the clock correction module, and send the corrected M_VID value to the digital frequency division module, and the digital frequency division module recovers the video clock according to the received reference clock and the M_VID value; the process of the clock correction module correcting the M_VID value is as follows: the clock correction module calculates the time T required for one frame of data transmission according to the frame synchronization signal, and then calculates the period of the video clock according to the time T, the reciprocal of the period of the video clock is the frequency of the video clock, the ratio of the frequency of the video clock to the frequency of the reference clock is used as the new M_VID value, and the new M_VID value is subtracted from the original M_VID value. If the difference is greater than a set threshold, the new M_VID value is used as the corrected M_VID value, otherwise, the original M_VID value is used as the corrected M_VID value.

7. The video clock correction system based on DP signal source recovery according to claim 6 is characterized in that: The proportional relationship acquisition unit is also used for: The analog module is used to send the reference clock to the digital frequency division module and the clock correction module. The DP signal source sends the video source data to the DP data analysis module. The DP data analysis module analyzes the original M_VID value according to the video source data.

8. The video clock correction system based on DP signal source recovery according to claim 7 is characterized in that: The clock correction module calculates the time T required for one frame of data transmission according to the frame synchronization signal, including: Start counting with the edge when the frame synchronization signal jumps from 0 to 1 using the reference clock, and stop counting when the frame synchronization signal jumps from 0 to 1 next time, and calculate the time required for one frame of data transmission T = link_cnt*T_link_clk, where link_cnt represents the reference clock count value and T_link_clk represents the period of the reference clock.

9. The video clock correction system based on DP signal source recovery according to claim 8, characterized in that: The step of calculating the period of the video clock according to the time T comprises: The period of the video clock is calculated using the formula T=Htotal*Vtotal*T_video_clk, where Htotal is the number of pixels in a whole horizontal row in the video source data, Vtotal is the number of pixels in a whole vertical column in the video source data, and T_video_clk is the period of the video clock.

10. The video clock correction system based on DP signal source recovery according to claim 6, characterized in that: The clock recovery and correction unit is also used for: The duty cycle of the video clock restored by the digital frequency division module is adjusted to 50% by using an analog PLL.

Images