Embedded flash memory below 110nm and its preparation method

Abstract

An embedded flash memory device with a size of less than 110nm and a method for fabricating the same include: a substrate, a memory array region, and a peripheral logic region on the substrate. The memory array region includes at least one memory cell, each memory cell comprising: a common source located in the substrate, a common line located above and connected to the common source; a pair of stacked gates located on either side of the common line, each stacked gate comprising a floating gate and a control gate vertically stacked above it; and a pair of select gates located adjacent to the non-common line sides of the stacked gates. The peripheral logic region includes at least one logic transistor, each logic transistor comprising a logic gate. The control gate in the memory cell is at the same height as the logic gate of the logic transistor. This embedded flash memory device has excellent and stable performance and reliability, and its fabrication method is simple, convenient, and low-cost.

Description

Technical Field

[0001] The present invention relates to an embedded flash memory below 110nm and a preparation method thereof, and in particular to an embedded flash memory below 90nm and a preparation method thereof. Background Art

[0002] Embedded flash memory, or eFlash, is commonly used in widely used electronic products such as microcontroller units (MCUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), and programmable logic devices (PLDs). Compared to traditional EEPROM solutions, eFlash offers advantages such as fast read and write speeds, a compact footprint, and low power consumption. As a result, it is playing an increasingly important role in applications such as the Internet of Things (IoT) and automotive electronics.

[0003] Embedded flash memory solutions primarily include traditional floating gate-based structures and charge-trapping structures. In the charge-trapping structure, charge is trapped in an insulating storage medium through a charge "trapping" mechanism. This solution is primarily used in silicon-oxide-nitride-oxide-silicon (SONOS), for example, by sequentially depositing silicon oxide, silicon nitride, and silicon oxide on a silicon substrate. While the manufacturing process is relatively simple, the inherent properties of nitrides result in poor reliability, generally limiting their use to consumer products. High-end applications still require floating gate embedded flash memory.

[0004] Among floating-gate embedded flash memories, the most widely used is the ESF3 structure from Silicon Storage Technologies (SST). This structure utilizes three gate layers: an erase gate (EG), a control gate (CG), and a floating gate (FG). Programming utilizes source-side injection, while erasing is performed from gate to gate. It can achieve over 300,000 read / write cycles, demonstrating excellent reliability and application scenarios. However, the ESF3 structure presents challenges in manufacturing. The erase gate must wrap around the floating gate to achieve sufficient erase efficiency and reduce erase voltage. Furthermore, the formation of three different gates is required, making process uniformity difficult to control and limiting the process's mass production window.

[0005] Another commonly used embedded flash memory architecture is the dual-transistor (2T) structure from NXP Semiconductors (NXP) of the Netherlands. The memory cell features two select gates (SG) and two stacked gates, creating a mirror-image symmetry. In the stacked gate structure, the control gate (CG) is stacked on top of the floating gate (FG). Compared to SST's ESF3, this structure offers a simpler structure and manufacturing. Programming utilizes the Fowler-Nordheim electron injection method, which requires high voltages. This increases the area of the pump circuitry in the peripheral logic area, and high voltages can also affect the reliability of the flash memory device.

[0006] Storage devices in embedded flash memory must be compatible with logic process technology. The gate height of storage devices in embedded flash memory must also be compatible with the gate height of logic devices. Currently, in domestic 2T-structure embedded flash memory fabricated at 110nm and above, the gate height of the peripheral logic device is approximately 2000 Å, the CG height of the storage device is approximately 1200 Å, the FG height is approximately 800 Å, and the SG height is approximately 2000 Å. As the industry's demand for smaller embedded flash memory continues to increase, the gate heights of both logic and storage devices must also be reduced accordingly. In processes of 110nm and below, such as 90nm and below, the gate height of standard logic transistors in the periphery of embedded flash memory has been reduced from 2000 Å to approximately 1000 Å. To ensure sufficient coupling efficiency between storage devices, the FG height must be at least 750 Å. Using existing fabrication methods at 110nm and above, the CG height is less than 300 Å. During the subsequent ion implantation (IMP) process, the implanted ions can easily penetrate the CG and implant into the ONO, affecting the reliability of the flash memory. Therefore, the industry demands smaller embedded flash memories with better performance and new fabrication methods. Summary of the Invention

[0007] The present invention provides an embedded flash memory with a size of less than 110 nm and a preparation method thereof. The embedded flash memory has good and stable performance and good reliability, and the preparation method is simple, convenient and low-cost.

[0008] The first aspect of the present invention relates to an embedded flash memory of less than 110nm, comprising: a substrate, and a memory array area and a peripheral logic area on the substrate, the memory array area containing at least one memory cell, the memory cell comprising: a common source located in the substrate, a common line located above and connected to the common source; a pair of stacked gates located on either side of the common line, each stacked gate comprising a floating gate and a control gate vertically stacked thereon; a pair of select gates located adjacent to the non-common line side of the two stacked gates; the peripheral logic area containing at least one logic transistor, the logic transistor comprising a logic gate; the control gate in the memory cell having the same height as the logic gate of the logic transistor.

[0009] In a preferred embodiment, the select gate and the stacked gate have the same or substantially the same height, the select gate comprises an upper and a lower portion, and a dielectric layer is provided between the control gate and the floating gate in the stacked gate;

[0010] The select gate and the stacked gate have substantially the same height, meaning that: there is no dielectric layer between the upper and lower portions of the select gate, resulting in its height being slightly lower than that of the stacked gate; the height difference is the height of the dielectric layer in the stacked gate. More preferably, the select gate and the stacked gate have the same structure and height; the upper and lower portions of the select gate have the same height as the control gate and floating gate, respectively; and there is also a dielectric layer between the upper and lower portions of the select gate, the same height as that of the stacked gate; and the lower portion of the select gate is electrically conductive to the upper portion of the dielectric layer.

[0011] In another preferred embodiment, the memory array includes rows and columns, and the arrangement direction of each memory cell in the array is the same; the connection direction of the same parts of the two select gates in the memory cells is the column direction, and the corresponding upper parts of the select gates and the control gates of each memory cell in each row are connected along the row to form a stripe; the corresponding floating gates of each memory cell in each row are not connected and are disconnected at the gap between two adjacent memory cells; or the connection direction of the same parts of the two select gates in the memory cells is the row direction, and the corresponding upper parts of the select gates and the control gates of each memory cell in each column are connected along the column to form a stripe; the corresponding floating gates of each memory cell in each column are not connected and are disconnected at the gap between two adjacent memory cells.

[0012] More preferably, in the memory cell, the select gate and the stacked gate have the same structure and height; a dielectric layer is provided between the control gate and the floating gate in the stacked gate; the upper and lower portions of the select gate have the same height as the control gate and the floating gate, respectively, and a dielectric layer is provided between the upper and lower portions of the select gate, the height of which is the same as that of the stacked gate; in the memory array, the connection direction of the same portions of the two select gates in the memory cell is in the column direction, and the upper and lower portions of the select gates corresponding to the memory cells in each row, and the dielectric layer therebetween, are connected along the row to form a stripe; in each row, at least one through-hole is provided in the dielectric layer between the aligned upper and lower portions of the select gate stripe, the bottom of the through-hole being electrically connected to the surface of the lower portion of the select gate stripe and the top of the through-hole being exposed to the top surface of the dielectric layer, thereby electrically connecting the lower portion of the select gate stripe to the top of the dielectric layer; preferably, in each row, a through-hole is provided in the dielectric layer between the aligned upper and lower portions of the select gate stripe for every 16-32 memory cells along the row; or In the memory array, the connection direction of the same parts of the two selection gates in the memory cells is the row direction, and the upper and lower parts of the selection gates corresponding to the memory cells in each column, and the dielectric layer therebetween, are connected along the column to form a stripe; in each column, there is at least one through-hole in the dielectric layer between the upper and lower partial strips of the selection gates aligned vertically, the bottom of the through-hole is electrically connected to the surface of the lower partial strip of the selection gate, and the top of the through-hole is exposed to the top surface of the dielectric layer, so that the lower partial strip of the selection gate is electrically connected to the top of the dielectric layer; preferably, in each column, there is a through-hole in the dielectric layer between the upper and lower partial strips of the selection gates aligned vertically for every 16-32 memory cells along the column.

[0013] More preferably, in the memory array, the connection direction of the same portion of the two selection gates in the memory cell is the column direction, and in each row, there is also a through-hole at a position in the upper partial strip of the selection gate corresponding to the through-hole in the underlying dielectric layer, which is electrically insulated from the upper partial strip of the selection gate surrounding it, and its bottom portion is connected to the through-hole in the underlying dielectric layer and is electrically connected internally, and its top portion exposes the top surface of the upper partial strip of the selection gate; or in the memory array, the connection direction of the same portion of the two selection gates in the memory cell is the row direction, and in each column, there is also a through-hole at a position in the upper partial strip of the selection gate corresponding to the through-hole in the underlying dielectric layer, which is electrically insulated from the upper partial strip of the selection gate surrounding it, and its bottom portion is connected to the through-hole in the underlying dielectric layer and is electrically connected internally, and its top portion exposes the top surface of the upper partial strip of the selection gate.

[0014] In another preferred embodiment, the embedded flash memory below 110 nm described in the present invention is an embedded flash memory device of 90 nm or below.

[0015] A second aspect of the present invention relates to a method for preparing the above-mentioned embedded flash memory having a thickness of less than 110 nm, comprising the following steps: the control gate in the memory cell and the logic gate in the logic transistor are formed in such a manner that a layer of gate material is deposited simultaneously at predetermined positions in the memory array area and the peripheral logic area in the same deposition step, and then different masks are used to etch the gate materials deposited on the array area and the peripheral logic area respectively.

[0016] In a preferred embodiment, the method further includes the following steps: before forming the control gate and the logic gate, there is deposited material formed on the substrate surface of the logic region as the memory cells in the memory array are prepared, and the deposited material is removed by etching.

[0017] In another preferred embodiment, the select gate comprises an upper and a lower portion, and a dielectric layer is provided between the control gate and the floating gate of the stacked gate; the method further comprises the following steps:

[0018] In the case where the height of the selection gate is the same as that of the stacked gate, there is a dielectric layer between the upper and lower parts of the selection gate, and the selection gate and the stacked gate are formed together through the same preparation steps; or in the case where the height of the selection gate is basically the same as that of the stacked gate, there is no dielectric layer between the upper and lower parts of the selection gate, and the selection gate and the stacked gate are formed together through basically the same preparation steps, except that the preparation of the selection gate does not include the deposition process of the dielectric layer in the stacked gate.

[0019] More preferably, the select gate and the stacked gate in the memory cell have the same structure and height, the upper and lower portions of the select gate have the same heights as the control gate and the floating gate, respectively, a dielectric layer is provided between the upper and lower portions of the select gate, the height of which is the same as that of the stacked gate, and the lower portion of the select gate is electrically connected to the upper portion of the dielectric layer; the memory array comprises rows and columns, and the memory cells in the array are arranged in the same direction; and the method comprises the following steps in sequence:

[0020] (1) On the substrate, a layer of gate oxide material and a layer of lower gate material are sequentially deposited; then, using a photomask, the deposited lower gate layer is etched away at the gaps between adjacent memory cells in a predetermined array area and at the locations between the floating gates corresponding to the predetermined adjacent memory cells, and the deposited lower gate layer is etched away in the region of the predetermined logic area; and the locations between the lower portions of the select gates corresponding to the predetermined adjacent memory cells are not etched;

[0021] In the case where the connection direction of the same portion of two select gates in the memory cell is in the column direction, the etching between adjacent memory cells in the array area is: etching along the row direction, in the region of each predetermined row of memory cells, at the portion between the floating gates corresponding to predetermined adjacent memory cells; or

[0022] In the case where the connection direction of the same portion of two select gates in the memory cell is in the row direction, the etching between adjacent memory cells in the array area is performed along the column direction, in a predetermined region of each column of memory cells, at a portion between the floating gates corresponding to predetermined adjacent memory cells;

[0023] (2) depositing a layer of dielectric oxide material on the lower gate layer in the array region and on the gate oxide layer in the logic region simultaneously; then, using a photomask, etching a through hole in the dielectric layer deposited in the array region, and etching away the dielectric layer deposited in the logic region;

[0024] The etching to form a through hole in the dielectric layer deposited in the array area comprises:

[0025] In a case where the connection direction of the same portion of the two select gates in the memory cell is in the column direction, in each predetermined row of memory cell regions, at least one through hole is etched in the dielectric layer above a predetermined lower portion of the select gate, wherein the bottom of the through hole contacts the surface of the lower gate layer and the top exposes the top surface of the dielectric layer;

[0026] In a case where the connection direction of the same portion of the two select gates in the memory cell is in the row direction, in each predetermined column of memory cell regions, at least one through hole is etched in the dielectric layer above a predetermined lower portion of the select gate, wherein the bottom of the through hole contacts the surface of the lower gate layer and the top exposes the top surface of the dielectric layer;

[0027] (3) depositing a layer of upper gate material on the dielectric layer in the array area and on the gate oxide layer in the logic area simultaneously; then, using a photomask in the storage array area, etching downward to the gate oxide layer in areas other than the predetermined selection gate and control gate, removing the upper and lower gate layers and the dielectric layer therebetween in these areas, and simultaneously forming a stripe on the upper portion of the selection gate, a stripe on the lower portion of the selection gate, a stripe on the control gate, and a floating gate; then, using a photomask in the logic area, etching away the upper gate material layer in areas other than the predetermined logic gate to form a logic gate.

[0028] More preferably, the etching of through holes in the dielectric layer deposited in the array area comprises: when the connection direction of the same portion of the two selection gates in the memory cell is in the column direction, in each predetermined row of memory cell areas, at every predetermined position of 16-32 memory cells along the row, etching at least one through hole in the dielectric layer above the area of the lower portion of the predetermined selection gate; or when the connection direction of the same portion of the two selection gates in the memory cell is in the row direction, in each predetermined column of memory cell areas, at every predetermined position of 16-32 memory cells along the column, etching at least one through hole in the dielectric layer above the area of the lower portion of the predetermined selection gate.

[0029] More preferably, the operation of etching in the array area to form the upper portion of the selection gate strips, the lower portion of the selection gate strips, the control gate strips, and the floating gate is specifically as follows: when the connection direction of the same portion of the two selection gates in the memory cell is the column direction, etching is performed in the predetermined area of each row of memory cells along the row direction to form two upper portion of the selection gate strips, two lower portion of the selection gate strips, two control gate strips, and the floating gate in each row; or when the connection direction of the same portion of the two selection gates in the memory cell is the row direction, etching is performed in the predetermined area of each column of memory cells along the column direction to form two upper portion of the selection gate strips, two lower portion of the selection gate strips, two control gate strips, and the floating gate in each column.

[0030] In another preferred embodiment, it further includes the following steps: before step (1), forming a well of a memory cell in the memory array in the substrate; and between step (2) and step (3), forming a well of a logic transistor in the peripheral logic region, then removing the gate oxide layer deposited in step (1) on the substrate surface of the logic region, and then regrowing the gate oxide layer of the logic region. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The same numbers in the drawings indicate the same or similar elements.

[0032] Figure 1 It is a partial top view of a specific embodiment of the embedded flash memory of the present invention.

[0033] Figure 2 yes Figure 1 The schematic diagram of the substrate in the flash memory is taken along the cross-section line BB before the formation of memory cells and logic devices.

[0034] Figure 3 is Figure 2 Schematic diagram of an N-well in a substrate forming a memory array.

[0035] Figure 4 is Figure 3 The schematic diagram shows that a layer of gate oxide material and a layer of lower gate material are deposited successively on the substrate.

[0036] Figure 5a is Figure 4 The structure shown is a schematic diagram before etching the lower gate material layer in the predetermined memory array region to form partitions PC between the floating gates of adjacent cells in each row of memory cells.

[0037] Figures 5b-5c They are Figure 1 The diagram shows a top view of a row of memory cells in a flash memory before and after etching to form partitions PC between the floating gates of adjacent memory cells.

[0038] Figure 5d is Figure 4 The schematic diagram shows the structure after etching the lower gate layer in the predetermined memory array area to form partitions PC between the floating gates of adjacent cells in each row of memory cells, and after etching away the lower gate layer in the predetermined logic area.

[0039] Figure 6 is Figure 5d Schematic diagram of depositing a dielectric layer on the lower gate material in the memory array area and on the gate oxide layer in the logic area of the structure shown.

[0040] Figure 7a is Figure 6 Schematic diagram of etching away the deposited dielectric layer in the logic area of the structure shown.

[0041] Figure 7b yes Figure 1 A top view of a row of memory cells in a flash memory during the step of etching to form through holes in a dielectric layer is shown.

[0042] Figure 8a 7a is a schematic diagram of forming P-well and N-well logic devices in low voltage (LV) and high voltage (HV) logic regions, respectively, in the substrate of the structure shown in FIG.

[0043] Figure 8b is Figure 8a Schematic diagram of removing the gate oxide layer previously formed with the memory array that remains in the low voltage and high voltage logic regions in the structure shown.

[0044] Figure 9 is Figure 8b Schematic diagram of forming a low-voltage gate oxide layer and a high-voltage gate oxide layer in the low-voltage and high-voltage logic regions of the structure shown.

[0045] Figure 10 is Figure 9Schematic diagram of depositing a layer of upper gate material on the dielectric layer of the memory array area and the gate oxide layer of the logic area of the structure shown.

[0046] Figures 11a-11b They are Figure 1 Schematic diagram of the structure of a memory cell in the flash memory along the CC section line before and after etching to form the gate.

[0047] Figures 11c-11d They are Figure 1 Schematic diagrams of the structure of the low-voltage logic device in the flash memory along the DD section line before and after etching to form the low-voltage logic gate are shown.

[0048] Figures 11e-11f They are Figure 1 Schematic diagrams of the structure of the high-voltage logic device in the flash memory along the EE section line before and after etching to form the high-voltage logic gate are shown.

[0049] Figures 12a-12b They are Figure 1 The structure of a memory cell in a flash memory along the CC section line is a schematic diagram showing the steps of sequentially forming a gate outer isolation wall, ion implantation of the source and drain, and removal of the gate oxide layer above the source and drain.

[0050] Figure 13 yes Figure 1 Schematic diagram of a 2×2 memory array of flash memory shown.

[0051] Figure 14 yes Figure 13 The bias signals connected to two memory cells in row 1 of the flash memory array are shown during different operations. DETAILED DESCRIPTION

[0052] The relevant definitions in this application are described as follows.

[0053] The height described herein refers to the dimension in the vertical direction from the surface of the substrate of the memory array.

[0054] The up and down mentioned in this article refers to the up and down relationship presented in a direction perpendicular to the surface of the substrate of the memory array.

[0055] The heights of the select gate and the stacked gate are substantially the same, meaning that there is no dielectric layer between the upper and lower portions of the select gate, resulting in its height being slightly lower than the stacked gate; the height difference being the height of the dielectric layer in the stacked gate.

[0056] The "corresponding gates of memory cells in each row and / or column" herein refer to the identically oriented gates of each memory cell in that row and / or column, which can be directly connected to form a straight line along the row and / or column. The gates may be a select gate, a control gate, a floating gate, an upper portion of a select gate, or a lower portion of a select gate.

[0057] The embedded flash memory device described in the present application is a small-sized embedded flash memory, preferably an embedded flash memory of less than 110 nm, more preferably 90 nm or less.

[0058] The embedded flash memory device of the present invention comprises a storage array area composed of storage cells and a logic area composed of peripheral standard logic devices (or standard logic transistors).

[0059] The peripheral logic region can include a low-voltage region and / or a high-voltage region. The low-voltage region can contain multiple low-voltage standard logic devices (or logic transistors), which can be of different types and housed in different well types depending on their application. Similarly, the high-voltage region can contain multiple high-voltage standard logic devices (or logic transistors), which can be of different types and housed in different well types depending on their application.

[0060] The gates of all logic devices (or logic transistors) in the logic area have the same height and are formed by depositing in the same deposition step and then etching.

[0061] In the memory array area, each memory cell is identical, and the overall structure of each memory cell is mirror-symmetrical.

[0062] Each memory cell comprises: a common source located in the substrate; a common line (COM) located on the substrate, directly above and connected to the common source; a pair of stacked gates located on the substrate and arranged in mirror-image symmetry on either side of the common line. Each stacked gate comprises a vertically stacked control gate (CG) and floating gate (FG); and two select gates (SG), located on the opposite side of the stacked gate from the common line, aligned with the stacked gates, and arranged in mirror-image symmetry along the common line. On the side of each select gate not adjacent to the stacked gate, there is a drain located in the substrate below each.

[0063] The control gate of the memory cell of the present invention is the same height as the logic gate of the logic transistor. This avoids defects caused by overly thin control gates in small-sized flash memories, ensuring the reliability of the memory cell and ensuring good and stable performance. The control gate of the memory cell and the logic gate of the logic transistor are formed by depositing a layer of gate material simultaneously at predetermined locations in the memory array area and the peripheral logic area during the same deposition step. Separately, the gate material layers deposited in the array area and the peripheral logic area are then etched using different photomasks.

[0064] In the present invention, the select gate and stacked gate of the memory cell are preferably of the same or substantially the same height. This simplifies the memory cell structure, facilitates fabrication, and ensures reliable and stable performance. More preferably, the select gate and stacked gate are of exactly the same height, and most preferably, the select gate and stacked gate have the same structure and height. This facilitates control and consistent, precise etching during fabrication, avoiding minor overetching that can lead to leakage and compromise reliability. The select gate comprises an upper and lower portion.

[0065] In a preferred embodiment, a stacked gate has a dielectric layer between the control gate and the floating gate. The upper and lower portions of the select gate have the same height as the control gate and floating gate, respectively. A dielectric layer is also placed between the upper and lower portions of the select gate, with the same height as the dielectric layer in the stacked gate. The lower portion of the select gate is electrically connected to the upper portion of the dielectric layer. In this case, the select gate and the stacked gate are formed together using the same fabrication steps.

[0066] In the case where the select gate and stacked gate of the memory cell have substantially the same height, a dielectric layer is present between the control gate and the floating gate in the stacked gate; the select gate is divided into upper and lower portions, each formed through two separate deposition steps, but without a dielectric layer between the upper and lower portions, resulting in a direct, integrated connection. In this case, the select gate and stacked gate are formed together through substantially the same fabrication steps, except that the fabrication steps for the select gate do not include the deposition step for the dielectric layer in the stacked gate.

[0067] The memory array of the present invention comprises rows and columns, and preferably, the memory cells in the array are arranged in the same direction.

[0068] Assuming that the connection direction of the same parts of the two selection gates in the memory cell is the column direction, preferably: the upper part of the selection gate and the control gate corresponding to each memory cell in each row are connected along the row to form a stripe; the floating gate corresponding to each memory cell in each row is not connected and is disconnected at the gap between two adjacent memory cells.

[0069] In the absence of a dielectric layer in the select gate, it is more preferred that: the upper portions of the select gates corresponding to the memory cells in each row are connected along the row to form a stripe, while the lower portions of the select gates corresponding to the memory cells in each row are not connected and, similar to floating gates, are disconnected at the gap between two adjacent memory cells. However, in each memory cell, the lower portion and the upper portion of each select gate are connected as a whole.

[0070] In the case where a dielectric layer is present in the select gate, it is more preferred that: the upper and lower portions of the select gates corresponding to the memory cells in each row are connected along the row to form a stripe, and the lower portion of the select gate stripe can be electrically connected to the upper portion of the dielectric layer. More preferably, in each row, there is at least one through-hole in the dielectric layer between the upper and lower portion of the select gate stripe aligned vertically, the bottom of the through-hole electrically connected to the surface of the lower portion of the select gate stripe, and the top of the through-hole exposes the top surface of the dielectric layer, so that the lower portion of the select gate stripe can be electrically connected to the upper portion of the dielectric layer. Even more preferably, in each row, there is a through-hole in the dielectric layer between the upper and lower portion of the select gate stripe aligned vertically for every 8-64 memory cells, more preferably every 16-32 memory cells along the row.

[0071] or

[0072] Assuming that the connection direction of the same parts of the two selection gates in the memory cell is the row direction, preferably: the upper part of the selection gate and the control gate corresponding to each memory cell in each column are connected along the column to form a stripe; the corresponding floating gate of each memory cell in each column is not connected and is disconnected at the gap between two adjacent memory cells.

[0073] In the absence of a dielectric layer in the select gate, it is more preferred that: the upper portions of the select gates corresponding to the memory cells in each column are connected along the column to form a stripe, while the lower portions of the select gates corresponding to the memory cells in each column are not connected and, similar to floating gates, are disconnected at the gap between two adjacent memory cells. However, in each memory cell, the lower portion and the upper portion of each select gate are connected as a whole.

[0074] In the case where a dielectric layer is included in the select gate, it is more preferred that: the upper and lower portions of the select gates corresponding to the memory cells in each column are connected along the column to form a stripe; and the lower portion of the select gate stripe is electrically conductive to the upper portion of the dielectric layer. More preferably, in each column, there is at least one through-hole in the dielectric layer between the upper and lower aligned select gate stripes, the bottom of the through-hole electrically connected to the surface of the lower portion of the select gate stripe, and the top of the through-hole exposes the top surface of the dielectric layer, so that the lower portion of the select gate stripe is electrically conductive to the upper portion of the dielectric layer. Even more preferably, in each column, there is a through-hole in the dielectric layer between the upper and lower aligned select gate stripes every 8-64 memory cells, more preferably every 16-32 memory cells along the column.

[0075] In the storage array of the present invention, when there are through holes in the dielectric layer between the upper and lower partial strips of the selection gate, preferably, there is also a through hole in the upper partial strip of the selection gate at a position corresponding to each through hole in the lower dielectric layer. The through hole is electrically insulated from the surrounding upper partial strips of the selection gate, the bottom is connected to the corresponding through holes in the lower dielectric layer and is electrically connected internally, and the top exposes the top surface of the upper partial strip of the selection gate, so that the through hole in the dielectric layer extends out to the top surface of the upper partial strip of the selection gate.

[0076] In the memory array of the present invention, the common source of the memory cell is connected to a common line (COM), the control gate is connected to a control line (CG'), and the drain of the select gate is connected to a bit line (BL). When the select gate does not have a dielectric layer, the upper and lower portions of the select gate are integral and connected to a word line (WL). When the select gate has a dielectric layer, when there is no through-hole in the upper portion of the select gate strip but there is a through-hole in the dielectric layer, the lower portion of the select gate strip is electrically connected to the upper portion of the select gate strip through the through-hole in the upper dielectric layer and connected to the word line (WL). Alternatively, when there are through-holes in both the upper portion of the select gate strip and the dielectric layer, and the through-holes extend from top to bottom and are electrically connected at the center, the lower portion of the select gate strip is preferably connected to the word line (WL) through the upper portion of the select gate strip and the interior of the through-hole in the dielectric layer, while the upper portion of the select gate strip is not connected to the word line. In this case, it is preferred that the via in the upper portion of the select gate stripe and the via in the dielectric layer below it have a circle of electrically insulating isolation walls on their inner surfaces, and a metal conductor is located in the center of the via. The metal conductor in the center of the via is electrically isolated from the upper portion of the select gate stripe outside the via by the isolation walls on the inner surface of the via.

[0077] In the memory array of the present invention, when the connection direction of the same portion of two select gates in the memory cells is in the column direction, the bit lines (BL) of the memory cells in each column are connected, and the word lines (WL), common lines (COM), and control lines (CG') of the memory cells in each row are connected respectively.

[0078] When the connection direction of the same portion of the two select gates in the memory cell is in the row direction, the bit lines (BL) of the memory cells in each row are connected, and the word lines (WL), common lines (COM), and control lines (CG') of the memory cells in each column are connected respectively.

[0079] The embedded flash memory of the present invention provides a programming channel from the channel region near the common source of the memory cell to the floating gate, while the erasing channel extends from the floating gate to the channel region in the underlying substrate. These are simple channels conventional in the industry, requiring no additional components to form new channels, such as an erase gate or floating gate side bumps. Consequently, the memory cell structure of the present invention is simple, and programming and erasing operations are straightforward.

[0080] In the memory array of the present invention, all memory cells can be erased simultaneously, while programming is bit-optional.

[0081] The present invention also relates to a method for preparing the above-mentioned small-size embedded flash memory, which comprises the following steps in sequence.

[0082] A. Providing a substrate and forming a well for a memory cell:

[0083] A substrate is provided, the surface of which includes parallel and adjacent active regions and isolation regions. Memory cells and logic devices are subsequently formed within the active regions. A well for the memory array is formed within the substrate below a predetermined region of the memory array. All memory cells in the memory array share the same well.

[0084] B. Deposit gate oxide and lower gate material and etch:

[0085] A layer of gate oxide (also known as the gate oxide layer) is first deposited on the substrate, followed by a layer of lower gate material. This first layer of gate material, also known as the lower gate material layer or lower gate layer, is deposited. The gate oxide layer is preferably grown to a height of 80-95 Å (angstroms). The lower gate layer is preferably grown to a height of 750-1000 Å, with a more preferred height of 800-900 Å. A lower lower gate layer height that is too low can affect device performance, for example, reducing the coupling efficiency of the memory cell. A higher lower gate layer height can prevent the use of flash memory manufacturing processes.

[0086] Then, a photomask (also called a photolithography mask) is used to etch away the deposited lower gate layer in the gaps between adjacent memory cells in a predetermined array area and between the floating gates corresponding to predetermined adjacent memory cells, thereby forming a partition between the floating gates of adjacent cells. The deposited lower gate layer is also etched away in the area of the predetermined logic area.

[0087] In the case where there is no dielectric layer in the selection gate of the memory cell, the deposited lower gate layer is also etched away in the gap between predetermined adjacent memory cells and in the area between the lower portions of the selection gates corresponding to predetermined adjacent memory cells, thereby forming a partition between the lower portions of the selection gates of adjacent cells; in the case where there is a dielectric layer in the selection gate of the memory cell, no etching is performed in the area between the lower portions of the selection gates corresponding to adjacent memory cells.

[0088] In the case where the connection direction of the same part of two select gates in the memory cell is the column direction, the etching between adjacent memory cells in the array area is: along the row direction, in the area of each predetermined row of memory cells, etching is performed at the part between the floating gates corresponding to predetermined adjacent memory cells. In the case where there is no dielectric layer in the select gate of the memory cell, etching is performed at the same time at the part between the lower parts of the select gates corresponding to predetermined adjacent memory cells. Or

[0089] When the connection direction of the same portion of two select gates in a memory cell is in the row direction, the etching between adjacent memory cells in the array area is performed along the column direction, in a predetermined region of each column of memory cells, at a portion between the floating gates corresponding to predetermined adjacent memory cells. When no dielectric layer is present in the select gates of the memory cells, the etching is performed simultaneously at a portion between the lower portions of the select gates corresponding to predetermined adjacent memory cells.

[0090] C. Deposition of dielectric oxide and etching:

[0091] A layer of dielectric oxide material (referred to as dielectric layer) is simultaneously deposited on the lower gate layer in the entire array area and the gate oxide layer in the logic area; however, in the case where there is no dielectric layer in the selection gate of the memory cell, no dielectric oxide material is deposited in the predetermined selection gate area.

[0092] Then, a photomask is used to etch away the dielectric layer deposited in the logic area. If there is a dielectric layer in the select gate of the memory cell, a through hole is simultaneously etched in the dielectric layer deposited above the predetermined select gate area in the array area.

[0093] The etching to form a through hole in the dielectric layer deposited in the array area comprises:

[0094] In a case where the connection direction of the same portion of the two select gates in the memory cell is in the column direction, at least one through hole is etched in the dielectric layer above the predetermined region of the lower portion of the select gate in each predetermined row of memory cells. Preferably, a through hole is etched in the dielectric layer above the predetermined region of the lower portion of the select gate at predetermined positions of every 8 to 64, more preferably every 16 to 32, memory cells along the row; the bottom of the through hole contacts the surface of the lower gate layer, and the top of the through hole exposes the top surface of the dielectric layer.

[0095] When the connection direction of the same portion of the two select gates in the memory cells is in the row direction, at least one through hole is etched in the dielectric layer above the predetermined region of the lower portion of the select gate in each predetermined column of memory cells. Preferably, one through hole is etched in the dielectric layer above the predetermined region of the lower portion of the select gate at predetermined locations of 8-64, more preferably 16-32, memory cells along the column. The bottom of the through hole contacts the surface of the lower gate layer, and the top of the through hole exposes the top surface of the dielectric layer.

[0096] A small number of vias is beneficial for reducing the area of the memory array. Too few vias will cause voltage drop due to the long flow through the WL.

[0097] D. Forming the wells and logic gate oxide layers of the logic devices in the logic area:

[0098] A logic device well is formed in a predetermined logic region. Forming the logic device well at this time can prevent the well from undergoing and being affected by the aforementioned fabrication steps, thereby maintaining stable performance of the logic device well, such as maintaining a constant ion distribution within the well.

[0099] The logic region includes low-voltage and / or high-voltage logic regions. The low-voltage region can contain multiple low-voltage standard logic devices (or logic transistors). Depending on their respective applications, the types of these low-voltage logic transistors and their well types also vary, resulting in multiple wells of different types within the low-voltage region. Therefore, it is necessary to form separate wells for each logic transistor type to be used. The high-voltage logic region is similar to the low-voltage logic region.

[0100] Next, the remaining gate oxide layer in the logic area, which was formed along with the memory array, is removed, and the gate oxide layer in the logic area is regrown. A certain gap is left between the regrown logic area gate oxide layer and the gate oxide layer in the memory array area to ensure insulation between the memory array and the logic area. The gate oxide layer in the low-voltage logic area is thinner, while the gate oxide layer in the high-voltage logic area is thicker, depending on the applicable voltage of their intended application.

[0101] E. Deposit the upper gate material and etch to form each gate:

[0102] A layer of upper gate material, also called an upper gate material layer or an upper gate layer, is deposited simultaneously on the gate oxide layer of the entire array area and the logic area.

[0103] Next, in the storage array area, a mask is used to block the predetermined selection gate and control gate areas, and outside these areas, etching is performed simultaneously downward to the gate oxide layer to remove the upper and lower gate layers and the dielectric layer in between, thereby simultaneously forming the stripe of the upper part of the selection gate, the lower part of the selection gate (when the selection gate has no dielectric layer) or the stripe of the lower part of the selection gate (when the selection gate has a dielectric layer), the stripe of the control gate, and the floating gate.

[0104] That is, when the connection direction of the same portion of two select gates in the memory cell is in the column direction, etching is performed along the row direction in the predetermined area of each row of memory cells to form two upper select gate strips, a lower select gate (when the select gate has no dielectric layer) or two lower select gate strips (when the select gate has a dielectric layer), two control gate strips, and a floating gate in each row; or

[0105] When the connection direction of the same portion of two select gates in a memory cell is in the row direction, etching is performed along the column direction in a predetermined area of each column of memory cells to form two upper select gate strips, a lower select gate (when the select gate has no dielectric layer) or two lower select gate strips (when the select gate has a dielectric layer), two control gate strips, and a floating gate in each column.

[0106] Then, in the logic region, a mask is used to mask the predetermined logic gate region, and outside of this region, the upper gate material layer is etched away to form the logic gate. Meanwhile, in the case where a dielectric layer is present in the select gate of the memory cell, preferably, etching is performed in the upper portion of the select gate strip formed in the memory array region at a location corresponding to a through hole in the underlying dielectric layer, thereby forming a through hole in the upper portion of the select gate strip. The bottom of the through hole penetrates and is electrically connected to the through hole in the underlying dielectric layer, and the top of the through hole exposes the surface of the upper portion of the select gate strip.

[0107] F. Forming source and drain

[0108] Next, a layer of isolation wall is formed on both sides of each gate electrode formed by etching, using an isolation dielectric material to provide electrical insulation. Simultaneously, if a through-hole is present in the upper portion of the select gate strip, an isolation wall is also formed on the inner surface of the through-hole and the underlying through-hole in the dielectric layer. If no through-hole is present in the upper portion of the select gate strip, no isolation wall is formed on the inner surface of the through-hole in the dielectric layer.

[0109] Then, ions are implanted into the active area of the substrate surface outside the isolation walls of each gate, forming the source and drain electrodes on either side of the select gate and stacked gate in the memory cell, as well as the source and drain electrodes of the logic transistor. In the memory cell, the ion-implanted region formed in the substrate below between the two stacked gates serves as the common source electrode; the ion-implanted region formed in the substrate below outside the select gate (on the side not adjacent to the stacked gate) serves as the drain electrode of the select gate.

[0110] Subsequently, the gate oxide remaining on the active area surface above each source and drain is removed with acid. A self-aligned polysilicide is formed above the common source of the memory cell and between the two stacked gates, forming a common line (COM). This line connects to the common source in the underlying substrate and the drain below the outer side of the memory cell's select gate (the side not adjacent to the stacked gate), which connects to the bit line (BL). In the absence of a dielectric layer in the memory cell's select gate, the upper and lower portions of the select gate are integrated and connected to the word line (WL).

[0111] In the case of a dielectric layer within the select gate, when there is no through-hole in the upper portion of the select gate strip, the lower portion of the select gate strip is electrically connected to the upper portion of the select gate strip through a through-hole in the dielectric layer above it, and is also connected to the word line (WL). If there is a through-hole within the upper portion of the select gate strip, the bottom of the through-hole is connected to the through-hole in the underlying dielectric layer, and both have a layer of isolation wall on their inner surfaces. A conductive line is formed in the center of the through-hole by etching with a mask and then filling with metal tungsten. The bottom of this conductive line is electrically connected to the lower portion of the select gate strip, while the top of the conductive line exposes the top surface of the upper portion of the select gate and is connected to the word line (WL), thereby connecting the lower portion of the select gate strip to the word line (WL), while the upper portion of the select gate strip is not connected to the word line (WL). When etching within the through-hole, a mask is used to avoid etching the isolation wall on the inner surface of the through-hole.

[0112] The materials used for the memory cells and logic transistors are all conventional materials in the industry. The common line is preferably made of salicide, and the gate is preferably made of polysilicon. The dielectric layer and isolation wall are also conventional materials known in the industry.

[0113] The following describes in detail the embedded flash memory below 110 nm of the present invention with reference to the accompanying drawings, but the scope of the present invention is not limited to the specific embodiments shown in the drawings.

[0114] Figure 1This is a partial top view of a specific embodiment of a 90nm embedded flash memory device according to the present invention. The figure shows only a partial memory array consisting of eight memory cells within the flash memory, as well as the surrounding low-voltage and high-voltage logic regions. The low-voltage logic region shows four independent low-voltage standard logic transistors; the high-voltage logic region shows four high-voltage standard logic transistors, two of which are connected in series. The memory array and the surrounding low-voltage and high-voltage logic regions within this flash memory share a common substrate.

[0115] Figure 1 All the memory cells in the flash memory shown are identical. The devices in the memory cells are PMOS type. All the memory cells share one N-well ( Figure 1 Not shown), built into the substrate. Figure 1 The four low-voltage logic transistors in the low-voltage logic region are identical, all of the NMOS type, and share a P-well; the four high-voltage logic transistors in the high-voltage logic region are identical, all of the PMOS type, and share an N-well. The P-well and N-well of the logic devices in the logic region are also constructed in the above substrate ( Figure 1 (Not shown). The gate heights of all logic devices (or logic transistors) in the logic region (including both low-voltage and high-voltage logic regions) are the same. They are formed by depositing the same gate material simultaneously in the same deposition step and then etching.

[0116] Figure 1 In a 10-nanolithography (100-nm) fabricated on-chip, memory cells and peripheral logic transistors are built in active areas (AA) on the substrate surface. These active areas are arranged alternately and parallel to shallow trench isolation (STI) regions.

[0117] Figure 1 In the memory array shown, all memory cells are arranged and oriented identically. The wiring of the two select gates in the same memory cell is in the column direction, with even and odd columns separated by shallow trench isolation (STI). The array shown has four memory cells per row and two memory cells per column.

[0118] The structure of the storage unit is shown as Figure 12b shown. Figure 12b yes Figure 1The structure of a memory cell in the flash memory shown is along the CC section line. It includes: a P common source located in the substrate; a common line (COM) located directly above the common source and connected to the common source at the bottom; a pair of stacked gates located on the substrate and arranged in a left-right mirror symmetric manner on both sides of the common line, each stacked gate including a vertically stacked control gate (CG) and a floating gate (FG), and a dielectric layer (DL) in between; a pair of select gates (SG) located on the side of the stacked gate opposite to the common line, aligned with the stacked gate, and arranged in a left-right mirror symmetric manner along the common line. On the side of the two select gates that is not adjacent to the stacked gate, there is a drain in the substrate below. Each select gate includes an upper and lower part, and a dielectric layer (DL) in between. The common source of the memory cell is connected to the common line (COM), and the control gate is connected to the control line (CG') ( Figure 12b (not shown in the figure), the drain of the select gate is connected to the bit line (BL); the lower part of the select gate is connected to the word line (WL).

[0119] The height of the control gate in the memory cell is the same as that of the logic gate in the logic transistor. They are formed by depositing the same gate material simultaneously in the same deposition step and then etching separately.

[0120] The select gate and stacked gate in the memory cell have identical structure and height. The upper and lower portions of the select gate, along with the dielectric layer between them, are identical in height and composition to the control gate and floating gate, as well as the dielectric layer between them, in the stacked gate. The select gate and stacked gate are formed using the same fabrication steps. Specifically, each corresponding portion of the select gate and stacked gate is formed from the same material and through the same fabrication steps. The upper and lower portions of the select gate, along with the dielectric layer between them, correspond to the control gate and floating gate, as well as the dielectric layer between them, in the stacked gate.

[0121] The materials used for various components of the memory cell and logic transistor are all standard materials in the industry. For example, the common line is made of salicide, and the gate is made of polysilicon.

[0122] In the memory array shown, the upper portion of the select gate, the lower portion of the select gate, and the control gate corresponding to all memory cells in each row are connected to form a strip along the row, spanning the isolation region (STI) between adjacent columns. These strips are parallel to each other. However, the floating gates corresponding to the memory cells in each row are not connected. There is a partition (PC) formed by etching between the floating gates of two adjacent cells in each row, and they are disconnected by the PC, as shown in FIG. Figure 1 shown.

[0123] A through-hole is located in the dielectric layer between the upper and lower select gate strips aligned vertically in each row. Every 16 memory cells along the row, a through-hole is located in the dielectric layer between the upper and lower select gate strips, with the bottom portion electrically connected to the lower select gate strip. In the upper select gate strip of the row, corresponding to the location of the through-hole in the dielectric layer below, a through-hole is located, with the top portion exposing the surface of the upper select gate strip and the bottom portion connecting to the through-hole in the dielectric layer below. A barrier is located on the inner surface of the upper and lower through-holes, and a metal conductor is located in the center of the through-hole. The conductor is electrically connected to the surface of the lower select gate strip at the bottom and to the word line (WL) at the top. This allows the lower select gate strip in each row to connect to the word line (WL) above, while the upper select gate is not connected to the word line (WL).

[0124] The bit lines (BL) of each memory cell in each column are connected, and the word lines (WL), common lines (COM), and control lines (CG') of each memory cell in each row are connected. Figure 13 shown.

[0125] Figure 2-10 (remove Figures 5b-5c and Figure 7b ) are Figure 1 Schematic diagram of the structure of a portion of memory cells and logic devices in a flash memory along the BB cross-section line during the preparation process (a step before etching to form a gate). Figures 11a-12b The steps for forming the gate of the memory cell and the logic device, as well as the steps for forming the source and drain, are shown respectively. Figure 1 The preparation process of the flash memory is shown.

[0126] A. Providing a substrate and forming a well for a memory cell:

[0127] Figure 2 yes Figure 1 The schematic diagram of the substrate in the flash memory is shown along the cross-section line BB before device formation begins. Active areas (AA) and shallow trench isolation (STI) are arranged alternately adjacent to each other on the substrate surface. Memory cells and logic devices are subsequently formed in the active areas. Figure 3 As shown, first, an N-well of the memory array is formed below a predetermined area of the memory array in the substrate.

[0128] B. Deposit gate oxide and lower gate material and etch:

[0129] like Figure 4 As shown, a layer of gate oxide material is deposited simultaneously on the substrate surface in the designated memory array and logic areas. Next, a layer of lower gate material is deposited over the entire gate oxide layer. The gate oxide layer is approximately 85 Å thick, and the floating gate is approximately 800 Å thick.

[0130] Then, using a mask, in the predetermined memory cell area of each row, at the predetermined gap between two adjacent memory cells, the deposited lower gate layer is etched away from the predetermined portion of the partition PC between the floating gates corresponding to the two adjacent memory cells to form a partition PC between the floating gates of adjacent cells; and the deposited lower gate layer is etched away in the predetermined logic area (including the low-voltage and high-voltage logic areas).

[0131] Figure 5a and 5d They are Figure 1 Schematic diagrams of the structure of a portion of memory devices and logic devices in the flash memory along the cross-section line BB before and after etching to form partitions PC between floating gates in each row. Figure 5a FIG. 3 shows the structure of a mask placed on the deposited lower gate layer before etching along the BB section line, wherein the PC region predetermined to be etched is exposed.

[0132] Figures 5b-5c They are Figure 1 The diagram shows a top view of a row of memory cells in a flash memory during the step of etching to form separations between adjacent cell floating gates. The diagram only shows predetermined areas of four memory cells in the row. Figure 5b The figure shows that before etching, a photomask (also called a photoresist mask) is placed on top of the lower gate layer deposited on the memory array area. The mask blocks most of the lower gate layer, exposing only the PC area to be etched. Etching is then performed to remove the exposed lower gate material, forming a PC partition between the floating gates of adjacent cells in the row, as shown in FIG. Figure 5c The partition PC formed by etching in this way includes the partition between the two floating gates of each memory cell in the row and the floating gates corresponding to the adjacent cells.

[0133] C. Deposition of dielectric oxide and etching:

[0134] like Figure 6 As shown, a layer of dielectric oxide material, ie, a dielectric layer, is deposited simultaneously on the lower gate layer of the memory array and the gate oxide layer of the logic area.

[0135] Then, if Figure 7a As shown, a photomask is used to etch away the dielectric layer deposited in the logic area. Simultaneously, in the array area, within each predetermined row of memory cells, a through hole is etched in the dielectric layer above the predetermined lower portion of the select gate at predetermined intervals of 16 memory cells along the row. The bottom of the through hole contacts the surface of the lower gate layer, while the top exposes the top surface of the dielectric layer. Figure 7a The through holes are not shown. Figure 7b It is shown in . Figure 7b yes Figure 1The top view of a row of memory cells in the flash memory after etching to form through holes in the dielectric layer is shown. The figure only shows the predetermined areas of four memory cells in the row, and a through hole is formed in each of the predetermined lower areas of the two selection gates in the row.

[0136] D. Forming the wells and logic gate oxide layers of the logic devices in the logic area:

[0137] like Figure 8a As shown, logic device wells are formed in predetermined logic regions. Low-voltage standard logic devices in the low-voltage (LV) logic region are NMOS transistors, and their wells are P-wells. High-voltage standard logic devices in the high-voltage (HV) logic region are PMOS transistors, and their wells are N-wells.

[0138] Then, if Figure 8b As shown, the gate oxide layer previously formed together with the memory array and remaining in the logic area is removed; and the gate oxide layer in the logic area is regrown, as shown Figure 9 As shown in Figure 3, there is a certain gap between the regenerated gate oxide layer in the logic area and the gate oxide layer in the memory array area. The gate oxide layer thicknesses in the low-voltage and high-voltage logic areas are different. The gate oxide layer in the low-voltage logic area is thinner, approximately 25Å, while the gate oxide layer in the high-voltage logic area is thicker, approximately 65Å. This results in a voltage of approximately 1.1V for low-voltage logic devices and approximately 2.5V for high-voltage logic devices. Alternatively, a thicker gate oxide layer of approximately 120Å can be formed in the high-voltage logic area to produce a 5V high-voltage logic device.

[0139] E. Deposit the upper gate material and etch to form each gate:

[0140] like Figure 10 As shown, a layer of upper gate material is deposited simultaneously on the dielectric layer of the memory array area and on the gate oxide layer of the logic area.

[0141] Then, in the memory array area, in the area of each row of memory cells, a mask is used to block the predetermined select gate and control gate portions, and in the area outside these portions, etching is performed simultaneously down to the gate oxide layer, removing the upper and lower gate layers and the dielectric layer between these portions, thereby simultaneously forming the upper select gate strip, the lower select gate strip, the control gate strip, and the floating gate in each row. In each row, there are two upper and lower select gate strips and two control gate strips, arranged parallel to the row direction, as shown in FIG. Figure 1 The storage array in is shown.

[0142] Figures 11a-11b They are Figure 1 A schematic diagram of a memory cell in a flash memory, showing the structure along the CC cross-section line in the column direction, before and after etching to form a gate. Figure 11aThe portion of the memory cell that is blocked by the photomask, ie, the portion where the select gate and the control gate are to be formed, is shown. Figure 11b FIG. 3 shows the upper and lower parts of the select gate (SG), the control gate (CG) and the floating gate (FG) in the stacked gate formed after etching in the memory cell.

[0143] Subsequently, in the logic area, a mask is used to shield the predetermined logic gate portions, and the upper gate material layer is etched away in areas other than these portions to form the logic gate. Figures 11c-11d Shown respectively Figure 1 The structure of the low-voltage logic device in the flash memory along the DD section line is shown, and the steps before and after etching to form the low-voltage logic gate. Figures 11e-11f Shown respectively Figure 1 The structure of the high-voltage logic device in the flash memory along the EE section line is shown, and the steps before and after etching to form the high-voltage logic gate. Figure 11c and Figure 11e The mask blocking areas are the locations where the low-voltage logic gate and the high-voltage logic gate are respectively formed.

[0144] At the same time, in the memory array area, etching is performed on the upper portion of the select gate strip formed in each row at the location corresponding to the through hole in the underlying dielectric layer, forming a through hole in the upper portion of the select gate strip. The bottom of the through hole penetrates the through hole in the underlying dielectric layer, extending the through hole in the underlying dielectric layer and exposing the surface of the upper portion of the select gate strip.

[0145] F. Forming source and drain:

[0146] On both sides of each gate formed by etching, a layer of isolation wall is formed with an isolation dielectric material to play an insulating role. At the same time, a layer of isolation wall is also formed on the inner surface of the through hole formed in the upper strip of the selection gate and the dielectric layer.

[0147] Then, ions are implanted into the substrate in the active area on the surface of the substrate outside the isolation wall of each gate to form P-type source and drain electrodes (such as Figure 12a as shown), and the source and drain of the logic transistor.

[0148] In the memory cell, the ion implantation region formed in the lower substrate between the two stacked gates is the common source; the ion implantation region formed in the lower substrate on the outer side of the selection gate (the side not adjacent to the stacked gate) is the drain of the selection gate.

[0149] Subsequently, the gate oxide layer remaining above each ion-implanted area is removed with acid. A self-aligned polysilicide is formed above the common source of the memory cell and between the two stacked gates, forming a common line (COM) that connects to the common source in the substrate below. The drain below the outer side of the memory cell's select gate (the side not adjacent to the stacked gate) connects to the bit line (BL).

[0150] A conductive line is formed by etching and filling the inner center of the through-hole in the upper portion of the select gate strip and the dielectric layer with metal tungsten. The bottom of this conductive line is electrically connected to the lower portion of the select gate strip, and the top is connected to the word line (WL). This ensures that the lower portion of the select gate is connected to the word line (WL), while the upper portion of the select gate strip is not connected to the word line (WL). When etching within the through-hole, a photomask is used to avoid etching the isolation wall on the inner surface of the through-hole.

[0151] The usage and operation process of the above 90nm embedded flash memory is as follows.

[0152] Figure 13 yes Figure 1 The circuit diagram of the 2×2 memory array of the flash memory is shown. During the operation, half of a memory cell is used as a unit for programming, reading, and erasing. Figure 13 In the circuit diagram of the memory array shown, the top row includes two memory cells, one of which includes a first half cell portion 100 and a second half cell portion 110, and the other memory cell includes a third half cell portion 120 and a fourth half cell portion 130. The following takes these four half cell portions, i.e., the first half cell portion 100, the second half cell portion 110, the third half cell portion 120, and the fourth half cell portion 130, as an example to describe the operation process. The structure of each memory cell is as follows: Figure 12b shown.

[0153] Figure 14 It is a bias signal to which the four half cell parts (ie, the first half cell part 100 , the second half cell part 110 , the third half cell part 120 , and the fourth half cell part 130 ) in the above two memory cells are connected during different operations.

[0154] The first half of the cell section 100 is selected for individual programming. During programming, electrons are injected from the channel region in the substrate near the common source into the floating gate. The first half of the cell section 100 is programmed by driving its BL to 4.5V, WL to 0V, CG to 2.5-4.5V, COM to 0V, and N-well to 3.5V.

[0155] In the first half cell 100, the potential of word line WL is lower than that of bit line BL and the N-well. Furthermore, the potential of floating gate FG, coupled from control gate CG, is also lower than that of the N-well. Consequently, an inversion channel forms between the bit line diffusion region and the common source region in the substrate. The voltage difference between the bit line diffusion region and the source region is 4.5V, creating a strong lateral electric field from the bit line diffusion region to the common source region. Consequently, holes are accelerated from one side of the channel to the other, leading to impact ionization in the depletion region of the common source. Hot electrons generated by impact ionization are attracted to the forward-biased floating gate and injected into it. Consequently, the number of electrons in the floating gate increases during programming.

[0156] The word line WL potential of the second half cell 110 is 7V, higher than that of the bit line BL and the N-well, and the channel is off. Although there is a potential difference between the bit line diffusion region and the source region, hole movement and impact ionization cannot occur. Therefore, programming is impossible.

[0157] The potentials of the bit line diffusion regions and source regions of the third half cell portion 120 and the fourth half cell portion 130 are both 0, no potential difference and no lateral electric field are formed, and programming does not occur.

[0158] During an erase operation, in a selected portion of a memory cell, electrons tunnel from the floating gate of the selected half of the cell to a channel region in the substrate below it, due to the high voltage between the floating gate and the substrate below it.

[0159] The erase bias signals for the first and third half cell sections 100 and 120 are identical. Their bit lines BL are left floating, and the word lines WL are at the same potential as the N-well. The control gate CG is at a much lower potential than the common source region and the N-well connected to the common line. The potential of the floating gate FG coupled to the control gate CG is also much lower than that of the source region and the N-well. Because the voltage between the floating gate and the N-well is greater than 10V, a high electric field is generated, sufficient to cause electrons trapped in the floating gate to tunnel into the channel. The tunneling mechanism is direct tunneling and / or Fowler-Nordheim tunneling.

[0160] The erase bias signals for the second half cell portion 110 and the fourth half cell portion 130 are identical. The control gate CG potential is 0, and the potential coupled to the floating gate FG is also 0. Since the voltage difference between the floating gate and the N-well is small, electrons in the floating gate cannot tunnel into the channel in the substrate.

[0161] In addition, the erase bias signals of the four half-cell portions can be set to be consistent, so that the four half-cell portions can be erased simultaneously.

[0162] In a read operation, data in a column of memory cells can be read simultaneously. The bit lines BL of the first half cell section 100, the second half cell section 110, the third half cell section 120, and the fourth half cell section 130 are selected, and the memory cell half to be read is selected based on whether the word line WL is turned on or not.

[0163] The word line WL of the first and second half cell sections 100 and 110 is at a lower potential than the bit line BL and the N-well. The potential to which the floating gate FG is coupled from the control gate CG is zero, also lower than that of the bit line and the N-well. This creates an inversion channel between the bit line diffusion region and the common source region in the substrate. Furthermore, a 2V potential difference exists between the bit line diffusion region and the common source region, creating a lateral electric field. Consequently, a read current is generated.

[0164] The potentials of the bit line diffusion regions and the common source regions of the third half cell portion 120 and the fourth half cell portion 130 are both 0, and no lateral electric field is formed. Therefore, no read current is generated.

[0165] Although only the currently preferred embodiments of the present invention have been described in detail, it will be apparent to those skilled in the art that other changes and modifications may be made without departing from the scope of the present invention as defined in the claims.

Claims

1. An embedded flash memory with a thickness of less than 110 nm, comprising: A substrate, and a memory array region and a peripheral logic region on the substrate, wherein the memory array region includes at least one memory cell, and the memory cell includes: a common source located in the substrate, a common line located above and connected to the common source; a pair of stacked gates located on either side of the common line, each stacked gate including a floating gate and a control gate vertically stacked thereon; a pair of select gates located adjacent to the non-common line side of the two stacked gates; the peripheral logic region includes at least one standard logic transistor, the standard logic transistor including a logic gate; the invention is characterized in that: the control gate in the memory cell is the same height as the logic gate of the standard logic transistor, and the control gate and the logic gate are formed by depositing gate material in the same deposition step and then etching separately during the process of preparing the standard logic transistor.

2. The embedded flash memory of less than 110 nm according to claim 1, characterized in that: The select gate and the stacked gate have the same or substantially the same height, the select gate comprises an upper and a lower portion, and a dielectric layer is provided between the control gate and the floating gate in the stacked gate; The heights of the selection gate and the stacked gate are substantially the same, which means that there is no dielectric layer between the upper and lower parts of the selection gate, resulting in its height being slightly lower than the stacked gate; the height difference is the height of the dielectric layer in the stacked gate.

3. The embedded flash memory of less than 110 nm according to claim 2, characterized in that: The structure and height of the selection gate and the stacked gate are the same; the heights of the upper and lower parts of the selection gate are the same as those of the control gate and the floating gate, respectively, and there is also a dielectric layer between the upper and lower parts of the selection gate, the height of which is the same as that of the stacked gate; the lower part of the selection gate is electrically connected to the top of the dielectric layer.

4. The embedded flash memory of less than 110 nm according to claim 2, characterized in that: The storage array comprises rows and columns, and the storage units in the array are arranged in the same direction; The connection direction of the same parts of the two select gates in the memory cells is the column direction, and the upper parts of the select gates and the control gates corresponding to the memory cells in each row are connected along the row to form a stripe; the corresponding floating gates of the memory cells in each row are not connected and are disconnected at the gap between two adjacent memory cells; or The connection direction of the same parts of the two select gates in the memory cells is the row direction, and the upper parts of the select gates and the control gates of the corresponding memory cells in each column are connected along the column to form a stripe; the corresponding floating gates of the memory cells in each column are not connected and are disconnected at the gap between two adjacent memory cells; The corresponding gates of each memory cell in each row or column refer to the gates with the same orientation in each memory cell in the row or column, and these gates are connected in a straight line along the direction of the row or column in the row or column. The gates are selection gates, upper portions of selection gates, lower portions of selection gates, control gates, or floating gates.

5. The embedded flash memory of less than 110 nm according to claim 4, characterized in that: In the memory cell, the select gate and the stacked gate have the same structure and height; the upper and lower portions of the select gate have the same height as the control gate and the floating gate, respectively; and a dielectric layer is also provided between the upper and lower portions of the select gate, the height of which is the same as that of the stacked gate; In the memory array, the connection direction of the same portion of the two select gates in the memory cells is the column direction, and the upper and lower portions of the select gates corresponding to the memory cells in each row, and the dielectric layer therebetween, are connected along the row to form a stripe; in each row, there is at least one through-hole in the dielectric layer between the upper and lower aligned select gate strips, the bottom portion of which is electrically connected to the surface of the lower portion of the select gate stripe and the top portion of which is exposed to the top surface of the dielectric layer, so that the lower portion of the select gate stripe is electrically connected to the upper portion of the dielectric layer; or In the memory array, the connection direction of the same parts of the two select gates in the memory cells is the row direction, and the upper and lower parts of the select gates corresponding to the memory cells in each column, and the dielectric layer therebetween, are connected along the column to form a stripe. In each column, there is at least one through-hole in the dielectric layer between the upper and lower strips of the select gates aligned vertically, the bottom of which is electrically connected to the surface of the lower stripe of the select gate and the top of which is exposed to the top surface of the dielectric layer, so that the lower stripe of the select gate is electrically connected to the top of the dielectric layer.

6. The sub-110 nm embedded flash memory according to claim 5, wherein: In the memory array, the connection direction of the same portion of the two select gates in the memory cell is the column direction. In each row, there is a through hole in the upper portion of the select gate strip corresponding to the through hole in the underlying dielectric layer. The through hole is electrically insulated from the surrounding upper portion of the select gate strip. The bottom of the through hole penetrates and is internally electrically connected to the through hole in the underlying dielectric layer, and the top of the through hole exposes the top surface of the upper portion of the select gate strip. or In the memory array, the connection direction of the same parts of the two selection gates in the memory cell is the row direction. In each column, there is also a through-hole at the position of the through-hole in the lower dielectric layer in the upper portion of the selection gate strip. The through-hole is electrically insulated from the upper portion of the selection gate strip surrounding it, and the bottom is connected to the through-hole in the lower dielectric layer and is electrically connected internally, and the top exposes the top surface of the upper portion of the selection gate strip.

7. The sub-110 nm embedded flash memory according to claim 5, wherein: In the memory array, the connection direction of the same portion of the two select gates in the memory cells is the column direction, and in each row, there is a through hole in the dielectric layer between the upper and lower partial strips of the aligned select gates every 16-32 memory cells along the row; or In the memory array, the connection direction of the same parts of the two selection gates in the memory cells is the row direction. In each column, there is a through hole in the dielectric layer between the upper and lower partial strips of the aligned selection gates every 16-32 memory cells along the column.

8. The embedded flash memory of less than 110 nm according to any one of claims 1 to 7, characterized in that: It is an embedded flash memory device at 90nm and below.

9. A method for preparing an embedded flash memory having a diameter of less than 110 nm, wherein the embedded flash memory is the embedded flash memory having a diameter of less than 110 nm as claimed in any one of claims 1 to 8; characterized in that: It includes the following steps: The control gate in the memory cell and the logic gate in the standard logic transistor are formed in such a manner that, in the same deposition step, a layer of gate material is deposited simultaneously at predetermined positions in the memory array area and the peripheral logic area, and then different masks are used to etch the gate materials deposited on the memory array area and the peripheral logic area respectively.

10. The method for preparing an embedded flash memory having a thickness of less than 110 nm according to claim 9, wherein: The method further comprises the steps of: Before forming the control gate and the logic gate, on the surface of the substrate in the peripheral logic region, there is a deposited material formed as the memory cells in the memory array are prepared. The deposited material is removed by etching.

11. The method for preparing an embedded flash memory having a thickness of less than 110 nm according to claim 9 or 10, wherein: The select gate comprises an upper and a lower portion, and a dielectric layer is provided between the control gate and the floating gate of the stacked gate. The method further comprises the following steps: In the case where the select gate and the stacked gate have the same height, a dielectric layer is provided between the upper and lower portions of the select gate, and the select gate and the stacked gate are formed together through the same fabrication steps; or In the case where there is no dielectric layer between the upper and lower parts of the selection gate, the height of the selection gate and the stacked gate are basically the same, that is, the height of the selection gate is slightly lower than the stacked gate, and the height difference is the height of the dielectric layer in the stacked gate; at this time, the selection gate and the stacked gate are formed together through basically the same preparation steps, and the basically the same preparation steps mean that the preparation steps of the selection gate are different from the preparation steps of the stacked gate, and only the deposition process of the dielectric layer in the stacked gate is missing.

12. The method for preparing an embedded flash memory having a thickness of less than 110 nm according to claim 11, wherein: The select gate and the stacked gate in the memory cell have the same structure and height, the upper and lower portions of the select gate have the same heights as the control gate and the floating gate, respectively, a dielectric layer is provided between the upper and lower portions of the select gate, the height of the dielectric layer being the same as that of the stacked gate, and the lower portion of the select gate is electrically conductive to the upper portion of the dielectric layer; The storage array comprises rows and columns, and the storage units in the array are arranged in the same direction; The method comprises the following steps in sequence: (1) On the substrate, a layer of gate oxide material and a layer of lower gate material are sequentially deposited; then, using a photomask, the deposited lower gate material layer is etched away at the gaps between adjacent memory cells in a predetermined memory array area and at the locations between the floating gates corresponding to the predetermined adjacent memory cells, and the deposited lower gate material layer is etched away at the predetermined peripheral logic area; and no etching is performed at the locations between the lower portions of the select gates corresponding to the predetermined adjacent memory cells; In a case where the connection direction of the same portion of the two select gates in the memory cell is in the column direction, the etching to remove the deposited lower gate material layer at the portion between the floating gates corresponding to the predetermined adjacent memory cells in the predetermined memory array region is: etching is performed along the row direction, in the region of each predetermined row of memory cells, at the portion between the floating gates corresponding to the predetermined adjacent memory cells; or In a case where the connection direction of the same portion of the two select gates in the memory cell is in the row direction, the etching to remove the deposited lower gate material layer at the portion between the floating gates corresponding to the predetermined adjacent memory cells in the predetermined memory array region is: etching is performed along the column direction, in the region of each predetermined column of memory cells, at the portion between the floating gates corresponding to the predetermined adjacent memory cells; (2) depositing a dielectric layer on the lower gate layer in the memory array region and on the gate oxide layer in the peripheral logic region simultaneously; then, using a photomask, etching a through hole in the dielectric layer deposited in the memory array region, and etching away the dielectric layer deposited in the peripheral logic region; The etching to form a through hole in the dielectric layer deposited in the memory array area comprises: In a case where the connection direction of the same portion of the two select gates in the memory cell is in the column direction, in each predetermined row of memory cell regions, at least one through hole is etched in the dielectric layer above a predetermined lower portion of the select gate, wherein the bottom of the through hole contacts the surface of the lower gate layer and the top exposes the top surface of the dielectric layer; In a case where the connection direction of the same portion of the two select gates in the memory cell is in the row direction, in each predetermined column of memory cell regions, at least one through hole is etched in the dielectric layer above a predetermined lower portion of the select gate, wherein the bottom of the through hole contacts the surface of the lower gate layer and the top exposes the top surface of the dielectric layer; (3) depositing a layer of upper gate material on the dielectric layer in the memory array area and on the gate oxide layer in the peripheral logic area at the same time; then, using a photomask in the memory array area, etching downward to the gate oxide layer in areas other than the predetermined selection gate and control gate, removing the upper and lower gate material layers and the dielectric layer therebetween in these areas, and simultaneously forming a stripe on the upper portion of the selection gate, a stripe on the lower portion of the selection gate, a stripe on the control gate, and a floating gate; then, using a photomask in the peripheral logic area, etching away the upper gate material layer in areas other than the predetermined logic gate to form a logic gate.

13. The method for preparing an embedded flash memory having a thickness of less than 110 nm according to claim 12, wherein: The etching to form a through hole in the dielectric layer deposited in the memory array area comprises: In a case where the connection direction of the same portion of the two select gates in the memory cell is in the column direction, in each predetermined row of memory cell regions, at least one through hole is etched in the dielectric layer above the predetermined lower portion of the select gate at every predetermined 16-32 memory cell positions along the row; In a case where the connection direction of the same portion of the two selection gates in the memory cell is in the row direction, in each predetermined column of memory cell areas, at least one through hole is etched in the dielectric layer above the area of the predetermined lower portion of the selection gate at every predetermined position of 16-32 memory cells along the column.

14. The method for preparing an embedded flash memory having a thickness of less than 110 nm according to claim 12, wherein: The operation of etching in the memory array region to form a select gate upper portion stripe, a select gate lower portion stripe, a control gate stripe, and a floating gate is specifically: In the case where the connection direction of the same portion of the two select gates in the memory cell is in the column direction, etching is performed along the row direction in the predetermined area of each row of memory cells to form two upper portion strips of the select gate, two lower portion strips of the select gate, two control gate strips, and a floating gate in each row; or When the connection direction of the same part of the two selection gates in the memory cell is the row direction, two upper selection gate strips, two lower selection gate strips, two control gate strips, and a floating gate are etched in the predetermined area of each column of memory cells along the column direction.

15. The method for preparing an embedded flash memory having a thickness of less than 110 nm according to any one of claims 12 to 14, wherein: It also includes the following steps: Before step (1), forming a well of a memory cell in a memory array in the substrate; and Between step (2) and step (3), a well of a standard logic transistor is formed in the peripheral logic region, and then the gate oxide layer deposited in step (1) is removed from the substrate surface of the peripheral logic region, and then the gate oxide layer of the logic region is regrown.

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