Low-temperature polycrystalline silicon thin film transistor with high uniformity and high stability and method

Abstract

The invention belongs to the technical field of semiconductors, and provides a low-temperature polycrystalline silicon thin film transistor with high uniformity and high stability and a method. The preparation method comprises the following steps: generating a first buffer layer on a substrate; amorphous silicon continues to be generated on the first buffer layer, and the amorphous silicon is crystallized into polycrystalline silicon to serve as an active layer; removing a natural oxide layer on the surface of the polycrystalline silicon and then performing fluorine plasma treatment on the polycrystalline silicon; after fluorine plasma processing, a layer of thin silicon oxide is grown on the surface of the active layer in a thermal oxidation mode to serve as a first dielectric layer, and a second dielectric layer is grown on the first dielectric layer; preparing a gate electrode on the second dielectric layer; performing graphical etching on the gate electrode, the second dielectric layer and the first dielectric layer, and growing a second buffer layer on the whole layer; carrying out ion implantation on the regions on the two sides of the gate electrode by using boron ions, and carrying out annealing activation after the implantation is finished to form a source region and a drain region; and etching the second buffer layer above the source region and the drain region to form contact holes of a source electrode and a drain electrode, and depositing the source electrode and the drain electrode to obtain the low-temperature polycrystalline silicon thin film transistor.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and particularly relates to a low-temperature polycrystalline silicon thin-film transistor with high uniformity and high stability and a method thereof. Background Art

[0002] The statements in this part merely provide background technical information related to the present invention and do not necessarily constitute prior art.

[0003] In order to meet the market demand for high resolution and high integration, with the continuous miniaturization of device sizes, the differences in the number of grains and grain boundaries in the channel make it difficult to ensure performance uniformity and device stability, severely restricting the development of low-temperature polycrystalline silicon (LTPS) in large-scale integrated circuits. Therefore, improving the uniformity and stability of LTPS thin-film transistors over a large area has become a hot research topic.

[0004] The prior art treats the LTPS thin film with hydrogen plasma, and uses the hydrogen plasma to passivate the trap states in the polycrystalline silicon thin-film interface and grain boundaries, improving the uniformity of the TFT (Thin Film Transistor). However, the weak Si-H bonds generated by the hydrogen plasma treatment will deteriorate the reliability of the TFT. The prior art also uses high-pressure steam annealing to effectively reduce the number of fixed oxide charges and interface traps in the TFT gate insulating layer, improving the DC characteristics and uniformity of the LTPS-TFT. However, the high-pressure annealing operation is difficult, the process conditions are harsh, and there will be a problem of increased production costs. In addition, it has also been reported that when laser scanning crystallization of the LTPS thin film is carried out, multiple scans can be performed to slow down the grain boundary protrusions on the surface of the LTPS thin film, thereby improving the uniformity of the device. Although this method does not add additional processes, it is complex, difficult to operate and not easy to repeat, and is difficult to use over a large area. Summary of the Invention

[0005] In order to solve the technical problems existing in the above background art, the present invention provides a low-temperature polycrystalline silicon thin-film transistor with high uniformity and high stability and a method thereof. By treating the LTPS thin film with fluorine plasma and changing the treatment time and power of the fluorine plasma, a low-temperature polycrystalline silicon thin-film transistor with good uniformity and high stability is prepared.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] The first aspect of the present invention provides a low-temperature polycrystalline silicon thin-film transistor with high uniformity and high stability.

[0008] A preparation method of a low-temperature polycrystalline silicon thin-film transistor with high uniformity and high stability, which includes:

[0009] Generate a first buffer layer on a substrate;

[0010] Continuously deposit amorphous silicon on the first buffer layer, and crystallize the amorphous silicon into polycrystalline silicon as the active layer;

[0011] Perform fluorine plasma treatment on the active layer; wherein, the treatment time of the fluorine plasma is controlled within 0 - 5 min, the power is set at 20 - 200 W, and the reaction temperature is controlled between 10 - 60 °C;

[0012] After the fluorine plasma treatment, grow a thin silicon oxide layer on the active layer by thermal oxidation as the first dielectric layer, and grow a second dielectric layer on the first dielectric layer;

[0013] Fabricate a gate electrode on the second dielectric layer;

[0014] Pattern and etch the gate electrode, the second dielectric layer and the first dielectric layer, and then grow a second buffer layer over the entire layer;

[0015] Perform ion implantation on both sides of the gate electrode using boron ions, and perform annealing activation after the implantation to form a source region and a drain region;

[0016] Etch the second buffer layer above the source region and the drain region to form contact holes for the source electrode and the drain electrode, and deposit the source electrode and the drain electrode to obtain a low-temperature polycrystalline silicon thin-film transistor.

[0017] As an implementation manner, the first dielectric layer is a silicon oxide thin film.

[0018] As an implementation manner, the second dielectric layer is an aluminum oxide thin film or a hafnium oxide thin film.

[0019] As an implementation manner, during the fluorine plasma treatment, the flow rate of the fluorine-containing gas is 10 - 100 sccm, and the flow rate of the inert gas is 10 - 200 sccm.

[0020] As an implementation manner, during the fluorine plasma treatment, in a PECVD or ICP reaction chamber, sulfur hexafluoride and argon, or tetrafluoromethane and argon, or trifluoromethane and argon are used and the gas flow rate is controlled.

[0021] As an implementation manner, before the fluorine plasma treatment, it further includes: removing the natural silicon oxide thin layer on the surface of the polycrystalline silicon with hydrofluoric acid, the concentration of the hydrofluoric acid is 1% - 5%, and drying is performed.

[0022] As an implementation manner, the implantation conditions for the ion implantation are: implantation energy 10 - 90 keV, implantation dose 5e 14 ~5e 15 atoms / cm 3 , and the implantation angle is 7°.

[0023] As an implementation manner, after the ion implantation is completed, an annealing activation treatment is carried out. The annealing temperature is 400°C, and the annealing time is 1 to 4 hours.

[0024] As an implementation manner, the thicknesses of the gate electrode, source electrode, and drain electrode are all 20 to 500 nm.

[0025] The second aspect of the present invention provides a low-temperature polycrystalline silicon thin-film transistor with high uniformity and high stability.

[0026] A low-temperature polycrystalline silicon thin-film transistor with high uniformity and high stability includes:

[0027] A low-temperature polycrystalline silicon thin-film transistor with high uniformity and high stability is prepared by using the preparation method as described above.

[0028] The beneficial effects of the present invention are as follows:

[0029] The present invention uses fluorine plasma to treat the LTPS thin film. By changing the treatment time and power of the fluorine plasma, a low-temperature polycrystalline silicon thin-film transistor with good uniformity and high stability is prepared. Compared with the existing technologies such as hydrogen plasma treatment, high-pressure steam annealing, and laser repeated scanning, the fluorine plasma treatment technology is a simple and easy-to-operate method that can be used for large-area preparation with good repeatability. This process can be realized at low cost, making it possible to achieve low-cost and high-performance LTPS TFTs, laying a foundation for their application in future large-scale integrated circuits and high-resolution display technologies.

[0030] The advantages of the additional aspects of the present invention will be partially given in the following description, partially become obvious from the following description, or be understood through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The specification drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention.

[0032] Figure 1 In (a), the LTPS thin film is not treated with fluorine plasma, and in (b), the TEM image of the LTPS thin film treated with fluorine plasma for 1 minute;

[0033] Figure 2 is a schematic diagram of the fluorine plasma treatment of the LTPS thin film according to an embodiment of the present invention;

[0034] Figure 3 is a schematic structural diagram of a low-temperature polycrystalline silicon thin-film transistor with high uniformity and high stability according to an embodiment of the present invention;

[0035] Figure 4 The I of LTPS thin film transistors in (a) without fluorine plasma treatment, (b) with 0.5-minute fluorine plasma treatment, and (c) with 1-minute fluorine plasma treatment in D -V G transfer curve graph, and (d) the uniformity graph of V and S-value parameters of LTPS thin film transistors under different fluorine plasma treatment times; TH

[0036] Figure 5 The I of LTPS thin film transistors in (a) without fluorine plasma treatment, (b) with 0.5-minute fluorine plasma treatment, and (c) with 1-minute fluorine plasma treatment in bias stability test at high temperature (125 °C) D -V G curve graph, and (d) the offset of V of LTPS thin film transistors under different fluorine plasma treatment times. TH

[0037] Among them, 1. Substrate; 2. First buffer layer; 3. Active layer; 4. Dielectric layer; 5. Second buffer layer; 6. Source electrode; 7. Drain electrode; 8. Gate electrode. Detailed implementation manners

[0038] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0039] It should be noted that the following detailed description is exemplary and is intended to provide further illustration of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs.

[0040] It should be noted that the terms used herein are only for describing specific implementation manners and are not intended to limit the exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0041] ​​With the booming development of the information age, electronic devices have been deeply integrated into all aspects of life. From flat panel displays such as smartphones and computers to wearable devices and various sensor nodes in the Internet of Things, the realization of their core functions depends on the support of advanced semiconductor technology. As a key technology, Thin Film Transistors (TFTs) play a crucial role in multiple aspects such as information acquisition, processing, storage, and display. The rapid development of the information age has also put forward higher requirements for thin film transistors, such as smaller device sizes, higher stability, better uniformity under large-area preparation, and lower preparation temperatures, so as to meet the actual application requirements for data processing speed, display quality, and device miniaturization.

[0042] In recent years, Low Temperature Polycrystalline Silicon (LTPS) has received much attention in large-area electronic application fields such as Active Matrix Liquid Crystal Displays (AMLCDs). Compared with other Amorphous Silicon (α-Si) and Amorphous Oxide Semiconductors (AOS), LTPS has higher mobility, current driving ability, and stability. The preparation of LTPS is usually achieved through Excimer Laser Annealing (ELA). Due to its advantages such as fast crystallization speed and relatively low process temperature, ELA technology has become the mainstream crystallization method. However, during the ELA crystallization process, due to the instability of the laser energy density, there are differences between grains, such as grain size and surface roughness, which also affect the difference in the density of defect states in grain boundaries. These differences will ultimately result in non-uniform electrical properties among the fabricated TFT devices. When used in flat panel displays, it will cause pixel brightness differences and image non-uniformity, thus restricting the development of display technology.

[0043] LTPS thin film transistors have broad application prospects. However, currently, with the trend of continuous miniaturization of device sizes, it is difficult to ensure the uniformity in large-area manufacturing. Although there are reports on using hydrogen plasma treatment to improve uniformity, it will deteriorate the stability of the device at the same time. There are also methods such as laser repeated scanning and high-voltage annealing, but they either have overly complex preparation processes and high operation difficulties, which limit the application scenarios, or increase the manufacturing cost.

[0044] Compared with the above technologies, fluorine plasma treatment has a series of advantages such as low cost, simple operation, ability to prepare in large areas, and good repeatability. In the present invention, in a Plasma Enhanced Chemical Vapor Deposition (PECVD) system or an Inductively Coupled Plasma Etching (ICP) system, the time of the plasma generated by F-containing gases (such as SF 6 、CF 4 、CHF 3 etc.) and the power of the radio frequency power supply are adjusted to treat the LTPS thin film, and the whole process is carried out at room temperature.

[0045] The experimental results show that the fluorine plasma treatment technology improves the grain boundary protrusions on the surface of LTPS, making the surface of the LTPS film smoother. As a result, the performance differences between the subsequent fabricated devices become smaller, greatly improving the device uniformity. In addition, during the fluorine plasma treatment process, fluorine ions passivate the defect states at the LTPS grain boundaries and on the surface, generating stronger Si-F bonds with greater bonding force, and improving the stability of the device under long-term stress. The present invention successfully fabricates LTPS thin film transistors with high uniformity and high stability, laying a foundation for their application in large-scale integrated circuits and high-resolution display technologies.

[0046] As Figure 3 shown, the low-temperature polysilicon thin film transistor with high uniformity and high stability is fabricated by the preparation method as described above.

[0047] Among them, the preparation method of the low-temperature polysilicon thin film transistor with high uniformity and high stability includes:

[0048] Step 1: Generate a first buffer layer 2 on a substrate 1.

[0049] The substrate can be one or several of silicon wafers, glass, and quartz glass; the buffer layer 2 material can be one or several of silicon oxide, silicon nitride, aluminum oxide, etc.; the growth method can be CVD, ALD, etc., and the thickness can be 100 - 500 nm.

[0050] Step 2: Continuously grow amorphous silicon on the first buffer layer 2, and crystallize the amorphous silicon into polysilicon as the active layer 3.

[0051] The growth method of continuously growing amorphous silicon on the first buffer layer 2 can be CVD, and the thickness can be 10 - 200 nm. Use ELA to crystallize the amorphous silicon into polysilicon as the active layer, where the direction of the excimer laser scanning is consistent with the channel direction of the subsequent fabricated devices. When the device channel direction is consistent with the laser scanning direction, devices with more uniform performance and better stability can be obtained.

[0052] Step 3: Perform fluorine plasma treatment on the active layer 3; among them, the treatment time of the fluorine plasma is controlled within 0 - 5 min, the power is set at 20 - 200 W, and the reaction temperature is controlled between 10 - 60 °C.

[0053] It should be noted here that the treatment time and power of the fluorine plasma can be specifically set according to the actual situation.

[0054] Among them, during the fluorine plasma treatment process, the flow rate of the fluorine-containing gas is 10 - 100 sccm, and the flow rate of the inert gas is 10 - 200 sccm.

[0055] In other embodiments, those skilled in the art can specifically set the flow rate of the fluorine-containing gas and the flow rate of the inert gas according to the actual situation.

[0056] During the fluorine plasma treatment, in a PECVD or ICP reaction chamber, sulfur hexafluoride and argon, or tetrafluoromethane and argon, or trifluoromethane and argon are used and the gas flow rate is controlled.

[0057] It should be noted here that the gases introduced for the fluorine plasma treatment include but are not limited to SF 6 , CF 4 , CHF 3 and other mixed gas atmospheres with Ar or other inert gases.

[0058] In other embodiments, the fluorine plasma treatment can also be carried out in other reaction chambers.

[0059] Before the fluorine plasma treatment, it further includes: removing the natural silicon oxide thin layer on the polysilicon surface with hydrofluoric acid, the concentration of the hydrofluoric acid is 1% - 5%, and drying is carried out.

[0060] Step 4: After the fluorine plasma treatment, a thin silicon oxide layer is grown on the active layer by thermal oxidation as the first dielectric layer, and a second dielectric layer is grown on the first dielectric layer.

[0061] The first dielectric layer and the second dielectric layer constitute the dielectric layer 4. The first dielectric layer is a silicon oxide thin film; the second dielectric layer is an aluminum oxide thin film or a hafnium oxide thin film.

[0062] After the sample is treated by fluorine plasma, the sample is placed in a rapid thermal annealing furnace, and a thin silicon oxide layer is grown by thermal oxidation as the first dielectric layer. The silicon oxide thin film grown by thermal oxidation is denser, and when the silicon oxide thin film contacts the polysilicon thin film, it has a better interface, fewer defects, and smaller hysteresis of the fabricated device.

[0063] Step 5: A gate electrode 8 is fabricated on the second dielectric layer.

[0064] One or several of metal materials such as molybdenum, tungsten, titanium, gold, etc. are selected as the gate electrode, and the growth method can be carried out in radio frequency magnetron sputtering, electron beam evaporation, thermal evaporation, and the film thickness is 20 - 500 nm.

[0065] Step 6: Pattern etching is carried out on the gate electrode 8, the second dielectric layer and the first dielectric layer, and then a second buffer layer 5 is grown over the entire layer.

[0066] The material of the second buffer layer 5 can be one or several of silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, and this process can be carried out in CVD, ALD, and the thickness of the second buffer layer is 20 - 200 nm.

[0067] Step 7: Use boron ions to perform ion implantation on both sides of the gate electrode 8. After the implantation is completed, annealing activation is carried out to form the source region and the drain region.

[0068] The advantages of the ion implantation buffer layer are that it can not only effectively reduce lattice damage, but also effectively prevent moisture in the air from entering the dielectric layer and the channel, improving the reliability of the device. The implantation conditions for ion implantation are: implantation energy 10 - 90 KeV, implantation dose 5e 14 ~5e 15 atoms / cm 3 , and the implantation angle is 7°.

[0069] Among them, after the ion implantation is completed, annealing activation treatment is carried out. The annealing temperature is 400 °C, and the annealing time is 1 - 4 hours.

[0070] Step 8: Etch the second buffer layer above the source region and the drain region to form contact holes for the source electrode 6 and the drain electrode 7, deposit the source electrode and the drain electrode, and obtain a low-temperature polycrystalline silicon thin-film transistor.

[0071] Select metal materials such as molybdenum, tungsten, aluminum, titanium, nickel, etc. as the source and drain electrodes. The growth method can be carried out in radio frequency magnetron sputtering, electron beam evaporation, or thermal evaporation, and the film thickness is 20 - 500 nm.

[0072] Detect, analyze, and characterize the morphology of the LTPS thin film before and after fluorine plasma treatment and the electrical properties of the corresponding device;

[0073] Use a transmission electron microscope (TEM) to test the morphology of the LTPS active layer before and after fluorine plasma treatment; use an Agilent B2900 semiconductor analyzer to test the electrical properties of the LTPS thin-film transistor. Table 1 shows the various characteristic parameters of the LTPS thin-film transistor in the embodiments of the present invention before and after fluorine plasma treatment.

[0074] Table 1 Various characteristic parameters of the LTPS thin-film transistor before and after fluorine plasma treatment

[0075]

[0076] Table 1 shows the various characteristic parameters of the LTPS thin-film transistor. Among them, the LTPS thin-film transistor after 1 minute of fluorine plasma treatment exhibits excellent electrical properties, with good hole mobility (~30 cm 2 V -1 s -1 ), low off-state current density (<10 -13 A um -1 ), high on / off current ratio (~10 7 ), and low subthreshold swing (0.23 V decade -1) Excellent bias stability at high temperatures (<4 mV).

[0077] Figure 1 (a) in [reference] shows that obvious grain boundary protrusions can be observed in the LTPS thin film without fluorine plasma treatment under TEM. The grain boundary protrusions will increase the roughness of the thin film, resulting in non-uniform device performance; they will also deteriorate properties such as subthreshold swing and stability. Figure 1 (b) in [reference] shows that after fluorine plasma treatment, the protrusions on the grain boundary surface are significantly improved, the surface becomes smoother, the roughness is greatly reduced, and the performance uniformity of the device is significantly improved, reflecting the process universality of preparing high-performance LTPS thin film transistors by this method.

[0078] Figure 2 is a schematic diagram of fluorine plasma treatment of LTPS thin films. In a plasma enhanced chemical vapor deposition system (PECVD) or an inductively coupled plasma etching system (ICP), the treatment time of the plasma generated by the fluorine-containing gas and the radio frequency power supply are adjusted to treat the LTPS thin film. The whole process is carried out at room temperature. It reflects the simplicity and easy operation of the preparation process. The treatment temperature is room temperature, and there is no need for cumbersome steps such as high-pressure annealing or laser repeated scanning, which further reduces the process cost, improves the process repeatability, and is easy for large-area preparation.

[0079] Figure 4 (a), (b), and (c) in [reference] show that the I D -V G transfer curves of LTPS thin film transistors without fluorine plasma treatment and after 0.5 minutes and 1 minute of fluorine plasma treatment in the linear region. It can be clearly seen from the figure that the electrical performance uniformity of the device is greatly improved after fluorine plasma treatment. While the on-state current of the device does not decrease significantly, the off-state current decreases by about one order of magnitude, and it has a higher on-off current ratio (~10 7 ) and lower power consumption. Figure 4 (d) in [reference] shows that during the fluorine plasma treatment process, fluorine ions passivate the defect states at the grain boundaries and on the surface, resulting in a significant reduction in the subthreshold swing of the device and a faster switching speed. In addition, the threshold voltage of the device moves forward and the change range is very small after fluorine plasma treatment, indicating that the device is easier to turn on and the uniformity is significantly improved.

[0080] Figure 5 (a), (b), and (c) in [reference] are the I D -V G curves of LTPS thin film transistors without fluorine plasma treatment, treated with fluorine plasma for 0.5 minutes, and treated for 1 minute during bias stability testing at 125 °C. During the testing process, the electric field strength of the gate dielectric layer exceeds 2 MV / cm.Figure 5 Among them, (d) is the comparison of the bias stability of the device after being treated with fluorine plasma for different times. In the figure, the threshold voltage of the device after being treated with fluorine plasma shows a smaller offset. Among them, for the device treated with fluorine plasma for 1 minute, under a bias stress of 10,000 s, the threshold voltage offset is no more than 4 mV, indicating that fluoride ions passivate the defect states at the grain boundaries and on the surface, generating more stable Si-F bonds, laying a foundation for the application of LTPS thin-film transistors in large-scale integrated circuits.

[0081] The present invention optimizes parameters such as the treatment time, the power of the radio frequency power supply, and the flow ratio of the introduced gases during the fluorine plasma treatment process, and successfully fabricates low-temperature polycrystalline silicon thin-film transistors with high uniformity and high stability. This method is simple, efficient, easy to repeat, and low in cost, and is suitable for industrial large-area production.

[0082] The LTPS thin-film transistors fabricated by this method exhibit excellent electrical properties: having good hole mobility (~30 cm 2 V -1 s -1 ), low off-state current density (<10 -13 A um -1 ), high on / off current ratio (~10 7 ), low subthreshold swing (0.23 V decade -1 ), and excellent bias stability at high temperature (<4 mV).

[0083] The above excellent electrical properties and stability can be obtained by large-area fluorine plasma treatment, and the difference between devices is small, ensuring the uniformity of the devices. The process temperature for fabricating the entire device does not exceed 400 °C, and it is compatible with the back-end engineering of integrated circuits, having broad application prospects in future large-scale integrated circuits and high-resolution displays.

[0084] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for preparing a low-temperature polysilicon thin film transistor with high uniformity and high stability, characterized in that: include: generating a first buffer layer on the substrate; Continue to generate amorphous silicon on the first buffer layer, and crystallize the amorphous silicon into polycrystalline silicon as an active layer; The active layer is treated with fluorine plasma; wherein the treatment time of the fluorine plasma is controlled at 0 to 5 minutes, the power is set at 20 to 200 W, and the reaction temperature is controlled at 10 to 60° C.; After the fluorine plasma treatment, a thin layer of silicon oxide is grown on the active layer as a first dielectric layer by thermal oxidation, and a second dielectric layer is grown on the first dielectric layer; preparing a gate electrode on the second dielectric layer; Patterning and etching the gate electrode, the second dielectric layer and the first dielectric layer, and then growing the second buffer layer in the entire layer; Boron ions are used to implant ions into the regions on both sides of the gate electrode, and annealing is performed after the implantation to form a source region and a drain region; The second buffer layer above the source region and the drain region is etched to form contact holes for the source electrode and the drain electrode, and the source electrode and the drain electrode are deposited to obtain a low-temperature polysilicon thin film transistor.

2. The preparation method according to claim 1, characterized in that The first dielectric layer is a silicon oxide film.

3. The preparation method according to claim 1, characterized in that: The second dielectric layer is an aluminum oxide film or a hafnium oxide film.

4. The preparation method according to claim 1, characterized in that: During the fluorine plasma treatment, the flow rate of the fluorine-containing gas is 10-100 sccm, and the flow rate of the inert gas is 10-200 sccm.

5. The preparation method according to claim 1, characterized in that: During the fluorine plasma treatment, sulfur hexafluoride and argon, or tetrafluoromethane and argon, or trifluoromethane and argon are used in a PECVD or ICP reaction chamber and the gas flow rates are controlled.

6. The preparation method according to claim 1, characterized in that: Before the fluorine plasma treatment, the method also includes: removing the natural silicon oxide thin layer on the surface of the polysilicon with hydrofluoric acid, the concentration of the hydrofluoric acid being 1% to 5%, and drying.

7. The preparation method according to claim 1, characterized in that: The implantation conditions of ion implantation are: implantation energy 10~90KeV, implantation dose 5e 14 ~5e 15 atoms / cm 3 , the injection angle is 7°.

8. The preparation method according to claim 1, characterized in that: After the ion implantation is completed, an annealing activation treatment is performed, the annealing temperature is 400° C., and the annealing time is 1 to 4 hours.

9. The preparation method according to claim 1, characterized in that: The thickness of the gate electrode, the source electrode and the drain electrode are all 20 to 500 nm.

10. A low temperature polysilicon thin film transistor with high uniformity and high stability, characterized in that: The method is prepared according to any one of claims 1 to 9.

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