Preparation method of semiconductor structure, semiconductor structure and semiconductor device

Abstract

The invention provides a preparation method of a semiconductor structure, the semiconductor structure and a semiconductor device. The preparation method comprises the following steps: providing a substrate; the base comprises a substrate and a first oxide layer formed on the surface of the substrate; wherein the substrate comprises a first region and a second region; forming a first gate material layer on the first oxide layer; wherein the first gate material layer comprises a first sacrificial gate material part located on the first region and a first gate material part located on the second region; using the first gate material part as a mask, removing the first sacrificial gate material part and the first sacrificial oxidation part based on a dry etching process, and forming a second gate oxidation part on the surface of the first region; wherein the thickness of the second gate oxidation part is different from that of the first gate oxidation part. Therefore, the problem of light resistance falling in the process of preparing the double-gate oxide layer can be improved, the quality of the double-gate oxide layer is improved, and the performance and the yield of the semiconductor structure are further ensured.

Description

Technical Field

[0001] The embodiments in the present application relate to the technical field of semiconductor manufacturing processes, and particularly to a method for manufacturing a semiconductor structure, a semiconductor structure, and a semiconductor device. Background Art

[0002] In the field of semiconductor manufacturing, the Dual Gate Oxide (Dual GOX) process is used to integrate transistors with different operating voltage requirements on the same chip. With the continuous development of integrated circuits, especially for mixed-signal and radio frequency applications, it is necessary to integrate low-voltage core logic circuits and high-voltage input / output (I / O) circuits on the same chip simultaneously. The traditional single gate oxide process cannot meet such diverse requirements because low-voltage circuits require thinner gate oxides to improve speed and reduce power consumption, while high-voltage circuits require thicker gate oxides to prevent breakdown and leakage current.

[0003] In response to this, the Dual GOX process can meet the voltage requirements of different regions by fabricating gate oxides with different thicknesses in different regions of the substrate. The Dual GOX process first grows a relatively thick gate oxide layer on the entire surface of the substrate, then removes the thick oxide layer covering some regions through photolithography and wet etching techniques, and finally grows a relatively thin gate oxide layer on these regions.

[0004] However, during the process of wet etching to remove the thick oxide layer covering some regions in the Dual GOX process, the photoresist is likely to peel off, resulting in defects in the subsequently grown thin oxide layer, affecting the performance and yield of the semiconductor structure. Summary of the Invention

[0005] In view of this, multiple embodiments of the present application are dedicated to providing a method for manufacturing a semiconductor structure, a semiconductor structure, and a semiconductor device, which can improve the problem of photoresist peeling off during the preparation of the dual gate oxide, enhance the quality of the dual gate oxide, and thus ensure the performance and yield of the semiconductor structure.

[0006] An embodiment of the present application provides a method for fabricating a semiconductor structure, including: providing a substrate; the substrate includes a substrate and a first oxide layer formed on the surface of the substrate; wherein, the substrate includes a first region and a second region; the first oxide layer includes a first sacrificial oxide portion located on the first region and a first gate oxide portion located on the second region; forming a first gate material layer on the first oxide layer; wherein, the first gate material layer includes a first sacrificial gate material portion located on the first region and a first gate material portion located on the second region; using the first gate material portion as a mask, removing the first sacrificial gate material portion and the first sacrificial oxide portion based on a dry etching process, and forming a second gate oxide portion on the surface of the first region; wherein, the thickness of the second gate oxide portion is different from the thickness of the first gate oxide portion.

[0007] Optionally, after the step of forming the first gate material layer on the first oxide layer, the method for fabricating the semiconductor structure further includes: Optionally, the second oxide layer includes a second sacrificial oxide portion located on the first region and a protective oxide portion located on the second region; during the process of removing the first sacrificial gate material portion and the first sacrificial oxide portion based on a dry etching process, the first gate material portion and the protective oxide portion are used as a mask together, and the second sacrificial oxide portion is removed.

[0008] Optionally, after forming the second gate oxide portion on the surface of the first region, the method for fabricating the semiconductor structure further includes: depositing and forming a second gate material layer on the surfaces of the second gate oxide portion and the protective oxide portion; wherein, the second gate material layer includes a second gate material portion located on the first region and a second sacrificial gate material portion located on the second region; using the protective oxide portion as a planarization stop layer, performing a planarization process on the second gate material layer to make the second gate material portion flush with the first gate material portion.

[0009] Optionally, in the step of using the protective oxide portion as a planarization stop layer and performing a planarization process on the second gate material layer, it includes: based on a first chemical mechanical polishing process, grinding the second gate material layer to be flush with the planarization stop layer; wherein, the second sacrificial gate material portion is removed; based on a second chemical mechanical polishing process, grinding the second gate material portion to be flush with the first gate material portion; wherein, the planarization stop layer is removed.

[0010] Optionally, after grinding the second gate material layer to be flush with the planarization stop layer based on the first chemical mechanical polishing process, a buffer portion is formed on the side of the planarization stop layer; wherein, during the second chemical mechanical polishing process, the buffer portion protects the remaining second gate material portion between the surface of the first region and the buffer portion.

[0011] Optionally, the thickness of the first gate oxide portion is greater than the thickness of the second gate oxide portion.

[0012] Optionally, the first region is a low-voltage region and the second region is a high-voltage region.

[0013] Optionally, the gate materials of the first gate material layer and the second gate material layer are the same.

[0014] An embodiment of the present application provides a semiconductor structure, which is prepared by using the preparation method of the semiconductor structure described in any of the foregoing embodiments.

[0015] An embodiment of the present application provides a semiconductor device, which includes the semiconductor structure described in any of the foregoing embodiments.

[0016] The unexpected effects of multiple embodiments provided by the present application are as follows: On the first oxide layer grown on the surface of the substrate, a first gate material layer is directly formed first, and then based on a dry etching process, the first sacrificial oxide portion located on the first region is removed, and then a second gate oxide portion with different thicknesses is formed on the surface of the first region. Since the dry etching process is used to remove the first sacrificial oxide portion, the problem of photoresist peeling caused by wet etching in the related art can be reduced, and during the dry etching process, the first gate material portion of the first gate material layer formed in advance and located on the second region is cleverly used as a mask layer, without introducing a hard mask material, which not only simplifies the process steps but also avoids the influence on the prepared double gate oxide layer caused by removing the hard mask material, thereby improving the quality of the double gate oxide layer and further ensuring the performance and yield of the semiconductor structure. Description of the Drawings

[0017] Figure 1 It is a schematic diagram of the preparation method of the semiconductor structure provided by the embodiment of the present application.

[0018] Figure 2 It is a schematic diagram of providing a substrate in the preparation method of the semiconductor structure provided by the embodiment of the present application.

[0019] Figure 3 It is a schematic diagram of forming a first gate material layer and a second oxide layer in the preparation method of the semiconductor structure provided by the embodiment of the present application.

[0020] Figure 4 and Figure 5 It is a schematic diagram of removing the first sacrificial oxide portion and the first sacrificial gate material portion in the preparation method of the semiconductor structure provided by the embodiment of the present application.

[0021] Figure 6Schematic diagram of forming a second gate oxide part in the method for preparing a semiconductor structure provided by an embodiment of the present application.

[0022] Figure 7 Schematic diagram of forming a second gate material layer in the method for preparing a semiconductor structure provided by an embodiment of the present application.

[0023] Figure 8 Schematic diagram of the first CMP process in the method for preparing a semiconductor structure provided by an embodiment of the present application.

[0024] Figure 9 Schematic diagram of the second CMP process in the method for preparing a semiconductor structure provided by an embodiment of the present application.

[0025] Figure 10 Schematic diagram of forming a gate in the method for preparing a semiconductor structure provided by an embodiment of the present application.

[0026] Description of reference numerals: 10. Substrate; 11. Substrate; 111. First region; 112. Second region; 12. First oxide layer; 13. First gate material layer; 14. Second oxide layer; 121. First sacrificial oxide part; 122. First gate oxide part; 131. First sacrificial gate material part; 132. First gate material part; 141. Second sacrificial oxide part; 142. Protection oxide part; 15. Second gate oxide part; 16. Second gate material layer; 161. Second gate material part; 162. Second sacrificial gate material part; 1611. Buffer part; 17. First gate structure; 18. Second gate structure. Detailed description of the invention

[0027] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments.

[0028] In the present application, the accompanying drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features.

[0029] Unless otherwise specified, all technical and scientific terms used in the present application have the same meaning as commonly understood by those skilled in the technical field of the present application. The terms used in the present application are only for the purpose of describing specific embodiments and are not intended to limit the scope of the present application. The term "and / or" used in the embodiments of the present application and the appended claims includes any and all combinations of one or more of the related listed items. The singular forms of "a", "above-mentioned" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0030] In the description of this application, it should be understood that the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the described features. In the description of the embodiments of this application, the meaning of "a plurality" is two or more, unless otherwise specifically defined.

[0031] In the description of this application, the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "height", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of simplifying the description of this application and does not indicate that the indicated device or element must have a specific orientation, be constructed and operated in a specific orientation, that is, it cannot be construed as a limitation to this application.

[0032] In the description of this application, unless otherwise clearly defined, the terms "installed", "connected", "joined", "fixed", "set", etc. shall be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and can also be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0033] In the related art, in the step of removing a thick oxide layer for an area that requires a thin oxide layer in the Dual GOX process, usually based on a wet etching method, the substrate with photoresist is immersed in an acid bath and soaked for a certain time to achieve the removal of the thick oxide layer. However, due to the acid resistance problem of photoresist materials (such as KRF photoresist, etc.), their stability in an acidic environment decreases, resulting in the problem that the photoresist is likely to fall off onto the substrate surface during the wet etching process, thereby causing defects in the thin oxide layer grown subsequently in the Dual GOX process and affecting the performance and reliability of the semiconductor structure.

[0034] In response to this, the technicians improved the process by adopting a dry etching method in the step of removing the thick oxide layer to reduce the problem of photoresist peeling off. However, there may be other problems when using the dry etching process.

[0035] Specifically, compared with wet etching, dry etching processes usually require the introduction of a hard mask material, such as BARC (bottom anti-reflection coating), as the hard mask layer to ensure etching accuracy and provide protection. Therefore, after etching, additional removal of the hard mask material is required, which may lead to problems such as incomplete removal, chemical contamination, and substrate surface damage, thereby affecting the quality of the prepared double gate oxide layer.

[0036] Therefore, it is necessary to provide a method for preparing a semiconductor structure that can improve the quality of the prepared double gate oxide layer, thereby ensuring the performance and yield of the semiconductor structure.

[0037] Please refer to Figures 1-10 This application provides a method for preparing a semiconductor structure in one embodiment. The method for preparing the semiconductor structure may include the following steps.

[0038] S110: Provide a substrate.

[0039] In this embodiment, as Figure 2 shown in, the substrate 10 includes a substrate 11 and a first oxide layer 12 formed on the surface of the substrate 11.

[0040] In this embodiment, the substrate 11 can serve as the basic structure of the semiconductor structure, not only providing mechanical support, but also affecting the electrical properties of the semiconductor structure, such as the working voltage and carrier mobility, by doping ions. Specifically, the substrate 11 can be made of silicon (Si), or can be made of other semiconductor materials according to requirements, such as silicon carbide (SiC) or gallium nitride (GaN), etc.

[0041] In this embodiment, according to different circuit design requirements, the substrate 11 can be divided into multiple regions with different working voltage requirements, and different thicknesses of gate oxide layers can be fabricated in each region to meet different working voltage requirements. For example, for regions with high breakdown voltage and high reliability requirements, the fabricated gate oxide layer can be thicker, while for regions with high operability and high flexibility requirements, such as logic circuits, the fabricated gate oxide layer can be thinner.

[0042] In this embodiment, the substrate 11 may include a first region 111 and a second region 112. The working voltage requirements of the first region 111 and the second region 112 are different. Specifically, the first region 111 can be a low-voltage region with a lower working voltage requirement, and can be used to form a thinner gate oxide layer. The second region 112 can be a high-voltage region with a higher working voltage requirement, and can be used to form a thicker gate oxide layer. It should be noted that the high and low voltage requirements referred to in this application are relative, that is, the second region 112 is higher than the first region 111, and it does not necessarily correspond to the voltage values of high voltage and low voltage in actual applications such as circuit design.

[0043] In this embodiment, the first oxide layer 12 may include a first sacrificial oxide portion 121 located on the first region 111 and a first gate oxide portion 122 located on the second region 112.

[0044] S120: Form a first gate material layer on the first oxide layer.

[0045] In this embodiment, as Figure 3 shown, the first gate material layer 13 may be directly formed on the first oxide layer 12 first, so as to jointly form a gate structure located in the second region 112 in subsequent processes. Specifically, for example, the material of the first gate material layer 13 may be polysilicon, or other gate materials such as aluminum metal.

[0046] In this embodiment, the first gate material layer 13 may include a first sacrificial gate material portion 131 located on the first region 111 and a first gate material portion 132 located on the second region 112.

[0047] In this embodiment, after the first gate material layer 13 is disposed on the first oxide layer 12, a second oxide layer 14 may be further disposed on the first gate material layer 13 to serve as a stop layer in subsequent planarization processes. The second oxide layer 14 may also include a second sacrificial oxide portion 141 located on the first region 111 and a protective oxide portion 142 located on the second region 112. In some embodiments, the second oxide layer 14 may not be provided, or a stop layer made of other materials may be provided. In this embodiment, the second oxide layer 14 may be made of the same material as the first oxide layer 12, such as silicon dioxide, so as to reduce the introduction of new materials in the process, thereby reducing the possible impact on the performance or reliability of the semiconductor structure in subsequent removal processes, and simplifying the process. Specifically, the thickness of the second oxide layer 14 may fall within the range of 180 Å to 220 Å. For example, the thickness of the second oxide layer 14 may be 200 Å, or 180 Å, 220 Å, etc.

[0048] S130: Using the first gate material portion as a mask, remove the first sacrificial gate material portion and the first sacrificial oxide portion based on a dry etching process, and form a second gate oxide portion on the surface of the first region. The thickness of the second gate oxide portion is different from the thickness of the first gate oxide portion.

[0049] In this embodiment, as Figure 4 and Figure 5As shown, a photoresist defining the first region 111 can be disposed on the second oxide layer 14, and dry etching process can be used for etching to remove the first sacrificial oxide portion 121, the first sacrificial gate material portion 131, and the second sacrificial oxide portion 141 on the first region 111, so as to expose the surface of the first region 111. Of course, in some embodiments, if the second oxide layer 14 is not provided, it can be understood that only the first sacrificial oxide portion 121 and the first sacrificial gate material portion 131 on the first region 111 are removed by dry etching. In this embodiment, through the selectivity control of the first gate material layer 13 relative to the first oxide layer 12, the remaining first gate material portion 132 except the first sacrificial gate material portion 131 can be used as a mask, which can, to a certain extent, replace the hard mask material in the related art and play a role in improving the etching accuracy.

[0050] Of course, in some embodiments, with the protective oxide portion 142 on the second region 112 retained, the first gate material portion 132 and the protective oxide portion 142 can be used together as a mask for the dry etching process. In this way, during the dry etching process, the protective oxide portion 142 can be used to protect the first gate material portion 132, and the protective oxide portion 142 can also be used as a mask in the subsequent step of growing the second gate oxide portion on the surface of the first region 111.

[0051] Next, as Figure 6 shown, with the first gate material portion 132 and the protective oxide portion 142 as masks, a second gate oxide portion 15 with a different thickness from the first oxide layer 12 is grown on the surface of the first region 111, thereby preparing a double gate oxide layer on the surface of the substrate 11. Specifically, both the second gate oxide portion 15 and the first oxide layer 12 can be silicon dioxide, and the thickness of the first oxide layer 12 can be greater than the thickness of the second gate oxide portion 15. Of course, in some possible embodiments, the thickness of the first oxide layer 12 can also be less than the thickness of the second gate oxide portion 15, and the specific thickness relationship between the first oxide layer 12 and the second gate oxide portion 15 can depend on the different voltage requirements corresponding to the first region 111 and the second region 112.

[0052] In this embodiment, the unexpected effect is that: on the first oxide layer 12 grown on the surface of the substrate 11, a first gate material layer 13 is directly formed first, and then based on a dry etching process, the first sacrificial oxide portion 121 located on the first region 111 is removed, and then a second gate oxide portion 15 with different thicknesses is formed on the surface of the first region 111. Since the dry etching process is used to remove the first sacrificial oxide portion 121, the problem of photoresist peeling caused by wet etching in the related art can be reduced, and during the dry etching process, the first gate material portion 132 of the first gate material layer 13 formed in advance and located on the second region 112 is cleverly used as a mask layer without introducing a hard mask material, which not only simplifies the process steps but also avoids the influence on the prepared double gate oxide layer caused by removing the hard mask material, thereby improving the quality of the double gate oxide layer and further ensuring the performance and yield of the semiconductor structure.

[0053] In some embodiments, after the second gate oxide portion is formed on the surface of the first region, the method for manufacturing the semiconductor structure further includes: depositing and forming a second gate material layer on the surfaces of the second gate oxide portion and the protective oxide portion; wherein, the second gate material layer includes a second gate material portion located on the first region and a second sacrificial gate material portion located on the second region; using the protective oxide portion as a planarization stop layer to perform a planarization process on the second gate material layer so that the first gate material portion is flush with the second gate material portion, the second oxide layer, the second oxide layer, the second oxide layer.

[0054] In some embodiments, as Figure 7 shown, by depositing a gate material on the surface of the structure as Figure 6 shown, a second gate material layer 16 is formed. It can be understood that the second gate material layer 16 may include a second gate material portion 161 located on the first region 111 and a second sacrificial gate material portion 162 located on the second region 112, wherein the second gate material portion 161 is located on the surface of the second gate oxide portion 15.

[0055] In some embodiments, the first gate material layer 13 and the second gate material layer 16 may use the same gate material, such as both being polysilicon, which is beneficial to the simplification of subsequent processes.

[0056] Then, a planarization process can be performed on the second gate material layer 16, such as a CMP (chemical mechanical polishing) process, to remove the portion protruding from the first gate material portion 132 to obtain a planarized gate layer. Specifically, the gate layer may include the first gate material portion 132 and the second gate material portion 161.

[0057] In some embodiments, the protective oxide portion 142 may be used as a planarization stop layer to protect the first gate material portion 132 covered by it during the planarization process.

[0058] In some embodiments, in the step of using the protective oxide portion as a planarization stop layer to perform a planarization process on the second gate material layer, it includes: based on a first chemical mechanical polishing process, grinding the second gate material layer until it is flush with the planarization stop layer; wherein, the second sacrificial gate material portion is removed; based on a second chemical mechanical polishing process, grinding the second gate material portion until it is flush with the first gate material portion; wherein, the planarization stop layer is removed.

[0059] In some embodiments, referring to Figure 7 、 Figure 8 and Figure 9 , performing a planarization process on the second gate material layer 16 may include a process of two CMP processes.

[0060] Specifically, as shown in Figure 7 and Figure 8 , first, through the first CMP process, the portion above the surface of the second oxide protective oxide portion 142 is ground and stopped on the planarization stop layer, so that the height of the second gate material layer 16 is flush with the planarization stop layer. After the first CMP process, the second sacrificial gate material portion 162 is removed, and the second gate material portion 161 may have a portion higher than the first gate material portion 132, which is located on the first region 111 and on the side of the planarization stop layer, and can be used as a buffer portion 1611 in the subsequent second CMP process. It can be understood that after the first CMP process, in addition to the buffer portion 1611, the second gate material portion 161 also has a remaining portion between the surface of the first region 111 and the buffer portion 1611.

[0061] Then, a second CMP process is performed on the planarization stop layer and the buffer portion to make the second gate material portion 161 flush with the first gate material portion 132, obtaining the structure as shown in Figure 9 . During the second CMP process, by controlling the selectivity ratio of the CMP, the buffer portion 1611 located on the first region 111 and on the side of the planarization stop layer can protect the remaining portion of the second gate material portion between the surface of the first region 111 and the buffer portion 1611, improving the planarization effect. This remaining portion of the second gate material portion can be used as a gate precursor 1612 on the first region 111 for subsequent gate fabrication.

[0062] In some embodiments, the width of the buffer portion 1611 falls within the range of 400 Å to 600 Å. Controlling the width of the buffer portion 1611 within this range results in a better planarization effect after the two CMP processes.

[0063] In some embodiments, as shown in Figure 10As shown, subsequent etching processes can be carried out to complete the fabrication of the gate at each position, such as forming the first gate structure 17 on the first region 111 and the second gate structure 18 on the second region 112. It can be understood that the thicknesses of the gate oxide layers of the first gate structure 17 and the second gate structure 18 are different, and thus they have different threshold voltages.

[0064] In some embodiments, since the first gate material portion 132 located on the second region has been formed in advance during the preparation of the dual gate oxide layer, only the first region 111 needs to be fabricated during the subsequent gate material fabrication, realizing the simplification of the process.

[0065] In some embodiments, according to the high or low working voltage requirements, the second region 112 can be a high-voltage region, for example, an input / output (I / O) region. The first region 111 can be a low-voltage region. Based on the relatively high working voltage requirements of the second region 112, the thickness of the first gate oxide portion 122 is greater than the thickness of the second gate oxide portion 15.

[0066] An embodiment of the present application provides a semiconductor structure, which is prepared by using the preparation method of the semiconductor structure described in any of the foregoing embodiments.

[0067] An embodiment of the present application provides a semiconductor device, which includes the semiconductor structure described in any of the foregoing embodiments.

[0068] It can be understood that the specific examples herein are only to help those skilled in the art better understand the embodiments of the present application, rather than limiting the scope of the present invention.

[0069] It can be understood that in various embodiments of the present application, the magnitudes of the serial numbers of the various processes do not mean the order of execution. The order of execution of the various processes should be determined by their functions and internal logics, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0070] It can be understood that the various embodiments described in the present application can be implemented alone or in combination, and the embodiments of the present application do not limit this.

[0071] Unless otherwise specified, all the technical and scientific terms used in the embodiments of the present application have the same meanings as those commonly understood by those skilled in the technical field of the present application. The terms used in the present application are only for the purpose of describing specific embodiments, and are not intended to limit the scope of the present application. The term "and / or" used in the embodiments of the present application and the appended claims includes any and all combinations of one or more of the related listed items. The singular forms "a", "the above" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0072] As described above, it is only a specific embodiment of the present application, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed in the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; The base comprises a substrate and a first oxide layer formed on the surface of the substrate; wherein the substrate comprises a first region and a second region; the first oxide layer comprises a first sacrificial oxide portion located on the first region and a first gate oxide portion located on the second region; forming a first gate material layer on the first oxide layer; wherein the first gate material layer comprises a first sacrificial gate material portion located on the first region and a first gate material portion located on the second region; Using the first gate material portion as a mask, the first sacrificial gate material portion and the first sacrificial oxide portion are removed based on a dry etching process, and a second gate oxide portion is formed on the surface of the first region; wherein the thickness of the second gate oxide portion is different from the thickness of the first gate oxide portion.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: After the step of forming a first gate material layer on the first oxide layer, the method for preparing the semiconductor structure further includes: forming a second oxide layer on the first gate material layer; wherein the second oxide layer comprises a second sacrificial oxide portion located on the first region and a protective oxide portion located on the second region; In the process of removing the first sacrificial gate material portion and the first sacrificial oxide portion based on the dry etching process, the first gate material portion and the protective oxide portion are used together as a mask, and the second sacrificial oxide portion is removed.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that: After forming a second gate oxide portion on the surface of the first region, the method for preparing the semiconductor structure further includes: Depositing a second gate material layer on the surface of the second gate oxide portion and the protective oxide portion; wherein the second gate material layer includes a second gate material portion located on the first region and a second sacrificial gate material portion located on the second region; The protective oxide portion is used as a planarization stop layer, and a planarization process is performed on the second gate material layer to make the second gate material portion flush with the first gate material portion.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that: The step of using the protective oxide portion as a planarization stop layer to perform a planarization process on the second gate material layer includes: Based on a first chemical mechanical polishing process, the second gate material layer is polished to be flush with the planarization stop layer; wherein the second sacrificial gate material portion is removed; Based on a second chemical mechanical polishing process, the second gate material portion is polished to be flush with the first gate material portion; wherein the planarization stop layer is removed.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that: After the second gate material layer is polished to be flush with the planarization stop layer based on the first chemical mechanical polishing process, a buffer portion is formed on the side of the planarization stop layer; wherein, during the second chemical mechanical polishing process, the buffer portion protects the remaining portion of the second gate material portion between the surface of the first area and the buffer portion.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that: The thickness of the first gate oxide portion is greater than the thickness of the second gate oxide portion.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that: The first region is a low-pressure region, and the second region is a high-pressure region.

8. The method for preparing a semiconductor structure according to claim 3, characterized in that: The first gate material layer and the second gate material layer have the same gate material.

9. A semiconductor structure, characterized in that: The semiconductor structure is prepared by the method for preparing a semiconductor structure as claimed in any one of claims 1 to 8.

10. A semiconductor device, characterized in that: The semiconductor device comprises the semiconductor structure according to claim 9.

Images