Manufacturing method of semiconductor structure and semiconductor structure

Abstract

The invention provides a manufacturing method of a semiconductor structure and the semiconductor structure. The method comprises the following steps: providing a substrate; an N-type buried layer is formed on the substrate, epitaxial layers are formed on the surfaces of the substrate and the N-type buried layer, and part of the N-type buried layer is located in the substrate; forming a first shallow trench isolation structure with an exposed surface in the epitaxial layer, wherein the first shallow trench isolation structure is located above the N-type buried layer; the first shallow trench isolation structure is subjected to first N-type ion implantation, a first N-type well region is formed between the lower part of the first shallow trench isolation structure and the N-type buried layer, the N-type buried layer and the first shallow trench isolation structure are respectively connected with the first N-type well region, the beta value of the PNP-type BJT tube is changed, and the controllability of the beta value of the PNP-type BJT tube is improved; moreover, the manufacturing method is suitable for various semiconductor structures, and a new photomask does not need to be added to adapt to a new semiconductor structure manufacturing method, so that zero extra photomask consumption is realized, and the manufacturing cost of the PNP type BJT is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor device preparation, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art

[0002] In semiconductor circuit applications, PNP BJT tube is a relatively common device, which is often used in amplifiers, switching circuits, signal modulation, voltage stabilization and other scenarios.

[0003] The existing PNP BJT tube is a vertical SP+(NW / NDF / SNW)+Psub&SPW structure, which has the following disadvantages: 1. The vertical PNP BJT tube is completely parasitic, and the overall structure and base area size cannot be adjusted, resulting in the solidification of the electrical parameters of the PNP BJT tube; 2. The overall vertical depth volume of the N area corresponding to the base area is large, and the current channel is long, so there are more electron-hole recombination in the base area, resulting in a small beta and a large on-resistance. Summary of the invention

[0004] The present invention provides a method for manufacturing a semiconductor structure and a semiconductor structure, which can solve the problems of solidified electrical parameters, small beta and large on-resistance of a PNP type BJT tube.

[0005] According to a first aspect of the present invention, a method for manufacturing a semiconductor structure is provided, the method comprising:

[0006] providing a substrate;

[0007] forming an N-type buried layer on the substrate, and forming an epitaxial layer on the substrate and the surface of the N-type buried layer, wherein part of the N-type buried layer is located in the substrate;

[0008] forming a first shallow trench isolation structure with an exposed surface in the epitaxial layer, wherein the first shallow trench isolation structure is located above the N-type buried layer;

[0009] A first N-type ion implantation is performed on the first shallow trench isolation structure to form a first N-type well region between the first shallow trench isolation structure and the N-type buried layer, and the N-type buried layer and the first shallow trench isolation structure are respectively connected to the first N-type well region.

[0010] Optionally, the above method further includes:

[0011] forming a plurality of second shallow trench isolation structures in the epitaxial layer, wherein a portion of the second shallow trench isolation structures is located on the N-type buried layer and surrounds the first shallow trench isolation structure;

[0012] Perform P-type ion implantation on the epitaxial layer to form a substrate lead-out terminal, a collector, and an emitter of the semiconductor structure. The collector is located between the substrate lead-out terminal and the emitter. There is the first shallow trench isolation structure between the collector and the emitter. Both the collector and the emitter are located above the N-type buried layer. There is the second shallow trench isolation structure between the substrate lead-out terminal and the collector, and the substrate lead-out terminal is located between adjacent second shallow trench isolation structures;

[0013] Perform N-type ion implantation on the epitaxial layer to form the base of the semiconductor structure. The base is located above the N-type buried layer and between the collector and the substrate lead-out terminal. There is the second shallow trench isolation structure between the base and both the collector and the substrate lead-out terminal.

[0014] Optionally, the performing P-type ion implantation on the epitaxial layer to form a substrate lead-out terminal, a collector, and an emitter of the semiconductor structure includes:

[0015] Perform a first P-type ion implantation on the epitaxial layer to form a plurality of independent P-type well regions in the epitaxial layer;

[0016] Perform a second P-type ion implantation on the plurality of P-type well regions to form P-type heavily doped regions on each of the P-type well regions to be used as the substrate lead-out terminal, the collector, and the emitter respectively. The P-type well regions under the collector and the emitter are respectively connected to the N-type buried layer.

[0017] Optionally, after performing the first P-type ion implantation on the epitaxial layer and before forming the P-type heavily doped regions, it further includes:

[0018] Perform a third P-type ion implantation on one of the plurality of P-type well regions to form a superposed P-type well region in the epitaxial layer, and the emitter is formed on the superposed P-type well region.

[0019] Optionally, the process of the first P-type ion implantation includes: 2 ion implantation processes. In the 2 implantation processes, the process parameters of the first time include:

[0020] The ions implanted for the first time are boron ions. The depth range of the boron ions is 2 μm to 2.4 μm, and the implantation dose range is 8.5e+12 KeV to 1.15e+13 KeV;

[0021] The process parameters of the second time include:

[0022] The ions implanted for the second time are boron ions. The depth range of the boron ions is 640 Å to 700 Å, and the implantation dose range is 2.55e+12 KeV to 3.45e+12 KeV.

[0023] Optionally, the N-type ion implantation of the epitaxial layer to form a base between the collector and the substrate lead-out terminal includes:

[0024] Performing a first N-type ion implantation on the epitaxial layer to form a second N-type well region in the epitaxial layer;

[0025] Performing a second N-type ion implantation on the second N-type well region to form an N-type heavily doped region as the base in the second N-type well region, and the base is located above the second N-type well region.

[0026] Optionally, the process of the first N-type ion implantation includes: 2 ion implantation processes. During the 2 implantation processes, the process parameters of the first time include:

[0027] The ions implanted for the first time are phosphorus ions, the depth range of the phosphorus ions is 2.3 μm to 2.7 μm, and the implantation dose range is 1e+13 KeV to 1.4e+13 KeV;

[0028] The process parameters of the second time include:

[0029] The ions implanted for the second time are arsenic ions, the depth range of the boron ions is 880 Å to 900 Å, and the implantation dose range is 2.2e+12 KeV to 2.8e+12 KeV.

[0030] According to the second aspect of the present invention, a semiconductor structure is provided, including:

[0031] A substrate;

[0032] An N-type buried layer, the N-type buried layer is located on the substrate, and a part of the N-type buried layer is located in the substrate;

[0033] An epitaxial layer, the epitaxial layer is located on the N-type buried layer, and the N-type buried layer is in contact with the epitaxial layer;

[0034] A first shallow trench isolation structure, the first shallow trench isolation structure is located in the epitaxial layer and exposes the surface, and the first shallow trench isolation structure is located above the N-type buried layer;

[0035] A first N-type well region, the first N-type well region is located in the epitaxial layer and under the first shallow trench isolation structure, and the first N-type well region is connected to the N-type buried layer and the first shallow trench isolation structure respectively.

[0036] Optionally, the above semiconductor structure further includes: a second shallow trench isolation structure, a substrate lead-out terminal, a collector, an emitter, and a base;

[0037] The second shallow trench isolation structure is located within the epitaxial layer and exposes a surface. A part of the second shallow trench isolation structure is located on the N-type buried layer and surrounds the first shallow trench isolation structure;

[0038] The collector is located between the substrate lead-out terminal and the emitter. There is the first shallow trench isolation structure between the collector and the emitter. Both the collector and the emitter are located above the N-type buried layer. There is the second shallow trench isolation structure between the substrate lead-out terminal and the collector. And the substrate lead-out terminal is located between adjacent second shallow trench isolation structures. The base is located above the N-type buried layer and between the collector and the substrate lead-out terminal. There are second shallow trench isolation structures between the base and both the collector and the substrate lead-out terminal.

[0039] Optionally, the above semiconductor structure further includes: a first P-type well region, a second P-type well region, a third P-type well region, a first N-type well region, and a second N-type well region;

[0040] The first P-type well region is connected to the emitter, the second P-type well region is connected to the collector, the third P-type well region is connected to the substrate lead-out terminal, the first N-type well region surrounds the first P-type well region, the second P-type well region surrounds the first N-type well region, the second N-type well region surrounds the second P-type well region, and the third P-type well region surrounds the second N-type well region.

[0041] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0042] In the manufacturing method of the semiconductor structure provided by the technical solution of the present invention, by forming the first shallow trench isolation structure that exposes the surface within the epitaxial layer, and then forming the first N-type well region located between the first shallow trench isolation structure and the N-type buried layer based on the first shallow trench isolation structure. Thus, the width of the first shallow trench isolation structure can be changed by adjusting the layout design, and further the depth of the first shallow trench isolation structure can be affected. Then, when ion implantation is performed on the first shallow trench isolation structure, the depth of the first N-type well region formed between the first shallow trench isolation structure and the N-type buried layer is controllable. Therefore, the width of the first shallow trench isolation structure can be increased through layout design to reduce the length of the current channel of the first N-type well region. And the first N-type well region acts as the base in the PNP type BJT transistor. Thus, the on-resistance of the PNP type BJT transistor can be reduced.

[0043] Furthermore, the above process is not affected by other ion implantation processes, which is equivalent to directly adjusting the ion concentration of the first N-type well region to change the beta value of the PNP type BJT transistor, and the controllability of the beta value of the PNP type BJT transistor can be increased.

[0044] In addition, since only the width of the first shallow trench isolation structure needs to be changed to change the length of the current channel of the first N-type well region or the ion concentration at the emitter end, various semiconductor structure manufacturing methods can be applied without adding a new photomask to adapt to the new semiconductor structure manufacturing method. Therefore, zero additional photomask consumption can be achieved, and the manufacturing cost of the PNP-type BJT can be reduced. Description of the Drawings

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0046] Figures 1 to 5 are schematic diagrams of the steps in the manufacturing method of the semiconductor structure in the embodiments of the present invention.

[0047] Reference Numerals:

[0048] 1 - Substrate;

[0049] 2 - N-type buried layer;

[0050] 3 - Epitaxial layer;

[0051] 4 - First shallow trench isolation structure;

[0052] 5 - Second shallow trench isolation structure;

[0053] 6 - First N-type well region;

[0054] 7 - P-type well region;

[0055] 8 - Second N-type well region;

[0056] 9 - Substrate lead-out terminal;

[0057] 10 - Collector;

[0058] 11 - Emitter;

[0059] 12 - Base. Detailed Embodiments

[0060] The existing method for manufacturing a PNP type BJT tube may specifically include the following steps: providing a substrate; growing an epitaxial layer on the substrate; forming a shallow trench isolation structure in the epitaxial layer; after forming the shallow trench isolation structure, performing a first P-type ion implantation on the epitaxial layer to form two independent P-type well regions in the epitaxial layer; performing a second P-type ion implantation on the two P-type well regions respectively to form a P-type heavily doped region on each P-type well region to serve as a collector. A first N-type ion implantation is performed on the epitaxial layer to form an N-type well region in the epitaxial layer, wherein the N-type well region is located between two independent P-type well regions and a shallow trench isolation structure; a second N-type ion implantation is performed on the N-type well region to form an N-type heavily doped region in the N-type well region as a base; after the second N-type ion implantation is performed on the N-type well region; after the N-type heavily doped region is formed in the N-type well region as a base, a second P-type ion implantation is performed on the N-type well region to form a P-type heavily doped region above the N-type well region as an emitter, the base and the N-type well region therebelow are located between the emitter and the N-type well region therebelow and the collector and the P-type well region therebelow, and a shallow trench isolation structure is provided between the base and the N-type well region therebelow and the collector and the P-type well region therebelow.

[0061] The PNP type BJT tube obtained by the above-mentioned manufacturing method has the following disadvantages as described in the background technology: 1. The vertically arranged PNP type BJT tube is completely parasitic, and the overall structure and the size of the base region cannot be adjusted, resulting in the solidification of the electrical parameters of the PNP type BJT tube; 2. The overall vertical depth volume of the N region corresponding to the base region is large, and the current channel is long, so there are more electron-hole recombination in the base region, resulting in a small beta and a large on-resistance.

[0062] In order to solve the above technical problems, the technical solution of the present invention provides a method for manufacturing a semiconductor structure, by making the depth of the first N-type well region formed below the first shallow trench isolation structure and between the N-type buried layer controllable, thereby, the width of the first shallow trench isolation structure can be increased through layout design to reduce the length of the current channel of the first N-type well region, thereby reducing the on-resistance of the PNP type BJT tube, and the ion concentration of the first N-type well region can be directly adjusted to change the beta value of the PNP type BJT tube, thereby increasing the controllability of the beta value of the PNP type BJT tube, and solving the problems of solidified electrical parameters, small beta and large on-resistance of the PNP type BJT tube.

[0063] To make the above objects, features, and advantages of the present invention more apparent and understandable, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0064] The terms "first", "second", "third", "fourth", etc. (if any) in the specification, claims, and drawings of the present invention are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices. In addition, directional terms such as above, below, up, down, upward, downward, left, right, etc. are used relative to the exemplary embodiments as shown in the figures, with the upward or upper direction towards the top of the corresponding figure and the downward or lower direction towards the bottom of the corresponding figure.

[0065] Figures 1 to 4 are schematic diagrams of the steps in the method for fabricating a semiconductor structure in an embodiment of the present invention.

[0066] Please refer to Figure 1 , and provide a substrate 1.

[0067] In this embodiment, the substrate 1 can be a silicon substrate.

[0068] In other embodiments, the substrate may include at least one of the following materials: Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors. Or the substrate may further include silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), or germanium-on-insulator (GeOI), etc.

[0069] Please continue to refer to Figure 1 , form an N-type buried layer 2 on the substrate 1, and form an epitaxial layer 3 on the surfaces of the substrate 1 and the N-type buried layer 2, with a part of the N-type buried layer 2 located within the substrate 1.

[0070] Specifically, the N-type buried layer 2 may include at least one of the following materials: P, As, Sb.

[0071] In this embodiment, the epitaxial layer 3 may include at least one of the following materials: Si, Ge, gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), or other compound semiconductors. Alternatively, the epitaxial layer 3 may further include silicon germanium (SiGe), aluminum gallium nitride (AlGaN), or other gold-containing semiconductor materials.

[0072] Please refer to Figure 2 , a first shallow trench isolation structure 4 with an exposed surface is formed in the epitaxial layer 3, and the first shallow trench isolation structure 4 is located above the N-type buried layer 2.

[0073] Further, please refer to Figure 3 , a first N-type ion implantation is performed on the first shallow trench isolation structure 4 to form a first N-type well region 6 between the first shallow trench isolation structure 4 and the N-type buried layer 2, and the N-type buried layer 2 and the first shallow trench isolation structure 4 are respectively connected to the first N-type well region 6.

[0074] In this embodiment, the process of the first N-type ion implantation may include two ion implantation processes.

[0075] Specifically, the process parameters of the first time may include: the ions implanted for the first time may be phosphorus ions, the depth range of the phosphorus ions is 2.3 μm to 2.7 μm, and the implantation dose range is 1e+13 KeV to 1.4e+13 KeV.

[0076] Further, the process parameters of the second time may include: the ions implanted for the second time are arsenic ions, the depth range of the boron ions is 880 Å to 900 Å, and the implantation dose range is 2.2e+12 KeV to 2.8e+12 KeV.

[0077] In one embodiment, the depth range of the first N-type ions can be divided into multiple first depth sub-ranges, and the implanted dose range can be divided into multiple first dose sub-ranges; the implantation process of the first N-type ions can consist of multiple ion implantation processes, and the number of implantation processes can be the same as the number of ranges of the first depth sub-ranges or the first dose sub-ranges. The first depth sub-ranges and the first dose sub-ranges of each first N-type ion implantation process are in a one-to-one correspondence in sequence. For example, the depth range (2.3 μm to 2.7 μm) of the phosphorus ions implanted for the first time can be divided into a first depth sub-range 1 [2.3 μm, 2.4 μm) and a first depth sub-range 2 [2.4 μm, 2.7 μm], and the implanted dose range can be divided into a first dose sub-range 1 [1e+13 KeV, D1 KeV) and a first dose sub-range 2 [D1 KeV, 1.4e+13 KeV], where 8.5e+12 < D1 < 1.15e+13. The implantation process of the phosphorus ions can be divided into 2 phosphorus ion implantation processes: 1. The first implantation process, the first sub-depth range of the phosphorus ions is [2.3 μm, 2.4 μm), and the first dose sub-range implanted is [1e+13 KeV, D1 KeV); 2. The second implantation process, the first depth sub-range of the phosphorus ions is [2.4 μm, 2.7 μm], and the first dose sub-range implanted is [D1 KeV, 1.4e+13 KeV].

[0078] In this embodiment, by forming a first shallow trench isolation structure exposing the surface in the epitaxial layer, and then forming a first N-type well region located between the first shallow trench isolation structure and the N-type buried layer based on the first shallow trench isolation structure. Thus, by adjusting the layout design, the width of the first shallow trench isolation structure can be changed, and further, the depth of the first shallow trench isolation structure can be affected, so that the depth of the first N-type well region formed between the first shallow trench isolation structure and the N-type buried layer by ion implanting the first shallow trench isolation structure is controllable. Therefore, the width of the first shallow trench isolation structure can be increased through the layout design to reduce the length of the current channel of the first N-type well region, and the first N-type well region acts as the base in the PNP-type BJT transistor, so that the on-resistance of the PNP-type BJT transistor can be reduced.

[0079] Furthermore, the above process is not affected by other ion implantation processes, which is equivalent to directly adjusting the ion concentration of the first N-type well region to change the beta value of the PNP-type BJT transistor, and the controllability of the beta value of the PNP-type BJT transistor can be increased.

[0080] In addition, since only the width of the first shallow trench isolation structure needs to be changed to change the length of the current channel of the first N-type well region or the ion concentration at the emitter end, various semiconductor structure manufacturing methods can be applied without adding a new photomask to adapt to the new semiconductor structure manufacturing method. Therefore, zero additional photomask consumption can be achieved, and the manufacturing cost of the PNP-type BJT can be reduced.

[0081] In one embodiment, while forming the first shallow trench isolation structure 4, a plurality of second shallow trench isolation structures 5 are formed in the epitaxial layer 3. Some of the second shallow trench isolation structures 5 are located on the N-type buried layer 2 and surround the first shallow trench isolation structure 4.

[0082] In this embodiment, continue to refer to Figure 2 , the second shallow trench isolation structure 5 may include multiple layers of the second shallow trench isolation structure 5. Between each of the second shallow trench isolation structures 5 and between the second shallow trench isolation structure 5 and the first shallow trench isolation structure 4, they are arranged at intervals. The multiple layers of the second shallow trench isolation structure 5 are stacked along the direction from the first shallow trench isolation structure 4 to the second shallow trench isolation structure 5 to surround the first shallow trench isolation structure 4.

[0083] In one embodiment, after forming the first shallow trench isolation structure 4 and a plurality of second shallow trench isolation structures 5, the epitaxial layer 3 may be subjected to P-type ion implantation to form the substrate lead-out terminal 9, the collector 10, and the emitter 11 of the semiconductor structure.

[0084] Among them, the collector 10 is located between the substrate lead-out terminal 9 and the emitter 11. There is the first shallow trench isolation structure 4 between the collector 10 and the emitter 11. Both the collector 10 and the emitter 11 are located above the N-type buried layer 2. There is the second shallow trench isolation structure 5 between the substrate lead-out terminal 9 and the collector 10, and the substrate lead-out terminal 9 is located between adjacent second shallow trench isolation structures 5.

[0085] In this embodiment, subjecting the epitaxial layer 3 to P-type ion implantation to form the substrate lead-out terminal 9, the collector 10, and the emitter 11 may include: performing a first P-type ion implantation on the epitaxial layer 3 to form a plurality of independent P-type well regions 7 in the epitaxial layer 3; performing a second P-type ion implantation on the plurality of P-type well regions 7 to form P-type heavily doped regions on each of the P-type well regions 7 to respectively serve as the substrate lead-out terminal 9, the collector 10, and the emitter 11. The P-type well regions 7 below the collector 10 and the emitter 11 are respectively connected to the N-type buried layer 2.

[0086] In this embodiment, the first P-type ion implantation is a light doping ion implantation, and the second P-type ion implantation is a heavy doping ion implantation.

[0087] Please refer to Figure 4 and Figure 5 ,Figure 5 is Figure 4 The top view of Figure 5 . The collector 10 is located between the substrate lead-out terminal 9 and the emitter 11. There is a first shallow trench isolation structure 4 between the collector 10 and the P-well region 7 thereunder and the emitter 11 and the P-well region 7 thereunder. The first shallow trench isolation structure 4 is located above the first N-well region 6. The collector 10 and the P-well region 7 thereunder and the emitter 11 and the P-well region 7 thereunder are respectively connected to the N-type buried layer 2. There is a second shallow trench isolation structure 5 between the substrate lead-out terminal 9 and the P-well region 7 thereunder and the collector 10 and the P-well region 7 thereunder.

[0088] Since the emitter 11 of the existing PNP type BJT is formed by performing a second P-type ion implantation on the N-well region to form a P-type heavily doped region above the N-well region as the emitter 11, the depth of the P-type heavily doped region in the prior art is relatively small. In this embodiment, the emitter 11 and the P-well region 7 thereunder are connected to the N-type buried layer 2, and the depth of the P-well region 7 is greater than the depth of the P-type heavily doped region formed above the N-well region in the prior art. Thereby, the depth of the emitter 11 end is increased and the electron concentration at the emitter 11 end is increased, thus increasing the beta value of the PNP type BJT.

[0089] In this embodiment, the process of the first P-type ion implantation may include: 2 ion implantation processes.

[0090] Specifically, in the 2 implantation processes, the process parameters of the first time may include: the ions implanted for the first time are boron ions, the depth range of the boron ions is 2 μm to 2.4 μm, and the implantation dose range is 8.5e+12 KeV to 1.15e+13 KeV.

[0091] Furthermore, the process parameters of the second time may include: the ions implanted for the second time are boron ions, the depth range of the boron ions is 640 Å to 700 Å, and the implantation dose range is 2.55e+12 KeV to 3.45e+12 KeV.

[0092] It should be noted that the ion type of the first P-type ion and the ion type of the second P-type ion may be the same or different. The ion implantation process of the first P-type ion and the ion type and ion implantation process of the second P-type ion may be the same or different.

[0093] In one embodiment, the depth range of the first P-type ions can be divided into multiple second depth sub-ranges, and the implanted dose range can be divided into multiple second dose sub-ranges; the implantation process of the first P-type ions can be composed of multiple ion implantation processes, and the number of implantation processes can be the same as the number of ranges of the second depth sub-ranges or the second dose sub-ranges. The second depth sub-ranges and the second dose sub-ranges of each first P-type ion implantation process are in a one-to-one correspondence in sequence. For example, the depth range of the boron ions implanted for the first time can be divided into a second depth sub-range 1 [2 μm, 2.2 μm) and a second depth sub-range 2 [2.2 μm, 2.4 μm], and the implanted dose range can be divided into a second dose sub-range 1 [8.5e+12 KeV, D1 KeV) and a second dose sub-range 2 [D1 KeV, 1.15e+13 KeV], where 8.5e+12 < D1 < 1.15e+13. The implantation process of the boron ions can be divided into 2 boron ion implantation processes: 1. The first implantation process, the second depth sub-range of the boron ions is [2 μm, 2.2 μm), and the second dose sub-range implanted is [8.5e+12 KeV, D1 KeV); 2. The second implantation process, the second depth sub-range of the boron ions is [2.2 μm, 2.4 μm], and the second dose sub-range implanted is [D1 KeV, 1.15e+13 KeV].

[0094] Please continue to refer to Figure 4 and Figure 5 In one embodiment, after performing P-type ion implantation on the epitaxial layer to form the substrate lead-out terminal 9, the collector 10, and the emitter 11 of the semiconductor structure, N-type ion implantation can be performed on the epitaxial layer to form the base 12 of the semiconductor structure. The base 12 is located above the N-type buried layer 2 and between the collector 10 and the substrate lead-out terminal 9. There are second shallow trench isolation structures 5 between the base 12 and both the collector 10 and the substrate lead-out terminal 9.

[0095] In one embodiment, performing N-type ion implantation on the epitaxial layer 3 to form the base 12 located between the collector 10 and the substrate lead-out terminal 9 may include: performing a first N-type ion implantation on the epitaxial layer 3 to form a second N-type well region 8 in the epitaxial layer 3; performing a second N-type ion implantation on the second N-type well region 8 to form an N-type heavily doped region as the base 12, and the base 12 is located above the second N-type well region 8.

[0096] In this embodiment, the first N-type ion implantation is a lightly doped ion implantation, and the second N-type ion implantation is a heavily doped ion implantation.

[0097] It should be noted that the ion types of the first N-type ions and the second N-type ions may be the same or different. The ion implantation process of the first N-type ions and the ion types and ion implantation processes of the second N-type ions may be the same or different.

[0098] Specifically, the first N-type ions implanted into the first N-type well region 6 and the second N-type ions implanted into the second N-type well region 8 are both nano-scale implantation materials, which can achieve higher integration and lower power consumption.

[0099] In the prior art, there is only an epitaxial layer 3 between the collector 10 and the substrate 1, which is equivalent to the collector 10 being directly connected to the substrate lead-out terminal 9, and the substrate lead-out terminal 9 is generally grounded, that is, the substrate lead-out terminal 9 is connected to 0 potential.

[0100] In this embodiment, the collector 10 is separated from the substrate lead-out terminal 9 through the base 12, and the collector 10 that can only be connected to 0 potential is stripped. Furthermore, the collector 10 can be connected to other potentials different from 0 potential, expanding the application scenarios of the PNP-type BJT transistor obtained by the semiconductor manufacturing method provided in this embodiment.

[0101] In one embodiment, the P-type well region 7 connected to the emitter 11 is the first P-type well region, the P-type well region 7 connected to the collector 10 is the second P-type well region, and the P-type well region 7 connected to the substrate lead-out terminal 9 is the third P-type well region.

[0102] Among them, the collector 10 surrounds the emitter 11, the base 12 surrounds the emitter 11, and the substrate lead-out terminal 9 surrounds the base 12. Then the first N-type well region 6 surrounds the first P-type well region, the second P-type well region surrounds the first N-type well region 6, the second N-type well region 8 surrounds the second P-type well region, and the third P-type well region surrounds the second N-type well region 8.

[0103] In one embodiment, after the first P-type ion implantation of the epitaxial layer 3 and before the formation of the P-type heavily doped region, a third P-type ion implantation can also be performed on one of the multiple P-type well regions 7 to form a superimposed P-type well region 7 in the epitaxial layer 3, and the emitter 11 is formed on the superimposed P-type well region. In this way, the number of holes at the emitter 11 end can be increased through the superimposed P-type well region 7, thereby reducing the on-resistance of the PNP-type BJT transistor and increasing the beta value of the PNP-type BJT transistor.

[0104] Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by using the manufacturing method of the above semiconductor structure. Please continue to refer to Figure 4, a semiconductor structure may include: a substrate 1; an N-type buried layer 2, the N-type buried layer 2 is located on the substrate 1, and a part of the N-type buried layer 2 is located within the substrate 1; an epitaxial layer 3, the epitaxial layer 3 is located on the N-type buried layer 2, and the N-type buried layer 2 and the epitaxial layer 3 are in contact; a first shallow trench isolation structure 4, the first shallow trench isolation structure 4 is located within the epitaxial layer 3 and exposes the surface, and the first shallow trench isolation structure 4 is located above the N-type buried layer 2; a first N-type well region 6, the first N-type well region 6 is located within the epitaxial layer 3 and is below the first shallow trench isolation structure 4, and the first N-type well region 6 is connected to the N-type buried layer 2 and the first shallow trench isolation structure 4 respectively.

[0105] Specifically, the substrate may include at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors. Or the substrate may also include silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanide on insulator (S-SiGeOI), silicon germanide on insulator (SiGeOI), or germanium on insulator (GeOI), etc.

[0106] Among them, the N-type buried layer 2 may include at least one of the following materials: P, As, Sb.

[0107] In this embodiment, the epitaxial layer 3 may include at least one of the following materials: Si, Ge, gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), or other compound semiconductors. Or the epitaxial layer 3 may also include silicon germanium (SiGe), aluminum gallium nitride (AlGaN), or other gold-containing semiconductor materials.

[0108] In this embodiment, the process of the first N-type ion implantation may include: 2 ion implantation processes.

[0109] Specifically, during the 2 implantation processes, the process parameters of the first time may include: the ions implanted for the first time are phosphorus ions, the depth range of the phosphorus ions is 2 μm to 2.4 μm, and the implantation dose range is 8.5e+12 KeV to 1.15e+13 KeV.

[0110] Furthermore, the process parameters of the second time may include: the ions implanted for the second time are arsenic ions, the depth range of the boron ions is 800 Å to 820 Å, and the implantation dose range is 1.7e+12 KeV to 2.3e+12 KeV.

[0111] The semiconductor structure provided by the embodiment of the present invention forms a first shallow trench isolation structure with an exposed surface in the epitaxial layer, and then forms a first N-type well region between the first shallow trench isolation structure and the N-type buried layer based on the first shallow trench isolation structure. Thus, by adjusting the layout design, the width of the first shallow trench isolation structure can be changed, and further, the depth of the first shallow trench isolation structure can be affected, so that when ion implantation is performed on the first shallow trench isolation structure, the depth of the first N-type well region formed between the first shallow trench isolation structure and the N-type buried layer is controllable. Therefore, the width of the first shallow trench isolation structure can be increased through layout design to reduce the length of the current channel of the first N-type well region, and the first N-type well region acts as the base in the PNP-type BJT transistor, so that the on-resistance of the PNP-type BJT transistor can be reduced.

[0112] Furthermore, the above process is not affected by other ion implantation processes, which is equivalent to directly adjusting the ion concentration of the first N-type well region to change the beta value of the PNP-type BJT transistor, and the controllability of the beta value of the PNP-type BJT transistor can be increased.

[0113] In addition, since only the width of the first shallow trench isolation structure needs to be changed, the length of the current channel of the first N-type well region or the ion concentration at the emitter end can be changed, so that it can be applied to the manufacturing methods of various semiconductor structures without adding a new photomask to adapt to the manufacturing methods of new semiconductor structures. Therefore, zero additional photomask consumption can be achieved, and the manufacturing cost of the PNP-type BJT transistor can be reduced.

[0114] In one embodiment, please continue to refer to Figure 4 , the above semiconductor structure may further include a second shallow trench isolation structure 5, a substrate lead-out terminal 9, a collector 10, an emitter 11, and a base 12. The second shallow trench isolation structure 5 is located in the epitaxial layer 3 and has an exposed surface. Part of the second shallow trench isolation structure 5 is located on the N-type buried layer 2 and surrounds the first shallow trench isolation structure 4. The collector 10 is located between the substrate lead-out terminal 9 and the emitter 11. There is a first shallow trench isolation structure 4 between the collector 10 and the emitter 11. Both the collector 10 and the emitter 11 are located above the N-type buried layer 2. There is a second shallow trench isolation structure 5 between the substrate lead-out terminal 9 and the collector 10, and the substrate lead-out terminal 9 is located between adjacent second shallow trench isolation structures 5. The base 12 is located above the N-type buried layer 2 and is located between the collector 10 and the substrate lead-out terminal 9. There is a second shallow trench isolation structure 5 between the base 12 and both the collector 10 and the substrate lead-out terminal 9.

[0115] In this embodiment, the process of the first P-type ion implantation may include: two ion implantation processes.

[0116] Specifically, during the two implantation processes, the process parameters of the first implantation may include: the ions implanted for the first time are boron ions, the depth range of the boron ions is from 2 μm to 2.4 μm, and the implantation dose range is from 8.5e+12 KeV to 1.15e+13 KeV.

[0117] Furthermore, the process parameters of the second implantation may include: the ions implanted for the second time are boron ions, the depth range of the boron ions is from 700 Å to 720 Å, and the implantation dose range is from 2.55e+12 KeV to 3.45e+12 KeV.

[0118] It should be noted that the ion types of the first P-type ions and the second P-type ions may be the same or different. The ion implantation processes of the first P-type ions and the ion types and ion implantation processes of the second P-type ions may be the same or different.

[0119] In one embodiment, please continue to refer to Figure 4 , the above semiconductor structure may further include a plurality of independent P-type well regions 7 and P-type heavily doped regions. The P-type heavily doped regions serve as the substrate lead-out terminal 9, the collector 10, and the emitter 11 respectively. The P-type well regions 7 below the collector 10 and the emitter 11 are respectively connected to the N-type buried layer 2, and the plurality of independent P-type well regions 7 are located in the epitaxial layer 3.

[0120] In one embodiment, the above semiconductor structure may further include a first P-type well region, a second P-type well region, a third P-type well region, a first N-type well region 6, and a second N-type well region 8; the first P-type well region is connected to the emitter 11, the second P-type well region is connected to the collector 10, and the third P-type well region is connected to the substrate lead-out terminal 9. Please refer to Figure 5 , the collector 10 surrounds the emitter 11, the base 12 surrounds the emitter 11, and the substrate lead-out terminal 9 surrounds the base 12; then the first N-type well region 6 surrounds the first P-type well region, the second P-type well region surrounds the first N-type well region 6, the second N-type well region 8 surrounds the second P-type well region, and the third P-type well region surrounds the second N-type well region 8.

[0121] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The method comprises: providing a substrate; forming an N-type buried layer on the substrate, and forming an epitaxial layer on the substrate and the surface of the N-type buried layer, wherein part of the N-type buried layer is located in the substrate; forming a first shallow trench isolation structure with an exposed surface in the epitaxial layer, wherein the first shallow trench isolation structure is located above the N-type buried layer; A first N-type ion implantation is performed on the first shallow trench isolation structure to form a first N-type well region between the first shallow trench isolation structure and the N-type buried layer, and the N-type buried layer and the first shallow trench isolation structure are respectively connected to the first N-type well region.

2. The method according to claim 1, characterized in that Also includes: forming a plurality of second shallow trench isolation structures in the epitaxial layer, wherein a portion of the second shallow trench isolation structures is located on the N-type buried layer and surrounds the first shallow trench isolation structure; Performing P-type ion implantation on the epitaxial layer to form a substrate lead-out terminal, a collector and an emitter of a semiconductor structure, wherein the collector is located between the substrate lead-out terminal and the emitter, the first shallow trench isolation structure is provided between the collector and the emitter, the collector and the emitter are both located above the N-type buried layer, the second shallow trench isolation structure is provided between the substrate lead-out terminal and the collector, and the substrate lead-out terminal is located between adjacent second shallow trench isolation structures; N-type ion implantation is performed on the epitaxial layer to form a base of the semiconductor structure, wherein the base is located above the N-type buried layer and between the collector and the substrate lead-out terminal, and the second shallow trench isolation structure is provided between the base, the collector and the substrate lead-out terminal.

3. The method according to claim 2, characterized in that The step of implanting P-type ions into the epitaxial layer to form a substrate lead-out terminal, a collector and an emitter of a semiconductor structure comprises: Performing a first P-type ion implantation on the epitaxial layer to form a plurality of mutually independent P-type well regions in the epitaxial layer; A second P-type ion implantation is performed on the multiple P-type well regions to form a P-type heavily doped region on each of the P-type well regions to serve as a substrate lead-out terminal, a collector and an emitter, respectively. The P-type well regions under the collector and the emitter are respectively connected to the N-type buried layer.

4. The method according to claim 3, characterized in that After performing the first P-type ion implantation on the epitaxial layer and before forming the P-type heavily doped region, the method further includes: A third P-type ion implantation is performed on one of the multiple P-type well regions to form an overlapping P-type well region in the epitaxial layer, and the emitter is formed on the overlapping P-type well region.

5. The method according to claim 3, characterized in that: The process of the first P-type ion implantation includes: two ion implantation processes, and the process parameters of the first implantation process include: The ions implanted for the first time are boron ions, the depth of the boron ions ranges from 2 μm to 2.4 μm, and the implantation dose ranges from 8.5e+12 KeV to 1.15e+13 KeV; The second process parameters include: The ions implanted for the second time are boron ions, the depth of the boron ions ranges from 640A to 700A, and the implantation dose ranges from 2.55e+12KeV to 3.45e+12KeV.

6. The method according to claim 2, characterized in that The step of performing N-type ion implantation on the epitaxial layer to form a base located between the collector and the substrate lead-out terminal comprises: Performing a first N-type ion implantation on the epitaxial layer to form a second N-type well region in the epitaxial layer; A second N-type ion implantation is performed on the second N-type well region to form an N-type heavily doped region in the second N-type well region to serve as a base, wherein the base is located above the second N-type well region.

7. The method according to claim 1, characterized in that The process of the first N-type ion implantation includes: two ion implantation processes, and the process parameters of the first implantation process include: The ions implanted for the first time are phosphorus ions, the depth of the phosphorus ions ranges from 2.3 μm to 2.7 μm, and the implantation dose ranges from 1e+13 KeV to 1.4e+13 KeV; The second process parameters include: The ions implanted for the second time are arsenic ions, the depth of the boron ions ranges from 880A to 900A, and the implantation dose ranges from 2.2e+12KeV to 2.8e+12KeV.

8. A semiconductor structure, characterized in that: include: substrate; An N-type buried layer, wherein the N-type buried layer is located on the substrate, and a portion of the N-type buried layer is located within the substrate; An epitaxial layer, wherein the epitaxial layer is located on the N-type buried layer, and the N-type buried layer is in contact with the epitaxial layer; a first shallow trench isolation structure, wherein the first shallow trench isolation structure is located in the epitaxial layer and has an exposed surface, and the first shallow trench isolation structure is located above the N-type buried layer; A first N-type well region, wherein the first N-type well region is located in the epitaxial layer and below the first shallow trench isolation structure, and the first N-type well region is connected to the N-type buried layer and the first shallow trench isolation structure respectively.

9. The structure according to claim 8, characterized in that Also includes: A second shallow trench isolation structure, a substrate lead terminal, a collector, an emitter, and a base; The second shallow trench isolation structure is located in the epitaxial layer and has an exposed surface, and a portion of the second shallow trench isolation structure is located on the N-type buried layer and surrounds the first shallow trench isolation structure; The collector is located between the substrate lead-out terminal and the emitter, and the first shallow trench isolation structure is provided between the collector and the emitter. The collector and the emitter are both located above the N-type buried layer, and the second shallow trench isolation structure is provided between the substrate lead-out terminal and the collector, and the substrate lead-out terminal is located between adjacent second shallow trench isolation structures. The base is located above the N-type buried layer and between the collector and the substrate lead-out terminal, and the second shallow trench isolation structure is provided between the base, the collector, and the substrate lead-out terminal.

10. The structure according to claim 9, characterized in that Also includes: a first P-type well region, a second P-type well region, a third P-type well region, a first N-type well region, and a second N-type well region; The first P-type well region is connected to the emitter, the second P-type well region is connected to the collector, the third P-type well region is connected to the substrate lead-out terminal, the first N-type well region surrounds the first P-type well region, the second P-type well region surrounds the first N-type well region, the second N-type well region surrounds the second P-type well region, and the third P-type well region surrounds the second N-type well region.

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