Formation method of semiconductor structure

Abstract

A method for forming a semiconductor structure comprises the steps that a substrate is provided, the substrate comprises a device region and a dummy device region adjacent to the device region, a laminated gate structure is formed at the top of the substrate of the device region and the dummy device region, and the laminated gate structure comprises a first gate structure and a second gate structure located above the first gate structure; forming an interlayer dielectric layer covering the side wall of the laminated gate structure on the substrate of the device region and the pseudo device region; removing the second gate structure; after the second gate structure is removed, the first gate structure in the device region is removed, an opening is formed in the device region, and the opening is defined by the opposite side walls of the adjacent interlayer dielectric layers and the top surface of the substrate; and forming a device gate structure in the opening, wherein the top of the device gate structure is flush with the top of the first gate structure in the dummy device region. The top surface flatness of the device gate structure and the thickness uniformity of the device gate structure are improved, and the performance of the semiconductor structure is further improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a method for forming a semiconductor structure. Background Art

[0002] With the gradual development of semiconductor process technology, semiconductor process nodes continue to decrease following Moore's law. In order to adapt to the reduction of process nodes, it is necessary to continuously shorten the channel length of MOSFET field effect transistors. However, as the channel length of the device is shortened, the distance between the source and drain of the device is also shortened, so the gate's control ability over the channel becomes worse, making the subthreshold leakage phenomenon, namely the so-called short-channel effects (SCE), more likely to occur.

[0003] Therefore, in order to better meet the requirements of proportional reduction of device size, non-planar MOS transistors have emerged, such as gate-all-around (GAA) transistors or fin field effect transistors (FinFET). In a FinFET, the gate can control the ultra-thin body (fin) from at least two sides, and has a stronger gate control ability over the channel compared to planar MOSFET devices, and can well suppress short-channel effects; and compared with other devices, FinFET has better compatibility with existing integrated circuit manufacturing. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which is beneficial to further improving the performance of the semiconductor structure.

[0005] To solve the above problems, embodiments of the present invention provide a method for forming a semiconductor structure, including: providing a substrate, the substrate includes a device region and a dummy device region adjacent thereto, a stacked gate structure is formed on the top of the substrate in the device region and the dummy device region, the stacked gate structure includes a first gate structure and a second gate structure located above the first gate structure; forming an interlayer dielectric layer covering the sidewalls of the stacked gate structure on the substrate in the device region and the dummy device region; removing the second gate structure; after removing the second gate structure, removing the first gate structure in the device region to form an opening in the device region, the opening is surrounded by the opposite sidewalls of the adjacent interlayer dielectric layers and the top surface of the substrate; forming a device gate structure in the opening, and the top of the device gate structure is flush with the top of the first gate structure in the dummy device region.

[0006] Optionally, the steps of forming a stacked gate structure include: forming a first gate material layer on the top of the substrate in the device region and the dummy device region; forming a second gate material layer on the top of the first gate material layer; forming a patterned hard mask layer on the top of the second gate material layer; using the hard mask layer as a mask, patterning the second gate material layer and the first gate material layer in sequence, the remaining second gate material layer serving as the second gate structure, the remaining first gate material layer serving as the first gate structure, and the first gate structure and the second gate structure constituting the stacked gate structure; removing the hard mask layer.

[0007] Optionally, the step of forming a first gate material layer on the top of the substrate in the device region and the dummy device region includes: forming a first gate film on the top of the substrate in the device region and the dummy device region; planarizing a partial thickness of the first gate film until the thickness of the remaining first gate film reaches a target thickness, and using the remaining first gate film as the first gate material layer.

[0008] Optionally, the process of patterning the second gate material layer and the first gate material layer in sequence includes a dry etching process.

[0009] Optionally, in the step of providing the substrate, a dielectric layer is formed on the top of the substrate in the device region and the dummy device region, and the dielectric layer is located between the first gate structure and the second gate structure; in the step of forming the stacked gate structure, the dielectric layer is used as an etch stop layer; after the step of removing the second gate structure and before removing the first gate structure in the device region, it further includes: removing the dielectric layer.

[0010] Optionally, the material of the dielectric layer includes one or both of silicon oxide and aluminum oxide.

[0011] Optionally, the process of removing the dielectric layer includes a wet etching process.

[0012] Optionally, before forming the interlayer dielectric layer, the method for forming the semiconductor structure further includes: forming a sidewall layer on the sidewalls of the stacked gate structure; after forming the sidewall layer, forming source / drain doping layers in the substrate on both sides of the stacked gate structure; in the step of forming the interlayer dielectric layer, the interlayer dielectric layer also covers the top of the source / drain doping layers.

[0013] Optionally, the steps of forming the sidewall layer include: forming a sidewall material layer on the top and sidewalls of the stacked gate structure and on the top of the substrate exposed by the stacked gate structure; removing the sidewall material layer on the top of the stacked gate structure and on the top of the substrate, and using the remaining sidewall material layer located on the sidewalls of the stacked gate structure as the sidewall layer.

[0014] Optionally, the step of forming the interlayer dielectric layer includes: forming an interlayer dielectric material layer covering the stacked gate structure on top of the substrates in the device region and the dummy device region; using the top of the second gate structure as a stop position, planarizing the interlayer dielectric material layer above the top of the second gate structure, and using the remaining interlayer dielectric material layer as the interlayer dielectric layer.

[0015] Optionally, the process of removing the second gate structure includes a wet etching process.

[0016] Optionally, after removing the second gate structure, the step of removing the first gate structure in the device region includes: forming a mask layer covering the first gate structure and the interlayer dielectric layer in the dummy device region, with the mask layer exposing the first gate structure in the device region; using the mask layer as a mask, removing the first gate structure in the device region; and removing the mask layer.

[0017] Optionally, the process of removing the first gate structure in the device region includes a dry etching process.

[0018] Optionally, the step of forming a device gate structure in the opening includes: forming a gate dielectric layer on the top and sidewalls of the interlayer dielectric layer in the dummy device region, on the top of the first gate structure, on the top of the interlayer dielectric layer in the device region, and on the bottom and sidewalls of the opening; forming a gate electrode layer covering the gate dielectric layer on top of the substrates in the device region and the dummy device region, with the gate electrode layer also filling the remaining space in the opening; using the top of the first gate structure as a stop position, planarizing the interlayer dielectric layer, the gate dielectric layer, and the gate electrode layer above the top of the first gate structure, and using the remaining gate dielectric layer and gate electrode layer in the opening as the device gate structure.

[0019] Optionally, the process of planarizing the interlayer dielectric layer, the gate dielectric layer, and the gate electrode layer above the top of the first gate structure includes a chemical mechanical polishing process.

[0020] Optionally, the material of the gate dielectric layer includes one or more of HfO 2 , ZrO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al 2 O 3 , SiO 2 , and La 2 O 3 ; the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0021] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0022] An embodiment of the present invention provides a method for forming a semiconductor structure. The substrate includes a device region and a dummy device region adjacent thereto. A stacked gate structure is formed on the top of the substrate in the device region and the dummy device region. The stacked gate structure includes a first gate structure and a second gate structure located above the first gate structure. An interlayer dielectric layer covering the sidewalls of the stacked gate structure is formed on the substrate in the device region and the dummy device region. The second gate structure is removed, and the first gate structure in the device region is removed. An opening surrounded by the opposing sidewalls of the adjacent interlayer dielectric layers and the top surface of the substrate is formed in the device region. Correspondingly, during the process of forming a device gate structure in the opening, the top of the first gate structure in the dummy device region can be used as a stop position, so that the top surface of the device gate structure in the device region is flush with the top of the first gate structure in the dummy device region, thereby improving the flatness of the top surface of the device gate structure and the thickness uniformity of the device gate structure, and further improving the performance of the semiconductor structure. Description of the Drawings

[0023] Figures 1 to 4 is a schematic structural diagram corresponding to a method for forming a semiconductor structure;

[0024] Figures 5 to 20 is a schematic structural diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention. Detailed Embodiments

[0025] Currently, the performance of semiconductor structures needs to be improved. The reason for the need to improve the performance is analyzed in combination with a schematic structural diagram corresponding to a method for forming a semiconductor structure.

[0026] Figures 1 to 4 is a schematic structural diagram corresponding to a method for forming a semiconductor structure.

[0027] Reference Figure 1 , a substrate 15 is provided. The substrate 15 includes a substrate 10 and fins 12 protruding from the substrate 10. A gate structure 13 spanning the fins 12 and covering part of the top and part of the sidewalls of the fins 12 is formed on the top of the substrate 10. A spacer layer 16 is formed on the sidewalls of the gate structure 13. An interlayer dielectric layer 15 covering the sidewalls of the spacer layer 16 is formed on the substrate 10 exposed by the gate structure 13.

[0028] Reference Figure 2 , the gate structure 13 is removed, and a gate opening 20 is formed in the interlayer dielectric layer 15.

[0029] Reference Figure 3 , a device gate material layer 26 is formed in the gate opening 20 and on the top of the interlayer dielectric layer 15.

[0030] Reference Figure 4, the device gate material layer 26 is planarized until the height of the remaining device gate material layer 26 reaches the target height, and the remaining device gate material layer 26 is used as the device gate layer 22.

[0031] It has been found through research that during the process of planarizing the device gate material layer 26, when the chemical mechanical polishing process is used to planarize the device gate material layer 26, since the top of none of the film layers can be used as the stop position for the planarization process, as a result, the flatness of the top surface of the device gate layer 22 is relatively low. Correspondingly, the height uniformity of the device gate layer 22 cannot be improved.

[0032] To solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate includes a device region and a dummy device region adjacent thereto, a stacked gate structure is formed on the top of the substrate in the device region and the dummy device region, the stacked gate structure includes a first gate structure and a second gate structure located above the first gate structure; forming an interlayer dielectric layer covering the sidewalls of the stacked gate structure on the substrate in the device region and the dummy device region; removing the second gate structure; after removing the second gate structure, removing the first gate structure in the device region, and forming an opening surrounded by the opposing sidewalls of the adjacent interlayer dielectric layers and the top surface of the substrate in the device region; forming a device gate structure in the opening, and the top of the device gate structure is flush with the top of the first gate structure in the dummy device region.

[0033] An embodiment of the present invention provides a method for forming a semiconductor structure. The substrate includes a device region and a dummy device region adjacent thereto. A stacked gate structure is formed on the top of the substrate in the device region and the dummy device region. The stacked gate structure includes a first gate structure and a second gate structure located above the first gate structure. An interlayer dielectric layer covering the sidewalls of the stacked gate structure is formed on the substrate in the device region and the dummy device region. The second gate structure is removed. The first gate structure in the device region is removed. An opening surrounded by the opposing sidewalls of the adjacent interlayer dielectric layers and the top surface of the substrate is formed in the device region. Correspondingly, during the process of forming the device gate structure in the opening, the top of the first gate structure in the dummy device region can be used as the stop position, so that the top of the device gate structure in the device region is flush with the top of the first gate structure in the dummy device region, thereby improving the flatness of the top surface of the device gate structure and the thickness uniformity of the device gate structure, and further improving the performance of the semiconductor structure.

[0034] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention is provided in conjunction with the accompanying drawings.

[0035] Figures 5 to 20 It is a schematic structural diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

[0036] refer to Figures 5 to 11 ,in, Figure 5 It is a top view. Figure 6 yes Figure 5 Cross-sectional view along AA direction, Figure 9 It is a top view. Figure 10 yes Figure 9 A cross-sectional view along the BB direction provides a substrate 105, which includes a device area 100A and a dummy device area 100B adjacent thereto, and a stacked gate structure 122 is formed on the top of the substrate 105 of the device area 100A and the dummy device area 100B. The stacked gate structure 122 includes a first gate structure 120 and a second gate structure 121 located above the first gate structure 120.

[0037] The substrate 105 provides a process platform for subsequent semiconductor structure formation processes.

[0038] In this embodiment, the base 105 includes a substrate 100 and a plurality of fins 102 separated on the substrate 100.

[0039] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrates or germanium on insulator substrates.

[0040] The fin 102 is used to provide a channel when the device is working.

[0041] In this embodiment, the material of the fin 102 is the same as that of the substrate 100 , that is, the material of the fin 102 is silicon.

[0042] In this embodiment, the substrate 105 includes a device region 100A and a dummy device region 100B adjacent thereto.

[0043] Specifically, the device area 100A is a device working area of ​​the semiconductor structure, and the dummy device area 100B (dummy area) is a non-working area of ​​the semiconductor structure.

[0044] In this embodiment, the method for forming a semiconductor structure further includes: after forming the fin 102 , forming an isolation layer 106 on the substrate 100 where the fin 102 is exposed, wherein the isolation layer 106 covers a portion of the sidewall of the fin 102 , and the top of the isolation layer 106 is lower than the top of the fin 102 .

[0045] The isolation layer 106 is used to isolate adjacent devices and can be made of silicon oxide, silicon nitride or silicon oxynitride.

[0046] As an example, the material of the isolation layer 106 is silicon nitride.

[0047] It should be noted that the stacked gate structure 122 provides a process basis for the subsequent formation of the sidewall layer and the interlayer dielectric layer, occupies a spatial position in advance for the subsequent formation of the device gate structure. At the same time, during the subsequent process of forming the device gate structure in the opening, the top of the first gate structure 120 located in the pseudo-device region 100B can serve as a stop position, making the device gate structure in the device region 100A flush with the top of the first gate structure 120 in the pseudo-device region 100B. That is to say, in the step of forming the first gate structure 120, by controlling the thickness of the first gate structure 120, the height of the subsequently formed device gate structure can also be controlled, thereby improving the controllability of the height of the device gate structure.

[0048] It should also be noted that during the subsequent process of forming the interlayer dielectric layer, the top of the second gate structure 121 can be used as a stop position for planarization treatment, improving the flatness of the top surface of the interlayer dielectric layer.

[0049] In this embodiment, the stacked gate structure 122 is a pseudo-gate structure.

[0050] Combined with Figures 5 to 11 , the steps of forming the stacked gate structure 122 will be described in detail.

[0051] Referring to Figures 5 to 7 , a first gate material layer 107 is formed on the top of the substrate 105 in the device region 100A and the pseudo-device region 100B.

[0052] Specifically, the first gate material layer 107 is used as the material layer for forming the first gate structure 120. At the same time, by forming the first gate material layer 107, in the subsequent step of forming the first gate structure 120, the thickness of the remaining first gate material layer 107 can be controlled, so that the thickness of the first gate structure 120 reaches the target thickness.

[0053] In this embodiment, the step of forming the first gate material layer 107 on the top of the substrate 105 in the device region 100A and the pseudo-device region 100B includes: forming a first gate film 101 on the top of the substrate 105 in the device region 100A and the pseudo-device region 100B; performing planarization treatment on a part of the thickness of the first gate film 101 until the thickness of the remaining first gate film 101 reaches the target thickness, and using the remaining first gate film 101 as the first gate material layer 107.

[0054] The first gate film 101 is used as the material layer for forming the first gate material layer 107.

[0055] It should be noted that since the distribution density of the fin portion 102 is relatively uniform, during the planarization process of the first gate film 101 with a partial thickness, the distribution density of the fin portion 102 has a relatively small impact on the planarization process. Correspondingly, the top surface flatness of the first gate material layer 107 is improved. At the same time, by planarizing the first gate film 101 with a partial thickness until the remaining thickness of the first gate film 101 reaches the target thickness, it means that the thickness of the first gate structure 120 is controlled by controlling the thickness of the first gate material layer 107, which is beneficial to controlling the height of the device gate structure formed subsequently through the first gate structure 120, thereby improving the controllability of the height of the device gate structure.

[0056] In this embodiment, the process of forming the first gate film 101 includes one or both of chemical vapor deposition process and atomic layer deposition process.

[0057] As an example, the material of the first gate material layer 107 includes polysilicon.

[0058] Reference Figure 8 , a second gate material layer 110 is formed on the top of the first gate material layer 107.

[0059] Specifically, the second gate material layer 110 is used as the material layer for forming the second gate structure 121. At the same time, by forming the second gate material layer 110, during the subsequent formation of the interlayer dielectric layer, the top of the second gate structure 121 can be used as the stop position for the planarization process, improving the top surface flatness of the interlayer dielectric layer.

[0060] It should be noted that during the formation of the interlayer dielectric layer, the top of the second gate structure 121 can be used as the stop position for the planarization process. Compared with the scheme of using the top of a single-layer gate structure as the stop position for the planarization process, the top of the second gate structure 121 only serves as the stop position once during the planarization process, resulting in a higher top surface flatness of the interlayer dielectric layer.

[0061] In this embodiment, the process of forming the second gate material layer 110 includes one or both of chemical vapor deposition process and atomic layer deposition process.

[0062] As an example, the material of the second gate material layer 110 includes polysilicon.

[0063] Reference Figures 9 to 10 , a patterned hard mask layer 113 is formed on the top of the second gate material layer 110.

[0064] It should be noted that the hard mask layer 113 is used as an etching mask for subsequently forming the first gate structure 120 and the second gate structure 121.

[0065] In this embodiment, the material of the hard mask layer 113 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0066] Reference Figure 11 , using the hard mask layer 113 as a mask, the second gate material layer 110 and the first gate material layer 107 are patterned in sequence. The remaining second gate material layer 110 serves as the second gate structure 121, and the remaining first gate material layer 107 serves as the first gate structure 120. The first gate structure 120 and the second gate structure 121 constitute a stacked gate structure 122.

[0067] It should be noted that by patterning the second gate material layer 110 and the first gate material layer 107 in sequence, the sidewall topography of the first gate structure 120 and the second gate structure 121 can be controlled. At the same time, the probability of over-etching during the formation of the first gate structure 120 and the second gate structure 121 is also reduced, and the probability of damaging the fin 102 and the substrate 105 is decreased.

[0068] It should also be noted that during the subsequent process of forming the device gate structure in the opening, the top of the first gate structure 120 located in the pseudo-device region 100B can serve as a stop position, making the device gate structure in the device region 100A flush with the top of the first gate structure 120 in the pseudo-device region 100B. Thereby, the top surface flatness of the device gate structure and the thickness uniformity of the device gate structure are improved, and further the performance of the semiconductor structure is enhanced.

[0069] As an example, the process of patterning the second gate material layer 110 and the first gate material layer 107 in sequence includes a dry etching process.

[0070] Specifically, the dry etching process is an anisotropic dry etching process. The anisotropic dry etching process has the characteristic of anisotropic etching, and its longitudinal etching rate is much greater than the lateral etching rate. By using the dry etching process to pattern the second gate material layer 110 and the first gate material layer 107, it is beneficial to improve the sidewall topography quality of the first gate structure 120 and the second gate structure 121, and reduce the process difficulty of depositing the sidewall layer on the sidewalls of the stacked gate structure 122 in the subsequent process.

[0071] It should be noted that after forming the stacked gate structure 122 and before forming the sidewall layer in the subsequent process, the method for forming the semiconductor structure further includes: removing the hard mask layer 113.

[0072] Removing the hard mask layer 113 provides a process basis for the subsequent formation of the sidewall layer and the interlayer dielectric layer.

[0073] In this embodiment, the process of removing the hard mask layer 113 includes a wet etching process.

[0074] As an example, in the step of providing the substrate 105, a dielectric layer 111 is formed on the top of the substrate 105 in the device region 100A and the dummy device region 100B, and the dielectric layer 111 is located between the first gate structure 120 and the second gate structure 121.

[0075] Specifically, the dielectric layer 111 is used to isolate the first gate structure 120 and the second gate structure 121. At the same time, in the step of forming the stacked gate structure 122, after forming the first gate material layer 107, the dielectric layer 111 is formed on the top of the first gate material layer 107, and the second gate material layer 110 is formed on the top of the dielectric layer 111. Correspondingly, in the process of patterning the second gate material layer 110 and the first gate material layer 107 in sequence, the dielectric layer 111 located on the top of the first gate material layer 107 is used as an etch stop layer, reducing the probability of over-etching the first gate material layer 107 and making the thickness uniformity of the second gate structure 121.

[0076] As an example, in the step of forming the stacked gate structure 122, the dielectric layer 111 is used as an etch stop layer, reducing the probability of over-etching the first gate material layer 107.

[0077] It should be noted that in the process of patterning the second gate material layer 110 and the first gate material layer 107 in sequence, it also includes patterning the dielectric layer 111 exposed on both sides of the second gate structure 121, so as to expose the top surface of the first gate material layer 107, which is beneficial to patterning the first gate material layer 107 to form the first gate structure 120.

[0078] In this embodiment, the material of the dielectric layer 111 includes one or both of silicon oxide and aluminum oxide.

[0079] Both silicon oxide and aluminum oxide are common materials for the dielectric layer 111, which have the characteristics of low process cost. At the same time, there is a high etch selectivity between silicon oxide and aluminum oxide and the materials selected for the second gate structure 121 and the first gate structure 120, reducing the process difficulty of forming the stacked gate structure 122.

[0080] Reference Figure 12 , before forming the interlayer dielectric layer subsequently, the method for forming the semiconductor structure further includes: forming a spacer layer 126 on the sidewalls of the stacked gate structure 122; after forming the spacer layer 126, forming source / drain doping layers 190 in the substrate 105 on both sides of the stacked gate structure 122.

[0081] The sidewall layer 126 is used to protect the sidewalls of the stacked gate structure 122 and also to define the formation positions of subsequent source / drain doping layers 190.

[0082] The sidewall layer 126 can be a single-layer structure or a stacked structure, and the material of the sidewall layer 126 can be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride.

[0083] In this embodiment, the sidewall layer 126 is a single-layer structure, and the material of the sidewall layer 126 is silicon nitride.

[0084] In this embodiment, the steps of forming the sidewall layer 126 include: forming a sidewall material layer on the top and sidewalls of the stacked gate structure 122 and on the top of the substrate 105 exposed by the stacked gate structure 122; removing the sidewall material layer on the top of the stacked gate structure 122 and on the top of the substrate 105, and the remaining sidewall material layer located on the sidewalls of the stacked gate structure 122 serves as the sidewall layer 126.

[0085] As an example, the process of forming the sidewall material layer includes an atomic layer deposition process.

[0086] The source / drain doping region is used as the source region or drain region of the transistor.

[0087] In this embodiment, the source / drain doping layer 190 is formed by an in-situ self-doping process.

[0088] When forming an NMOS transistor, the source / drain doping layer 190 includes a stress layer doped with N-type ions, that is, the first type of ions is N-type ions.

[0089] Specifically, the material of the stress layer is Si or SiC, and the stress layer provides a tensile stress effect on the channel region of the NMOS transistor, thereby facilitating the improvement of the carrier mobility of the NMOS transistor. Among them, the N-type ions are P ions, As ions, or Sb ions.

[0090] When forming a PMOS transistor, the source / drain doping layer 190 includes a stress layer doped with P-type ions, that is, the second type of ions is P-type ions.

[0091] The material of the stress layer is Si or SiGe, and the stress layer provides a compressive stress effect on the channel region of the PMOS transistor, thereby facilitating the improvement of the carrier mobility of the PMOS transistor. Among them, the P-type ions are B ions, Ga ions, or In ions.

[0092] Reference Figures 13 to 14 , an interlayer dielectric layer 129 covering the sidewalls of the stacked gate structure 122 is formed on the substrate 105 in the device region 100A and the dummy device region 100B.

[0093] The interlayer dielectric layer 129 is used for electrically isolating adjacent devices.

[0094] Among them, the material of the interlayer dielectric layer 129 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the interlayer dielectric layer 129 is silicon oxide.

[0095] In this embodiment, the steps of forming the interlayer dielectric layer 129 include: forming an interlayer dielectric material layer 128 covering the stacked gate structure 122 on the top of the substrate 105 in the device region 100A and the dummy device region 100B; using the top of the second gate structure 121 as a stop position, planarizing the interlayer dielectric material layer 128 above the top of the second gate structure 121, and using the remaining interlayer dielectric material layer 128 as the interlayer dielectric layer 129.

[0096] Specifically, the interlayer dielectric layer 129 is formed by sequentially performing a deposition process and a planarization process (e.g., a chemical mechanical polishing process).

[0097] It should be noted that since the interlayer dielectric material layer 128 above the top of the second gate structure 121 is planarized, the top of the interlayer dielectric layer 129 is flush with the top of the stacked gate structure 122.

[0098] As an example, in the steps of forming the interlayer dielectric layer 129, the interlayer dielectric layer 129 also covers the top of the source / drain doping layer 190.

[0099] Specifically, the interlayer dielectric layer 129 covers the top of the source / drain doping layer 190. During the subsequent process of removing the second gate structure 121, the probability of damaging the source / drain doping layer 190 by the process of removing the second gate structure 121 can be reduced, thereby improving the electrical connection performance between the source / drain doping layer 190 and the subsequent formed interconnect structure (e.g., source / drain plug).

[0100] Refer to Figure 15 , remove the second gate structure 121.

[0101] Specifically, removing the second gate structure 121 provides a spatial position for the subsequent formation of the device gate structure.

[0102] In this embodiment, the process of removing the second gate structure 121 includes a wet etching process.

[0103] Specifically, the wet etching process is an isotropic etching process, and its lateral etching rate is close to the longitudinal etching rate. By using the wet etching process to remove the second gate structure 121, the second gate structure 121 can be removed completely.

[0104] As an example, the etching solution used in the wet etching process is TMAH (tetramethylammonium hydroxide).

[0105] It should be noted that during the process of removing the second gate structure 121, the dielectric layer 111 located on top of the first gate structure 120 plays a protective role for the first gate structure 120, reducing the probability of damage to the first gate structure 120 caused by the process of removing the second gate structure 121.

[0106] Reference Figure 16 , after the step of removing the second gate structure 121, before subsequently removing the first gate structure 120 in the device region 100A, it further includes: removing the dielectric layer 111.

[0107] It should be noted that by removing the dielectric layer 111, the first gate structure 120 is exposed, which is beneficial for providing a spatial position for forming the device gate structure after subsequently removing the first gate structure 120.

[0108] In this embodiment, the process of removing the dielectric layer 111 includes a wet etching process.

[0109] Specifically, the wet etching process is an isotropic etching process, and its lateral etching rate is close to the longitudinal etching rate. By using the wet etching process to remove the dielectric layer 111, the dielectric layer 111 can be removed completely.

[0110] As an example, the etching solution used in the wet etching process is NH 4 OH (ammonium hydroxide) solution.

[0111] Reference Figures 17 to 18 , after removing the second gate structure 121, the first gate structure 120 in the device region 100A is removed, and an opening 180 is formed in the device region 100A. The opening 180 is surrounded by the opposite sidewalls of the adjacent interlayer dielectric layer 129 and the top surface of the substrate 105.

[0112] Specifically, the opening 180 provides a spatial position for subsequently forming the device gate structure.

[0113] In this embodiment, the step of removing the first gate structure 120 in the device region 100A includes: forming a mask layer 132 covering the first gate structure 120 and the interlayer dielectric layer 129 in the pseudo-device region 100B, and the mask layer 132 exposes the first gate structure 120 in the device region 100A; using the mask layer 132 as a mask to remove the first gate structure 120 in the device region 100A; removing the mask layer 132.

[0114] Specifically, the mask layer 132 is used to shield the first gate structure 120 in the pseudo-device region 100B that is not desired to be etched away. At the same time, it is also used as an etching mask for removing the first gate structure 120 in the device region 100A.

[0115] In this embodiment, the mask layer 132 includes an organic material layer (not shown in the figure), an anti-reflection coating (not shown in the figure) located on the organic material layer, and a photoresist layer (not shown in the figure) located on the anti-reflection coating.

[0116] The material of the organic material layer includes organic materials. In this embodiment, the material of the organic material layer is spin-on carbon (SOC).

[0117] In other embodiments, the material of the organic material layer can also be other organic materials, such as one or more of ODL (organic dielectric layer, organic dielectric layer 111) material, DUO (Deep UV Light Absorbing Oxide, deep ultraviolet light absorbing oxide layer) material, and APF (Advanced Patterning Film, advanced patterning film) material.

[0118] The material of the anti-reflection coating includes BARC (bottom anti-reflective coating) material. As an example, the BARC material is Si-ARC (silicon-containing anti-reflective coating) material.

[0119] In this embodiment, the process of removing the first gate structure 120 in the device region 100A includes a dry etching process.

[0120] Specifically, the dry etching process is an anisotropic dry etching process. The anisotropic dry etching process has the characteristics of anisotropic etching, and its longitudinal etching rate is much greater than the lateral etching rate. By using the dry etching process to remove the first gate structure 120 in the device region 100A, the probability of the first gate structure 120 remaining on the top of the substrate 105 is reduced, and the performance of the semiconductor structure is improved after the subsequent formation of the device gate structure.

[0121] It should be noted that after removing the first gate structure 120 in the device region 100A, the method for forming the semiconductor structure further includes: removing the mask layer 132.

[0122] Removing the mask layer 132 provides a spatial position for the subsequent formation of the device gate structure.

[0123] Reference Figures 19 to 20, a device gate structure 160 is formed in the opening 180, and the top of the device gate structure 160 is flush with the top of the first gate structure 120 in the dummy device region 100B.

[0124] Specifically, the device gate structure 160 is used to control the opening and closing of the channel in the device region 100A.

[0125] In this embodiment, the step of forming the device gate structure 160 in the opening 180 includes: as Figure 19 shown, a gate dielectric layer (not shown in the figure) is formed on the top and sidewalls of the interlayer dielectric layer 129 in the dummy device region 100B, the top of the first gate structure 120, the top of the interlayer dielectric layer 129 in the device region 100A, and the bottom and sidewalls of the opening 180; continue as Figure 19 shown, a gate electrode layer covering the gate dielectric layer is formed on the top of the substrate 105 in the device region 100A and the dummy device region 100B, and the gate electrode layer also fills the remaining space in the opening 180; as Figure 20 shown, taking the top of the first gate structure 120 as the stop position, the interlayer dielectric layer 129, the gate dielectric layer, and the gate electrode layer above the top of the first gate structure 120 are planarized, and the remaining gate dielectric layer and gate electrode layer in the opening 180 are used as the device gate structure 160.

[0126] Specifically, the top of the first gate structure 120 located in the dummy device region 100B can be used as the stop position, so that the device gate structure 160 in the device region 100A is flush with the top of the first gate structure 120 in the dummy device region 100B, thereby improving the flatness of the top surface of the device gate structure 160 and the thickness uniformity of the device gate structure 160, and further improving the performance of the semiconductor structure.

[0127] In this embodiment, the process of planarizing the interlayer dielectric layer 129, the gate dielectric layer, and the gate electrode layer above the top of the first gate structure 120 includes a chemical mechanical polishing process.

[0128] In this embodiment, the material of the gate dielectric layer includes HfO 2 , ZrO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al 2 O 3 , SiO 2 and La 2 O 3 or more of them.

[0129] Specifically, the gate dielectric layer includes a gate oxide layer conformally covering the top portion, partial sidewalls, and partial bottom of the fin 102, and a high-k gate dielectric layer conformally covering the gate oxide layer. Among them, the material of the high-k gate dielectric layer is a high-k dielectric material, and the high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide.

[0130] The gate electrode layer is used for electrical connection with an external structure. In this embodiment, the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. Specifically, the gate electrode layer may include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer may also include only the work function layer.

[0131] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, comprising: providing a substrate, the substrate including a device region and a dummy device region adjacent thereto, a stacked gate structure being formed on top of the substrates of the device region and the dummy device region, the stacked gate structure including a first gate structure and a second gate structure located above the first gate structure; forming an interlayer dielectric layer on the substrates of the device region and the dummy device region to cover sidewalls of the stacked gate structure; removing the second gate structure; after removing the second gate structure, removing the first gate structure in the device region, and forming an opening in the device region, the opening being surrounded by opposing sidewalls of the adjacent interlayer dielectric layer and the top surface of the substrate; forming a device gate structure in the opening, the top of the device gate structure being flush with the top of the first gate structure in the dummy device region.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, the step of forming the stacked gate structure includes: forming a first gate material layer on top of the substrates of the device region and the dummy device region; forming a second gate material layer on top of the first gate material layer; forming a patterned hard mask layer on top of the second gate material layer; using the hard mask layer as a mask, sequentially patterning the second gate material layer and the first gate material layer, the remaining second gate material layer serving as the second gate structure, the remaining first gate material layer serving as the first gate structure, the first gate structure and the second gate structure constituting the stacked gate structure; removing the hard mask layer.

3. The method for forming a semiconductor structure according to claim 2, characterized in that, the step of forming the first gate material layer on top of the substrates of the device region and the dummy device region includes: forming a first gate film on top of the substrates of the device region and the dummy device region; planarizing a partial thickness of the first gate film until the remaining first gate film reaches a target thickness, and using the remaining first gate film as the first gate material layer.

4. The method for forming a semiconductor structure according to claim 2, characterized in that, the process of sequentially patterning the second gate material layer and the first gate material layer includes a dry etching process.

5. The method for forming a semiconductor structure according to claim 1, characterized in that, in the step of providing the substrate, a dielectric layer is formed on top of the substrates of the device region and the dummy device region, the dielectric layer being located between the first gate structure and the second gate structure; in the step of forming the stacked gate structure, the dielectric layer is used as an etch stop layer; after the step of removing the second gate structure and before removing the first gate structure in the device region, further comprising: removing the dielectric layer.

6. The method for forming a semiconductor structure according to claim 5, characterized in that, the material of the dielectric layer includes one or both of silicon oxide and aluminum oxide.

7. The method for forming a semiconductor structure according to claim 5, characterized in that, the process of removing the dielectric layer includes a wet etching process.

8. The method for forming a semiconductor structure as described in claim 1, wherein, before forming the interlayer dielectric layer, the method for forming the semiconductor structure further includes: forming a spacer layer on the sidewalls of the stacked gate structure; after forming the spacer layer, forming source / drain doping layers in the substrates on both sides of the stacked gate structure; in the step of forming the interlayer dielectric layer, the interlayer dielectric layer also covers the top of the source / drain doping layers.

9. The method for forming a semiconductor structure as described in claim 8, wherein, the step of forming the spacer layer includes: forming a spacer material layer on the top and sidewalls of the stacked gate structure, and on the top of the substrate exposed by the stacked gate structure; removing the spacer material layer on the top of the stacked gate structure and on the top of the substrate, and the remaining spacer material layer located on the sidewalls of the stacked gate structure serves as the spacer layer.

10. The method for forming a semiconductor structure as described in claim 1, wherein, the step of forming the interlayer dielectric layer includes: forming an interlayer dielectric material layer covering the stacked gate structure on the top of the substrates in the device region and the dummy device region; using the top of the second gate structure as a stop position, performing planarization on the interlayer dielectric material layer above the top of the second gate structure, and using the remaining interlayer dielectric material layer as the interlayer dielectric layer.

11. The method for forming a semiconductor structure as described in claim 1, wherein, the process of removing the second gate structure includes a wet etching process.

12. The method for forming a semiconductor structure as described in claim 1, wherein, after removing the second gate structure, the step of removing the first gate structure in the device region includes: forming a mask layer covering the first gate structure and the interlayer dielectric layer in the dummy device region, and the mask layer exposes the first gate structure in the device region; using the mask layer as a mask, removing the first gate structure in the device region; removing the mask layer.

13. The method for forming a semiconductor structure as described in claim 1 or 12, wherein, the process of removing the first gate structure in the device region includes a dry etching process.

14. The method for forming a semiconductor structure as described in claim 1, wherein, the step of forming a device gate structure in the opening includes: forming a gate dielectric layer on the top and sidewalls of the interlayer dielectric layer in the dummy device region, on the top of the first gate structure, on the top of the interlayer dielectric layer in the device region, and on the bottom and sidewalls of the opening; forming a gate electrode layer covering the gate dielectric layer on the top of the substrates in the device region and the dummy device region, and the gate electrode layer also fills the remaining space in the opening; using the top of the first gate structure as a stop position, performing planarization on the interlayer dielectric layer, the gate dielectric layer, and the gate electrode layer above the top of the first gate structure, and using the remaining gate dielectric layer and gate electrode layer in the opening as the device gate structure.

15. The method for forming a semiconductor structure as described in claim 14, wherein, The process of planarizing the interlayer dielectric layer, gate dielectric layer, and gate electrode layer above the top of the first gate structure includes a chemical mechanical polishing process.

16. The method for forming a semiconductor structure according to claim 14, wherein, The material of the gate dielectric layer includes HfO 2 , ZrO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al 2 O 3 , SiO 2 and La 2 O 3 or more of them; the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

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