Contact Hole Forming Method and Image Sensor

Abstract

The present invention discloses a method for forming contact holes and an image sensor. The method includes: forming a contact hole etching stop layer on the device structures in the logic region and the pixel region of the image sensor; filling a thickened interlayer dielectric layer on the contact hole etching stop layer, and the increased thickness is equal to the thickness of the protective layer; forming a first hard mask layer and a second hard mask layer on the interlayer dielectric layer; etching contact holes in the logic region using the first hard mask layer as a mask, and only forming a mask pattern on the pixel region under the protection of the second hard mask layer; forming a sacrificial layer for protecting the contact holes in the logic region; etching the contact holes in the pixel region until above the protective layer; continuing to etch the protective layer below the contact holes in the pixel region while etching the interlayer dielectric layer with the same thickness; removing the sacrificial layer in the logic region and filling all the contact holes. The contact holes in the logic region and the pixel region of the present invention can be etched separately, and over-etching of the logic region substrate caused by the height difference can be avoided, which is beneficial to maintaining electrical stability.

Description

Technical Field

[0001] The present invention relates to the field of manufacturing semiconductor devices, and particularly to a method for forming contact holes and an image sensor. Background Art

[0002] As Figure 1 shown, a CIS device (CMOS IMAGE SENSOR) includes a logic area and a pixel area. In the traditional process, before forming contact holes, in order to reduce the contact resistance, a layer of metal silicide 105 is formed in the logic area; at the same time, a self-aligned barrier oxide (abbreviated as SAB OX) is formed in the pixel area in advance as a protective layer 104 to prevent the pixel area from contacting metal, which may cause metal contamination, resulting in an increase in electrical offset, dark current, and white dot defects of the image sensor, and a decrease in the imaging quality of the image sensor.

[0003] Since the pixel area has an additional layer of SAB OX compared to the logic area, it is likely to cause over-etching damage to the substrate 101 and difficult filling of the interlayer dielectric layer 102 (Inter Layer Dielectric, abbreviated as ILD) during the etching process of the contact hole 106. Specifically: 1) The active area (abbreviated as AA) plane and the top of the gate in the logic area only have a contact hole etch stop layer 103 (abbreviated as CESL), while the AA plane and the top of the gate in the pixel area are both a stack of SAB OX and CESL. Therefore, a stack difference is formed between the logic area and the pixel area. During the contact hole etching process, it is easy to cause over-etching of the logic area substrate when etching the SAB OX (as shown at the position of the dotted circle in Figure 1 ), which may easily lead to abnormal metal silicide and unstable resistance value. 2) Because of the stack difference between the logic area and the pixel area, a thicker CESL is required to eliminate the etching load effect. However, the thickened CESL will increase the aspect ratio of the via filling in the interlayer dielectric layer ILD, thereby causing a high aspect ratio process (abbreviated as HARP), resulting in holes 107 and gaps in the filling, and a decrease in the isolation performance. Summary of the Invention

[0004] The main purpose of the present invention is to provide a method for forming contact holes and an image sensor, which can prevent over-etching damage to the device and stabilize the contact resistance when forming contact holes.

[0005] The technical solution adopted by the present invention is as follows:

[0006] Provided is a method for forming contact holes, including the following steps:

[0007] On the device structures of the logic region and the pixel region of a pre-fabricated image sensor, a contact hole etch stop layer is formed, where the device structure of the pixel region has one more protective layer than that of the logic region;

[0008] A thickened interlayer dielectric layer is filled on the contact hole etch stop layer, and the increased thickness is equal to the thickness of the protective layer; and a first hard mask layer is formed on the interlayer dielectric layer, and a second hard mask layer is also formed above the first hard mask layer in the pixel region;

[0009] Using the first hard mask layer as a mask, contact holes are etched in the logic region, and in the pixel region, only a mask pattern is formed thereon under the protection of the second hard mask layer;

[0010] An organic carbon layer is spin-coated on both the logic region and the pixel region to form a sacrificial layer for protecting the contact holes in the logic region;

[0011] The organic carbon layer is etched to expose the mask pattern in the pixel region, and contact hole etching in the pixel region is carried out until above the protective layer;

[0012] Continue to etch the protective layer below the contact holes in the pixel region, and at the same time, etch and thin the interlayer dielectric layer by the same thickness;

[0013] Remove the sacrificial layer in the logic region and fill all the contact holes.

[0014] Following the above technical solution, the formed contact hole etch stop layer is a thinned contact hole etch stop layer, and its thickness is less than the thickness of the protective layer.

[0015] Following the above technical solution, the thickness of the first hard mask layer is the same as the thickness of the contact hole etch stop layer.

[0016] Following the above technical solution, the specific process of forming the contact holes in the logic region is as follows: A photoresist layer and an anti-reflection coating are formed on the first hard mask layer in the logic region and the second hard mask layer in the pixel region; Through exposure and development, a contact hole mask pattern for the logic region and the pixel region is formed; A first etching gas is selected to etch the first hard mask layer in the logic region; A second etching gas is selected to etch the second hard mask layer in the pixel region, and at the same time, a part of the interlayer dielectric layer in the logic region is etched; A third etching gas is selected to continue to etch downward in the logic region to form contact holes, and at the same time, the first hard mask layer in the pixel region is etched to form a contact hole mask pattern in the pixel region; The photoresist layer and the anti-reflection coating are removed.

[0017] Following the above technical solution, when etching the organic carbon layer, no photomask is required, and it is directly etched through an etching gas, and the etching gas is oxygen or an oxygen-containing gas.

[0018] Continuing with the above technical solution, the formation process of the second hard mask layer in the pixel region is specifically as follows: form the second hard mask layer on the first hard mask layer; form a photoresist layer on the second hard mask layer; perform exposure and development on the photoresist layer through a photomask to form a mask layer, where the photomask is the same photomask used for preparing the protection layer; etch the second hard mask layer using the mask layer as a mask; remove the photoresist.

[0019] Continuing with the above technical solution, the contact hole etching process in the pixel region is specifically as follows: initially form the pixel region contact holes by etching the interlayer dielectric layer using the mask pattern in the pixel region as a mask, while etching the second hard mask layer; continue to etch the contact hole etch stop layer below the pixel region contact holes, while etching the first hard mask layer in the pixel region and the logic region; continue to etch the protection layer below the pixel region contact holes to form the final pixel region contact holes.

[0020] Continuing with the above technical solution, the first hard mask layer and the contact hole etch stop layer are made of the same material.

[0021] Continuing with the above technical solution, the second hard mask layer and the first hard mask layer are made of different materials.

[0022] Continuing with the above technical solution, the second hard mask layer and the interlayer dielectric layer are made of the same material.

[0023] The present invention also provides an image sensor, which prepares the contact holes in the pixel region and the logic region using the contact hole formation method described in the above technical solution.

[0024] The beneficial effects of the present invention are as follows: by introducing different hard mask layers in the logic region and the pixel region in the present invention, where only one hard mask layer is prepared in the logic region and two hard mask layers are prepared in the pixel region, unexpectedly, under the action of different hard mask layers, the contact holes in the logic region and the pixel region can be etched separately without over-etching due to the height difference; after the contact holes in the logic region are etched, a sacrificial layer for protecting the contact holes in the logic region is formed by spin-coating an organic carbon layer, so that the contact holes in the logic region are not affected at all when etching the contact holes in the pixel region; and when forming the interlayer dielectric layer, its thickness is increased to be the same as the thickness of the protection layer in the pixel region, so that when etching the protection layer subsequently, as an etching compensation, they offset each other, still maintaining the thickness of the interlayer dielectric layer unchanged and still maintaining the aspect ratio unchanged when filling the contact holes subsequently.

[0025] Furthermore, by thinning the contact hole etch stop layer, the aspect ratio during subsequent filling of the interlayer dielectric layer can be reduced, avoiding the occurrence of holes and gaps during filling and thus preventing the isolation performance from deteriorating.

[0026] Further, when etching the contact holes in the logic region, by selecting different etching gases for etching, while forming the contact holes in the logic region, only the transfer of the contact hole mask pattern in the pixel region is completed, so that the contact holes in the logic region and the pixel region can be completed separately and at different times, avoiding the over-etching of the logic region substrate caused by the height difference in the traditional synchronous etching method.

[0027] Further, when forming the second hard mask layer in the pixel region, the photomask used for preparing the protection layer is directly used without an additional photomask, saving costs.

[0028] Further, when etching the contact holes in the pixel region, different layers are etched in segments by different etching methods. Also, since the thicknesses of the first hard mask layer and the contact hole etching stop layer are the same, they can be etched off simultaneously during etching.

[0029] Of course, it is not necessary for any product implementing the present invention to achieve all the above-mentioned advantages simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following briefly introduces the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0031] Figure 1 is a cross-sectional schematic diagram of a CIS device with contact holes in the related art;

[0032] Figure 2 is a flowchart of a method for forming contact holes according to an embodiment of the present invention;

[0033] Figure 3A is a cross-sectional schematic diagram of a device when forming a contact hole etching stop layer according to an embodiment of the present invention;

[0034] Figure 3B is a cross-sectional schematic diagram of forming a first hard mask layer and a second hard mask layer according to an embodiment of the present invention;

[0035] Figure 3C is a cross-sectional schematic diagram of forming a contact hole mask pattern according to an embodiment of the present invention;

[0036] Figure 3D is a cross-sectional schematic diagram after etching the first hard mask layer according to an embodiment of the present invention;

[0037] Figure 3E is a cross-sectional schematic diagram after etching off the second hard mask layer according to an embodiment of the present invention;

[0038] Figure 3FIt is a cross-sectional schematic diagram of forming a logic region contact hole according to an embodiment of the present invention;

[0039] Figure 3G It is a cross-sectional schematic diagram after spin-coating organic carbon according to an embodiment of the present invention;

[0040] Figure 3H It is a cross-sectional schematic diagram of forming a logic region sacrificial layer according to an embodiment of the present invention;

[0041] Figure 3I It is a cross-sectional schematic diagram of preliminarily forming a pixel region contact hole according to an embodiment of the present invention;

[0042] Figure 3J It is a cross-sectional schematic diagram of continuously etching an etch stop layer below the pixel region contact hole according to an embodiment of the present invention;

[0043] Figure 3K It is a cross-sectional schematic diagram of etching a protective layer below the pixel region contact hole according to an embodiment of the present invention;

[0044] Figure 3L It is a cross-sectional schematic diagram of removing the logic region sacrificial layer to form a final pixel region contact hole according to an embodiment of the present invention;

[0045] Figure 3M It is a cross-sectional schematic diagram after filling the contact hole according to an embodiment of the present invention.

[0046] In the figure: 101, substrate; 102, interlayer dielectric layer; 103, contact hole etch stop layer; 104, protective layer; 105, metal silicide; 106, contact hole; 107, hole; 301, substrate; 302, gate oxide layer; 303, polysilicon gate; 304, contact layer; 305, protective layer; 306, contact hole etch stop layer; 307, interlayer dielectric layer; 308, first hard mask layer; 309, second hard mask layer; 310, photoresist layer; 311, logic region contact hole; 312, organic carbon layer; 313, pixel region contact hole. Detailed implementation manners

[0047] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0048] It should be noted that the diagrams provided in the embodiments of the present invention only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape and size of the components in actual implementation. The types, numbers and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0049] In the present invention, it should also be noted that, when terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or positional relationship indicated thereby is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation to the present application. In addition, when terms such as "first" and "second" appear, they are only used for descriptive and distinguishing purposes and cannot be construed as indicating or implying relative importance.

[0050] In addition, it should also be noted that the features of various embodiments of the present invention can be partially or wholly combined or integrated, and as can be understood by those skilled in the art, they can interact and operate in different ways. Each embodiment can be implemented independently of each other or in an associated relationship.

[0051] In order to overcome the problem that the height difference between the logic region and the image region of the CIS device affects the etching of subsequent contact holes due to different structures, the solution of the present invention mainly completes the etching of the contact holes by dividing the regions. During this process, different hard mask layers are introduced in the logic region and the pixel region, and corresponding etching gases are selected for staged etching. When etching the contact holes in the pixel region, a sacrificial layer for protecting the contact holes in the logic region is formed, so that the etching of the contact holes in the pixel region will not affect the contact holes in the logic region at all, thereby avoiding the over-etching problem caused by the height difference.

[0052] As Figure 2 shown, the method for forming contact holes in the embodiment of the present invention mainly includes the following steps:

[0053] S1. Form a contact hole etching stop layer on the device structures of the logic region and the pixel region of the pre-completed image sensor, wherein the device structure of the pixel region has one more protective layer than the logic region;

[0054] S2. Fill a thickened interlayer dielectric layer on the contact hole etching stop layer, and the increased thickness is equal to the thickness of the protective layer; and form a first hard mask layer on the interlayer dielectric layer, and a second hard mask layer is also formed above the first hard mask layer in the pixel region;

[0055] S3. Use the first hard mask layer as a mask to etch the contact holes in the logic region, and only form a mask pattern on the pixel region under the protection of the second hard mask layer;

[0056] S4. Spin-coat an organic carbon layer on both the logic region and the pixel region to form a sacrificial layer for protecting the contact holes in the logic region;

[0057] S5. Etch the organic carbon layer to expose the mask pattern in the pixel region, and perform the etching of the contact holes in the pixel region until above the protective layer;

[0058] S6. Continue to etch the protective layer below the pixel area contact hole, and at the same time etch and thin the interlayer dielectric layer by the same thickness;

[0059] S7. Remove the sacrificial layer in the logic area and fill all the contact holes.

[0060] As Figure 3A shown, the device structures of the logic area and the pixel area of the image sensor have been pre-completed, which mainly includes a substrate 301. Above the substrate 301, it is divided into a logic area and a pixel area. The logic area includes a gate oxide layer 302 (GateOX, abbreviated as GOX), a polysilicon gate 303, and a contact layer 304 from bottom to top. The contact layer 304 is located on top of the gate and is a metal silicide, such as nickel silicide or cobalt silicide. The film thickness of the contact layer 304 is relatively thin and is mainly used to reduce the contact resistance. Among them, the substrate 301 can be a silicon substrate, a silicon-germanium substrate, or other semiconductor material substrates well-known to those skilled in the art. The pixel area includes a gate oxide layer GOX, a polysilicon gate 303, and a protective layer 305 (i.e., Self-Aligned Barrier Oxide, abbreviated as SAB OX) from bottom to top. In some embodiments, a sidewall structure (for example, a sidewall with an ONO structure) will also be formed on the side of the polysilicon gate 303. It should be noted that the polysilicon gate, the contact layer, the sidewall, the gate oxide layer, etc. in this embodiment can all be formed by traditional or known processes, and the specific details of these structures are not elaborated in this invention. In addition, an active area is also formed on the substrate 301, which can be prepared by known techniques, and this invention does not elaborate too much on the active area.

[0061] In step S1 of this embodiment, a contact hole etch stop layer 306 (silicon nitride can be selected) is mainly formed on the pre-completed entire device structure. In order to reduce the filling difficulty of the interlayer dielectric layer, avoid gaps and holes during filling, and further reduce the aspect ratio of the interlayer dielectric layer filling, the thickness of the contact hole etch stop layer 306 can be thinned, and its thickness is less than the thickness of the protective layer 305. In the prior art, the thickness of the contact hole etch stop layer 306 is generally 350 Å, and in this embodiment, it can be thinned to 300 Å, that is, at least thinned by 10%.

[0062] As Figure 3BAs shown in the figure, in step S2, the thickness of the interlayer dielectric layer 307 is increased in this embodiment, and the increased thickness is equal to the thickness of the protective layer 305. The purpose is to serve as an etching compensation during the subsequent etching of the protective layer 305, canceling each other out, maintaining the thickness of the interlayer dielectric layer unchanged and the aspect ratio of the subsequent contact hole filling unchanged. Specifically, the interlayer dielectric layer 307 can be deposited first and then formed by chemical mechanical polishing. The interlayer dielectric layer 307 can be formed by traditional or known processes, which will not be elaborated here. In the embodiment of the present invention, the thickness of the protective layer 305 is about 330 Å, and the interlayer dielectric layer 307 also reserves an additional thickness of about 330 Å. The material of the interlayer dielectric layer 307 is generally an oxide layer, such as silicon dioxide, which mainly serves as a dielectric material between the device and the metal layer to form electrical isolation. The contact holes are many small vertical through-holes formed in the interlayer dielectric layer 307 and are the connection channels between the transistors and the metal layer.

[0063] As Figure 3B shown, in the embodiment of the present invention, only the first hard mask layer 308 is formed on the interlayer dielectric layer 307, and a second hard mask layer 309 is further formed above the first hard mask layer 308 in the pixel region. The main purpose is to enable the subsequent contact holes in the logic region and the pixel region to be etched separately, avoiding the over-etching of the logic region substrate caused by the height difference in the synchronous etching in the traditional solution. The thickness of the first hard mask layer 308 is close to the thickness of the contact hole etching stop layer 306, and the materials are similar or the same, so that the two can be etched off simultaneously when etching the contact holes in the pixel region. Specifically, the formation process of the second hard mask layer 309 in the pixel region is as follows: form the second hard mask layer 309 on the first hard mask layer 308; form a photoresist layer 310 on the second hard mask layer 309; perform exposure and development on the photoresist layer 310 through a photomask to form a mask layer; etch the second hard mask layer 309 using the mask layer as a mask; remove the photoresist 310. The photomask used in this process is the same as the photomask used when preparing the protective layer 305, without the need for an additional photomask, thus saving costs.

[0064] As Figures 3C - 3F shown, in step S3, the formation process of the logic region contact holes is specifically as follows:

[0065] (1) Form a photoresist layer 310 (abbreviated as PR) on the first hard mask layer 308 in the logic region and the second hard mask layer 309 in the pixel region, and an anti-reflection coating (abbreviated as BARC) can also be formed thereon;

[0066] (2) Form a contact hole mask pattern for the logic region and the pixel region through exposure and development, as Figure 3C shown;

[0067] (3) Select the first etching gas to etch the first hard mask layer 308 in the logic region, and specifically, it can be etched by dry etching, as Figure 3DAs shown, since the materials of the first hard mask layer 308 and the second hard mask layer 309 are different, different etching gases are selected for etching. When etching the first hard mask layer 308, the second hard mask layer 309 will not be etched. Therefore, in this process, the pixel region is protected by the second hard mask layer 309 and is not etched;

[0068] (4) Select a second etching gas to etch the second hard mask layer 309 in the pixel region, and at the same time etch a part of the interlayer dielectric layer 307 in the logic region, such as Figure 3E As shown. Since the materials of the second hard mask layer 309 and the interlayer dielectric layer 307 are similar or the same, when the second etching gas etches the second hard mask layer 309, a part of the interlayer dielectric layer 307 is also etched;

[0069] (5) Select a third etching gas to continue etching downward in the logic region to form a contact hole (until the contact hole etch stop layer 306 is etched away), and at the same time etch the first hard mask layer 308 in the pixel region to form a contact hole mask pattern in the pixel region, such as Figure 3F As shown; A gas with a high selectivity ratio, such as C4F8 or CF4, can be selected for etching. Also, since the thickness of the first hard mask layer 308 in the pixel region is close to the thickness of the contact hole etch stop layer 306, this high-selectivity etching gas can etch only the first hard mask layer 308 in the pixel region while completing the etching of the contact hole 311 in the logic region, just forming a mask pattern for the pixel region contact hole 313 on it;

[0070] (6) Remove the photoresist layer 310 and the anti-reflection coating.

[0071] In step S4, organic carbon spin coating is performed, which can fill the etched logic region contact hole 311, and this is used as a sacrificial layer to self-align and protect the logic region contact hole 311, such as Figure 3G As shown. At the same time, the organic carbon also fills the voids of the mask pattern of the pixel region contact hole 313. This part of the organic carbon can be etched away first. At this time, no photomask is required, and it is directly etched through the etching gas, such as Figure 3H As shown. When performing organic carbon spin coating to form a sacrificial layer for protecting the logic region contact hole, it is specifically formed through a self-alignment process to reduce the complexity and cost in the manufacturing process, while improving the performance and reliability of the product. Spin-coated carbon self-alignment protection can avoid the overlay error problem in the traditional yellow light process.

[0072] Next, step S5 is performed. A high-selectivity etching gas (this etching gas cannot etch the organic carbon layer 312 used as a sacrificial layer in the logic region and the first hard mask layer 308) can be selected to further etch the second hard mask layer 309 and the interlayer dielectric layer 307 in the pixel region until the contact hole etch stop layer 306, and initially form the pixel region contact hole 313, such as Figure 3IAs shown. Continue to select an etching gas to etch the contact hole etching stop layer 306. Since the materials of the first hard mask layer 308 and the contact hole etching stop layer 306 are similar or the same, and their thicknesses are approximately the same, the first hard mask layer 308 is etched away while etching the contact hole etching stop layer 306, and the logic region is protected by the organic carbon layer 312 as a sacrificial layer and is not damaged, as Figure 3J shown.

[0073] In step S6, continue to etch downward the protective layer 305 in the pixel region to form the final pixel region contact hole 313, as Figure 3K shown. When etching the protective layer 305 in the pixel region, the interlayer dielectric layer 307 with the same thickness is etched. Because the thickness of the interlayer dielectric layer 307 is increased when forming the interlayer dielectric layer 307 to make it the same as the thickness of the protective layer 305 in the pixel region, when etching the protective layer 305 at this time, the thickened interlayer dielectric layer 307 serves as an etching compensation and cancels each other out, keeping the thickness of the interlayer dielectric layer unchanged and the aspect ratio unchanged during subsequent contact hole filling.

[0074] In step S7, remove the sacrificial layer in the logic region, as Figure 3L shown, and fill all the contact holes, as Figure 3M shown. The main filling material is a conductive metal, such as tungsten. Also, since the contact holes in the logic region and the pixel region are formed separately, the contact hole etching stop layer 306 only needs to balance the height loads of their respective active regions and the polysilicon gate 303, and does not need to consider the additional height load brought by the SAB OX protective layer 305. Thinning the thickness of the contact hole etching stop layer 306 can reduce the filling difficulty of the interlayer dielectric layer, which is beneficial for the HARP to fill out a seamless and hole-free structure, and further beneficial for the stability of the isolation performance.

[0075] An image sensor according to an embodiment of the present invention mainly uses the contact hole forming method in the above embodiment to prepare the contact holes in the pixel region and the logic region. The contact holes formed by this method will not over-etch the substrate 301, and the interlayer dielectric layer after final filling is seamless and hole-free, and the isolation performance is stable.

[0076] In summary, in the present invention, different hard mask layers are introduced in the logic region and the pixel region. Specifically, only one hard mask layer is prepared in the logic region, while two hard mask layers are prepared in the pixel region. An unexpected effect is that the contact holes in the logic region and the pixel region can be etched separately, avoiding the over-etching of the logic region substrate caused by the height difference in the synchronous etching in the traditional solution. After the etching of the logic region contact hole 311 is completed, a sacrificial layer for protecting the logic region contact hole 311 is formed by spin-coating an organic carbon layer 312 in a self-aligned manner, such that the etching of the pixel region contact hole 313 will not affect the logic region contact hole 311 at all. Moreover, when forming the interlayer dielectric layer 307, its thickness is increased to be the same as that of the protective layer 305 in the pixel region, so as to serve as an etching compensation during the subsequent etching of the protective layer 305 and offset each other, still maintaining the aspect ratio unchanged during the subsequent hole filling.

[0077] It should be noted that, according to the needs of implementation, each step / component described in the present application can be split into more steps / components, or two or more steps / components or partial operations of steps / components can be combined into new steps / components to achieve the purpose of the present invention.

[0078] In the above embodiments, the magnitudes of the sequence numbers of the steps do not imply the order of execution. The order of execution of each process should be determined according to its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0079] It should be understood that those of ordinary skill in the art can make improvements or transformations according to the above description, and all such improvements and transformations should fall within the protection scope of the appended claims of the present invention.

Claims

1. A method for forming a contact hole, characterized in that, The steps include the following: On the device structures of the logic region and the pixel region of a prefabricated image sensor, a contact hole etching stop layer is formed, wherein the device structure of the pixel region has one more protective layer than that of the logic region; A thickened interlayer dielectric layer is filled on the contact hole etching stop layer, and the increased thickness is equal to the thickness of the protective layer; A first hard mask layer is formed on the interlayer dielectric layer, and a second hard mask layer is further formed above the first hard mask layer in the pixel region; Using the first hard mask layer as a mask, contact holes are etched in the logic region, and in the pixel region, only a mask pattern is formed thereon under the protection of the second hard mask layer; An organic carbon layer is spin-coated on both the logic region and the pixel region to form a sacrificial layer for protecting the contact holes in the logic region; The organic carbon layer is etched to expose the mask pattern in the pixel region, and contact hole etching in the pixel region is carried out until above the protective layer; Continue to etch the protective layer below the contact hole in the pixel region, and at the same time, etch and thin the interlayer dielectric layer by the same thickness; Remove the sacrificial layer in the logic region and fill all the contact holes; 2. The contact hole forming method according to claim 1, characterized in that, The formed contact hole etching stop layer is a thinned contact hole etching stop layer, and its thickness is less than the thickness of the protective layer; 3. The contact hole forming method according to claim 1 or 2, characterized in that, The thickness of the first hard mask layer is the same as the thickness of the contact hole etching stop layer; 4. The contact hole forming method according to claim 1, wherein The specific process of forming the contact holes in the logic region is as follows: A photoresist layer and an anti-reflection coating are formed on the first hard mask layer in the logic region and the second hard mask layer in the pixel region; Through exposure and development, a contact hole mask pattern for the logic region and the pixel region is formed; A first etching gas is selected to etch the first hard mask layer in the logic region; A second etching gas is selected to etch the second hard mask layer in the pixel region, and at the same time, a part of the interlayer dielectric layer in the logic region is etched; A third etching gas is selected to continue to etch downward in the logic region to form contact holes, and at the same time, the first hard mask layer in the pixel region is etched to form a contact hole mask pattern in the pixel region; The photoresist layer and the anti-reflection coating are removed; 5. The contact hole forming method according to claim 1, characterized in that, When etching the organic carbon layer, no photomask is required, and it is directly etched through an etching gas, and the etching gas is oxygen or an oxygen-containing gas; 6. The contact hole forming method according to claim 1, wherein The specific process of forming the second hard mask layer in the pixel region is as follows: A second hard mask layer is formed on the first hard mask layer; A photoresist layer is formed on the second hard mask layer; Through a photomask, exposure and development are carried out on the photoresist layer to form a mask layer, wherein the photomask is the photomask used when preparing the protective layer; Using the mask layer as a mask, the second hard mask layer is etched; The photoresist is removed; 7. The contact hole forming method according to claim 6, characterized in that, The materials of the second hard mask layer and the first hard mask layer are different; 8. The contact hole forming method according to claim 1, wherein The specific process of contact hole etching in the pixel region is as follows: Using the mask pattern in the pixel region as a mask, the interlayer dielectric layer is etched to initially form contact holes in the pixel region, and at the same time, the second hard mask layer is etched; Continue to etch the contact hole etching stop layer below the contact hole in the pixel region, and at the same time, etch the first hard mask layer in the pixel region and the logic region; Continue to etch the protective layer below the contact hole in the pixel region to form the final contact holes in the pixel region; 9. The contact hole forming method according to claim 1, characterized in that, The materials of the second hard mask layer and the interlayer dielectric layer are the same; 10. An image sensor, characterized in that, The contact holes in the pixel region and the logic region are prepared by using the contact hole forming method described in any one of claims 1-9;

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