Solar cell, preparation method thereof and power utilization device
By forming a mask layer on the P-type doped region of the solar cell and diffusing the N-type material, combined with hydrofluoric acid cleaning treatment, the mechanical damage caused by traditional laser treatment is solved, and the performance of the solar cell is improved.
Patent Information
- Application Number
- CN202311586922.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-24
- Publication Date
- 2025-05-30
AI Technical Summary
When traditionally preparing the doped region of the solar cell substrate, laser treatment leads to mechanical damage, which is difficult to repair, and reduces the performance of the solar cell.
A mask layer is formed on the P-type doped region, and then the N-type material is diffused to form a co-doped layer, and the hydrofluoric acid cleaning treatment is used to corrode the composite glass material with different rates of hydrofluoric acid to uniformly corrode the preset N-type doped region.
It effectively avoids mechanical damage caused by laser treatment, avoids the formation of defect centers, and improves the performance of solar cells.
Smart Images
Figure CN120076444A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of batteries, and particularly to a solar cell, a preparation method thereof, and an electrical device. Background Art
[0002] Among renewable clean energies, solar photovoltaics (SPV) is one of the most potential and sustainable energies in the world. Solar photovoltaics such as solar cells can convert light energy into electrical energy, causing no pollution to the environment during energy conversion, and is a new type of energy. Solar cells are mainly divided into crystalline silicon solar cells, compound solar cells (such as gallium arsenide, copper indium gallium selenide), organic solar cells (such as perovskite, etc.), and dye-sensitized solar cells. Among them, crystalline silicon solar cells occupy an absolute dominant position in the commercial market due to mature technology and rich raw materials. Currently, the market share exceeds 85%, and will maintain the leading position in the next decade or even longer. Improving the conversion efficiency of the battery and reducing the production cost of the battery have always been the goals pursued by the photovoltaic industry. Among them, the improvement of the conversion efficiency often also brings a certain degree of cost reduction. The early products of silicon solar cells were aluminum back surface field (Al-BSF) with an efficiency of less than 20%; later, it was upgraded to passivated emitter and rear cell (PERC), with a conversion efficiency exceeding 22.5%. Although polysilicon occupies a relatively large scale due to its low-cost advantage, in 2019, n-type and p-type monocrystalline silicon cells accounted for 60% of the market share. Among them, the n-type cell technology will continue to grow, mainly including n-type heterojunction (SHJ), tunnel oxide passivated contact (TOPCon), and interdigitated back contact (IBC) structures. The structural feature of the IBC cell is that there are no grid lines on the front side, and the positive and negative electrodes are both formed in a cross-arrangement structure on the back side. This front-side unobstructed structure completely eliminates the shielding loss caused by the grid line electrodes, realizes the maximum utilization of incident photons, and thus effectively improves the battery efficiency and power generation.
[0003] In the traditional preparation of IBC cells, a laser is used to prepare the doped region in the substrate. Due to the uneven distribution of laser energy, mechanical damage is generated during laser grooving. Even if a cleaning process is adopted subsequently, it is difficult to repair, and finally, defect centers are formed by laser treatment, reducing the performance of the solar cell. Summary of the Invention
[0004] Based on this, in order to avoid the mechanical damage caused by laser treatment during the preparation of the doped region in the traditional substrate and improve the performance of the solar cell, the present application provides a solar cell, a preparation method thereof, and an electrical device.
[0005] The present application provides a preparation method of a solar cell, comprising the following steps:
[0006] Providing a substrate, the substrate having a first surface and a second surface opposite to the first surface;
[0007] Preparing a P-type material layer on the first surface, and preparing a mask layer on a preset P-type doped region of the P-type material layer;
[0008] Diffusing an N-type material into the P-type material layer not covered by the mask layer at a temperature of 360°C to 650°C to prepare a co-doped layer, performing a first cleaning until a part of the substrate is exposed, removing the mask layer, and preparing a prefabricated structure containing a P-type doped region, wherein the conditions of the first cleaning include: cleaning with an aqueous hydrofluoric acid solution;
[0009] Preparing a stacked tunneling oxide material layer and an N-type doped polysilicon material layer on the first surface of the prefabricated structure, removing the tunneling oxide material and the N-type doped polysilicon material on the P-type doped region, and preparing a tunneling oxide layer and an N-type doped polysilicon layer.
[0010] In one embodiment, the time of the first cleaning is 10 s to 1000 s, and the mass percentage of hydrofluoric acid in the aqueous hydrofluoric acid solution is 3% to 7%.
[0011] In one embodiment, the temperature for preparing the P-type material layer is 900°C to 1050°C.
[0012] In one embodiment, the doping concentration of the N-type material in the co-doped layer is 1e10 to 1e16.
[0013] In one embodiment, the temperature for diffusing the N-type material is 400°C to 600°C.
[0014] In one embodiment, the temperature for preparing the N-type doped polysilicon material layer is 600°C to 800°C.
[0015] In one embodiment, after preparing the N-type doped polysilicon layer, it further includes: preparing a stacked first passivation layer and a first antireflection layer on the N-type doped polysilicon layer, and preparing a stacked second passivation layer and a second antireflection layer on the second surface.
[0016] In one embodiment, after preparing the first antireflection layer and the second antireflection layer, the method further includes: preparing a first electrode and a second electrode, where the first electrode penetrates through the first passivation layer and the first antireflection layer and is connected to the P-type doped region, and the second electrode penetrates through the first passivation layer and the first antireflection layer and is connected to the N-type doped polysilicon layer.
[0017] This application also provides a solar cell prepared by the above preparation method.
[0018] This application also provides an electrical device including the above solar cell as a power source.
[0019] The solar cell provided by this application forms a mask layer on the P-type region and then diffuses the N-type material, forms a co-doped composite glass material on the non-P-type region, undergoes hydrofluoric acid cleaning treatment. By utilizing the different etching rates of the hydrofluoric acid on the composite glass material and the P-type glass material, the etching rate is increased. Without damaging other structures of the battery, it is also possible to uniformly etch a preset N-type doped region in the substrate, which is beneficial to the subsequent process of preparing a uniform N-type doped region, effectively avoiding the mechanical damage generated when preparing the doped region in the substrate by traditional laser treatment, and avoiding the formation of defect centers to improve the performance of the solar cell. Description of the Drawings
[0020] Figure 1 It is a schematic structural diagram of a solar cell according to a specific example provided by this application;
[0021] Description of the reference numerals: 10: solar cell; 100: substrate; 110: P-type doped region; 120: tunneling oxide layer; 130: N-type doped polysilicon layer; 140: first passivation layer; 150: first antireflection layer; 160: second passivation layer; 170: second antireflection layer; 180: first electrode; 190: second electrode. Detailed Embodiments
[0022] To facilitate the understanding of this application, the following will describe this application more comprehensively with reference to the relevant drawings. The preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure content of this application more thorough and comprehensive.
[0023] In addition, the terms "first" and "second" are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In the description of the invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically defined. In the description of the present application, "several" means at least one, such as one, two, etc., unless otherwise specifically defined.
[0024] The terms "preferably", "more preferably", etc. in the present application refer to embodiments of the present application that can provide certain beneficial effects in certain cases. However, in the same or other cases, other embodiments may also be preferred. In addition, the description of one or more preferred embodiments does not imply that other embodiments are not available, nor is it intended to exclude other embodiments from the scope of the present application.
[0025] When a numerical range is disclosed herein, the above range is considered continuous and includes the minimum and maximum values of the range, as well as each value therebetween. Further, when the range refers to integers, it includes each integer between the minimum and maximum values of the range. In addition, when multiple ranges are provided to describe features or characteristics, the ranges can be combined. In other words, unless otherwise specified, all ranges disclosed herein should be understood to include any and all sub-ranges subsumed therein.
[0026] When describing positional relationships, unless otherwise specified, when an element such as a layer, film, or substrate is referred to as being "on" another film layer, it can be directly on the other film layer or there can also be an intermediate film layer. Further, when a layer is referred to as being "under" another layer, it can be directly below or there can be one or more intermediate layers. It can also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or there can also be one or more intermediate layers.
[0027] In cases where "comprising", "having", and "including" as described herein are used, the intention is to cover non-exclusive inclusion. Unless a clear limiting term such as "only", "consisting of", etc. is used, another component can also be added.
[0028] Unless otherwise mentioned, terms in the singular form can include the plural form and should not be understood as having a quantity of one.
[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" as used herein includes any and all combinations of one or more of the related listed items.
[0030] This application provides a method for preparing a solar cell 10 as Figure 1 shown, comprising the following steps:
[0031] Providing a substrate 100, the substrate 100 having a first surface and a second surface opposite to the first surface;
[0032] Preparing a P-type material layer on the first surface, and preparing a mask layer on a preset P-type doping region of the P-type material layer;
[0033] Diffusing an N-type material into the P-type material layer not covered by the mask layer at a temperature of 360 °C to 650 °C to prepare a co-doped layer, performing a first cleaning until a part of the substrate is exposed, removing the mask layer, and preparing a prefabricated structure containing a P-type doping region 110, wherein the conditions for the first cleaning include: cleaning with an aqueous hydrofluoric acid solution;
[0034] Preparing a stacked tunneling oxide material layer and an N-type doped polysilicon material layer on the first surface of the prefabricated structure, removing the tunneling oxide material and the N-type doped polysilicon material on the P-type doping region, and preparing a tunneling oxide layer 120 and an N-type doped polysilicon layer 130.
[0035] The solar cell provided by this application forms a mask layer on the P-type doping region 110 and then diffuses the N-type material, forms a co-doped composite glass material on the non-P-type region, and after hydrofluoric acid cleaning treatment, by utilizing the different etching rates of the hydrofluoric acid on the composite glass material and the P-type glass material, the etching rate is increased. Without damaging other structures of the battery, it is also possible to uniformly etch a preset N-type doping region in the substrate, which is beneficial to the subsequent process of preparing a uniform N-type doping region, effectively avoiding the mechanical damage generated when preparing the doping region in the substrate 100 by traditional laser treatment, and avoiding the formation of defect centers to improve the performance of the solar cell.
[0036] In a specific example, the substrate 100 is an N-type silicon wafer substrate 100. Further, the N-type silicon wafer substrate 100 is double-sided polished. Specifically, the above substrate 100 is placed in an aqueous solution of sodium hydroxide with a mass percentage of 6% - 9% for polishing treatment. Further still, before entering the polishing treatment, the above substrate 100 also includes being placed in an aqueous solution of hydrogen peroxide with a concentration of 0.2% - 1% to clean the surface oil stain, and after the polishing treatment, it also includes using a mixed solution of hydrochloric acid and hydrofluoric acid to clean metal ions and the oxide layer, as well as drying treatment.
[0037] In a specific example, the temperature for preparing the P-type material layer is 900°C - 1050°C. The method for preparing the P-type material layer includes but is not limited to chemical vapor deposition. Specifically, boron chloride is used to diffuse the substrate 100 at a temperature of 900°C - 1050°C.
[0038] Specifically, the temperature for preparing the P-type material layer can be but is not limited to 900°C, 910°C, 920°C, 930°C, 940°C, 950°C, 960°C, 970°C, 980°C, 990°C, 1000°C, 1010°C, 1020°C, 1030°C, 1040°C or 1050°C.
[0039] Further, the thickness of the above P-type material layer is 80nm - 120nm, and the sheet resistance of the P-type material layer is 40Ω - 200Ω. Specifically, the thickness of the P-type material layer can be but is not limited to 80nm, 90nm, 100nm, 110nm or 120nm, and the sheet resistance of the P-type material layer can be but is not limited to 40Ω, 60Ω, 80Ω, 100Ω, 120Ω, 140Ω, 160Ω, 180Ω or 200Ω.
[0040] In a specific example, the method for preparing the mask layer can be but is not limited to screen printing.
[0041] In a specific example, the thickness of the mask layer is 50nm - 500nm. Further, the thickness of the mask layer can be but is not limited to 50nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm or 500nm.
[0042] In a specific example, the material of the mask layer includes one or both of nano-silicon and ink. It can be understood that the above nano-silicon and ink are not easily soluble in hydrofluoric acid solution and can be removed by alkali solution.
[0043] Furthermore, the method for diffusing the N-type material to the first surface includes but is not limited to chemical vapor deposition. Specifically, phosphorus oxychloride is used to diffuse the P-type material layer at a temperature of 400°C to 600°C. Due to the blocking of the mask layer, phosphorus oxychloride is only diffused to the area where no mask layer is formed, forming a composite BPSG material composed of phosphosilicate glass and borosilicate glass. It can be understood that during the process of the above P-type material, borosilicate glass is formed. The etching rates of the above materials by hydrofluoric acid are different. Specifically, the etching rates of hydrofluoric acid for borosilicate glass (BSG), phosphosilicate glass (PSG), and the composite BPSG material formed by phosphosilicate glass and borosilicate glass are as follows: V(PSG) > V(BPSG) > V(BSG). By wet chemical HF etching, the etching rate is increased, thus solving the problem of uneven laser energy and avoiding the formation of defect centers in subsequent processes. Specifically, the temperature for diffusing the N-type material can be but is not limited to 400°C, 440°C, 460°C, 480°C, 520°C, 560°C, or 600°C.
[0044] In one specific example, the doping concentration of the N-type material in the co-doped layer is 1e10 to 1e16, which can achieve a better etching rate difference. The doping concentration of the N-type material in the co-doped layer can be but is not limited to 1e10, 1e11, 1e12, 1e13, 1e14, 1e15, or 1e16.
[0045] In one specific example, after the first cleaning and before preparing the prefabricated structure containing the P-type doped region 110, it further includes: polishing the exposed P-type doped region 110 and part of the substrate 100.
[0046] It can be understood that the polishing treatment here is also carried out by placing it in an aqueous solution of sodium hydroxide with a mass percentage of 6% to 9%.
[0047] In one specific example, the conditions for the first cleaning further include: the cleaning time is 10s to 1000s, and the mass percentage of hydrofluoric acid in the hydrofluoric acid aqueous solution is 3% to 7%.
[0048] In one specific example, the temperature for preparing the N-type doped polysilicon material layer is 600°C to 800°C.
[0049] Furthermore, the method for preparing the stacked tunneling oxide material layer and the N-type doped polysilicon material layer includes but is not limited to putting the cleaned silicon wafer into an LPCVD device and growing a layer of 1nm to 2nm of SiO 2 ; at the same time, growing a layer of intrinsic polysilicon at a temperature of 500°C to 650°C, and diffusing the above intrinsic polysilicon with phosphorus oxychloride at 600°C to 800°C. The sheet resistance of the N-type doped polysilicon material layer is 30Ω to 100Ω.
[0050] Specifically, the temperature for preparing the N-type doped polysilicon material layer can be, but is not limited to, 600 °C, 650 °C, 700 °C, 730 °C, 750 °C, 770 °C or 800 °C. The sheet resistance of the N-type doped polysilicon material layer can be, but is not limited to, 30 Ω, 40 Ω, 50 Ω, 60 Ω, 70 Ω, 80 Ω, 90 Ω or 100 Ω.
[0051] Furthermore, the method for removing the tunneling oxide material on the P-type doped region 110 and the N-type doped polysilicon material can be, but is not limited to, laser treatment.
[0052] In a specific example, due to the phosphorus-silicon glass PSG formed on the second surface of the substrate 100 during the preparation of the N-type doped polysilicon material layer, it is removed by a chain method.
[0053] In a specific example, after preparing the N-type doped polysilicon layer 130, it further includes: preparing a stacked first passivation layer 140 and a first antireflection layer 150 on the N-type doped polysilicon layer 130, and preparing a stacked second passivation layer 160 and a second antireflection layer 170 on the second surface.
[0054] Further, the materials of the first passivation layer 140 and the second passivation layer 160 each independently include alumina. The thicknesses of the first passivation layer 140 and the second passivation layer 160 are each independently 5 nm to 10 nm.
[0055] Furthermore, the materials of the first antireflection layer 150 and the second antireflection layer 170 each independently include one or more of silicon nitride, silicon oxide and silicon oxynitride, and the thicknesses of the first antireflection layer 150 and the second antireflection layer 170 are each independently 40 nm to 100 nm.
[0056] In a specific example, before preparing the second passivation layer 160, it further includes: performing a texturing treatment on the second surface.
[0057] It can be understood that the second surface is textured with an aqueous solution of NaOH with a mass percentage of 1% to 2.5%. Further, before the texturing treatment, the region on the first surface that has been laser-treated is etched. Specifically, the polysilicon on the laser-treated area of the first surface is removed with an aqueous solution of NaOH with a mass percentage of 6% to 9% to expose the BSG. Furthermore, after the texturing treatment, RCA cleaning is performed, and the BSG and PSG on the first surface are removed with a mixed acid solution of hydrofluoric acid and hydrochloric acid, and finally a drying treatment is performed.
[0058] In a specific example, after preparing the first antireflection layer 150, the following steps are further included: preparing a first electrode 180 that penetrates through the first passivation layer 140 and the first antireflection layer 150 and is connected to the P-type doped region 110, and preparing a second electrode 190 that penetrates through the first passivation layer 140 and the first antireflection layer 150 and is connected to the N-type doped polysilicon layer 130.
[0059] The preparation methods of the above-mentioned first electrode 180 and second electrode 190 can be, but are not limited to, screen printing. Further, the first electrode 180 is made of silver-aluminum paste. After printing the paste of the first electrode 180, low-temperature drying is carried out under the condition of 300°C to 450°C. The second electrode 190 is made of silver paste. After printing the paste of the second electrode 190, high-temperature sintering is carried out under the condition of 700°C to 900°C to form a good ohmic contact between the silver paste and the silicon wafer.
[0060] This application also provides a solar cell 10 prepared according to the above preparation method.
[0061] This application also provides an electrical device including the above-mentioned solar cell 10 as a power source.
[0062] Further, an electrical device is provided, including the above-mentioned solar cell as a power source. It can be understood that the above-mentioned electrical device can include, but is not limited to, a transformer, a reactor, a capacitor, a combined electrical apparatus, a circuit breaker, an instrument transformer, a lightning arrester, a coupling capacitor, a transmission line, a power cable, a grounding device, a generator, a synchronous condenser, a motor, an enclosed busbar, and a thyristor.
[0063] The following provides specific embodiments to further illustrate the solar cell and its preparation method of this application in detail. The raw materials involved in the following specific implementation manners can be obtained from the market without special instructions.
[0064] Example 1
[0065] This embodiment provides a preparation method of a solar cell, including the following steps:
[0066] (1) Polish both sides of the N-type silicon wafer. Place the silicon wafer in an aqueous solution of H 2 O 2 with a mass percentage of 5% for surface oil stain cleaning; polish the silicon wafer in an aqueous solution of NaOH with a mass percentage of 8%; use a mixed acid solution of HCl and HF with a mass ratio of 1:3 to clean metal ions and the oxide layer, and finally carry out a drying treatment;
[0067] (2) Perform B diffusion on one side of the substrate to form about 100 nm of BSG (the first surface). Specifically, use boron trichloride at 940°C for diffusion in a diffusion furnace tube, and control the sheet resistance at 90 Ω to form a P-type emitter;
[0068] (3) using screen printing to perform texturing, firstly patterning the surface of the mask layer material to form a mask layer on the preset P-type doping area, and the unprinted area is the preset N-type doping area, and the mask layer material is nano-silicon;
[0069] (4) Phosphorus oxychloride is used for diffusion in a diffusion furnace tube at 600°C, the diffusion is blocked at the printed mask layer, and low-concentration P doping is performed in the unprinted area to form a BPSG area;
[0070] (5) cleaning the BPSG region with a 5% by mass hydrofluoric acid aqueous solution, cleaning the mask layer with an alkaline solution, and polishing the BPSG region with an 8% by mass NaOH aqueous solution by using a tank-type device to prepare a prefabricated structure containing a P-type doped region;
[0071] (6) Preparation of tunnel oxide layer and polysilicon layer: The cleaned silicon wafer is placed in the LPCVD equipment and a 1-2 nm SiO layer is grown at 650°C. 2 ; At the same time, a layer of intrinsic polysilicon is grown at 540°C;
[0072] (7) Preparation of N emitter: Phosphorus oxychloride was diffused on the first surface of the battery at 750°C; the square resistance was controlled at 50Ω;
[0073] (8) P-area grooving: Laser is used to remove PSG in the P-area (non-windowing area);
[0074] (9) The first surface is covered with a water film, and the PSG on the second surface is removed in a chain manner;
[0075] (10) The first surface laser area is etched by groove method, the second surface is textured, and RCA is cleaned;
[0076] Specifically, a NaOH aqueous solution with a mass percentage of 8% is used to remove the polysilicon at the laser on the first surface, so that the BSG is exposed in the P region, and then a NaOH aqueous solution with a mass percentage of 6% is used to perform texturing on the second surface of the silicon wafer, and a mixed acid solution of HCl and HF with a mass ratio of 1:3 is used to clean the metal ions and the oxide layer to remove the BSG and PSG on the first surface, and finally a drying treatment is performed;
[0077] (11) Depositing aluminum oxide and silicon nitride on the first surface and the second surface respectively: Place the silicon wafer in a two-in-one PECVD device, first grow an 8nm thick aluminum oxide layer on the second surface, and then grow a 79nm thick SiNx layer; the first surface is the same;
[0078] (12) Using screen printing, special silver-aluminum paste is used to print the P+ region grid lines to form a positive emitter; low-temperature drying is carried out at 450 °C; special silver paste is used to print the N+ region grid lines to form a negative electrode; high-temperature sintering is carried out at 800 °C to make the silver paste form a good ohmic contact with the silicon wafer.
[0079] Comparative Example 1
[0080] (1) The N-type silicon wafer is polished on both sides. The silicon wafer is placed in an aqueous solution of H 2 O 2 with a mass percentage of 5% for cleaning the surface oil stain; the silicon wafer is polished in an aqueous solution of NaOH with a mass percentage of 8%; a mixed acid solution of HCl and HF with a mass ratio of 1:3 is used to clean metal ions and the oxide layer, and finally drying treatment is carried out;
[0081] (2) B diffusion is carried out on one side of the substrate to form about 100 nm of BSG (the first surface). Specifically, boron trichloride is used for diffusion in a diffusion furnace tube at 900 °C, and the sheet resistance is controlled at 110 Ω to form a P-type emitter;
[0082] (3) Texturing treatment is carried out by screen printing. The first surface is patterned to print the mask layer material, and a mask layer is formed on the preset P-type doping region. The unprinted region is the preset N-type doping region, and the mask layer material is nano-silicon;
[0083] (4) Phosphorus oxychloride is used for diffusion in a diffusion furnace tube at 700 °C. The diffusion is blocked at the printed mask layer material, and low-concentration P doping is carried out in the unprinted region to form a BPSG region;
[0084] (5) The BPSG region is cleaned by a trough-type device under the condition of an aqueous solution of hydrofluoric acid with a mass percentage of 5%, the mask layer is cleaned with an alkali solution, and the BPSG region is polished with an aqueous solution of NaOH with a mass percentage of 8% to prepare a prefabricated structure containing a P-type doping region;
[0085] (6) Preparation of the tunneling oxide layer and the polysilicon layer: The cleaned silicon wafer is placed in an LPCVD device, and a layer of 1-2 nm of SiO 2 is grown at 650 °C; at the same time, an intrinsic polysilicon layer is grown at 540 °C;
[0086] (7) Preparation of the N emitter: Single-sided diffusion is carried out on the first surface of the battery at 750 °C; the sheet resistance is controlled at 40 Ω;
[0087] (8) P-region grooving: Laser is used to remove PSG in the P-region (non-opening region);
[0088] (9) A water film is covered on the first surface, and the PSG on the second surface is removed by a chain;
[0089] (10) Etch the first surface laser area using a groove, texture the second surface, and perform RCA cleaning;
[0090] Specifically, use an aqueous NaOH solution with a mass percentage of 8% to remove the polysilicon at the laser area of the first surface, expose the P region of BSG, then perform texturing treatment on the second surface of the silicon wafer in an aqueous NaOH solution with a mass percentage of 6%, use a mixed acid solution of HCl and HF with a mass ratio of 1:3 to clean metal ions and the oxide layer, remove the BSG and PSG on the first surface, and finally perform drying treatment;
[0091] (11) Deposit alumina and silicon nitride on the first surface and the second surface respectively: Place the silicon wafer in a two-in-one PECVD device. First, grow a layer of alumina with a thickness of 8 nm on the second surface, and then grow a layer of 79 nm SiN x layer; The same for the first surface;
[0092] (12) Use screen printing to print the P+ region grid lines with special silver-aluminum paste to form a positive emitter; perform low-temperature drying at 450 °C; use special silver paste to print the N+ region grid lines to form a negative electrode; perform high-temperature sintering at 800 °C to make the silver paste form a good ohmic contact with the silicon wafer.
[0093] Comparative Example 2
[0094] (1) Polish both sides of the N-type silicon wafer, place the silicon wafer in an aqueous H 2 O 2 solution with a mass percentage of 5% to clean the surface oil stain; polish the silicon wafer in an aqueous NaOH solution with a mass percentage of 8%; use a mixed acid solution of HCl and HF with a mass ratio of 1:3 to clean metal ions and the oxide layer, and finally perform drying treatment;
[0095] (2) Perform B diffusion on one side of the substrate to form about 100 nm BSG (the first surface). Specifically, use boron trichloride at 900 °C for diffusion in a diffusion furnace tube, control the sheet resistance at 130 Ω, and make it form a P-type emitter;
[0096] (3) Use the screen printing method for texturing treatment, pattern the printing mask layer material on the first surface, form a mask layer on the preset P-type doping area, and the unprinted area is the preset N-type doping area. The mask layer material is nano-silicon;
[0097] (4) Use phosphorus oxychloride at 750 °C for diffusion in a diffusion furnace tube. The diffusion is blocked at the printed mask layer material area, and low-concentration P doping is performed in the unprinted area to form a BPSG area;
[0098] (5) Clean the BPSG region with a hydrofluoric acid aqueous solution at a mass percentage of 3% using a slot-type device, clean the mask layer with an alkaline solution, and polish the BPSG region in an aqueous solution of NaOH at a mass percentage of 8% to prepare a prefabricated structure containing a P-type doped region;
[0099] (6) Preparation of the tunneling oxide layer and polysilicon layer: Place the cleaned silicon wafer into an LPCVD device and grow a 1 - 2 nm SiO layer at 670 °C; 2 At the same time, grow an intrinsic polysilicon layer at 540 °C;
[0100] (7) Preparation of the N emitter: Perform single-sided diffusion on the first surface of the cell at 750 °C; control the sheet resistance at 30 Ω;
[0101] (8) Grooving in the P region: Use a laser to remove the PSG in the P region (non-window region);
[0102] (9) Cover the first surface with a water film and remove the PSG on the second surface in a chain;
[0103] (10) Use a slot-type device to etch the laser region on the first surface, texture the second surface, and perform RCA cleaning;
[0104] Specifically, use an aqueous solution of NaOH at a mass percentage of 8% to remove the polysilicon on the laser area of the first surface, expose the BSG in the P region, then perform texturing treatment on the front surface of the silicon wafer in a 6% NaOH solution, clean metal ions and the oxide layer in a mixed acid solution of HCl / HF, remove the BSG and PSG on the first surface, and finally perform a drying treatment;
[0105] (11) Deposit alumina and silicon nitride on the first surface and the second surface respectively: Place the silicon wafer into a two-in-one PECVD device. First, grow an alumina layer with a thickness of 8 nm on the second surface, and then grow a 79 nm SiNx layer; the same for the first surface;
[0106] (12) Use screen printing to print the P+ region grid lines with a special silver-aluminum paste to form a positive emitter; perform low-temperature drying at 450 °C; use a special silver paste to print the N+ region grid lines to form a negative electrode; perform high-temperature sintering at 800 °C to make the silver paste form a good ohmic contact with the silicon wafer.
[0107] Performance testing methods and result analysis
[0108] celltype Voc (mV) Isc (A) FF (%) Eta (%) Maximum term eta Rs (mΩ) Rsh (Ω) Irev_12 (A) Comparative Example 1 723.23 14.271 78.10 24.34 24.75 1.89 805 3.79 Comparative Example 2 723.56 14.271 78.36 24.43 24.87 1.90 815 3.31 Example 1 727.85 14.311 78.72 24.76 25.10 1.85 1000 2.66
[0109] It can be seen that Comparative Example 1 and Comparative Example 2 respectively adjust the doping temperature of the N-type material, resulting in changes in the N-type material concentration, which affect the formation of phosphosilicate glass and its densification, and thus have a certain impact on its electrical properties. The leakage current (Irev_12) of the battery prepared by the optimized method of the present application is small and the open-circuit voltage (Voc) is large, and the battery structure has good electrical properties.
[0110] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.
[0111] The above-described embodiments merely represent several implementation manners of the present application, which are convenient for understanding the technical solutions of the present application specifically and in detail, but should not be construed as a limitation on the scope of patent protection of the application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several deformations and improvements can still be made, and these all belong to the protection scope of the present application. It should be understood that the technical solutions obtained by those skilled in the art through logical analysis, reasoning or limited experiments on the basis of the technical solutions provided by the present application are all within the protection scope of the appended claims of the present application. Therefore, the protection scope of the patent of the present application should be subject to the content of the appended claims, and the specification can be used to explain the content of the claims.
Claims
1. A method for preparing a solar cell, characterized in that, it comprises the following steps: providing a substrate having a first surface and a second surface opposite to the first surface; preparing a P-type material layer on the first surface, and preparing a mask layer on a preset P-type doping region of the P-type material layer; diffusing an N-type material into the P-type material layer not covered by the mask layer at a temperature of 360°C to 650°C to prepare a co-doped layer, performing a first cleaning until part of the substrate is exposed, removing the mask layer, and preparing a prefabricated structure containing a P-type doping region, wherein the conditions for the first cleaning include: cleaning with an aqueous hydrofluoric acid solution; preparing a stacked tunneling oxide material layer and an N-type doped polysilicon material layer on the first surface of the prefabricated structure, removing the tunneling oxide material and the N-type doped polysilicon material on the P-type doping region, and preparing a tunneling oxide layer and an N-type doped polysilicon layer.
2. The preparation method according to claim 1, characterized in that, the time for the first cleaning is 10 s to 1000 s, and the mass percentage of hydrofluoric acid in the aqueous hydrofluoric acid solution is 3% to 7%.
3. The preparation method according to claim 1, characterized in that, the temperature for preparing the P-type material layer is 900°C to 1050°C.
4. The preparation method according to claim 1, characterized in that, the doping concentration of the N-type material in the co-doped layer is 1e10 to 1e16.
5. The preparation method according to claim 1, characterized in that, the temperature for diffusing the N-type material is 400°C to 600°C.
6. The preparation method according to claim 1, characterized in that, the temperature for preparing the N-type doped polysilicon material layer is 600°C to 800°C.
7. The preparation method according to any one of claims 1 to 6, characterized in that, after preparing the N-type doped polysilicon layer, it further includes: preparing a stacked first passivation layer and a first antireflection layer on the N-type doped polysilicon layer, and preparing a stacked second passivation layer and a second antireflection layer on the second surface.
8. The preparation method according to claim 7, characterized in that, after preparing the first antireflection layer and the second antireflection layer, it further includes: preparing a first electrode and a second electrode, the first electrode penetrates through the first passivation layer and the first antireflection layer and is connected to the P-type doping region, and the second electrode penetrates through the first passivation layer and the first antireflection layer and is connected to the N-type doped polysilicon layer.
9. A solar cell, characterized in that, it is prepared according to the preparation method according to any one of claims 1 to 8.
10. An electrical device, characterized in that, it includes the solar cell according to claim 9 as a power source.