Light-emitting diode chip, chip set thereof and display module

Abstract

The invention provides a light-emitting diode chip, a chip set thereof and a display module, and relates to the technical field of semiconductors, and the light-emitting diode chip comprises an N-type electrode, a P-type electrode and a light-emitting layer. The light-emitting layer comprises a first light-emitting layer with a first light-emitting wavelength and a second light-emitting layer with a second light-emitting wavelength, and the first light-emitting wavelength is smaller than the second light-emitting wavelength; at least part of the first light-emitting layer and at least part of the second light-emitting layer are stacked, the first light-emitting layer is located on the side, close to the P-type electrode, of the second light-emitting layer, and light emitted by the first light-emitting layer is used for exciting the second light-emitting layer to emit light. The light-emitting diode chip has two light-emitting mechanisms of photoluminescence and electroluminescence at the same time. According to the invention, the sizes of the light-emitting diode chips and the full-color chip set can be flexibly adjusted, and the transfer number and transfer difficulty in mass transfer are reduced, so that the problems of process, yield and cost represented by mass transfer in ultra-high-density pixel display products can be solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technologies, and particularly to a light-emitting diode chip, a chipset thereof, and a display module. Background Art

[0002] In semiconductor lighting technologies, a light-emitting diode (LED), as a light-emitting device that converts electrical energy into light energy, has advantages such as energy conservation, environmental protection, long service life, and high luminous efficiency, and is widely used in many fields such as indication, display, decoration, and lighting.

[0003] When an LED is applied to the display field, an ultra-high density display product mainly based on a micro light-emitting diode (micro LED) usually forms a pixel unit with three independent single chips, that is, a pixel unit is composed of three single-core monochromatic single sub-pixels. The number of chips in the micro LED is extremely large and the chip size is small. In the manufacturing process of the micro LED, a mass transfer process needs to be used.

[0004] However, the above-mentioned manufacturing process of the micro LED has problems of high process difficulty, low yield, and high cost. Summary of the Invention

[0005] The present application provides a light-emitting diode chip, a chipset thereof, and a display module, which can flexibly adjust the sizes of the light-emitting diode chip and the full-color chipset, reduce the transfer quantity and transfer difficulty in mass transfer, and thus can overcome problems such as processes, yield, and cost represented by mass transfer in ultra-high density pixel display products.

[0006] In a first aspect, the present application provides a light-emitting diode chip, including an N-type electrode, a P-type electrode, and a light-emitting layer disposed between the N-type electrode and the P-type electrode; the light-emitting layer is electrically connected to the N-type electrode and the P-type electrode respectively.

[0007] The light-emitting layer includes a first light-emitting layer having a first emission wavelength and a second light-emitting layer having a second emission wavelength, and the first emission wavelength is less than the second emission wavelength; along the thickness direction of the light-emitting diode chip, at least a part of the first light-emitting layer and at least a part of the second light-emitting layer are stacked; in the stacked first light-emitting layer and second light-emitting layer, the first light-emitting layer is located on the side of the second light-emitting layer close to the P-type electrode, and the light emitted by the first light-emitting layer is used to excite the second light-emitting layer to emit light.

[0008] The first light-emitting layer and the second light-emitting layer are used to form at least two side-by-side arranged sub-pixels, and the at least two sub-pixels include a first sub-pixel having a first emission wavelength and a second sub-pixel having a second emission wavelength.

[0009] In a second aspect, the present application provides a light-emitting diode chip group, including a plurality of the above-mentioned light-emitting diode chips, and the plurality of light-emitting diode chips are arranged in an array;

[0010] Two adjacent light-emitting diode chips include a first light-emitting diode chip and a second light-emitting diode chip, and a partial number of sub-pixels of the first light-emitting diode chip and a partial number of sub-pixels of the second light-emitting diode chip together form a pixel unit.

[0011] In a third aspect, the present application provides a display module, including a driving backplane and the above-mentioned light-emitting diode chip group, the light-emitting diode chip group is disposed on the driving backplane and electrically connected to the driving backplane.

[0012] For the light-emitting diode chip, its chip group, and the display module provided by the present application, by placing the light-emitting layer between the N-type electrode and the P-type electrode and electrically conducting with both, electrons provided by the N-type electrode and holes provided by the P-type electrode are combined in the light-emitting layer to excite the light-emitting material in the light-emitting layer to emit light. The light-emitting layer includes a first light-emitting layer with a first light-emitting wavelength and a second light-emitting layer with a second light-emitting wavelength, and the first light-emitting wavelength is less than the second light-emitting wavelength. In the stacked first light-emitting layer and at least a part of the second light-emitting layer, the first light-emitting layer is located on the side of the second light-emitting layer close to the P-type electrode, and the light emitted by the first light-emitting layer is used to excite the second light-emitting layer to emit light, so that the light-emitting diode chip of the present application has both electroluminescence and photoluminescence mechanisms. The present application adopts a single-core dual-color multi-sub-pixel arrangement method, that is, at least two sub-pixels are used to form a pixel subgroup, and full-color pixel units are formed by arranging the pixel subgroups, thereby forming a full-color chip group. The present application can flexibly adjust the size of the light-emitting diode chip and the full-color chip group, reduce the transfer operation difficulty in the mass transfer process, and can reduce the number of mass transfers, thereby overcoming problems such as process, yield, and cost represented by mass transfer in ultra-high-density pixel display products.

[0013] The structure of the present application and its other invention purposes and beneficial effects will become more obvious and understandable through the description of the preferred embodiments in conjunction with the drawings. Description of the Drawings

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required to be used in the description of the embodiments or the prior art. Obviously, the following drawings are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0015] Figure 1 It is a top view of the first light-emitting diode chip provided by the embodiment of the present application;

[0016] Figure 2 A cross-sectional view of the first light-emitting diode chip provided by an embodiment of the present application;

[0017] Figure 3 A top view of the second light-emitting diode chip provided by an embodiment of the present application;

[0018] Figure 4 A cross-sectional view of the second light-emitting diode chip provided by an embodiment of the present application;

[0019] Figure 5 A top view of the third light-emitting diode chip provided by an embodiment of the present application;

[0020] Figure 6 A cross-sectional view of the third light-emitting diode chip provided by an embodiment of the present application;

[0021] Figure 7 A top view of the fourth light-emitting diode chip provided by an embodiment of the present application;

[0022] Figure 8 A cross-sectional view of the fourth light-emitting diode chip provided by an embodiment of the present application;

[0023] Figure 9 A cross-sectional view of the first light-emitting diode chip provided by an embodiment of the present application, with a reflective layer, a hole blocking layer, and a light blocking member provided;

[0024] Figure 10 A cross-sectional view of the fifth light-emitting diode chip provided by an embodiment of the present application;

[0025] Figure 10 (a) A cross-sectional view of the fifth light-emitting diode chip provided by an embodiment of the present application, without a second light filtering layer provided;

[0026] Figure 11 A cross-sectional view of the sixth light-emitting diode chip provided by an embodiment of the present application;

[0027] Figure 11 (a) A cross-sectional view of the sixth light-emitting diode chip provided by an embodiment of the present application, without a second light filtering layer provided;

[0028] Figure 12 A cross-sectional view of the seventh light-emitting diode chip provided by an embodiment of the present application;

[0029] Figure 12 (a) A cross-sectional view of the seventh light-emitting diode chip provided by an embodiment of the present application, without a second light filtering layer provided;

[0030] Figure 13A cross-sectional view of the fifth light-emitting diode chip provided by the embodiment of the present application, with a reflective layer, a hole blocking layer, and a light blocking member;

[0031] Figure 14 A top view of the eighth light-emitting diode chip provided by the embodiment of the present application;

[0032] Figure 15 A cross-sectional view of the eighth light-emitting diode chip provided by the embodiment of the present application;

[0033] Figure 16 A cross-sectional view of the ninth light-emitting diode chip provided by the embodiment of the present application;

[0034] Figure 17 A top view of the tenth light-emitting diode chip provided by the embodiment of the present application;

[0035] Figure 18 A cross-sectional view of the tenth light-emitting diode chip provided by the embodiment of the present application;

[0036] Figure 19 A top view of the eleventh light-emitting diode chip provided by the embodiment of the present application;

[0037] Figure 20 A cross-sectional view of the eleventh light-emitting diode chip provided by the embodiment of the present application;

[0038] Figure 21 A cross-sectional view of the twelfth light-emitting diode chip provided by the embodiment of the present application;

[0039] Figure 22 A cross-sectional view of the eighth light-emitting diode chip provided by the embodiment of the present application, with a reflective layer, a hole blocking layer, and a light blocking member;

[0040] Figure 23 A cross-sectional view of the thirteenth light-emitting diode chip provided by the embodiment of the present application;

[0041] Figure 24 A top view of the fourteenth light-emitting diode chip provided by the embodiment of the present application;

[0042] Figure 25 A top view of the fifteenth light-emitting diode chip provided by the embodiment of the present application;

[0043] Figure 26 A cross-sectional view of the thirteenth light-emitting diode chip provided by the embodiment of the present application, with a reflective layer, a hole blocking layer, and a light blocking member;

[0044] Figure 27 A top view of the sixteenth light-emitting diode chip provided by the embodiment of the present application;

[0045] Figure 28 The top view of the seventeenth light-emitting diode chip provided by the embodiment of the present application;

[0046] Figure 29 The top view of the eighteenth light-emitting diode chip provided by the embodiment of the present application;

[0047] Figure 30 The top view of the nineteenth light-emitting diode chip provided by the embodiment of the present application;

[0048] Figure 31 The top view of the twentieth light-emitting diode chip provided by the embodiment of the present application;

[0049] Figure 32 The top view of the twenty-first light-emitting diode chip provided by the embodiment of the present application;

[0050] Figure 33 The cross-sectional view of the twenty-first light-emitting diode chip provided by the embodiment of the present application;

[0051] Figure 34 The top view of the twenty-second light-emitting diode chip provided by the embodiment of the present application;

[0052] Figure 35 The top view of the twenty-third light-emitting diode chip provided by the embodiment of the present application;

[0053] Figure 36 The top view of the twenty-fourth light-emitting diode chip provided by the embodiment of the present application;

[0054] Figure 37 The first integrated structure schematic diagram of the light-emitting diode chip provided by the embodiment of the present application;

[0055] Figure 38 The second integrated structure schematic diagram of the light-emitting diode chip provided by the embodiment of the present application;

[0056] Figure 39 The third integrated structure schematic diagram of the light-emitting diode chip provided by the embodiment of the present application;

[0057] Figure 40 The fourth integrated structure schematic diagram of the light-emitting diode chip provided by the embodiment of the present application;

[0058] Figure 41 The structural flowchart of the first preparation method of the light-emitting diode chip provided by the embodiment of the present application;

[0059] Figure 42 The structural flowchart of the second preparation method of the light-emitting diode chip provided by the embodiment of the present application;

[0060] Figure 43 Structural flowchart of the third preparation method of the light-emitting diode chip provided by the embodiment of the present application;

[0061] Figure 44 Structural flowchart of the fourth preparation method of the light-emitting diode chip provided by the embodiment of the present application;

[0062] Figure 45 Schematic structural diagram of the light-emitting diode chip provided by the embodiment of the present application with a light conversion layer provided;

[0063] Figure 46 Schematic structural diagram of the first type of the light-emitting diode chip group provided by the embodiment of the present application;

[0064] Figure 47 Schematic structural diagram of the second type of the light-emitting diode chip group provided by the embodiment of the present application;

[0065] Figure 48 Schematic structural diagram of the third type of the light-emitting diode chip group provided by the embodiment of the present application;

[0066] Figure 49 Schematic structural diagram of the fourth type of the light-emitting diode chip group provided by the embodiment of the present application;

[0067] Figure 50 Schematic structural diagram of the fifth type of the light-emitting diode chip group provided by the embodiment of the present application;

[0068] Figure 51 Schematic structural diagram of the sixth type of the light-emitting diode chip group provided by the embodiment of the present application;

[0069] Figure 52 Schematic structural diagram of the seventh type of the light-emitting diode chip group provided by the embodiment of the present application;

[0070] Figure 53 Schematic structural diagram of the eighth type of the light-emitting diode chip group provided by the embodiment of the present application;

[0071] Figure 54 Schematic structural diagram of the ninth type of the light-emitting diode chip group provided by the embodiment of the present application;

[0072] Figure 55 Schematic structural diagram of the tenth type of the light-emitting diode chip group provided by the embodiment of the present application;

[0073] Figure 56 Schematic structural diagram of the eleventh type of the light-emitting diode chip group provided by the embodiment of the present application;

[0074] Figure 57 Schematic structural diagram of the twelfth type of the light-emitting diode chip group provided by the embodiment of the present application;

[0075] Figure 58 The thirteenth structural schematic diagram of the light-emitting diode chip group provided by the embodiment of the present application;

[0076] Figure 59 The fourteenth structural schematic diagram of the light-emitting diode chip group provided by the embodiment of the present application;

[0077] Figure 60 The fifteenth structural schematic diagram of the light-emitting diode chip group provided by the embodiment of the present application;

[0078] Figure 61 The sixteenth structural schematic diagram of the light-emitting diode chip group provided by the embodiment of the present application;

[0079] Figure 62 The seventeenth structural schematic diagram of the light-emitting diode chip group provided by the embodiment of the present application;

[0080] Figure 63 The first size diagram of the light-emitting diode chip group provided by the embodiment of the present application;

[0081] Figure 63 (a) The size diagram of the chip group of the light-emitting diode chip provided by the embodiment of the present application having multiple sub-pixels along the first direction;

[0082] Figure 64 The second size diagram of the light-emitting diode chip group provided by the embodiment of the present application;

[0083] Figure 65 The third size diagram of the light-emitting diode chip group provided by the embodiment of the present application;

[0084] Figure 66 The fourth size diagram of the light-emitting diode chip group provided by the embodiment of the present application;

[0085] Figure 67 The fifth size diagram of the light-emitting diode chip group provided by the embodiment of the present application;

[0086] Figure 68 The eighteenth structural schematic diagram of the light-emitting diode chip group provided by the embodiment of the present application;

[0087] Figure 69 The nineteenth structural schematic diagram of the light-emitting diode chip group provided by the embodiment of the present application;

[0088] Figure 70 The first structural schematic diagram of the display module provided by the embodiment of the present application;

[0089] Figure 71A second structural schematic diagram of the display module provided in an embodiment of the present application.

[0090] Description of reference numerals:

[0091] 100, substrate; 101, buffer layer; 102, N-type electrode; 103, N-type semiconductor layer; 104, P-type electrode; 105, P-type semiconductor layer; 106, current spreading layer; 107, reflective layer; 108, first insulating layer; 109, second insulating layer; 110, bonding substrate; 111, binding layer; 112, color conversion layer; 114, first filter layer; 115, second filter layer; 116, isolation material; 117, hole blocking layer; 118, light blocking layer; 119a, first light-emitting layer; 119b, second light-emitting layer; 119c, third light-emitting layer; 200, driving backplane; 201, driving substrate; 202, driving unit. DETAILED DESCRIPTION

[0092] In LED display products, three single-core monochrome single-sub-pixel chips are usually used to form a pixel unit. The size of a single chip in ultra-high-density display products represented by micro LED is relatively small, and the number of chips that make up the display product is relatively large. In the manufacturing process of display products, micro LED chips need to be grown on wafers, and then transferred to a specific substrate through mass transfer technology to complete the binding assembly. In the mass transfer process, due to the small size and large number of chips, the transfer operation is difficult, the number of operations is numerous, and the operation alignment requirements on the substrate are high. As a result, the manufacturing process of micro LED display products is difficult, the yield is low, the production cycle is long, and the cost is high.

[0093] In related technologies, in LED display products, several chips are packaged together through the MIP (Micro LED in Package) packaging process to form an integrated chipset that can emit multiple wavelengths. The traditional MIP packaging process is suitable for LED display products with pixel sizes greater than 0.3 mm. Due to the limitations of existing mass transfer technology capabilities, the MIP packaging process requires that the single-core monochrome single-sub-pixel chip used must be larger, that is, the sub-pixel size is larger. A single chipset is usually an RGB pixel unit, and there are a large number of chips and chipsets used on the application side.

[0094] The light-emitting diode chip, chip set, and display module provided by the present application. In the light-emitting diode chip, a light-emitting layer is disposed between an N-type electrode and a P-type electrode and electrically connected to both of them, so that electrons provided by the N-type electrode and holes provided by the P-type electrode combine in the light-emitting layer, and the light-emitting material in the light-emitting layer is excited to emit light. There is a first light-emitting layer with a first emission wavelength and a second light-emitting layer with a second emission wavelength, and the first emission wavelength is less than the second emission wavelength. In the stacked first light-emitting layer and at least a part of the second light-emitting layer, the first light-emitting layer is located on the side of the second light-emitting layer closer to the P-type electrode, and the light emitted by the first light-emitting layer is used to excite the second light-emitting layer to emit light, so that the light-emitting diode chip of the present application has both electroluminescence and photoluminescence mechanisms. The present application adopts an arrangement method of single-core dual-color multi-subpixels, that is, at least two subpixels are used to form a pixel subgroup, and full-color pixel units are formed by arranging the pixel subgroups, so as to form a full-color chip set. The present application can flexibly adjust the sizes of the light-emitting diode chip and the full-color chip set, reduce the difficulty of transfer operations in the mass transfer process, and can reduce the number of mass transfers, thereby overcoming problems such as process, yield, and cost in ultra-high-density pixel display products represented by mass transfer.

[0095] Compared with the integrated chip set that emits multiple wavelengths formed by integrating several chips in the related art, the related art needs to overcome the process difficulties of integrating multiple chips, so the process difficulty is relatively large, the yield is relatively low, and the cost is relatively high. The present application directly obtains dual-color multi-subpixels in a single light-emitting diode chip, the process is simpler, the technical difficulty is smaller, and the cost is lower.

[0096] Furthermore, by using the light-emitting diode chip with single-core dual-color multi-subpixels of the present application to form a light-emitting diode chip set, under the condition of the same light-emitting area and the same pixel density (Pixels Per Inch, abbreviated as PPI), it is possible to flexibly adjust the size of the light-emitting diode chip while ensuring that the subpixel size is relatively small, and at the same time, the number of light-emitting diode chips is greatly reduced, so as to overcome problems such as relatively large preparation process difficulty, relatively low product yield, and relatively high preparation cost, which helps to promote the mass production of mini LED and micro LED as soon as possible.

[0097] When the light-emitting diode chip with single-core dual-color multi-subpixels of the present application is used to form a full-color integrated chip set (for example, taking three 2*n combined chips to form a chip set as an example), n*2 pixel units can be obtained. When combined with the backplane, the chip set used is 1 / 2n of the traditional MIP package, which greatly reduces the preparation time, reduces the process and raw material costs, and at the same time greatly improves the yield. Furthermore, the pixel size applicable to the full-color integrated package of the present application can be flexibly adjusted and can be much smaller than the pixel size applicable to the traditional MIP process.

[0098] To make the objectives, technical solutions, and advantages of this application clearer, the following will describe the technical solutions in the embodiments of this application in more detail in conjunction with the accompanying drawings in the preferred embodiments of this application. In the accompanying drawings, the same or similar reference numerals represent the same or similar components or components with the same or similar functions from beginning to end. The described embodiments are some, but not all, of the embodiments of this application. The embodiments described below by referring to the accompanying drawings are exemplary and are intended to explain this application and should not be construed as a limitation of this application. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of this application. The following will explain the embodiments of this application in detail with reference to the accompanying drawings.

[0099] In this application, some terms can be understood as having the following meanings:

[0100] Sub pixel (abbreviated as SP): A single blue light pixel, or a single green light pixel, or a single red light pixel is called a sub pixel. In this patent, a sub pixel can also be a single arbitrary wavelength.

[0101] Pixel subgroup (abbreviated as PSG): A combination formed by multiple sub pixels.

[0102] Pixel unit (abbreviated as PU): A unit including the three primary colors of blue light sub pixels, green light sub pixels, and red light sub pixels, or including other three or more different wavelengths and sub pixels that can form white light.

[0103] Single-core monochromatic single-sub pixel chip: A single light-emitting diode chip can only emit one wavelength of light and only contains one sub pixel, such as one blue light sub pixel, or one green light sub pixel, or one red light sub pixel.

[0104] Single-core monochromatic multi-sub pixel chip: A single chip can only emit one wavelength of light, but contains two or more sub pixels, such as two red light sub pixels, three red light sub pixels, or more red light sub pixels.

[0105] Single-core two-color multi-sub pixel chip: A single chip can emit two different wavelengths of light and contains two or more sub pixels, such as one red light sub pixel + one green light sub pixel, two red light sub pixels + two green light sub pixels, multiple blue light sub pixels + multiple red light sub pixels, multiple green light sub pixels + multiple blue light sub pixels, or multiple green light sub pixels + multiple red light sub pixels.

[0106] Light-emitting diode chip (abbreviated as C): A solid-state semiconductor device with a light-emitting layer between a P-type electrode and an N-type electrode.

[0107] Light-emitting diode chip group (abbreviated as CG): Composed of two or more single-core dual (single)-color multi-sub-pixel chips, including one or more pixel units.

[0108] Microdisplay module (abbreviated as DMB): A display device formed by electrically connecting a light-emitting diode chip group and a driving backplane.

[0109] Electro-luminescence (abbreviated as EL): When an electric current passes through a P-type semiconductor and an N-type semiconductor, holes generated in the P-type semiconductor and electrons generated in the N-type semiconductor recombine in the light-emitting layer to emit light.

[0110] Photo-luminescence (abbreviated as PL): Light emitted by exciting the light-emitting layer with light.

[0111] In a first aspect, an embodiment of the present application provides a light-emitting diode chip. Referring to Figures 1 - 21 as shown, the light-emitting diode chip includes an N-type electrode, a P-type electrode, and a light-emitting layer disposed between the N-type electrode and the P-type electrode; the light-emitting layer is electrically connected to the N-type electrode and the P-type electrode respectively.

[0112] The light-emitting layer includes a first light-emitting layer 119a having a first light-emitting wavelength and a second light-emitting layer 119b having a second light-emitting wavelength, and the first light-emitting wavelength is less than the second light-emitting wavelength; along the thickness direction of the light-emitting diode chip, at least a part of the first light-emitting layer 119a and at least a part of the second light-emitting layer 119b are stacked; in the stacked first light-emitting layer 119a and second light-emitting layer 119b, the first light-emitting layer 119a is located on the side of the second light-emitting layer 119b close to the P-type electrode, and the light emitted by the first light-emitting layer 119a is used to excite the second light-emitting layer 119b to emit light;

[0113] The first light-emitting layer 119a and the second light-emitting layer 119b are used to form at least two side-by-side arranged sub-pixels, and the at least two sub-pixels include a first sub-pixel having a first light-emitting wavelength and a second sub-pixel having a second light-emitting wavelength.

[0114] It should be noted that an electric field is formed between the N-type electrode and the P-type electrode, and the light-emitting layer is disposed between the N-type electrode and the P-type electrode, which can be understood that the light-emitting layer is located in this electric field. Referring to Figure 2 、 4As shown in 6, 8, 9, 10 - 13, 15, 16, 18, and 20 - 25, in the thickness direction of the chip, all or part of the thickness of the light - emitting layer is located between the N - type electrode and the P - type electrode. The light - emitting layer is electrically connected to the N - type electrode and the P - type electrode respectively, which may mean that the light - emitting layer is in contact conduction with the N - type electrode and the P - type electrode respectively, or the light - emitting layer is electrically connected to the N - type electrode through the N - type semiconductor layer 103 and is electrically connected to the P - type electrode through the P - type semiconductor layer 105.

[0115] Among them, on the basis that the first emission wavelength is less than the second emission wavelength, the first light - emitting layer 119a and the second light - emitting layer 119b are any two of a red - light - emitting material layer, a green - light - emitting material layer, a blue - light - emitting material layer, a violet - light - emitting material layer, and an ultraviolet - light - emitting material layer.

[0116] Exemplarily, the first light - emitting layer is a green - light - emitting material layer and the second light - emitting layer is a red - light - emitting material layer; or, the first light - emitting layer is a blue - light - emitting material layer and the second light - emitting layer is a green - light - emitting material layer or a red - light - emitting material layer; or, the first light - emitting layer is a violet - light - emitting material layer and the second light - emitting layer is a blue - light - emitting material layer, a green - light - emitting material layer, or a red - light - emitting material layer.

[0117] Correspondingly, on the basis that the first emission wavelength is less than the second emission wavelength, the two sub - pixels formed by the first light - emitting layer and the second light - emitting layer can be any two of a red - photon sub - pixel (R), a green - photon sub - pixel (G), a blue - photon sub - pixel (B), an ultraviolet - photon sub - pixel (UVA), or a violet - photon sub - pixel (Pur).

[0118] Exemplarily, the first sub - pixel is a green - photon sub - pixel and the second sub - pixel is a red - photon sub - pixel (i.e., G + R). Or, the first sub - pixel is a blue - photon sub - pixel and the second sub - pixel is a green - photon sub - pixel (i.e., B + G). Or, the first sub - pixel is a blue - photon sub - pixel and the second sub - pixel is a red - photon sub - pixel (i.e., B + R). Or, the first sub - pixel is a violet - photon sub - pixel and the second sub - pixel is a blue - photon sub - pixel (i.e., Pur + B). Or, the first sub - pixel is a violet - photon sub - pixel and the second sub - pixel is a red - photon sub - pixel (i.e., Pur + R). Or, the first sub - pixel is a violet - photon sub - pixel and the second sub - pixel is a green - photon sub - pixel (i.e., Pur + G). Or, the first sub - pixel is an ultraviolet - photon sub - pixel and the second sub - pixel is a blue - photon sub - pixel (i.e., UVA + B), as Figure 31 and Figure 32 shown.

[0119] In the embodiments of the present application, taking the first emission wavelength as the blue - light wavelength, the first light - emitting layer as the blue - light - emitting material layer, the first sub - pixel as the blue - photon sub - pixel (B), the second emission wavelength as the green - light wavelength, the second light - emitting layer as the green - light - emitting material layer, and the second sub - pixel as the green - photon sub - pixel (G) as an example, the following description is given.

[0120] In this application, a light-emitting diode chip is formed by combining two sub-pixels with different emission wavelengths, that is, a single-core dual-color multi-sub-pixel arrangement is adopted. Compared with the related art that uses a single sub-pixel to form a chip, this application can flexibly adjust the size of the light-emitting diode chip, reduce the transfer difficulty and alignment difficulty in the mass transfer operation. Moreover, it can effectively reduce the number of light-emitting diode chips required for display products with the same light-emitting area and the same pixel density, thereby reducing the complexity of the mass transfer operation and the manufacturing cost. In this way, the yield of products with ultra-high density pixel display can also be improved.

[0121] Next, the structure and light-emitting mechanism of the light-emitting diode chip according to the embodiments of this application will be described.

[0122] Referring to Figure 1 and Figure 2 As shown, for the light-emitting diode chip of the first structure, the entire first light-emitting layer 119a and the entire second light-emitting layer 119b are stacked; the surface of the first light-emitting layer 119a facing away from the second light-emitting layer 119b is electrically connected to the P-type electrode, and the surface of the second light-emitting layer 119b facing away from the first light-emitting layer 119a is electrically connected to the N-type electrode.

[0123] The first light-emitting layer 119a includes a first region and a second region arranged side by side and spaced apart, and the second light-emitting layer 119b includes a third region and a fourth region arranged side by side and spaced apart; the first region and the third region are opposite to each other and are used to form a first sub-pixel, and the second region and the fourth region are opposite to each other and are used to form a second sub-pixel.

[0124] It should be noted that the first region and the second region of the first light-emitting layer 119a can be two regions arranged side by side along the thickness direction perpendicular to the light-emitting diode chip. The same applies to the third region and the fourth region. For example, Figure 2 in the first region can be the part of the first light-emitting layer 119a close to the left side, the second region can be the part of the first light-emitting layer 119a close to the right side, the third region can be the part of the second light-emitting layer 119b close to the left side, and the fourth region can be the part of the second light-emitting layer 119b close to the right side. In other embodiments, the positions of the first region and the second region can be interchanged, and the positions of the third region and the fourth region can also be interchanged.

[0125] In this application, "side by side" or "side-by-side arrangement" can mean that the two are corresponding to each other along the thickness direction perpendicular to the light-emitting diode chip, that is, the two are at the same thickness position of the light-emitting diode chip; it can also mean that the two are on the same layer of the light-emitting diode chip, and the two are misaligned in the thickness direction of the light-emitting diode chip can also be considered side by side or side-by-side arrangement.

[0126] The light-emitting diode chip of this embodiment further includes a first filter layer CF1 and a second filter layer CF2 arranged side by side. The first filter layer CF1 corresponds to the first region, and the second filter layer CF2 corresponds to the second region. Both the first filter layer CF1 and the second filter layer CF2 are located on the light-emitting side of the light-emitting diode. The passing wavelength of the first filter layer CF1 is the first emission wavelength, and the passing wavelength of the second filter layer CF2 is the second emission wavelength.

[0127] The passing wavelength of the first filter layer CF1 is the first emission wavelength, that is, among the light rays emitted by the first light-emitting layer 119a and the second light-emitting layer 119b, only the light rays with the first emission wavelength can pass through the first filter layer CF1. Similarly, only the light rays with the second emission wavelength can pass through the second filter layer CF2. In this way, the light-emitting diode chip can emit light rays with two different wavelengths.

[0128] It should be noted that the filter layer can be a color filter, or a Bragg reflector (or, distributed Bragg reflector, abbreviated as DBR). The Bragg reflector can also filter the wavelength of the passing light rays, so as to emit light rays with different wavelengths. The Bragg reflector can be alternately stacked with two materials of aluminum nitride and gallium nitride, or alternately stacked with two materials of titanium oxide and silicon oxide, or alternately stacked with two materials of silicon oxide and silicon nitride. Optionally, the thickness of the Bragg reflector is 2-6 micrometers. In other embodiments, this thickness value can be adjusted as needed, and this application does not limit it.

[0129] Combined with Figure 9 As shown, the light-emitting diode chip of this embodiment further includes a reflective layer 107, and the reflective layer 107 is located on the backlight side of the light-emitting diode chip. The reflective layer 107 is arranged on the backlight side, which can ensure that the light rays are emitted from the light-emitting side. Figure 9 The reflective layer 107 shown in [reference] is located on the side of the P-type electrode facing away from the N-type electrode, and the side of the N-type electrode facing away from the P-type electrode forms the light-emitting side of the light-emitting diode chip. The reflective layer 107 can be a metal layer or a Bragg reflector. The above-mentioned first filter layer CF1 and second filter layer CF2 are arranged on the side of the N-type electrode facing away from the P-type electrode.

[0130] Continue to refer to Figure 9As shown, the light-emitting diode chip of this embodiment further includes a light-blocking layer 118. The light-blocking layer 118 is located on the light-emitting side of the light-emitting diode chip and between two adjacent sub-pixels. Based on the fact that the reflective layer 107 is disposed on the side of the P-type electrode facing away from the N-type electrode, the light-emitting side is restricted to the side of the N-type electrode facing away from the P-type electrode. Therefore, the light-blocking layer 118 in this embodiment is located on the side of the N-type electrode facing away from the P-type electrode. The light-blocking layer 118 can be made of a black resin material and has the function of absorbing and blocking light. The light-blocking layer 118 is located between two adjacent sub-pixels, that is, it can be located between the positions corresponding to the first region and the second region, or between the positions corresponding to the third region and the fourth region. In this way, the problem of light mixing between two sub-pixels can be avoided, and the light-emitting effect of the light-emitting diode chip can be ensured.

[0131] Based on the fact that the light-blocking layer 118, the first light-filtering layer CF1, and the second light-filtering layer CF2 are all disposed on the light-emitting side, the light-blocking layer 118 can be located between the first light-filtering layer CF1 and the second light-filtering layer CF2. In this way, both the light-filtering and light-blocking effects can be ensured, and the structural regularity of the light-emitting diode chip can also be ensured.

[0132] Continue to refer to Figure 9 As shown, the light-emitting diode chip of this embodiment further includes a hole-blocking layer 117. The hole-blocking layer 117 is disposed between any two adjacent layers of the stacked first light-emitting layer 119a, second light-emitting layer 119b, and third light-emitting layer 119c. The hole-blocking layer 117 can block the passage of holes, but allows electrons to pass through. The material of the hole-blocking layer 117 can be gallium nitride doped with silicon. The sum of the thicknesses of the hole-blocking layer 117 and the first light-emitting layer 119a can be greater than the diffusion length of holes, so that holes can be prevented from migrating to the second light-emitting layer 119b.

[0133] Refer to Figure 9 As shown, during the operation of the light-emitting diode chip, after the N-type electrode is energized, electrons can be provided, and after the P-type electrode is energized, holes can be provided. Among them, holes and electrons can migrate to the position where the first light-emitting layer 119a is located. After the holes and electrons recombine, light with a first emission wavelength can be emitted. Due to the presence of the hole-blocking layer 117, holes will not migrate to the position where the first light-emitting layer 119a is located. The light-emitting mechanism of the first light-emitting layer 119a is electroluminescence. The light with the first emission wavelength emitted by the first light-emitting layer 119a can excite the second light-emitting layer 119b to emit light, and the light-emitting mechanism of the second light-emitting layer 119b is photoluminescence. In summary, the light-emitting mechanism of the light-emitting diode chip with the first structure is a hybrid mechanism of electroluminescence and photoluminescence.

[0134] It should be noted that the reflective layer 107, the light-blocking layer 118, and the hole-blocking layer 117 in the light-emitting diode chip of the first structure can all be applied to the light-emitting diode chips of the following other structures, and are similar in structure and function to those in the light-emitting diode chip of the first structure, and will not be elaborated hereinafter.

[0135] In some other embodiments, during the operation of the light-emitting diode chip, after the N-type electrode and the P-type electrode are energized, holes and electrons can migrate to the position where the first light-emitting layer 119a is located. After the holes and electrons recombine, light with a first emission wavelength can be emitted. When no hole-blocking layer 117 is provided between the first light-emitting layer 119a and the second light-emitting layer 119b, and the thickness of the first light-emitting layer 119a is small and the thickness of the second light-emitting layer 119b is large, holes will also reach the position where the second light-emitting layer 119b is located. After the holes and electrons recombine, light with a second emission wavelength can be emitted. At this time, the light-emitting mechanism of the second light-emitting layer 119b is a hybrid mechanism of electroluminescence and photoluminescence.

[0136] In the light-emitting diode chip of the first structure described above, an isolation structure can also be provided. The isolation structure is located between the first region and the second region, and between the third region and the fourth region. It should be noted that in some embodiments, the isolation structure can only include a channel (Channel, abbreviated as CN), that is, the channel may not be filled with an isolation material. The channel can spatially isolate the first region and the second region, or the third region and the fourth region. Figure 7 and Figure 8 As shown, the channel CN is filled with an electrically insulating isolation material, such as silicon nitride or silicon oxide, etc. In some embodiments, the electrically insulating isolation material can also have a light-shielding effect, such as a black organic material, etc. In this way, the mixing of light between the first sub-pixel and the second sub-pixel can be reduced or avoided, and the light-emitting effect of the light-emitting diode chip can be improved. In some other embodiments, the isolation structure can also be an ion implantation layer, a structure with an electrical isolation effect and a light-blocking effect formed by an ion implantation process. In the following embodiments, the isolation structure is the same, and will not be elaborated hereinafter.

[0137] In Figure 1 、 Figure 2 and Figure 9 In the light-emitting diode chip shown, the first sub-pixel and the second sub-pixel formed are synchronously driven. In other embodiments, the first sub-pixel and the second sub-pixel can also be independently driven. The light-emitting diode chip that can be independently driven will be described below.

[0138] Combined with Figure 3 and Figure 4As shown in the figure, as the structure of the second light-emitting diode chip, the P-type electrode includes a first P-type electrode and a second P-type electrode that are separated from each other. The first P-type electrode is electrically connected to the surface of the third region facing away from the N-type electrode, and the second P-type electrode is electrically connected to the surface of the fourth region facing away from the N-type electrode; the isolation structure is also located between the first P-type electrode and the second P-type electrode.

[0139] When the first P-type electrode and the N-type electrode are in the energized state, the first region and the third region can be independently driven to emit light. When the second P-type electrode and the N-type electrode are in the energized state, the second region and the fourth region can be independently driven to emit light. In this way, the first sub-pixel and the second sub-pixel can emit light separately.

[0140] Combined Figures 5 - 8 As shown in the figure, as the structures of the third and fourth light-emitting diode chips, the N-type electrode includes a first N-type electrode and a second N-type electrode that are separated from each other. The first N-type electrode is electrically connected to the surface of the third region facing away from the P-type electrode, and the second N-type electrode is electrically connected to the surface of the fourth region facing away from the P-type electrode; the isolation structure is also located between the first N-type electrode and the second N-type electrode.

[0141] When the first N-type electrode and the P-type electrode are in the energized state, the first region and the third region can be independently driven to emit light. When the second N-type electrode and the P-type electrode are in the energized state, the second region and the fourth region can be independently driven to emit light. In this way, the first sub-pixel and the second sub-pixel can emit light separately.

[0142] The light-emitting diode chip further includes an N-type semiconductor layer 103 and a P-type semiconductor layer 105. The N-type semiconductor and the P-type semiconductor are respectively located on opposite sides of the light-emitting layer in the thickness direction. The N-type electrode is electrically connected to the light-emitting layer through the N-type semiconductor, and the P-type electrode is electrically connected to the light-emitting layer through the P-type semiconductor; in the above-mentioned structure with a discrete N-type electrode and a separated P-type electrode, the isolation structure can also be set as follows.

[0143] Referring to Figure 8 As shown in the figure, when the N-type electrode includes a first N-type electrode and a second N-type electrode that are separated from each other, at least part of the isolation structure extends into the P-type semiconductor layer 105. Alternatively, when the P-type electrode includes a first P-type electrode and a second P-type electrode that are separated from each other, at least part of the isolation structure extends into the N-type semiconductor layer 103 (not shown). In this way, both the process difficulty can be reduced and the isolation effect of the isolation structure on the first sub-pixel and the second sub-pixel can be improved.

[0144] Referring to Figures 10 - 13As shown, in the light-emitting diode chip, the first light-emitting layer 119a includes a first region and a second region. The first region and at least a part of the thickness of the second region are arranged side by side between the N-type electrode and the P-type electrode; the first region is stacked with the second light-emitting layer 119b and is used to form a second sub-pixel; the second region is used to form a first sub-pixel.

[0145] The surface of the first region facing away from the second light-emitting layer 119b is electrically connected to the P-type electrode, the surface of the second light-emitting layer 119b facing away from the first region is electrically connected to the N-type electrode, and the second region is electrically connected to the P-type electrode and the N-type electrode respectively.

[0146] It should be noted that the first region and at least a part of the thickness of the second region are arranged side by side, and the first region and the second light-emitting layer 119b are stacked. When both the N-type electrode and the P-type electrode are in the energized state, the first region and the second region emit light through the recombination of electrons and holes, and the light-emitting mechanism of both is electroluminescence. The light emitted by the first region can stimulate the second light-emitting layer 119b stacked therewith to emit light, and the light-emitting mechanism of the second light-emitting layer 119b is photoluminescence.

[0147] In the above-mentioned light-emitting diode chip, a filter layer is further provided on the light-emitting side of the light-emitting diode. The filter layer corresponds to the first region, and the passing wavelength of the filter layer is the second emission wavelength. The filter layer can allow the light of the second emission wavelength to pass through. In this way, the second sub-pixel corresponding to the first region can emit light of the second emission wavelength, and the one corresponding to the second region directly emits light with the first emission wavelength.

[0148] Refer to Figure 13 As shown, a reflective layer 107 is further provided on the backlight side of the light-emitting diode chip. The reflective layer 107 is located on the side of the P-type electrode facing away from the N-type electrode, and the side of the N-type electrode facing away from the P-type electrode is the light-emitting side of the light-emitting diode chip.

[0149] A light-blocking layer 118 is further provided on the light-emitting side of the light-emitting diode chip. The light-blocking layer 118 is located between two adjacent sub-pixels. The light-blocking layer 118 can avoid the problem of light mixing between the two sub-pixels and ensure the light-emitting effect of the light-emitting diode chip. Based on the fact that the filter layer is located on the light-emitting side of the light-emitting diode chip, the light-blocking layer 118 can be arranged side by side with the filter layer.

[0150] A hole-blocking layer 117 is provided between the first region of the first light-emitting layer 119a and the second light-emitting layer 119b of the light-emitting diode chip. The sum of the thickness of the hole-blocking layer 117 and the first light-emitting layer 119a can be greater than the diffusion length of holes. In this way, the hole-blocking layer 117 can block the migration of holes into the second light-emitting layer 119b.

[0151] Refer to Figure 10As shown, as a first implementable embodiment, the first region and the second region with a partial thickness are arranged side by side, and the second light-emitting layer 119b is arranged side by side with another second region with a partial thickness.

[0152] In the above embodiment, the light-emitting diode chip further includes an isolation structure, which is located between the first region and the second region arranged side by side, and between the second light-emitting layer 119b and the second region arranged side by side. The isolation structure can form a structural and electrical isolation between the first region and the second region arranged side by side, and between the second light-emitting layer 119b and the second region arranged side by side, so as to ensure the light-emitting effect of the light-emitting diode. Among them, on the side of the N-type electrode facing away from the P-type electrode, that is, on the light-emitting side of the light-emitting diode chip, a second filter layer CF2 is provided, and the second filter layer CF2 is opposite to the second light-emitting layer 119b.

[0153] Refer to Figure 10 (a) As shown, in some other embodiments, the second filter layer CF2 may not be provided on the light-emitting side of the light-emitting diode chip.

[0154] Combined with Figure 12 As shown, as a second implementable embodiment, the first region and the second region with a full thickness are arranged side by side, and the second light-emitting layer 119b is arranged side by side with the N-type electrode with a partial thickness. The light-emitting diode chip further includes an isolation structure, which is located between the first region and the second region, and between the second light-emitting layer 119b and the N-type electrode arranged side by side. The isolation structure can form a structural and electrical isolation between the first region and the second region arranged side by side, and between the second light-emitting layer 119b and the N-type electrode arranged side by side, so as to ensure the light-emitting effect of the light-emitting diode.

[0155] The first sub-pixel and the second sub-pixel formed by the above light-emitting diode chip can be driven synchronously. In other embodiments, the first sub-pixel and the second sub-pixel can also be driven independently. The light-emitting diode chip that can be independently driven will be described below.

[0156] Refer to Figure 11As shown, the P-type electrode includes a first P-type electrode and a second P-type electrode that are discrete from each other. The first P-type electrode electrically conducts the surface of the first region facing away from the N-type electrode, and the second P-type electrode electrically conducts the surface of the second region facing away from the N-type electrode; the isolation structure is also located between the first P-type electrode and the second P-type electrode. When the first P-type electrode and the N-type electrode are in the energized state, the first region and the second light-emitting layer 119b can be independently driven to emit light. When the second P-type electrode and the N-type electrode are in the energized state, the second region can be independently driven to emit light. In this way, the first sub-pixel and the second sub-pixel can emit light separately. Among them, on the side of the N-type electrode facing away from the P-type electrode, that is, on the light-emitting side of the light-emitting diode chip, a second filter layer CF2 is provided, and the second filter layer CF2 is opposite to the second light-emitting layer 119b.

[0157] Referring to Figure 11 (a) As shown, in some other embodiments, the second filter layer CF2 may not be provided on the light-emitting side of the light-emitting diode chip.

[0158] Referring to Figure 12 As shown, the N-type electrode includes a first N-type electrode and a second N-type electrode that are discrete from each other. The first N-type electrode electrically conducts the surface of the second light-emitting layer 119b facing away from the P-type electrode, and the second N-type electrode electrically conducts the surface of the second region facing away from the P-type electrode; the isolation structure is also located between the first N-type electrode and the second N-type electrode. When the first N-type electrode and the P-type electrode are in the energized state, the first region and the second light-emitting layer 119b can be independently driven to emit light. When the second N-type electrode and the P-type electrode are in the energized state, the second region can be independently driven to emit light. In this way, the first sub-pixel and the second sub-pixel can emit light separately. Among them, on the side of the N-type electrode facing away from the P-type electrode, that is, on the light-emitting side of the light-emitting diode chip, a second filter layer CF2 is provided, and the second filter layer CF2 is opposite to the second light-emitting layer 119b.

[0159] Referring to Figure 12 (a) As shown, in some other embodiments, the second filter layer CF2 may not be provided on the light-emitting side of the light-emitting diode chip.

[0160] Referring to Figures 14 - 21 As shown, the second light-emitting layer 119b includes a third region and a fourth region. The third region and at least a part of the thickness of the fourth region are arranged side by side between the N-type electrode and the P-type electrode; the third region is stacked with the first light-emitting layer 119a and is used to form the first sub-pixel; the fourth region is used to form the second sub-pixel.

[0161] The surface of the third region facing away from the first light-emitting layer 119a is electrically conducted with the N-type electrode, the surface of the first light-emitting layer 119a facing away from the third region is electrically conducted with the P-type electrode, and the fourth region is electrically conducted with the P-type electrode and the N-type electrode respectively.

[0162] It should be noted that the third region is arranged side by side with the fourth region having at least a part of its thickness, and the third region is stacked with the first light-emitting layer 119a. When both the N-type electrode and the P-type electrode are in the energized state, the first light-emitting layer 119a and the fourth region emit light through the recombination of electrons and holes, and the light-emitting mechanisms of both are electroluminescence. The light emitted by the first light-emitting layer 119a can excite the third region stacked therewith to emit light, and the light-emitting mechanism of the third region is photoluminescence.

[0163] In the above light-emitting diode chip, a filter layer is further provided on the light-emitting side of the light-emitting diode. The filter layer corresponds to the third region, and the passing wavelength of the filter layer is the first light-emitting wavelength. The filter layer can allow the light of the first light-emitting wavelength to pass through. In this way, the first sub-pixel corresponding to the third region can emit the light of the first light-emitting wavelength, and the second sub-pixel corresponding to the fourth region directly emits the light having the second light-emitting wavelength.

[0164] Refer to Figure 21 As shown, a reflective layer 107 is further provided on the backlight side of the light-emitting diode chip. The reflective layer 107 is located on the side of the P-type electrode facing away from the N-type electrode, and the side of the N-type electrode facing away from the P-type electrode is the light-emitting side of the light-emitting diode chip.

[0165] A light-blocking layer 118 is further provided on the light-emitting side of the light-emitting diode chip. The light-blocking layer 118 is located between two adjacent sub-pixels. The light-blocking layer 118 can avoid the problem of light mixing between the two sub-pixels and ensure the light-emitting effect of the light-emitting diode chip. Based on the fact that the filter layer is located on the light-emitting side of the light-emitting diode chip, the light-blocking layer 118 can be arranged side by side with the filter layer.

[0166] A hole-blocking layer 117 is provided between the third regions of the first light-emitting layer 119a and the second light-emitting layer 119b of the light-emitting diode chip. The sum of the thicknesses of the hole-blocking layer 117 and the first light-emitting layer 119a can be greater than the diffusion length of holes. In this way, the hole-blocking layer 117 can block the migration of holes into the third region.

[0167] Refer to Figure 16 As shown, as a first implementable embodiment, the third region is arranged side by side with a part of the thickness of the fourth region, and the first light-emitting layer 119a is arranged side by side with another part of the thickness of the fourth region.

[0168] In the above embodiment, the light-emitting diode chip further includes an isolation structure. The isolation structure is located between the third region and the fourth region arranged side by side, and between the first light-emitting layer 119a and the fourth region arranged side by side. The isolation structure can form a structural and electrical isolation between the third region and the fourth region arranged side by side, and between the first light-emitting layer 119a and the fourth region arranged side by side to ensure the light-emitting effect of the light-emitting diode.

[0169] Refer to Figure 15 As shown, the third region is arranged side by side with the fourth region of the entire thickness, and the first light-emitting layer 119a is arranged side by side with the P-type electrode of a partial thickness.

[0170] In the above embodiment, the light-emitting diode chip further includes an isolation structure, which is located between the third region and the fourth region, and between the first light-emitting layer 119a and the P-type electrode arranged side by side. The isolation structure can form a structural and electrical isolation between the third region and the fourth region arranged side by side, and between the first light-emitting layer 119a and the P-type electrode arranged side by side, so as to ensure the light-emitting effect of the light-emitting diode.

[0171] The first sub-pixel and the second sub-pixel formed by the above light-emitting diode chip can be driven synchronously. In other embodiments, the first sub-pixel and the second sub-pixel can also be driven independently. The light-emitting diode chip that can be independently driven will be described below.

[0172] Refer to Figure 18 As shown, the P-type electrode includes a first P-type electrode and a second P-type electrode that are separated from each other. The first P-type electrode is electrically connected to the surface of the first light-emitting layer 119a facing away from the N-type electrode, and the second P-type electrode is electrically connected to the surface of the fourth region facing away from the N-type electrode; the isolation structure is also located between the first P-type electrode and the second P-type electrode. When the first P-type electrode and the N-type electrode are in the energized state, the first light-emitting layer 119a and the third region can be independently driven to emit light. When the second P-type electrode and the N-type electrode are in the energized state, the fourth region can be independently driven to emit light. In this way, the first sub-pixel and the second sub-pixel can emit light separately. Among them, the light-emitting side of the light-emitting diode chip is located on the side of the N-type electrode facing away from the P-type electrode, and a first filter layer CF1 can be provided on the side of the N-type electrode facing away from the P-type electrode.

[0173] In some other embodiments, refer to Figure 19 As shown, the first filter layer CF1 may not be provided on the side of the N-type electrode facing away from the P-type electrode. At this time, the light-emitting layer of the light-emitting diode chip is located on the side of the P-type electrode facing away from the N-type electrode.

[0174] Refer to Figure 20 As shown, the N-type electrode includes a first N-type electrode and a second N-type electrode that are separated from each other. The first N-type electrode is electrically connected to the surface of the third region facing away from the P-type electrode, and the second N-type electrode is electrically connected to the surface of the fourth region facing away from the P-type electrode; the isolation structure is also located between the first N-type electrode and the second N-type electrode. When the first N-type electrode and the P-type electrode are in the energized state, the first light-emitting layer 119a and the third region can be independently driven to emit light. When the second N-type electrode and the P-type electrode are in the energized state, the fourth region can be independently driven to emit light. In this way, the first sub-pixel and the second sub-pixel can emit light separately.

[0175] Refer toFigures 23 - 26 As shown, the light-emitting layer further includes a third light-emitting layer 119c having a third light-emitting wavelength, and the third light-emitting wavelength is less than the first light-emitting wavelength.

[0176] Along the thickness direction of the light-emitting diode chip, the third light-emitting layer 119c is stacked with at least one of the first light-emitting layer 119a and the second light-emitting layer 119b; in the stacked area, the third light-emitting layer 119c is located on the side of the corresponding stacked light-emitting layer close to the P-type electrode, and the light emitted by the third light-emitting layer 119c is used to excite the corresponding stacked light-emitting layer to emit light.

[0177] It should be noted that the third light-emitting layer 119c can also be selected from one of a red light-emitting material layer, a green light-emitting material layer, a blue light-emitting material layer, a purple light-emitting material layer, and an ultraviolet light-emitting material layer, as long as the third light-emitting wavelength is less than the first light-emitting wavelength and the second light-emitting wavelength. In other embodiments, the first light-emitting layer 119a, the second light-emitting layer 119b, and the third light-emitting layer 119c can also select light-emitting material layers of other wavelengths, as long as the relationship of the light-emitting wavelengths of the three is ensured, and this embodiment does not limit it.

[0178] The third light-emitting layer 119c can be stacked only with the first light-emitting layer 119a, and the third light-emitting layer 119c can excite the first light-emitting layer 119a to emit light. The third light-emitting layer 119c can also be stacked only with the second light-emitting layer 119b, and the third light-emitting layer 119c can excite the second light-emitting layer 119b to emit light.

[0179] In some embodiments, at least part of the third light-emitting layer 119c is stacked with the stacked first light-emitting layer 119a and second light-emitting layer 119b. Among the stacked first light-emitting layer 119a, second light-emitting layer 119b, and third light-emitting layer 119c, along the direction from the P-type electrode to the N-type electrode, the third light-emitting layer 119c, the first light-emitting layer 119a, and the second light-emitting layer 119b are arranged in sequence, and the light emitted by the third light-emitting layer 119c is used to excite the first light-emitting layer 119a and the second light-emitting layer 119b to emit light.

[0180] Figure 23 As shown in, the first light-emitting layer 119a, the second light-emitting layer 119b, and the third light-emitting layer 119c are all stacked. The third light-emitting layer 119c is electroluminescent, and the second light-emitting layer 119b and the third light-emitting layer 119c are both photoluminescent. A first filter layer CF1 and a second filter layer CF2 with different wavelengths can be provided on the light-emitting side of the light-emitting diode chip, so as to emit two kinds of light with different wavelengths, respectively forming a first sub-pixel and a second sub-pixel.

[0181] Figure 24As shown, the third light-emitting layer 119c, the first region of the first light-emitting layer 119a, and the second light-emitting layer 119b are stacked, and the third light-emitting layer 119c is stacked with the second region of the first light-emitting layer 119a. On the light-emitting side of the light-emitting diode chip, a filter layer can be provided at a position corresponding to the second light-emitting layer 119b, and the passing wavelength of the filter layer is the second light-emitting wavelength. Light with the second light-emitting wavelength can be emitted at a position corresponding to the filter layer, thereby forming a second sub-pixel. Light with the first light-emitting wavelength can be emitted at a position corresponding to the second region of the first light-emitting layer 119a, thereby forming a first sub-pixel.

[0182] Figure 25 As shown, the third light-emitting layer 119c, the third region of the first light-emitting layer 119a, and the second light-emitting layer 119b are stacked, and the third light-emitting layer 119c is stacked with the fourth region of the second light-emitting layer 119b. On the light-emitting side of the light-emitting diode chip, a filter layer can be provided at a position corresponding to the first light-emitting layer 119a, and the passing wavelength of the filter layer is the first light-emitting wavelength. Light with the first light-emitting wavelength can be emitted at a position corresponding to the filter layer, thereby forming a first sub-pixel. Light with the second light-emitting wavelength can be emitted at a position corresponding to the fourth region of the second light-emitting layer 119b, thereby forming a second sub-pixel.

[0183] Referring to Figure 26 As shown, the above-mentioned light-emitting diode chip further includes a reflective layer 107, and the reflective layer 107 is located on the backlight side of the light-emitting diode chip. The reflective layer 107 is located on the side where the P-type electrode faces away from the N-type electrode, and the side where the N-type electrode faces away from the P-type electrode forms the light-emitting side of the light-emitting diode chip.

[0184] The above-mentioned light-emitting diode chip further includes a light-blocking layer 118, and the light-blocking layer 118 is located on the light-emitting side of the light-emitting diode chip and between two adjacent sub-pixels. The light-blocking layer 118 can avoid the problem of light mixing between two sub-pixels and ensure the light-emitting effect of the light-emitting diode chip. Based on the fact that the first filter layer CF1 and the second filter layer CF2 are located on the light-emitting side of the light-emitting diode chip, the light-blocking layer 118 can be located between them.

[0185] The above-mentioned light-emitting diode chip further includes a hole-blocking layer 117, and the hole-blocking layer 117 is provided between any two adjacent layers of the stacked first light-emitting layer 119a, second light-emitting layer 119b, and third light-emitting layer 119c. The sum of the thickness of the hole-blocking layer 117 and the third light-emitting layer 119c can be greater than the diffusion length of holes. In this way, the hole-blocking layer 117 can block the migration of holes into the first light-emitting layer 119a and the second light-emitting layer 119b.

[0186] The light-emitting diode chip having the third light-emitting layer 119c can also be independently driven. That is, the N-type electrode is set as a discrete first N-type electrode and a second N-type electrode, or the P-type electrode is set as a mutually discrete first P-type electrode and a second P-type electrode. In the mutually discrete structure, an isolation structure can also be provided. The specific structure can refer to the above embodiments and will not be elaborated here.

[0187] In the light-emitting diode chip provided by the embodiment of the present application, at least two of the above sub-pixels can form one pixel subgroup or multiple pixel subgroups; the same pixel subgroup includes multiple sub-pixels, and among the multiple sub-pixels, the number of the first sub-pixels and the number of the second sub-pixels are equal or unequal.

[0188] It should be noted that both the first sub-pixel and the second sub-pixel can be one. Or, both of them can be two, three, four, etc. For Figure 27 example, all four sub-pixels belong to the same pixel subgroup, among which, the first sub-pixel B can be three, and the second sub-pixel G is one. For Figure 28 example, all four sub-pixels belong to the same pixel subgroup, among which, the second sub-pixel G can be three, and the first sub-pixel B is one. The present application does not limit the number of the first sub-pixel and the second sub-pixel in the same pixel subgroup.

[0189] Exemplarily, the number of sub-pixels in the pixel subgroup can be a positive integer greater than or equal to 2, and it can be an odd number greater than 2, that is, 3, 5, 7, etc. Exemplarily, the number of sub-pixels in the pixel subgroup can also be an even number greater than or equal to 2, that is, 2*N (refer to Figure 47 shown), where N is a positive integer greater than or equal to 1. For example, the number of sub-pixels in the pixel subgroup can be 2*10, or 2*100, or 2*1000, etc.

[0190] In some embodiments, the shape of the sub-pixel is any one of a rectangle, a square, a circle, an ellipse, a triangle, a rhombus, a parallelogram, and a polygon with more than four sides. Among them, the shapes of different sub-pixels are the same or different. That is, the shapes of the first sub-pixel B and the second sub-pixel G can both be Figure 1 or Figure 3 the rectangle shown in

[0191] In some embodiments, the shape of the light-emitting diode chip can be any one of a rectangle, a square, a circle, an ellipse, a triangle, a rhombus, a parallelogram, and a polygon with more than four sides. When multiple light-emitting diode chips form a light-emitting diode chip group, the shapes of different light-emitting diode chips can be the same or different.

[0192] In some embodiments, the sizes of different sub-pixels are equal or unequal. The size of a sub-pixel affects its light-emitting area. That is, the light-emitting areas of different sub-pixels can be equal or unequal. The sizes of different sub-pixels can be adjusted according to the brightness attenuation of the sub-pixels. For example, if the brightness attenuation rate of a certain sub-pixel is relatively large, the size of this sub-pixel can be appropriately increased to ensure uniform light output requirements. The sizes of different sub-pixels can also be adjusted according to whether there is a sharing situation between different pixel units (Pixel unit, abbreviated as PU). For example, referring to Figure 51 As shown, sub-pixel (B) and sub-pixel (R) are shared by two pixel units respectively during the formation of pixel units PU1 and PU2, sub-pixel (G) is not shared and belongs entirely to pixel unit PU1. Therefore, the sizes of sub-pixel (B) and sub-pixel (R) are larger than the size of sub-pixel (G). In this way, the luminous brightness of the shared sub-pixels in each pixel unit can be ensured.

[0193] It should be noted that the above-mentioned "size" can be understood as the extension length of a sub-pixel in a certain extension direction. For example, it can be the length or width of a rectangular sub-pixel, or the major axis length or minor axis length of an elliptical sub-pixel, or the diameter of a circular sub-pixel, etc.

[0194] In some embodiments, the size of the pixel sub-group is greater than or equal to 50 microns. The size of the light-emitting diode chip composed of this pixel sub-group can also be greater than or equal to 50 microns. For example, it can be 50 - 100 microns, or 100 - 150 microns, or greater than 150 microns. Of course, in some embodiments, the size of this light-emitting diode chip can also be less than 50 microns. The light-emitting diode chip can be selected with different sizes according to different usage scenarios.

[0195] In some embodiments, the size range of the sub-pixel is 0.001 - 200 microns. When the size of the sub-pixel is 0.001 microns - 0.1 microns, the size of this sub-pixel is at the nanoscale and is a nano LED (nano LED). During the preparation of nano LED, the arrangement method of single-core dual-color multi-sub-pixels in this application can be referred to, which helps to increase the size of a single chip of nano LED containing multiple sub-pixels, so that the size of a single chip is close to or falls within the size range of LED chips that can be operated by the current mass transfer process, thereby reducing the operation difficulty during the preparation process of nano LED and improving its operability.

[0196] In some other embodiments, taking a light-emitting diode chip with a 2*2 combination of sub-pixels applied to a large TV as an example, the size of a single sub-pixel can be 50 microns, and the pitch between two adjacent sub-pixels can be 10 microns. The length and width of the light-emitting diode chip are both 110 microns, and its size can be calculated as 110*110 microns. A light-emitting diode chip with such a size can use the packaging process of mini LED.

[0197] The sizes of the light-emitting diode chip and the sub-pixels will vary according to the usage scenario of the light-emitting diode chip. Below, an exemplary description is given of the sizes of the light-emitting diode chip and the sub-pixels in different usage scenarios.

[0198] When the light-emitting diode chip is applied to display products such as home TVs and desktop computers, at a pixel density of 50 - 150, the size (pitch) of a pixel unit composed of several sub-pixels in multiple light-emitting diode chips can be 150 - 700 microns, the size (sub pitch) of the sub-pixels in the light-emitting diode chip can be less than 250 microns, and the size of the light-emitting diode chip can be greater than 100 microns.

[0199] When the light-emitting diode chip is applied to display products such as laptops and tablets, at a pixel density of 150 - 250, the size of the sub-pixels can be less than 70 microns, the size of the pixel unit is 100 - 200 microns, and the size of the light-emitting diode chip can be greater than 60 microns.

[0200] When the light-emitting diode chip is applied to display products such as mobile phones and smartwatches, at a pixel density greater than 300, the size of the sub-pixels can be less than 30 microns, the size of the pixel unit is less than 100 microns, and the size of the light-emitting diode chip can be greater than 50 microns.

[0201] Based on this, the light-emitting diode chip provided in the embodiments of the present application adopts a single-core dual-color multi-sub-pixel arrangement method. The size range of the sub-pixels and the light-emitting diode chip is relatively large, which can be applicable to different usage scenarios and increases the applicability of the light-emitting diode chip.

[0202] Refer to Figures 29 - 31 As shown, the light-emitting layer can include two pixel sub-groups. In other embodiments, the light-emitting layer can also include three, four, five or more pixel sub-groups. Taking two pixel sub-groups as an example, both of the two pixel sub-groups include a first sub-pixel B and a second sub-pixel G. Among them, the first direction is the direction shown by x in the figure, and the second direction is the direction shown by y in the figure.

[0203] Among them, the pixel subgroup includes a first pixel subgroup and a second pixel subgroup. The emission wavelengths of the first sub-pixel B of the first pixel subgroup and the first sub-pixel B of the second pixel subgroup are the same, and the emission wavelengths of the second sub-pixel G of the first pixel subgroup and the second sub-pixel G of the second pixel subgroup are the same. Figures 29 - 31 Both include two rows of sub-pixels. Among them, the two sub-pixels in the first row form a first pixel subgroup, and the two sub-pixels in the second row form a second pixel subgroup.

[0204] Optionally, referring to Figure 29 As shown, along the first direction, the first sub-pixel B of the first pixel subgroup corresponds to the first sub-pixel B of the second pixel subgroup, and the second sub-pixel G of the first pixel subgroup corresponds to the second sub-pixel G of the second pixel subgroup.

[0205] Optionally, referring to Figure 30 As shown, the first sub-pixel B of the first pixel subgroup corresponds to the second sub-pixel G of the second pixel subgroup, and the second sub-pixel G of the first pixel subgroup corresponds to the first sub-pixel B of the second pixel subgroup.

[0206] In the embodiments of the present application, the driving methods of the two pixel subgroups may include simultaneous driving and independent driving. Below, the different arrangement structures of these two driving methods will be described in detail.

[0207] Optionally, the light-emitting diode chip includes an N-type electrode and a P-type electrode. All the sub-pixels in the two pixel subgroups are respectively in contact with the N-type electrode and the P-type electrode, so as to realize the simultaneous driving of multiple sub-pixels.

[0208] Optionally, the N-type electrode includes at least two sub-N-type electrodes that are mutually discrete, and the number of sub-N-type electrodes is the same as the number of sub-pixels; one side of a sub-pixel facing away from the P-type electrode correspondingly contacts one sub-N-type electrode; the sides of the sub-pixels facing away from the N-type electrode are all in contact with the P-type electrode. In this way, when multiple N-type electrodes are respectively in the energized state and the P-type electrode is in the energized state, the independent driving of multiple sub-pixels can be realized.

[0209] Optionally, the P-type electrode includes at least two sub-P-type electrodes that are mutually discrete, and the number of sub-P-type electrodes is the same as the number of sub-pixels; one side of a sub-pixel facing away from the N-type electrode correspondingly contacts one sub-P-type electrode; the sides of the sub-pixels facing away from the P-type electrode are all in contact with the N-type electrode. In this way, when multiple P-type electrodes are respectively in the energized state and the N-type electrode is in the energized state, the independent driving of multiple sub-pixels can be realized. Figure 29 and Figure 30 As shown, it includes four sub-P-type electrodes, namely sub-P-type electrode P11, sub-P-type electrode P12, sub-P-type electrode P21, and sub-P-type electrode P22. The four sub-P-type electrodes are respectively connected to four sub-pixels, and the four sub-pixels are all connected to the N-type electrode.

[0210] In some embodiments, when the size of the overall light-emitting diode chip is large and the conductivity of a single electrode is not high, if all sub-pixels share the same electrode, for example, sharing a P-type electrode or sharing an N-type electrode, the light-emitting brightness of the sub-pixels in some areas will be relatively low, and the light-emitting effect of the overall light-emitting diode chip will be uneven. Therefore, in this application, all sub-pixels of the entire light-emitting diode chip are divided into multiple regions, and the sub-pixels within the same region are set to share electrodes. In this way, the sub-pixels in the same region share one electrode. Compared with all sub-pixels in all regions sharing the same electrode, the uniformity of the light-emitting effect of the sub-pixels in multiple regions and the overall light-emitting diode chip can be ensured.

[0211] Exemplarily, the N-type electrode includes at least two mutually discrete sub-N-type electrodes, and the number of sub-N-type electrodes is the same as the number of sub-pixels; the P-type electrode includes at least two mutually discrete sub-P-type electrodes, and the number of sub-P-type electrodes is less than the number of sub-pixels; one side of a sub-pixel facing away from the P-type electrode correspondingly contacts one sub-N-type electrode, and one side of a partial number of sub-pixels facing away from the N-type electrode contacts the same sub-P-type electrode. That is, on the basis of independent driving of multiple sub-pixels, multiple sub-pixels in some regions can share one sub-P-type electrode.

[0212] Another exemplarily, referring to Figure 31 As shown, the P-type electrode includes at least two mutually discrete sub-P-type electrodes, and the number of sub-P-type electrodes is the same as the number of sub-pixels; the N-type electrode includes at least two mutually discrete sub-N-type electrodes, and the number of sub-N-type electrodes is less than the number of sub-pixels; one side of a sub-pixel facing away from the N-type electrode correspondingly contacts one sub-P-type electrode, and one side of a partial number of sub-pixels facing away from the P-type electrode contacts the same sub-N-type electrode. Figure 31 As shown in, it includes four sub-P-type electrodes and two sub-N-type electrodes, namely sub-P-type electrode P11, sub-P-type electrode P12, sub-P-type electrode P21, and sub-P-type electrode P22, and sub-N-type electrode N1 and sub-N-type electrode N2. The first sub-pixel of the first pixel sub-group contacts sub-P-type electrode P11, and the second sub-pixel contacts sub-P-type electrode P21, and both contact sub-N-type electrode N1. The first sub-pixel of the second pixel sub-group contacts sub-P-type electrode P22, and the second sub-pixel contacts sub-P-type electrode P12, and both contact sub-N-type electrode N2. In this way, all sub-pixels of the first pixel sub-group can share one sub-N-type electrode, and all sub-pixels of the second pixel sub-group can share another sub-N-type electrode, ensuring the light-emitting uniformity of the overall light-emitting diode chip.

[0213] In some embodiments, referring to Figures 34 - 36As shown, the light-emitting diode chip can also be a monochromatic multi-subpixel chip. That is, the light-emitting layer includes a plurality of monochromatic subpixels. For example, the light-emitting layer of the light-emitting diode chip C1 can include 4 subpixels B( Figure 34 ), or the light-emitting layer of the light-emitting diode chip C2 includes 4 subpixels G( Figure 35 ), or the light-emitting layer of the light-emitting diode chip C3 includes 4 subpixels R( Figure 36 ). In other embodiments, the number of monochromatic subpixels in the light-emitting layer can be adjusted to 2, 3, 5 or more. Combining a plurality of monochromatic subpixels to form a light-emitting diode chip can also flexibly adjust the size of the light-emitting diode chip.

[0214] The structures and arrangements of the N-type electrode, P-type electrode, and light-emitting layer in the light-emitting diode chip are described in detail above. Hereinafter, other structures and arrangements of the light-emitting diode chip will be described in detail.

[0215] Referring to Figure 37 As shown, the light-emitting diode chip provided in the embodiment of the present application further includes a buffer layer 101, an N-type semiconductor layer 103, a P-type semiconductor layer 105, a current spreading layer 106, a reflective layer 107, and a first insulating layer 108. The buffer layer 101 and the N-type semiconductor layer 103 are stacked, the light-emitting layer is disposed on a side of the N-type semiconductor layer 103 away from the buffer layer 101, and the P-type semiconductor layer 105 is disposed on a side of the light-emitting layer away from the buffer layer 101; the current spreading layer 106 is in contact with a surface of the P-type semiconductor layer 105 away from the buffer layer 101, the N-type electrode 102 is in contact with the N-type semiconductor layer 103, and the P-type electrode 104 is in contact with the P-type semiconductor layer 105 and the current spreading layer 106; the first insulating layer 108 is disposed on a side of the current spreading layer 106 and a part of the N-type semiconductor layer 103 away from the buffer layer 101. In this way, a light-emitting diode chip with a thin-film flip-chip structure can be formed. The light-emitting layer includes a stacked first light-emitting layer 119a and a second light-emitting layer 119b.

[0216] Optionally, the reflective layer 107 is disposed on a side of the buffer layer 101 away from the light-emitting layer. In this way, the light-emitting direction of the light-emitting diode chip is toward the direction away from the buffer layer 101. Optionally, referring to Figure 37 As shown, the reflective layer 107 is disposed on a side of the first insulating layer 108 away from the buffer layer 101, and a second insulating layer 109 is further disposed on a side of the reflective layer 107 away from the buffer layer 101. In this way, the light-emitting direction of the light-emitting diode chip is toward the direction where the buffer layer 101 is located, that is, the downward arrow direction shown in the figure. The first filter layer 114 and the second filter layer 115 are disposed at the bottom of the buffer layer 101, and a light-blocking layer 118 is disposed between the first filter layer 114 and the second filter layer 115.

[0217] Among them, the material of the buffer layer 101 can be one or more of gallium nitride, aluminum gallium nitride, and indium gallium aluminum nitride, and the thickness of the buffer layer 101 can be 10 - 40 nanometers. The material of the N-type semiconductor layer 103 can be N-type doped gallium nitride, and the material of the P-type semiconductor layer 105 can be P-type doped gallium nitride. The material of the current spreading layer 106 can be a transparent conductive material (indium tin oxide, ITO) or silver, etc., and its function is to improve the distribution ability of the P-type electrode and make the holes as evenly distributed as possible in the area where the P-type semiconductor layer 105 is located. The material of the first insulating layer 108 can be silicon oxide, silicon nitride.

[0218] Referring to Figure 38 and Figure 39 As shown, based on the above thin-film light-emitting diode chip, the light-emitting diode chip further includes a substrate 100, and the substrate 100 is disposed on the side of the buffer layer 101 away from the light-emitting layer. The material of the substrate 100 can be one or more composites of sapphire, gallium nitride, aluminum nitride, silicon, and silicon carbide.

[0219] Referring to Figure 38 As shown, when the reflective layer 107 is disposed on the side of the buffer layer 101 away from the light-emitting layer, the reflective layer 107 is disposed on the side of the substrate 100 away from the buffer layer 101. Figure 38 The light-emitting direction is the upward direction indicated by the arrow in the figure, forming a surface-mounted structure light-emitting diode chip. The first filter layer 114 and the second filter layer 115 are disposed on the top of the first insulating layer 108, and an optical blocking layer 118 can be disposed at a position where they are close to each other. The optical blocking layer 118 is located on the side of the first filter layer 114 and the second filter layer 115 away from the bonding substrate 110. Figure 39 The light-emitting direction is the downward direction indicated by the arrow in the figure, forming an inverted structure light-emitting diode chip. The first filter layer 114 and the second filter layer 115 are disposed at the bottom of the substrate 100, and the optical blocking layer 118 is located between them.

[0220] Referring to Figure 40As shown, the light-emitting diode chip may further include a bonding substrate 110, a bonding layer 111, an N-type semiconductor layer 103, a P-type semiconductor layer 105, and a reflective layer 107; the bonding substrate 110 and the bonding layer 111 are sequentially disposed on the P-type electrode 104, the P-type semiconductor layer 105 is disposed on a side of the bonding layer 111 away from the bonding substrate 110 and is in contact with the bonding layer 111; the light-emitting layer is disposed on a side of the P-type semiconductor layer 105 away from the bonding substrate 110, the N-type semiconductor layer 103 is disposed on a side of the light-emitting layer away from the bonding substrate 110, and the N-type electrode 102 contacts a side of the N-type semiconductor layer 103 away from the bonding substrate 110; the reflective layer 107 is disposed on a side of the P-type semiconductor layer 105 close to the bonding substrate 110. The first light-filtering layer 114 and the second light-filtering layer 115 are disposed on the top of the first insulating layer 108, and an opaque layer 118 may be disposed at a position where they are close to each other. The opaque layer 118 is located on a side of the first light-filtering layer 114 and the second light-filtering layer 115 away from the bonding substrate 110. The light-emitting direction of the light-emitting diode chip may be the upward direction indicated by the arrow in the figure. A light-emitting diode chip with a vertical structure is formed.

[0221] In a second aspect, an embodiment of the present application provides a method for manufacturing a light-emitting diode chip, and this manufacturing method can be used to manufacture the above-mentioned light-emitting diode chip.

[0222] As a first manufacturing method of the light-emitting diode chip, referring to Figure 41 as shown, the first region that can be used to manufacture the first light-emitting layer 119a and the second light-emitting layer 119b are stacked, and the first sub-pixel and the second sub-pixel formed by the first light-emitting layer 119a and the second light-emitting layer 119b are driven synchronously. Specifically, this manufacturing method includes:

[0223] Form a substrate 100 through a deposition process ( Figure 41 (a)); sequentially form a buffer layer 101, an N-type semiconductor layer 103, and a second light-emitting layer 119b on the substrate 100 through an epitaxial growth process ( Figure 41 (b)); remove the second light-emitting layer 119b in the fourth region through a patterning process to expose the top surface of a part of the N-type semiconductor layer 103 ( Figure 41 (c)); form a first light-emitting layer 119a covering the second light-emitting layer 119b and the N-type semiconductor layer 103 through an epitaxial growth process ( Figure 41 (d)); form a P-type semiconductor layer 105 covering the first light-emitting layer 119a through an epitaxial growth process ( Figure 41 (e)); form a step ( Figure 41 (f)); form a patterned current spreading layer 106 ( Figure 41 (g)); form a patterned first insulating layer 108 covering the current spreading layer 106, and a part of the first insulating layer 108 is located at the stepFigure 41 (h)); forming a patterned reflective layer 107 covering the first insulating layer 108 Figure 41 (i)); forming a patterned second insulating layer 109 covering the reflective layer 107 Figure 41 (j)); forming an N-type electrode 102 and a P-type electrode 104 Figure 41 (k)); forming a second light filtering layer 115 and a light blocking layer 118 on a side of the substrate 100 facing away from the reflective layer 107 Figure 41 (l), wherein the second light filtering layer 115 may be formed first, the light blocking layer 118 may be formed later, or the formation order of the two may be reversed, and this embodiment does not limit this. In the following embodiments, the formation order of the light blocking layer 118 and the second light filtering layer 115 may be the same, and will not be elaborated herein

[0224] Among them, the second light filtering layer 115 may not be formed

[0225] As a second preparation method of the light emitting diode chip, referring to Figure 42 as shown, a first region for preparing the first light emitting layer 119a and the second light emitting layer 119b are stacked, an isolation structure is formed therebetween, and the first sub-pixel and the second sub-pixel formed by the first light emitting layer 119a and the second light emitting layer 119b are independently driven. (The isolation material filled in the channel is not shown in the figure). Specifically, this preparation method includes:

[0226] forming a substrate 100 through a deposition process Figure 42 (a)); sequentially forming a buffer layer 101, an N-type semiconductor layer 103, and a second light emitting layer 119b on the substrate 100 through an epitaxial growth process Figure 42 (b)); removing the second light emitting layer 119b in the fourth region through a patterning process to expose the top surface of a part of the N-type semiconductor layer 103 Figure 42 (c)); forming a first light emitting layer 119a covering the second light emitting layer 119b and the N-type semiconductor layer 103 through an epitaxial growth process Figure 42 (d)); forming a P-type semiconductor layer 105 covering the first light emitting layer 119a through an epitaxial growth process Figure 42 (e)); forming a step and a channel Figure 42 (f)); forming a patterned current spreading layer 106 Figure 42 (g)); forming a patterned first insulating layer 108 covering the current spreading layer 106, and a part of the first insulating layer 108 is located at the step Figure 42 (h)); forming a patterned reflective layer 107 covering the first insulating layer 108 Figure 42 (i)); forming a patterned second insulating layer 109 covering the reflective layer 107 Figure 42(j)); form an N-type electrode 102 and a P-type electrode 104( Figure 42 (k)); form a second light filtering layer 115 and a light blocking layer 118 on a side of the substrate 100 away from the reflective layer 107( Figure 42 (l)).

[0227] Among them, the second light filtering layer 115 may not be formed.

[0228] As a third preparation method of the light emitting diode chip, referring to Figure 43 as shown, it can be used to prepare the first light emitting layer 119a and the second light emitting layer 119b which are both stacked, and no isolation structure is formed between them. The first sub-pixel and the second sub-pixel formed by the first light emitting layer 119a and the second light emitting layer 119b are driven simultaneously. Specifically, the preparation method includes:

[0229] Form a substrate 100 through a deposition process Figure 43 (a)); sequentially form a buffer layer 101, an N-type semiconductor layer 103, a second light emitting layer 119b, a first light emitting layer 119a, and a P-type semiconductor layer 105 on the substrate 100 through an epitaxial growth process Figure 43 (b)); form a step Figure 43 (c)); form a patterned current spreading layer 106 Figure 43 (d)); form a patterned first insulating layer 108 covering the current spreading layer 106, and a part of the first insulating layer 108 is located at the step Figure 43 (e)); form a patterned reflective layer 107 covering the first insulating layer 108 Figure 43 (f)); form a patterned second insulating layer 109 covering the reflective layer 107 Figure 43 (g)); form an N-type electrode 102 and a P-type electrode 104 Figure 43 (h)); form a first light filtering layer 114, a second light filtering layer 115, and a light blocking layer 118 on a side of the substrate 100 away from the reflective layer 107 Figure 43 (i).

[0230] As a fourth preparation method of the light emitting diode chip, referring to Figure 44 as shown, it can be used to prepare the first light emitting layer 119a and the second light emitting layer 119b which are both stacked, and an isolation structure is formed between them. The first light emitting layer 119a and the second light emitting layer 119b are both stacked and independently driven. (The isolation material filled in the channel is not shown in the figure). Specifically, the preparation method includes:

[0231] Form a substrate 100 through a deposition process Figure 44(a)); A buffer layer 101, an N-type semiconductor layer 103, a second light-emitting layer 119b, a first light-emitting layer 119a, and a P-type semiconductor layer 105 are sequentially formed on a substrate 100 by an epitaxial growth process ( Figure 44 (b)); Steps and channels are formed.( Figure 44 (c)); A patterned current spreading layer 106 is formed.( Figure 44 (d)); A patterned first insulating layer 108 covering the current spreading layer 106 is formed, and a part of the first insulating layer 108 is located at the step.( Figure 44 (e)); A patterned reflective layer 107 covering the first insulating layer 108 is formed.( Figure 44 (f)); A patterned second insulating layer 109 covering the reflective layer 107 is formed.( Figure 44 (g)); An N-type electrode 102 and a P-type electrode 104 are formed.( Figure 44 (h)); A first light filtering layer 114, a second light filtering layer 115, and a light blocking layer 118 are formed on a side of the substrate 100 facing away from the reflective layer 107.( Figure 44 (i)).

[0232] Referring to Figure 45 As shown, in some embodiments, the light-emitting diode chip may further include a color conversion layer 112. The color conversion layer 112 is disposed on the light-emitting side of a part of the light-emitting diode chip and is correspondingly disposed with at least a part of the sub-pixels. The orthographic projection of the color conversion layer 112 on the plane where the corresponding sub-pixel is located may cover all regions of a single sub-pixel or only cover a part of the regions of a single sub-pixel. The material of the color conversion layer 112 may be a quantum dot material, a phosphor material, etc. Using the color conversion layer 112 can adjust the light-emitting wavelength of the light-emitting diode chip and enrich the types of its light-emitting wavelengths.

[0233] Taking a light-emitting diode chip with a front-mounted structure as an example, the light-emitting wavelengths of the first sub-pixel SP1, the second sub-pixel SP2, and the color conversion layer 112 are different from each other. In this way, the color conversion layer 112 is disposed on the light-emitting side of the second sub-pixel SP2 and is opposite to a part of the second sub-pixel SP2, which can convert a part of the light emitted by the second sub-pixel SP2 into light with a third light-emitting wavelength other than the light with the first light-emitting wavelength of the first sub-pixel SP1 and the light with the second light-emitting wavelength of the second sub-pixel SP2. Therefore, the light-emitting diode chip can emit light with the first light-emitting wavelength, the second light-emitting wavelength, and the third light-emitting wavelength. Figure 45 The light-emitting direction is the upward direction indicated by the arrow in the figure.

[0234] In a third aspect, an embodiment of the present application provides a light-emitting diode chip group, which includes a plurality of the above-mentioned light-emitting diode chips, and the plurality of light-emitting diode chips are arranged in an array; two adjacent light-emitting diode chips include a first light-emitting diode chip and a second light-emitting diode chip, and a partial number of sub-pixels of the first light-emitting diode chip and a partial number of sub-pixels of the second light-emitting diode chip together form a pixel unit. It should be noted that the partial number of sub-pixels in the first light-emitting diode chip and the second light-emitting diode chip that form the pixel unit can be all or part of the sub-pixels in the same pixel sub-group. Optionally, the emission wavelengths of two sub-pixels of the first light-emitting diode chip and one sub-pixel of the second light-emitting diode chip are different from each other. In this way, pixel units with multiple emission wavelengths can be formed.

[0235] Next, in this embodiment, different arrangements between different light-emitting diode chips are used to form pixel units, and a chip group composed of dual-color multi-sub-pixel light-emitting diode chips will be described in detail.

[0236] As a first implementable embodiment, the entire regions of two sub-pixels of the first light-emitting diode chip and the entire region of one sub-pixel of the second light-emitting diode chip together form a pixel unit. The starting sub-pixel can be any one, such as R, such as B, such as G, and the arrangement order of the sub-pixels in the pixel unit can be changed arbitrarily.

[0237] For example, referring to Figure 46 As shown, the first light-emitting diode chip includes two pixel sub-groups, that is, two pixel sub-groups in the first column. The pixel sub-group in the first row includes a first sub-pixel B and a second sub-pixel G, and the pixel sub-group in the second row includes a third sub-pixel B and a fourth sub-pixel G. The second light-emitting diode chip includes two pixel sub-groups, that is, two pixel sub-groups in the second column. The pixel sub-group in the first row includes a first sub-pixel R and a second sub-pixel B, and the pixel sub-group in the second row includes a third sub-pixel R and a fourth sub-pixel B.

[0238] Using the first light-emitting diode chip and the second light-emitting diode chip in the above example to form a pixel unit, the first sub-pixel B and the second sub-pixel G in the first row of the first light-emitting diode chip and the first sub-pixel R in the first row of the second light-emitting diode chip together form a pixel unit PU1. According to this arrangement method, the first light-emitting diode chip and the second light-emitting diode chip also form a pixel unit PU2.

[0239] The light-emitting diode chip group may further include a third light-emitting diode chip. Continuing to refer to Figure 46 As shown, the third light-emitting diode chip includes two pixel sub-groups, that is, two pixel sub-groups in the third column. The pixel sub-group in the first row includes a first sub-pixel G and a second sub-pixel R, and the pixel sub-group in the second row includes a third sub-pixel G and a fourth sub-pixel R.

[0240] The second light-emitting diode chip and the third light-emitting diode chip form a pixel unit. The second sub-pixel B in the first row of the second light-emitting diode chip, the first sub-pixel G and the second sub-pixel R in the first row of the third light-emitting diode chip together form a pixel unit PU3. According to this arrangement method, the second light-emitting diode chip and the third light-emitting diode chip also form a pixel unit PU4.

[0241] Refer to Figure 47 and Figure 48 As shown, in the above arrangement method, the light-emitting diode chip includes three pixel sub-groups ( Figure 47 ), or four pixel sub-groups (not shown in the figure), or five pixel sub-groups ( Figure 48 Five pixel sub-groups are drawn in the figure, and the subsequent ellipsis indicates more pixel sub-groups), and even more pixel sub-groups can form pixel units.

[0242] The above-mentioned pixel unit PU1, pixel unit PU2, pixel unit PU3 and pixel unit PU4 together form a chip group CG1. According to the above arrangement method, a chip group CG2 can be formed. Figures 46 - 48 Both show two chip groups, namely chip group CG1 and chip group CG2. The arrangement methods of chip group CG1 and chip group CG2 can be the same, and the arrangement methods of the formed pixel units can also be the same. In other embodiments, the arrangement methods of chip group CG1 and chip group CG2 can also be different, and the arrangement methods of the formed pixel units can also be different.

[0243] In some embodiments, the arrangement methods of the sub-pixels in the first light-emitting diode chip, the second light-emitting diode chip and the third light-emitting diode chip can be different from those in the above embodiments. The following gives embodiments of different arrangement methods of the sub-pixels in the first light-emitting diode chip, the second light-emitting diode chip and the third light-emitting diode chip.

[0244] Refer to Figure 49As shown, in some embodiments, in the first light-emitting diode chip of the first column, the pixel subgroup in the first row includes a first sub-pixel G and a second sub-pixel R. The pixel subgroup in the second row includes a first sub-pixel G and a second sub-pixel R. In the second light-emitting diode chip of the second column, the pixel subgroup in the first row includes a first sub-pixel B and a second sub-pixel G, and the pixel subgroup in the second row includes a first sub-pixel B and a second sub-pixel G. In the third light-emitting diode of the third column, the pixel subgroup in the first row includes a first sub-pixel R and a second sub-pixel B, and the pixel subgroup in the second row includes a first sub-pixel R and a second sub-pixel B. In this way, the first sub-pixel G and the second sub-pixel R of the pixel subgroup in the first row of the first light-emitting diode chip, together with the first sub-pixel B of the pixel subgroup in the first row of the second light-emitting diode chip, form a pixel unit PU1. In this way, pixel units PU2, PU3, and PU4 can be formed. The arrangement of the sub-pixels and pixel units in chip group CG1 and chip group CG2 is the same.

[0245] Referring to Figure 50 As shown, in some embodiments, in the first light-emitting diode chip of the first column, the pixel subgroup in the first row includes a first sub-pixel R and a second sub-pixel B. The pixel subgroup in the second row includes a first sub-pixel R and a second sub-pixel B. In the second light-emitting diode chip of the second column, the pixel subgroup in the first row includes a first sub-pixel G and a second sub-pixel R, and the pixel subgroup in the second row includes a first sub-pixel G and a second sub-pixel R. In the third light-emitting diode of the third column, the pixel subgroup in the first row includes a first sub-pixel B and a second sub-pixel G, and the pixel subgroup in the second row includes a first sub-pixel B and a second sub-pixel G. In this way, the first sub-pixel R and the second sub-pixel B of the pixel subgroup in the first row of the first light-emitting diode chip, together with the first sub-pixel G of the pixel subgroup in the first row of the second light-emitting diode chip, form a pixel unit PU1. In this way, pixel units PU2, PU3, and PU4 can be formed. The arrangement of the sub-pixels and pixel units in chip group CG1 and chip group CG2 is the same.

[0246] In some embodiments, the sub-pixels between different chip groups can also form pixel units. By way of example, referring to Figure 51As shown, the chipset CG1 includes three pixel subgroups. The sub-pixels in the three pixel subgroups are respectively the first sub-pixel B and the second sub-pixel G of the first pixel subgroup, the third sub-pixel R and the fourth sub-pixel B of the second pixel subgroup, and the fifth sub-pixel G and the sixth sub-pixel R of the third pixel subgroup. The chipset CG2 includes multiple pixel subgroups. The sub-pixels in the three pixel subgroups are respectively the first sub-pixel B and the second sub-pixel G of the first pixel subgroup, the third sub-pixel R and the fourth sub-pixel B of the second pixel subgroup, and the fifth sub-pixel G and the sixth sub-pixel R of the third pixel subgroup. The chipset CG1 and the chipset CG2 can be arranged in two rows and are misaligned with each other (that is, along the arrangement direction of the chipset CG1 and the chipset CG2, the sub-pixels in the chipset CG1 and the chipset CG2 are misaligned with each other). The sub-pixels in the chipset CG1 and the chipset CG2 can form multiple pixel units. Specifically: The first sub-pixel B of the chipset CG1, together with the second sub-pixel G and the third sub-pixel R of the chipset CG2, form the pixel unit PU1. The second sub-pixel G and the third sub-pixel R of the chipset CG1, together with the fourth sub-pixel B of the chipset CG2, form the pixel unit PU2. The fourth sub-pixel B of the chipset CG1, together with the fifth sub-pixel G and the sixth sub-pixel R of the chipset CG2, form the pixel unit PU3.

[0247] As a second implementable embodiment, partial regions of two sub-pixels of the first light-emitting diode chip and a partial region of one sub-pixel of the second light-emitting diode chip together form a pixel unit. Refer to Figure 52 As shown, the first light-emitting diode chip in the first column includes a pixel subgroup, and this pixel subgroup includes a first sub-pixel B and a second sub-pixel G, and the size of the first sub-pixel B is larger than that of the second sub-pixel G. The second light-emitting diode chip in the second column includes a pixel subgroup, and this pixel subgroup includes a first sub-pixel R and a second sub-pixel G, and the size of the first sub-pixel R is larger than that of the second sub-pixel G. A partial region of the first sub-pixel B of the first light-emitting diode chip, the entire region of the second sub-pixel G, and a partial region of the first sub-pixel R of the second light-emitting diode chip together form the pixel unit PU1.

[0248] The third light-emitting diode chip in the third column includes a pixel subgroup, and this pixel subgroup includes a first sub-pixel B and a second sub-pixel G, and the size of the first sub-pixel B is larger than that of the second sub-pixel G. A partial region of the first sub-pixel R of the second light-emitting diode chip, the entire region of the second sub-pixel G, and a partial region of the first sub-pixel B of the third light-emitting diode chip together form the pixel unit PU2.

[0249] The first light-emitting diode chip and the second light-emitting diode chip together form a chip group CG1. In the above arrangement, the third light-emitting diode chip and the fourth and third light-emitting diode chips in the fourth column can form a chip group CG12. A partial area of the first sub-pixel B, the entire area of the second sub-pixel G of the third light-emitting diode chip, and a partial area of the first sub-pixel B of the fourth light-emitting diode chip together form a pixel unit PU3.

[0250] In the above embodiment, the shared sub-pixels are sub-pixel B and sub-pixel R. In some other embodiments, the sub-pixels shared for forming the pixel unit are different. Embodiments of the arrangement of the chip group sharing different sub-pixels are given below.

[0251] Refer to Figure 53 As shown, the first light-emitting diode chip in the first column includes a pixel sub-group, which includes a first sub-pixel B and a second sub-pixel G, and the size of the first sub-pixel B is smaller than that of the second sub-pixel G. The second light-emitting diode chip in the second column includes a pixel sub-group, which includes a first sub-pixel B and a second sub-pixel R, and the size of the first sub-pixel B is smaller than that of the second sub-pixel R. A partial area of the first sub-pixel G of the first light-emitting diode chip, the entire area of the first sub-pixel B of the second light-emitting diode chip, and a partial area of the second sub-pixel R together form a pixel unit PU1. In this way, pixel units PU2 and PU3 can be formed. In this embodiment, the shared sub-pixels are sub-pixel G and sub-pixel R.

[0252] Refer to Figure 54 As shown, the first light-emitting diode chip in the first column includes a pixel sub-group, which includes a first sub-pixel B and a second sub-pixel G, and the size of the first sub-pixel B is smaller than that of the second sub-pixel G. The second light-emitting diode chip in the second column includes a pixel sub-group, which includes a first sub-pixel R and a second sub-pixel B, and the size of the first sub-pixel R is smaller than that of the second sub-pixel R. A partial area of the first sub-pixel G of the first light-emitting diode chip, the entire area of the first sub-pixel R of the second light-emitting diode chip, and a partial area of the second sub-pixel B together form a pixel unit PU1. In this way, pixel units PU2 and PU3 can be formed. In this embodiment, the shared sub-pixels are sub-pixel G and sub-pixel B.

[0253] It should be noted that in two adjacent pixel units, for example, the first pixel unit and the second pixel unit. When the sub-pixels in the first pixel unit have insufficient emission brightness, some or all of the sub-pixels in the adjacent second pixel unit can be borrowed flexibly to complete the emission of the second pixel unit. That is, the sub-pixels borrowed in the first pixel unit can be used for the emission of the second pixel unit instead of the emission of the first pixel unit. In this way, the structural flexibility of the chip and the light extraction effect can be improved. Among them, the first pixel unit can also borrow the sub-pixels of the second pixel unit for emission for other reasons, and the present application does not limit this.

[0254] As a third implementable embodiment, among at least two sub-pixels of the first light-emitting diode chip and at least two sub-pixels of the second light-emitting diode chip, the emission wavelengths of some of the sub-pixels are the same; and at least two sub-pixels of the first light-emitting diode chip and at least two sub-pixels of the second light-emitting diode chip together form a pixel unit.

[0255] Referring to Figure 55 As shown, the first light-emitting diode chip C1 in the first column includes a plurality of pixel sub-groups. The pixel sub-group in the first row includes a first sub-pixel R and a second sub-pixel B. The second light-emitting diode chip C2 in the second column includes a plurality of pixel sub-groups. The pixel sub-group in the first row includes a first sub-pixel G and a second sub-pixel R. The first sub-pixel R, the second sub-pixel B of the first light-emitting diode chip C1, and the first sub-pixel G, the second sub-pixel R of the second light-emitting diode chip C2 together form a pixel unit PU. The number of sub-pixels in this pixel unit is greater than 3 and includes sub-pixels with three different emission wavelengths. In this arrangement, the pixel sub-groups in the second row of the first light-emitting diode chip C1 and the pixel sub-groups in the second row of the second light-emitting diode chip C2 can also form another pixel unit.

[0256] Figure 56 The shown pixel unit includes two sub-pixels R, one sub-pixel G, and one sub-pixel B. In other embodiments, the pixel unit can also include two sub-pixels R, two sub-pixels B, and one sub-pixel G, or the pixel unit can also include 5 sub-pixels, such as three sub-pixels R, one sub-pixel B, and one sub-pixel G, etc., or the pixel unit can also include 6, 7, 8, or more sub-pixels. The first light-emitting diode chip C1 and the second light-emitting diode chip C2 together form a chip group CG.

[0257] Based on the different luminous efficiencies of sub-pixels with different emission wavelengths, by using the above arrangement method, the uniformity of light with different wavelengths in a pixel unit can be adjusted, ensuring the consistency of light output and improving the light output effect of the light-emitting diode chip group. Moreover, when the number of a certain sub-pixel is multiple, for example, there are two sub-pixels R, and one sub-pixel R is damaged, the other sub-pixel R can be used to replace it for light output.

[0258] Referring to Figure 56 As shown, the first light-emitting diode chip C1 may include a pixel subgroup, including a first sub-pixel G and a second sub-pixel B, and the second light-emitting diode chip C2 may include a pixel subgroup, including a first sub-pixel B and a second sub-pixel R. The pixel subgroups of the first light-emitting diode chip C1 and the second light-emitting diode chip C2 together form a pixel unit, including two sub-pixels B, one sub-pixel G, and one sub-pixel R.

[0259] Referring to Figure 57 As shown, the first light-emitting diode chip C1 may include a pixel subgroup, including a first sub-pixel G and a second sub-pixel B, and the second light-emitting diode chip C2 may include a pixel subgroup, including a first sub-pixel G and a second sub-pixel R. The pixel subgroups of the first light-emitting diode chip C1 and the second light-emitting diode chip C2 together form a pixel unit, including two sub-pixels G, one sub-pixel B, and one sub-pixel R.

[0260] Referring to Figures 46 - 50 As shown, the shapes of different light-emitting diode chips may be the same and are regular shapes.

[0261] Referring to Figures 58 - 62 As shown, in the light-emitting diode chip group provided in this embodiment, the first light-emitting diode chip C1 and the second light-emitting diode chip C2 may also both be irregularly shaped. The first light-emitting diode chip C1 has a protruding area, and the second light-emitting diode chip C2 has a recessed area. Among them, the protruding area may be a cube, a cone, a hemisphere, or other irregular shapes, and the shapes of the protruding area and the recessed area are adapted to each other and fit together. The number of the protruding area and the recessed area may each be 1, 2, or multiple, and the numbers of both are equal.

[0262] It should be noted that taking Figure 58Taking this as an example, the first light-emitting diode chip C1 and the second light-emitting diode chip C2 are both stepped. The protruding area A2 of the step of the first light-emitting diode chip C1 is relatively joined with the concave area A1 of the step of the second light-emitting diode chip C2, and they are joined in this way. In this way, the first light-emitting diode chip C1, the second light-emitting diode chip C2, and the third light-emitting diode chip C3 are completed to be joined. Among them, the sizes of the sub-pixels in the first light-emitting diode chip C1 are the same. In the present application, by the mutual alignment and joining of the protruding area and the concave area, a structure similar to a "mortise and tenon structure" can be formed, which is convenient for the self-alignment assembly of different light-emitting diode chips, reduces the alignment difficulty, and improves the preparation efficiency and yield.

[0263] Of course, the shape of the light-emitting diode chip can also be convex-shaped or concave-shaped ( Figure 59 as shown); or, in the stepped light-emitting diode chip, the sizes of different sub-pixels are different ( Figure 60 as shown); or, the light-emitting diode chip has a serrated edge ( Figure 61 as shown); or, the light-emitting diode chip has an arc-shaped edge ( Figure 62 as shown).

[0264] Referring to Figure 63 as shown, the light-emitting diode chip group includes a first light-emitting diode chip C1, a second light-emitting diode chip C2, and a third light-emitting diode chip C3 that are arranged adjacent to each other in sequence. The first light-emitting diode chip C1, the second light-emitting diode chip C2, and the third light-emitting diode chip C3 each include a pixel subgroup.

[0265] The first sub-pixel B, the second sub-pixel G of the first light-emitting diode chip C1 (the pixel subgroup in the first row and the first column), and the first sub-pixel R of the second light-emitting diode chip C2 (the pixel subgroup in the first row and the second column) have different emission wavelengths and jointly form the first pixel unit; the second sub-pixel B of the second light-emitting diode chip C2, the first sub-pixel G, and the second sub-pixel R of the third light-emitting diode chip C3 (the pixel subgroup in the first row and the third column) have different emission wavelengths and jointly form the second pixel unit. The first light-emitting diode chip C1, the second light-emitting diode chip C2, and the third light-emitting diode chip C3 jointly form a chip group CG1.

[0266] Among them, multiple light-emitting diode chips form multiple chip groups arranged in an array. The multiple chip groups can also include a chip group CG2, a chip group CG3, and a chip group CG4.

[0267] Among them, referring to Figure 63As shown, along the second direction y, in the chipset CG1, the sum of the size of the first sub-pixel B of the first light-emitting diode chip and the distance between the first sub-pixel B of the first light-emitting diode chip and the second sub-pixel G of the first light-emitting diode chip is the first size. The size of the first sub-pixel B of the first light-emitting diode chip is a, the distance between the first sub-pixel B of the first light-emitting diode chip and the second sub-pixel G of the first light-emitting diode chip is b, the first size = a + b, and the first size is the sub-pixel size (Sub pitch) of the first sub-pixel B.

[0268] The sum of the size of the second sub-pixel G of the first light-emitting diode chip and the distance between the second sub-pixel G of the first light-emitting diode chip and the first sub-pixel R of the second light-emitting diode chip is the second size. The size of the second sub-pixel G of the first light-emitting diode chip is c, the distance d between the second sub-pixel G of the first light-emitting diode chip and the first sub-pixel R of the second light-emitting diode chip, the second size = c + d, and the second size is the sub-pixel size of the second sub-pixel G.

[0269] The sum of the size of the first sub-pixel R of the second light-emitting diode chip and the distance between the first sub-pixel R of the second light-emitting diode chip and the second sub-pixel B of the second light-emitting diode chip is the third size. The size of the first sub-pixel R of the second light-emitting diode chip is e, the distance between the first sub-pixel R of the second light-emitting diode chip and the second sub-pixel B of the second light-emitting diode chip is f, the third size = e + f, and the third size is the sub-pixel size of the first sub-pixel R.

[0270] The sum of the size of the second sub-pixel B of the second light-emitting diode chip and the distance between the second sub-pixel B of the second light-emitting diode chip and the first sub-pixel G of the third light-emitting diode chip is the fourth size. The size of the second sub-pixel B of the second light-emitting diode chip is a, the distance between the second sub-pixel B of the second light-emitting diode chip and the first sub-pixel G of the third light-emitting diode chip is g, the fourth size = a + g, and the fourth size is the sub-pixel size of the second sub-pixel B.

[0271] The sum of the size of the first sub-pixel G of the third light-emitting diode chip and the distance between the first sub-pixel G of the third light-emitting diode chip and the second sub-pixel R of the third light-emitting diode chip is the fifth size. The size of the first sub-pixel G of the third light-emitting diode chip is c, the distance between the first sub-pixel G of the third light-emitting diode chip and the second sub-pixel R of the third light-emitting diode chip is h, the fifth size = c + h, and the fifth size is the sub-pixel size of the first sub-pixel G.

[0272] The sum of the distance between the first sub-pixel B of the first light-emitting diode chip and the edge of the chip group CG1, the size of the second sub-pixel R of the third light-emitting diode chip, the distance between the second sub-pixel R of the third light-emitting diode chip and the edge of the chip group CG1, and the distance between the adjacent chip groups CG1 and CG2 is the sixth dimension.

[0273] The distance between the first sub-pixel B of the first light-emitting diode chip and the edge of the chip group CG1 is k, the size of the second sub-pixel R of the third light-emitting diode chip is e, the distance between the second sub-pixel R of the third light-emitting diode chip and the edge of the chip group CG1 is i, and the distance between the adjacent chip groups CG1 and CG2 is l. The sixth dimension = k + e + i + l.

[0274] Optionally, the first dimension, the second dimension, the third dimension, the fourth dimension, the fifth dimension, and the sixth dimension are all equal; the sum of the first dimension, the second dimension, and the third dimension is equal to the sum of the fourth dimension, the fifth dimension, and the sixth dimension. Among them, the sum of the first dimension, the second dimension, and the third dimension can be the pixel pitch of the pixel unit composed of the first sub-pixel B of the first light-emitting diode chip, the second sub-pixel G of the first light-emitting diode chip, and the first sub-pixel R of the second light-emitting diode chip. Similarly, the sum of the fourth dimension, the fifth dimension, and the sixth dimension can all be the pixel pitch of the pixel unit composed of the second sub-pixel B of the second light-emitting diode chip, the first sub-pixel G of the third light-emitting diode chip, and the second sub-pixel R of the third light-emitting diode chip. Of course, in other embodiments, the first dimension, the second dimension, the third dimension, the fourth dimension, the fifth dimension, and the sixth dimension can be unequal. The sum of the first dimension, the second dimension, and the third dimension may not be equal to the sum of the fourth dimension, the fifth dimension, and the sixth dimension.

[0275] Continue to refer to Figure 63 Along the first direction x, in the chip group CG1, the size of the first sub-pixel B of the first light-emitting diode chip is m. The distance between the first sub-pixel B of the first light-emitting diode chip in the chip group CG1 and the first sub-pixel B of the first light-emitting diode chip in the chip group CG3 is n.

[0276] The first sub-pixel B, the second sub-pixel G of the first light-emitting diode chip in the chip group CG1, and the first sub-pixel R of the second light-emitting diode chip can form a pixel unit. The sum of m and n can be the pixel pitch of the pixel unit along the first direction x. The sum of a, b, c, d, e, and f can be the pixel pitch of the pixel unit along the second direction y. The sum of m and n and the sum of a, b, c, d, e, and f can be equal or unequal.

[0277] When the number of sub-pixels of the chip group along the first direction x is 1, along the first direction x, the sum of the size of the chip and the spacing between the chip groups can be flexibly adjusted, that is, Figure 63 The sum of m and n shown in Figure 63 can be flexibly adjusted. In this way, display panels with different pixel sizes can be adapted.

[0278] When the number of sub-pixels of the chip group along the first direction x is greater than 1, along the first direction x, the sum of the size of the chip and the spacing between the chip groups is limited. Continuing to refer to Figure 63 (a) shown, taking the chip group having 2 sub-pixels along the first direction x as an example for illustration. In chip group CG1 and chip group CG2, the size of the first sub-pixel B is m. In chip group CG1, the spacing between two adjacent first sub-pixels B is n. In chip group CG2, the spacing between two adjacent first sub-pixels is p. The spacing between the first sub-pixel B of chip group CG1 and the first sub-pixel B of chip group CG2 is o. The above sizes need to satisfy that the sum of m and n, the sum of m and o, and the sum of m and p can be equal or not equal. m, n, o, and p can all be flexibly adjusted according to display panels with different pixel sizes to flexibly correspond to display panels with different pixel sizes.

[0279] In the embodiments of the present application, a plurality of light-emitting diode chips form a plurality of chip groups arranged in an array and a plurality of pixel units arranged in an array. Taking one light-emitting diode chip including one pixel sub-group and one pixel sub-group including two sub-pixels as an example, and taking a plurality of light-emitting diode chips forming a light-emitting diode chip group as an example, in the formed pixel units, the number of sub-pixels in the pixel units will be different, which will be described in detail below.

[0280] Referring to Figure 64 and Figure 65 shown, both light-emitting diode chip group CG1 and light-emitting diode chip group CG2 include light-emitting diode chip C1, light-emitting diode chip C2, and light-emitting diode chip C3.

[0281] The formed pixel units include an odd number of sub-pixels. For example, referring to Figure 64 shown, the formed pixel units PU1, pixel unit PU2, pixel unit PU3, and pixel unit PU4, each pixel unit has 3 sub-pixels. Referring to Figure 65 shown, the formed pixel units PU1 and pixel unit PU2, each pixel unit has 5 sub-pixels. In other embodiments, the number of sub-pixels in the pixel unit can also be 7, 9, 11 or more odd numbers.

[0282] Among them, in each light-emitting diode chip, the distance between two adjacent sub-pixels can be d1. The distance between adjacent chip groups can be d2. The distance between adjacent pixel units can be d3. The distance between two adjacent light-emitting diode chips can be d4. When the number of sub-pixels in a pixel unit is odd, d1, d2, d3, and d4 are all equal, which can ensure the light emission uniformity of each light-emitting diode chip.

[0283] Referring to Figure 66 and Figure 67 As shown, the light-emitting diode chip group CG1 and the light-emitting diode chip group CG2 both include a light-emitting diode chip C1, a light-emitting diode chip C2, and a light-emitting diode chip C3.

[0284] The formed pixel unit includes an even number of sub-pixels. For example, referring to Figure 66 As shown, the formed pixel units PU1, PU2, and PU3, and each pixel unit has 4 sub-pixels. Referring to Figure 67 As shown, the formed pixel units PU1 and PU2, and each pixel unit has 6 sub-pixels. In other embodiments, the number of sub-pixels in a pixel unit can also be 8, 10, or more even numbers.

[0285] When the number of sub-pixels in a pixel unit is even, d1, d2, d3, and d4 can all be equal, or they can be different from each other in pairs. That is, d1 can be not equal to d2, can be not equal to d3, and can be not equal to d4; d2 can be not equal to d3, and can be not equal to d4; d3 can be not equal to d4. Among them, d3 can be determined by the PPI of the full-color display screen prepared from this light-emitting diode chip group, and the flexible adjustment of d3 can achieve efficient layout for various applications from a watch to a large-size TV.

[0286] In this way, d1 can be less than d3, and the distance between sub-pixels in the light-emitting diode chip can be flexibly adjusted, so as to adjust the arrangement area of the light-emitting diode chip and avoid waste of the arrangement area. And, d2 can be greater than d1, which is convenient for the arrangement between light-emitting diode chips and convenient for assembly. Of course, when d1, d2, d3, and d4 are equal, the arrangement regularity of each sub-pixel, each light-emitting diode chip, each light-emitting diode chip group, and each pixel unit can be effectively improved, and the light emission uniformity can be improved.

[0287] Referring to Figure 68 and Figure 69 As shown, in some embodiments, a dual-color light-emitting diode chip can be combined with a single-color light-emitting diode chip to form a full-color chip group. Referring to Figure 68As shown, the light-emitting diode chip C1 includes two sub-pixels with different emission wavelengths (i.e., sub-pixel B and sub-pixel G), which is a two-color light-emitting diode chip. The light-emitting diode chip C2 includes one sub-pixel R. The two sub-pixels of the light-emitting diode chip C1 and the one sub-pixel of the light-emitting diode chip C2 can form a full-color pixel unit. In this embodiment, the sizes of the two sub-pixels of the light-emitting diode chip C1 and the one sub-pixel of the light-emitting diode chip C2 can be equal.

[0288] Referring to Figure 69 As shown, in some other embodiments, the sizes of the two sub-pixels of the light-emitting diode chip C1 and the one sub-pixel of the light-emitting diode chip C2 can be unequal. For example, the size of sub-pixel R is larger than the sizes of sub-pixel G and sub-pixel B.

[0289] Fourthly, an embodiment of the present application provides a display module. The display module includes a driving backplane and the above-mentioned light-emitting diode chip group. The light-emitting diode chip group is disposed on the driving backplane and is electrically connected to the driving backplane.

[0290] The driving backplane can be a TFT (Thin Film Transistor) driving backplane or a CMOS (Complementary Metal Oxide Semiconductor) driving backplane.

[0291] As a first implementable embodiment, referring to Figure 70 As shown, there are multiple light-emitting diode chip groups, and the multiple light-emitting diode chip groups are arranged in an array on the driving backplane 200. The driving backplane 200 can provide driving current for the multiple light-emitting diode chip groups, so as to drive the multiple light-emitting diode chip groups to emit light. Figure 70 shows that the light-emitting diode chip group CG1 and the light-emitting diode chip group CG2 are arranged on the driving backplane 200. In some embodiments, there may also be 3, 4 or more light-emitting diode chip groups, and the multiple light-emitting diode chip groups are arranged in an array.

[0292] Both the light-emitting diode chip group CG1 and the light-emitting diode chip group CG2 include the light-emitting diode chip C1, the light-emitting diode chip C2 and the light-emitting diode chip C3. Each light-emitting diode chip includes a pixel sub-group, and the pixel sub-group includes two sub-pixels. In some embodiments, the number of light-emitting diode chips in the light-emitting diode chip group, the number of pixel sub-groups and sub-pixels in the light-emitting diode chip can all be adjusted, and this embodiment does not limit this.

[0293] As a second implementable embodiment, referring to Figure 71As shown, the driving backplane 200 includes a driving substrate 201 and a plurality of driving units 202. One driving unit 202 is electrically connected to one light-emitting diode chip group correspondingly, and the plurality of driving units 202 are all electrically connected to the driving substrate 201. The driving unit 202 and the driving substrate 201 can also be TFT and CMOS.

[0294] One driving unit 202 and one light-emitting diode chip group can form a micro-display module. Figure 71 The micro-display modules DBM1 and DBM2 are shown, both of which are electrically connected to the driving substrate 201. The driving substrate 201 can provide driving current for the driving units 202 in the micro-display module, so as to drive the light-emitting diode chip group to emit light through the driving units 202. In some embodiments, the number of micro-display modules can be 3, 4, 5 or more. The specific value of this number is not limited in this embodiment.

[0295] Figure 71 The light-emitting diode chip group CG1 and the light-emitting diode chip group CG2 are shown being electrically connected to two different driving units 202 respectively, and the two driving units 202 are both electrically connected to the driving substrate 201. The light-emitting diode chip group CG1 and the light-emitting diode chip group CG2 both include a light-emitting diode chip C1, a light-emitting diode chip C2 and a light-emitting diode chip C3. Each light-emitting diode chip includes a pixel subgroup, and the pixel subgroup includes two sub-pixels. In this embodiment, the number of light-emitting diode chip groups, the number of light-emitting diode chips in the light-emitting diode chip group, and the number of pixel subgroups and sub-pixels in the light-emitting diode chips can all be adjusted, and this embodiment also does not limit this.

[0296] In a fifth aspect, an embodiment of the present application provides a full-color display screen, and the full-color display screen can be manufactured by encapsulating the above-mentioned display module.

[0297] In a sixth aspect, an embodiment of the present application provides an electronic device, and the electronic device includes the above-mentioned full-color display screen. The electronic device can be a television, an electronic watch, an e-book, a desktop computer, a laptop computer, a tablet computer, a mobile phone, an AR device (Augmented Reality), or a VR device (Virtual Reality), etc. When the light-emitting diode chip of the electronic device includes an ultraviolet pixel, the electronic device can also be an ultraviolet curing lamp or an ultraviolet detection lamp, etc.

[0298] In the description of the embodiments of the present application, it should be understood that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, or an indirect connection through an intermediate medium, or the communication inside two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances. The orientation or positional relationship indicated by the terms "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically and precisely defined.

[0299] The terms "first", "second", "third", "fourth", etc. (if any) in the specification, claims and above-mentioned drawings of the present application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0300] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A light emitting diode chip, characterized in that: It includes an N-type electrode, a P-type electrode, and a light-emitting layer disposed between the N-type electrode and the P-type electrode; the light-emitting layer is electrically connected to the N-type electrode and the P-type electrode respectively; The light-emitting layer comprises a first light-emitting layer having a first light-emitting wavelength and a second light-emitting layer having a second light-emitting wavelength, wherein the first light-emitting wavelength is shorter than the second light-emitting wavelength; At least part of the first light-emitting layer and at least part of the second light-emitting layer are stacked along the thickness direction of the light-emitting diode chip; in the stacked first light-emitting layer and the second light-emitting layer, the first light-emitting layer is located on a side of the second light-emitting layer close to the P-type electrode, and the light emitted by the first light-emitting layer is used to excite the second light-emitting layer to emit light; The first light-emitting layer and the second light-emitting layer are used to form at least two sub-pixels arranged side by side, and the at least two sub-pixels include a first sub-pixel having a first light-emitting wavelength and a second sub-pixel having a second light-emitting wavelength.

2. The light emitting diode chip according to claim 1, characterized in that: All of the first light-emitting layer and all of the second light-emitting layer are stacked; The surface of the first light-emitting layer facing away from the second light-emitting layer is electrically connected to the P-type electrode, and the surface of the second light-emitting layer facing away from the first light-emitting layer is electrically connected to the N-type electrode; The first light-emitting layer includes a first region and a second region arranged side by side and at intervals, and the second light-emitting layer includes a third region and a fourth region arranged side by side and at intervals; the first region and the third region are opposite to each other and are used to form the first sub-pixel, and the second region and the fourth region are opposite to each other and are used to form the second sub-pixel.

3. The light emitting diode chip according to claim 2, characterized in that: An isolation structure is also included, wherein the isolation structure is located between the first region and the second region, and between the third region and the fourth region.

4. The light emitting diode chip according to claim 2, characterized in that: It also includes a first filter layer and a second filter layer arranged side by side, the first filter layer corresponds to the first area, and the second filter layer corresponds to the second area; the first filter layer and the second filter layer are both located on the light emitting side of the light emitting diode; the passing wavelength of the first filter layer is the first light emitting wavelength, and the passing wavelength of the second filter layer is the second light emitting wavelength.

5. The light emitting diode chip according to claim 3, characterized in that: The N-type electrode comprises a first N-type electrode and a second N-type electrode separated from each other, the first N-type electrode electrically conducts to a surface of the third region away from the P-type electrode, and the second N-type electrode electrically conducts to a surface of the fourth region away from the P-type electrode; the isolation structure is also located between the first N-type electrode and the second N-type electrode; Alternatively, the P-type electrode includes a first P-type electrode and a second P-type electrode that are separate from each other, the first P-type electrode electrically conducts the surface of the third region away from the N-type electrode, and the second P-type electrode electrically conducts the surface of the fourth region away from the N-type electrode; the isolation structure is also located between the first P-type electrode and the second P-type electrode.

6. The light emitting diode chip according to claim 1, characterized in that: The first light-emitting layer includes a first region and a second region, the first region and at least a portion of the thickness of the second region are arranged side by side between the N-type electrode and the P-type electrode; the first region is stacked with the second light-emitting layer and is used to form the second sub-pixel; the second region is used to form the first sub-pixel; The surface of the first region facing away from the second light-emitting layer is electrically connected to the P-type electrode, the surface of the second light-emitting layer facing away from the first region is electrically connected to the N-type electrode, and the second region is electrically connected to the P-type electrode and the N-type electrode respectively.

7. The light emitting diode chip according to claim 6, characterized in that: It also includes a filter layer, which is located on the light-emitting side of the light-emitting diode and corresponds to the first area. The passing wavelength of the filter layer is the second light-emitting wavelength.

8. The light emitting diode chip according to claim 6, characterized in that: The first region and a partial thickness of the second region are arranged side by side, and the second light emitting layer and another partial thickness of the second region are arranged side by side.

9. The light emitting diode chip according to claim 8, characterized in that: Also included is an isolation structure, the isolation structure is located between the first region and the second region arranged side by side, and between the second light-emitting layer and the second region arranged side by side; The N-type electrode comprises a first N-type electrode and a second N-type electrode separated from each other, the first N-type electrode electrically conducts to a surface of the second light-emitting layer away from the P-type electrode, and the second N-type electrode electrically conducts to a surface of the second region away from the P-type electrode; the isolation structure is also located between the first N-type electrode and the second N-type electrode; Alternatively, the P-type electrode includes a first P-type electrode and a second P-type electrode that are separate from each other, the first P-type electrode electrically conducts the surface of the first region away from the N-type electrode, and the second P-type electrode electrically conducts the surface of the second region away from the N-type electrode; the isolation structure is also located between the first P-type electrode and the second P-type electrode.

10. The light emitting diode chip according to claim 6, characterized in that: The first region and the second region with a full thickness are arranged side by side, and the second light emitting layer and the N-type electrode with a partial thickness are arranged side by side.

11. The light emitting diode chip according to claim 10, characterized in that: It also includes an isolation structure, wherein the isolation structure is located between the first region and the second region, and between the second light-emitting layer and the N-type electrodes arranged side by side; The N-type electrode comprises a first N-type electrode and a second N-type electrode separated from each other, the first N-type electrode electrically conducts to a surface of the second light-emitting layer away from the P-type electrode, and the second N-type electrode electrically conducts to a surface of the second region away from the P-type electrode; the isolation structure is also located between the first N-type electrode and the second N-type electrode; Alternatively, the P-type electrode includes a first P-type electrode and a second P-type electrode that are separate from each other, the first P-type electrode electrically conducts the surface of the first region away from the N-type electrode, and the second P-type electrode electrically conducts the surface of the second region away from the N-type electrode; the isolation structure is also located between the first P-type electrode and the second P-type electrode.

12. The light emitting diode chip according to claim 1, characterized in that: The second light-emitting layer includes a third region and a fourth region, wherein the third region and at least a portion of the thickness of the fourth region are arranged side by side between the N-type electrode and the P-type electrode; the third region is stacked with the first light-emitting layer and is used to form the first sub-pixel; the fourth region is used to form the second sub-pixel; The surface of the third region facing away from the first light-emitting layer is electrically connected to the N-type electrode, the surface of the first light-emitting layer facing away from the third region is electrically connected to the P-type electrode, and the fourth region is electrically connected to the P-type electrode and the N-type electrode respectively.

13. The light emitting diode chip according to claim 12, characterized in that: It also includes a filter layer, which is located on the light output side of the light-emitting diode chip and corresponds to the third area, and the passing wavelength of the filter layer is the first light-emitting wavelength.

14. The light emitting diode chip according to claim 12, characterized in that: The third region is arranged side by side with a partial thickness of the fourth region, and the first light emitting layer is arranged side by side with another partial thickness of the fourth region.

15. The light emitting diode chip according to claim 14, characterized in that: Also included is an isolation structure, the isolation structure is located between the third region and the fourth region arranged side by side, and between the first light-emitting layer and the fourth region arranged side by side; The N-type electrode comprises a first N-type electrode and a second N-type electrode separated from each other, the first N-type electrode electrically conducts to a surface of the third region away from the P-type electrode, and the second N-type electrode electrically conducts to a surface of the fourth region away from the P-type electrode; the isolation structure is also located between the first N-type electrode and the second N-type electrode; Alternatively, the P-type electrode includes a first P-type electrode and a second P-type electrode that are separate from each other, the first P-type electrode electrically conducts the surface of the first light-emitting layer that is away from the N-type electrode, and the second P-type electrode electrically conducts the surface of the fourth region that is away from the N-type electrode; the isolation structure is also located between the first P-type electrode and the second P-type electrode.

16. The light emitting diode chip according to claim 12, characterized in that: The third region is arranged side by side with the fourth region having a full thickness, and the first light emitting layer is arranged side by side with the P-type electrode having a partial thickness.

17. The light emitting diode chip according to claim 16, characterized in that: It also includes an isolation structure, which is located between the third region and the fourth region, and between the first light-emitting layer and the P-type electrodes arranged side by side; The N-type electrode comprises a first N-type electrode and a second N-type electrode separated from each other, the first N-type electrode electrically conducts to a surface of the third region away from the P-type electrode, and the second N-type electrode electrically conducts to a surface of the fourth region away from the P-type electrode; the isolation structure is also located between the first N-type electrode and the second N-type electrode; Alternatively, the P-type electrode includes a first P-type electrode and a second P-type electrode that are separate from each other, the first P-type electrode electrically conducts the surface of the first light-emitting layer that is away from the N-type electrode, and the second P-type electrode electrically conducts the surface of the fourth region that is away from the N-type electrode; the isolation structure is also located between the first P-type electrode and the second P-type electrode.

18. The light emitting diode chip according to any one of claims 1 to 17, characterized in that: The light-emitting layer further comprises a third light-emitting layer having a third light-emitting wavelength, wherein the third light-emitting wavelength is smaller than the first light-emitting wavelength; Along the thickness direction of the light-emitting diode chip, the third light-emitting layer is stacked with at least one of the first light-emitting layer and the second light-emitting layer; in the stacking area, the third light-emitting layer is located on the side of the corresponding stacked light-emitting layer close to the P-type electrode, and the light emitted by the third light-emitting layer is used to excite the corresponding stacked light-emitting layer to emit light.

19. The light emitting diode chip according to claim 18, characterized in that: At least a portion of the third light-emitting layer is stacked with the first light-emitting layer and the second light-emitting layer; In the stacked first light-emitting layer, second light-emitting layer and third light-emitting layer, along the direction from the P-type electrode to the N-type electrode, the third light-emitting layer, the first light-emitting layer and the second light-emitting layer are arranged in sequence, and the light emitted by the third light-emitting layer is used to excite the first light-emitting layer and the second light-emitting layer to emit light.

20. The light emitting diode chip according to any one of claims 2 to 19, characterized in that: The invention also comprises a reflective layer, wherein the reflective layer is located at the backlight side of the light emitting diode chip.

21. The light emitting diode chip according to any one of claims 2 to 19, characterized in that: It also includes a light-blocking layer, which is located on the light-emitting side of the light-emitting diode chip and between two adjacent sub-pixels.

22. The light emitting diode chip according to any one of claims 2 to 19, characterized in that: The invention also includes a hole blocking layer, which is arranged between any two adjacent layers of the stacked first light-emitting layer, the second light-emitting layer and the third light-emitting layer.

23. The light emitting diode chip according to any one of claims 2 to 19, characterized in that: The first light-emitting layer, the second light-emitting layer and the third light-emitting layer are any three of a red light-emitting material layer, a green light-emitting material layer, a blue light-emitting material layer, a purple light-emitting material layer and an ultraviolet light-emitting material layer respectively.

24. The light emitting diode chip according to any one of claims 3, 5, 9, 11, 15 and 17, characterized in that: The isolation structure includes a channel; or, the isolation structure includes a channel and an isolation material disposed in the channel; or, the isolation structure is an ion implantation layer; The light-emitting diode chip further includes an N-type semiconductor layer and a P-type semiconductor layer, wherein the N-type semiconductor and the P-type semiconductor are respectively located on opposite sides of the light-emitting layer in the thickness direction, the N-type electrode is electrically connected to the light-emitting layer through the N-type semiconductor, and the P-type electrode is electrically connected to the light-emitting layer through the P-type semiconductor; When the N-type electrode includes a first N-type electrode and a second N-type electrode separated from each other, at least a portion of the isolation structure extends into the P-type semiconductor layer; When the P-type electrode includes a first P-type electrode and a second P-type electrode that are separate from each other, at least a portion of the isolation structure extends into the N-type semiconductor layer.

25. The light emitting diode chip according to any one of claims 1 to 17, characterized in that: At least two of the sub-pixels form one pixel subgroup or a plurality of pixel subgroups; The same pixel subgroup includes a plurality of sub-pixels, and among the plurality of sub-pixels, the number of the first sub-pixels and the number of the second sub-pixels are equal to or different from each other.

26. The light emitting diode chip according to claim 25, characterized in that: The light-emitting layer includes at least two pixel subgroups, at least two pixel subgroups are arranged in sequence along a first direction, and the first subpixels and the second subpixels are arranged in sequence along a second direction; wherein the first direction and the second direction intersect each other.

27. The light emitting diode chip according to claim 26, characterized in that: The pixel subgroups include a first pixel subgroup and a second pixel subgroup, the first subpixel of the first pixel subgroup and the first subpixel of the second pixel subgroup have the same light emission wavelength, and the second subpixel of the first pixel subgroup and the second subpixel of the second pixel subgroup have the same light emission wavelength; Along the first direction, the first subpixel of the first pixel subgroup corresponds to the first subpixel of the second pixel subgroup, and the second subpixel of the first pixel subgroup corresponds to the second subpixel of the second pixel subgroup; or, the first subpixel of the first pixel subgroup corresponds to the second subpixel of the second pixel subgroup, and the second subpixel of the first pixel subgroup corresponds to the first subpixel of the second pixel subgroup.

28. The light emitting diode chip according to claim 26, characterized in that: The N-type electrode comprises at least two separate sub-N-type electrodes, and the number of the sub-N-type electrodes is the same as the number of the sub-pixels; one side of a sub-pixel facing away from the P-type electrode is electrically connected to one sub-N-type electrode; A side of the sub-pixel facing away from the N-type electrode is electrically connected to the P-type electrode; Alternatively, the P-type electrode includes at least two separate sub-P-type electrodes, and the number of the sub-P-type electrodes is the same as the number of the sub-pixels; one side of the sub-pixel facing away from the N-type electrode is electrically connected to a corresponding sub-P-type electrode; and one side of the sub-pixel facing away from the P-type electrode is electrically connected to the N-type electrode.

29. The light emitting diode chip according to claim 26, characterized in that: The N-type electrode includes at least two separate sub-N-type electrodes, and the number of the sub-N-type electrodes is the same as the number of the sub-pixels; the P-type electrode includes at least two separate sub-P-type electrodes, and the number of the sub-P-type electrodes is less than the number of the sub-pixels; one side of a sub-pixel away from the P-type electrode is electrically connected to one sub-N-type electrode, and one side of a part of the sub-pixels away from the N-type electrode is electrically connected to the same sub-P-type electrode; Or, the P-type electrode includes at least two separate sub-P-type electrodes, and the number of the sub-P-type electrodes is the same as the number of the sub-pixels; the N-type electrode includes at least two separate sub-N-type electrodes, and the number of the sub-N-type electrodes is less than the number of the sub-pixels; one side of the sub-pixel facing away from the N-type electrode is electrically connected to one sub-P-type electrode, and one side of a part of the sub-pixels facing away from the P-type electrode is electrically connected to the same sub-N-type electrode.

30. The light emitting diode chip according to any one of claims 1 to 17, characterized in that: The size of the light emitting diode chip is greater than or equal to 50 microns; And / or, the shape of the light-emitting diode chip is any one of a rectangle, a square, a circle, an ellipse, a triangle, a rhombus, a parallelogram and a polygon with more than four sides; and / or, the sub-pixel has a size ranging from 0.001 to 200 micrometers; And / or, the sub-pixel has a shape of any one of a rectangle, a square, a circle, an ellipse, a triangle, a rhombus, a parallelogram and a polygon with more than four sides; And / or, the shapes of different sub-pixels are the same or different; And / or, sizes of different sub-pixels are equal or different.

31. The light emitting diode chip according to any one of claims 1 to 17, characterized in that: It also includes a buffer layer, an N-type semiconductor layer, a P-type semiconductor layer, a current spreading layer, a reflective layer and a first insulating layer; The buffer layer and the N-type semiconductor layer are stacked, the light-emitting layer is arranged on a side of the N-type semiconductor layer away from the buffer layer, and the P-type semiconductor layer is arranged on a side of the light-emitting layer away from the buffer layer; The current spreading layer is in contact with a side of the P-type semiconductor layer away from the buffer layer, the N-type electrode is in contact with the N-type semiconductor layer, and the P-type electrode is in contact with the P-type semiconductor layer and the current spreading layer; The first insulating layer is arranged on a side of the current spreading layer away from the buffer layer; The reflective layer is arranged on a side of the buffer layer away from the light-emitting layer, or the reflective layer is arranged on a side of the first insulating layer away from the buffer layer, and a second insulating layer is further arranged on the side of the reflective layer away from the buffer layer.

32. The light emitting diode chip according to claim 31, characterized in that: It also includes a substrate, which is arranged on a side of the buffer layer away from the light-emitting layer; When the reflective layer is disposed on a side of the buffer layer away from the light-emitting layer, the reflective layer is disposed on a side of the substrate away from the buffer layer.

33. The light emitting diode chip according to any one of claims 1 to 17, characterized in that: Also includes a bonding substrate, a binding layer, an N-type semiconductor layer, a P-type semiconductor layer and a reflective layer; The bonding substrate and the binding layer are sequentially arranged on the P-type electrode, and the P-type semiconductor layer is arranged on a side of the binding layer away from the bonding substrate and in contact with the binding layer; The light emitting layer is arranged on a side of the P-type semiconductor layer away from the bonding substrate, the N-type semiconductor layer is arranged on a side of the light emitting layer away from the bonding substrate, and the N-type electrode contacts the side of the N-type semiconductor layer away from the bonding substrate; The reflective layer is arranged on a side of the P-type semiconductor layer close to the bonding substrate.

34. The light emitting diode chip according to any one of claims 1 to 17, characterized in that: It also includes a color conversion layer, which is arranged on the light-emitting side of a portion of the light-emitting diode chip and corresponds to at least a portion of the sub-pixel area.

35. A light emitting diode chipset, characterized in that: Comprising a plurality of light emitting diode chips as claimed in any one of claims 1 to 34, wherein the plurality of light emitting diode chips are arranged in an array; The two adjacent LED chips include a first LED chip and a second LED chip, and a part of the sub-pixels of the first LED chip and a part of the sub-pixels of the second LED chip together form a pixel unit.

36. The light emitting diode chipset according to claim 35, characterized in that: The light emitting wavelengths of the two sub-pixels of the first light emitting diode chip and the light emitting wavelengths of one sub-pixel of the second light emitting diode chip are different.

37. The light emitting diode chip set according to claim 36, characterized in that: The entire area of ​​the two sub-pixels of the first LED chip and the entire area of ​​one sub-pixel of the second LED chip together form one pixel unit.

38. The light emitting diode chipset according to claim 36, characterized in that: Partial areas of two sub-pixels of the first LED chip and partial areas of one sub-pixel of the second LED chip together form one pixel unit.

39. The light emitting diode chipset according to claim 35, characterized in that: Among the at least two sub-pixels of the first LED chip and the at least two sub-pixels of the second LED chip, some of the sub-pixels have the same light emission wavelength; Furthermore, at least two of the sub-pixels of the first LED chip and at least two of the sub-pixels of the second LED chip together form one pixel unit.

40. The light emitting diode chip set according to any one of claims 35 to 39, characterized in that: The first LED chip and the second LED chip are both of special shapes, the first LED chip has a protruding area, and the second LED chip has a concave area; The protruding area and the recessed area are matched in shape and fit together.

41. The light emitting diode chipset according to claim 35, characterized in that: It also includes a third light-emitting diode chip, wherein the first light-emitting diode chip, the second light-emitting diode chip and the third light-emitting diode chip are arranged adjacent to each other in sequence; The first sub-pixel and the second sub-pixel of the first LED chip and the first sub-pixel of the second LED chip have different light emission wavelengths and together constitute a first pixel unit; The second sub-pixel of the second LED core, the first sub-pixel and the second sub-pixel of the third LED chip have different light emission wavelengths and together form a second pixel unit; The first LED chip, the second LED chip and the third LED chip together form a chipset; Wherein, the plurality of light emitting diode chips form a plurality of chip groups arranged in an array.

42. The light emitting diode chipset according to claim 35, characterized in that: The plurality of light-emitting diode chips form a plurality of chip groups arranged in an array and a plurality of pixel units arranged in an array; in the same light-emitting diode chip, the spacing between adjacent sub-pixels is d1; the spacing between adjacent chip groups is d2; the spacing between adjacent pixel units is d3; and the spacing between adjacent light-emitting diode chips is d4; When the pixel unit includes an odd number of sub-pixels, d1, d2, d3 and d4 are all equal; When the pixel unit includes an even number of the sub-pixels, d1, d2, d3 and d4 are all equal, or d1, d2, d3 and d4 are not equal to each other.

43. A display module, characterized in that: It comprises a driving backplane and a light-emitting diode chipset as described in any one of claims 34-42, wherein the light-emitting diode chipset is arranged on the driving backplane and electrically connected to the driving backplane.

44. The display module according to claim 43, characterized in that: There are multiple light emitting diode chip groups; A plurality of the light emitting diode chip groups are arranged in an array on the driving backplane; Alternatively, the driving backplane includes a driving substrate and a plurality of driving units, one of the driving units is electrically connected to one of the light emitting diode chipsets, and the plurality of driving units are electrically connected to the driving substrate.

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