Light-emitting diode chip, chip set thereof and display module

Abstract

The invention provides a light-emitting diode chip, a chip set thereof and a display module, and relates to the technical field of semiconductors, the light-emitting diode chip comprises an N-type electrode, a P-type electrode and a light-emitting layer, and the light-emitting layer comprises N light-emitting materials with different light-emitting wavelengths; at least one light-emitting material in the N light-emitting materials and the other light-emitting materials are stacked, and light emitted by the light-emitting material is used for exciting the other light-emitting materials to emit light; the N light-emitting materials are used for forming M sub-pixels arranged side by side, and the light-emitting wavelengths of at least part of the sub-pixels are unequal; n and M are positive integers greater than or equal to 3. The light-emitting diode chip has two light-emitting mechanisms of photoluminescence and electroluminescence at the same time. According to the invention, the sizes of the light-emitting diode chips and the full-color chip set can be flexibly adjusted, and the transfer number and transfer difficulty in mass transfer are reduced, so that the problems of process, yield and cost represented by mass transfer in ultra-high-density pixel display products can be solved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a light-emitting diode chip, a chip set thereof, and a display module. Background Art

[0002] In semiconductor lighting technology, a light-emitting diode (LED), as a light-emitting device that converts electrical energy into light energy, has the advantages of energy conservation, environmental protection, long service life, and high luminous efficiency, and is widely used in many fields such as indication, display, decoration, and lighting.

[0003] When an LED is applied to the display field, a super-high-density display product mainly based on a micro light-emitting diode (micro LED) usually forms a pixel unit with three independent single chips, that is, a pixel unit is composed of three single-core monochromatic single sub-pixels. The number of chips in the micro LED is extremely large and the chip size is small. In the manufacturing process of the micro LED, a mass transfer process needs to be used.

[0004] However, the above-mentioned manufacturing process of the micro LED has problems of high process difficulty, low yield, and high cost. Summary of the Invention

[0005] This application provides a light-emitting diode chip, a chip set thereof, and a display module, which can flexibly adjust the sizes of the light-emitting diode chip and the full-color chip set, reduce the transfer quantity and transfer difficulty in mass transfer, and thus can overcome problems such as processes, yield, and cost represented by mass transfer in super-high-density pixel display products.

[0006] In a first aspect, this application provides a light-emitting diode chip. The light-emitting diode chip includes an N-type electrode, a P-type electrode, and a light-emitting layer disposed between the N-type electrode and the P-type electrode; the light-emitting layer is electrically connected to the N-type electrode and the P-type electrode respectively.

[0007] The light-emitting layer includes N light-emitting materials with different emission wavelengths; along the thickness direction of the light-emitting diode chip, at least one of the N light-emitting materials is stacked with the remaining light-emitting materials.

[0008] Among the several stacked light-emitting materials, at least one light-emitting material is located on the side of the remaining light-emitting materials close to the P-type electrode, and the light emitted by this light-emitting material is used to excite the remaining light-emitting materials to emit light.

[0009] The N light-emitting materials are used to form M sub-pixels arranged side by side. Among the M sub-pixels, at least some of the sub-pixels have different emission wavelengths; where N and M are both positive integers greater than or equal to 3.

[0010] In a second aspect, the present application provides a light-emitting diode chip group, including a plurality of the above-mentioned light-emitting diode chips. Along a direction intersecting the thickness direction of the light-emitting diode chips, the plurality of light-emitting diode chips are arranged in an array.

[0011] In a third aspect, the present application provides a display module, including a driving backplane and the above-mentioned light-emitting diode chip group. The light-emitting diode chip group is disposed on the driving backplane and electrically connected to the driving backplane.

[0012] For the light-emitting diode chip, its chip group, and the display module provided by the present application, by placing the light-emitting layer between the N-type electrode and the P-type electrode and electrically conducting with both, electrons provided by the N-type electrode and holes provided by the P-type electrode are combined in the light-emitting layer, and the light-emitting material in the light-emitting layer is excited to emit light. The light-emitting layer includes N light-emitting materials, and the emission wavelengths of the N light-emitting materials are different. The N light-emitting materials are used to form M sub-pixels arranged side by side, and the emission wavelengths of the M sub-pixels are different; where N and M are both positive integers greater than or equal to 3. In this way, the present application adopts a single-core multi-color multi-sub-pixel arrangement method, that is, a plurality of sub-pixels are used to form a pixel sub-group, and pixel units are formed by arranging the pixel sub-groups, thereby forming a full-color chip group. In the present application, a partial number of sub-pixels in a single chip can form a complete full-color pixel unit, and the use of this chip is more convenient. A partial number of sub-pixels in a plurality of chips can also be assembled into a complete full-color pixel unit, and the splicing method of this chip is relatively flexible, which can meet diverse display requirements.

[0013] In the present application, at least one of the N light-emitting materials is stacked with the remaining light-emitting materials. In this way, among the several stacked light-emitting materials, at least one light-emitting material is located on the side of the remaining light-emitting materials close to the P-type electrode, and the light emitted by this light-emitting material is used to excite the remaining light-emitting materials to emit light. In this way, two light-emitting mechanisms of electroluminescence and photoluminescence can be integrated in the light-emitting diode chip. The present application can flexibly adjust the size of the light-emitting diode chip and the chip group, reduce the transfer operation difficulty in the mass transfer process, and can reduce the number of mass transfers, thereby overcoming problems such as process, yield, and cost in ultra-high-density pixel display products represented by mass transfer.

[0014] The structure of the present application and its other invention purposes and beneficial effects will become more obvious and understandable through the description of the preferred embodiments in conjunction with the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0016] Figure 1 Top view of the first light-emitting diode chip provided by the embodiment of the present application;

[0017] Figure 2 Cross-sectional view of the first light-emitting diode chip provided by the embodiment of the present application;

[0018] Figure 3 Top view of the second light-emitting diode chip provided by the embodiment of the present application;

[0019] Figure 4 Cross-sectional view of the second light-emitting diode chip provided by the embodiment of the present application;

[0020] Figure 5 Top view of the third light-emitting diode chip provided by the embodiment of the present application;

[0021] Figure 6 Cross-sectional view of the third light-emitting diode chip provided by the embodiment of the present application;

[0022] Figure 7 Cross-sectional view of the fourth light-emitting diode chip provided by the embodiment of the present application;

[0023] Figure 8 Cross-sectional view of the fifth light-emitting diode chip provided by the embodiment of the present application;

[0024] Figure 9 Cross-sectional view of the sixth light-emitting diode chip provided by the embodiment of the present application;

[0025] Figure 10 Cross-sectional view of the seventh light-emitting diode chip provided by the embodiment of the present application;

[0026] Figure 11 Cross-sectional view of the eighth light-emitting diode chip provided by the embodiment of the present application;

[0027] Figure 12 Cross-sectional view of the ninth light-emitting diode chip provided by the embodiment of the present application;

[0028] Figure 13 Cross-sectional view of the tenth light-emitting diode chip provided by the embodiment of the present application;

[0029] Figure 14The cross-sectional view of the eleventh light-emitting diode chip provided by the embodiment of the present application;

[0030] Figure 15 The cross-sectional view of the twelfth light-emitting diode chip provided by the embodiment of the present application;

[0031] Figure 16 The cross-sectional view of the thirteenth light-emitting diode chip provided by the embodiment of the present application;

[0032] Figure 17 The cross-sectional view of the fourteenth light-emitting diode chip provided by the embodiment of the present application;

[0033] Figure 18 The cross-sectional view of the fifteenth light-emitting diode chip provided by the embodiment of the present application;

[0034] Figure 19 The cross-sectional view of the sixteenth light-emitting diode chip provided by the embodiment of the present application;

[0035] Figure 20 The cross-sectional view of the seventeenth light-emitting diode chip provided by the embodiment of the present application;

[0036] Figure 21 The cross-sectional view of the eighteenth light-emitting diode chip provided by the embodiment of the present application;

[0037] Figure 22 The cross-sectional view of the nineteenth light-emitting diode chip provided by the embodiment of the present application;

[0038] Figure 23 The cross-sectional view of the twentieth light-emitting diode chip provided by the embodiment of the present application;

[0039] Figure 24 The cross-sectional view of the twenty-first light-emitting diode chip provided by the embodiment of the present application;

[0040] Figure 25 The cross-sectional view of the twenty-second light-emitting diode chip provided by the embodiment of the present application;

[0041] Figure 26 The cross-sectional view of the twenty-third light-emitting diode chip provided by the embodiment of the present application;

[0042] Figure 27 The structural schematic diagram of the partial number of quantum pixels of the light-emitting diode chip provided by the embodiment of the present application sharing the N-type electrode;

[0043] Figure 28 The structural schematic diagram of the partial number of quantum pixels of the light-emitting diode chip provided by the embodiment of the present application sharing the P-type electrode;

[0044] Figure 29Top view of the first light-emitting diode chip provided by the embodiment of the present application;

[0045] Figure 30 Top view of the second light-emitting diode chip provided by the embodiment of the present application;

[0046] Figure 31 Top view of the third light-emitting diode chip provided by the embodiment of the present application;

[0047] Figure 32 Top view of the fourth light-emitting diode chip provided by the embodiment of the present application;

[0048] Figure 33 Top view of the fifth light-emitting diode chip provided by the embodiment of the present application;

[0049] Figure 34 Top view of the sixth light-emitting diode chip provided by the embodiment of the present application;

[0050] Figure 35 Top view of the seventh light-emitting diode chip provided by the embodiment of the present application;

[0051] Figure 36 Top view of the eighth light-emitting diode chip provided by the embodiment of the present application;

[0052] Figure 37 Top view of the ninth light-emitting diode chip provided by the embodiment of the present application;

[0053] Figure 38 Top view of the tenth light-emitting diode chip provided by the embodiment of the present application;

[0054] Figure 39 Top view of the eleventh light-emitting diode chip provided by the embodiment of the present application;

[0055] Figure 40 Top view of the twelfth light-emitting diode chip provided by the embodiment of the present application;

[0056] Figure 41 Top view of the thirteenth light-emitting diode chip provided by the embodiment of the present application;

[0057] Figure 42 Top view of the fourteenth light-emitting diode chip provided by the embodiment of the present application;

[0058] Figure 43 Schematic diagram of the first integrated structure of the light-emitting diode chip provided by the embodiment of the present application;

[0059] Figure 44 Schematic diagram of the second integrated structure of the light-emitting diode chip provided by the embodiment of the present application;

[0060] Figure 45 The third integrated structure schematic diagram of the light-emitting diode chip provided by the embodiment of the present application;

[0061] Figure 46 The fourth integrated structure schematic diagram of the light-emitting diode chip provided by the embodiment of the present application;

[0062] Figure 47 The flow schematic diagram of the first preparation method of the light-emitting diode chip provided by the embodiment of the present application;

[0063] Figure 48 The flow schematic diagram of the second preparation method of the light-emitting diode chip provided by the embodiment of the present application;

[0064] Figure 49 The flow schematic diagram of the third preparation method of the light-emitting diode chip provided by the embodiment of the present application;

[0065] Figure 50 The flow schematic diagram of the fourth preparation method of the light-emitting diode chip provided by the embodiment of the present application;

[0066] Figure 51 The flow schematic diagram of the fifth preparation method of the light-emitting diode chip provided by the embodiment of the present application;

[0067] Figure 52 The size diagram of the light-emitting diode chip group provided by the embodiment of the present application;

[0068] Figure 53 The top view of the first light-emitting diode chip group provided by the embodiment of the present application;

[0069] Figure 54 The top view of the second light-emitting diode chip group provided by the embodiment of the present application;

[0070] Figure 55 The top view of the third light-emitting diode chip group provided by the embodiment of the present application;

[0071] Figure 56 The top view of the fourth light-emitting diode chip group provided by the embodiment of the present application;

[0072] Figure 57 The top view of the fifth light-emitting diode chip group provided by the embodiment of the present application;

[0073] Figure 58 The top view of the sixth light-emitting diode chip group provided by the embodiment of the present application;

[0074] Figure 59Top view of the seventh light-emitting diode chipset provided by the embodiments of the present application;

[0075] Figure 60 Top view of the eighth light-emitting diode chipset provided by the embodiments of the present application;

[0076] Figure 61 Top view of the ninth light-emitting diode chipset provided by the embodiments of the present application;

[0077] Figure 62 Top view of the tenth light-emitting diode chipset provided by the embodiments of the present application;

[0078] Figure 63 Top view of the eleventh light-emitting diode chipset provided by the embodiments of the present application;

[0079] Figure 64 Top view of the twelfth light-emitting diode chipset provided by the embodiments of the present application;

[0080] Figure 65 First structural schematic diagram of the display module provided by the embodiments of the present application;

[0081] Figure 66 Second structural schematic diagram of the display module provided by the embodiments of the present application.

[0082] Explanation of reference numerals:

[0083] 100, substrate; 101, buffer layer; 102, N-type electrode; 103, N-type semiconductor layer; 104, P-type electrode; 105, P-type semiconductor layer; 106, current spreading layer; 107, reflective layer; 108, first insulating layer; 109, second insulating layer; 110, bonding substrate; 111, bonding layer; 112, color conversion layer; 113, light-emitting layer; 113-1, first light-emitting material; 113-2, second light-emitting material; 113-3, third light-emitting material; 113-n-1, (n-1)th light-emitting material; 113-n, nth light-emitting material; 114, isolation structure; 114a, isolation material; 115, hole blocking layer; 116, light-blocking layer; 117, light-filtering layer; 117a, first light-filtering layer; 117b, second light-filtering layer; 117c, third light-filtering layer; 200, driving backplane; 201, driving substrate; 202, driving unit. Detailed implementation manners

[0084] In LED display products, usually three single-core, single-color, single-sub-pixel chips are used to form a pixel unit. In ultra-high density display products represented by micro LEDs, the size of a single chip is small, and the overall number of chips forming the display product is large. In the manufacturing process of the display product, micro LED chips need to be grown on a wafer, and then transferred to a specific substrate through a mass transfer technology to complete the bonding and assembly. In the mass transfer process, due to the small size and large number of chips, the transfer operation is difficult, the number of operations is numerous, and the alignment requirements for operations on the substrate are high. As a result, the manufacturing process of micro LED display products is difficult, the yield is low, the production cycle is long, and the cost is high.

[0085] In related technologies, in LED display products, several chips are encapsulated together through a MIP (Micro LED in Package) packaging process to form an integrated chip group that can emit multiple wavelengths. The traditional MIP packaging process is applicable to LED display products with a pixel size greater than 0.3 mm. In the MIP packaging process, limited by the existing mass transfer technology capabilities, the size of the single-core, single-color, single-sub-pixel chips used needs to be large, that is, the sub-pixel size is large. A single chip group is usually a pixel unit, and the number of chips and chip groups applied to the application side is large.

[0086] The light-emitting diode chip, its chip group, and the display module provided in this application place the light-emitting layer between the N-type electrode and the P-type electrode and are electrically connected to both, so that the electrons provided by the N-type electrode and the holes provided by the P-type electrode are combined in the light-emitting layer, and the light-emitting material in the light-emitting layer is excited to emit light. The light-emitting layer includes N light-emitting materials, and the emission wavelengths of the N light-emitting materials are different. The N light-emitting materials are used to form M sub-pixels arranged side by side, and the emission wavelengths of the M sub-pixels are different; where N and M are positive integers greater than or equal to 3. In this way, this application adopts the arrangement method of single-core, multi-color, and multi-sub-pixels, that is, multiple sub-pixels are used to form a pixel subgroup, and a full-color pixel unit is formed through the arrangement of the pixel subgroups, thereby forming a full-color chip group. In this application, a partial number of sub-pixels in a single chip can form a complete full-color pixel unit, and the use of this chip is more convenient. A partial number of sub-pixels in multiple chips can also be assembled into a complete full-color pixel unit, and the splicing method of this chip is relatively flexible and can meet diverse display requirements.

[0087] By laminating at least one of the N light-emitting materials with the remaining light-emitting materials in the thickness direction of the light-emitting diode chip. In this way, among the several laminated light-emitting materials, at least one light-emitting material is located on the side of the remaining light-emitting materials close to the P-type electrode, and the light emitted by this light-emitting material is used to excite the remaining light-emitting materials to emit light. In this way, two light-emitting mechanisms, namely electroluminescence and photoluminescence, can be integrated in the light-emitting diode chip. The present application can flexibly adjust the size of the light-emitting diode chip and the chip group, reduce the difficulty of the transfer operation in the mass transfer process, and can reduce the number of mass transfers, thereby overcoming the problems of process, yield, and cost in high-density pixel display products represented by mass transfer.

[0088] Compared with the integrated chip group that emits multiple wavelengths formed by integrating several chips in the related art, the related art needs to overcome the process difficulties of integrating multiple chips, so the process difficulty is relatively large, the yield is relatively low, and the cost is relatively high. The present application directly obtains multi-color and multi-sub-pixels in a single light-emitting diode chip, with a simpler process, lower technical difficulty, and lower cost.

[0089] Furthermore, by using the single-core multi-color and multi-sub-pixel light-emitting diode chip or the light-emitting diode chip group of the present application, under the condition of the same light-emitting area and the same pixel density (Pixels Per Inch, abbreviated as PPI), it is possible to flexibly adjust the size of the light-emitting diode chip while ensuring a small sub-pixel size, and at the same time, the number of light-emitting diode chips is greatly reduced, thereby overcoming the problems of relatively large preparation process difficulty, relatively low product yield, and relatively high preparation cost, and contributing to the rapid mass production of mini LED and micro LED.

[0090] The single-core multi-color and multi-sub-pixel chip in the present application includes n full-color pixel units, where n is a positive integer greater than or equal to 1. The single-core multi-color and multi-sub-pixel chip can be directly combined with the backplane, and a single chip can achieve the effect of n MIP packages. When the single-core multi-color and multi-sub-pixel light-emitting diode chips of the present application are used to form a full-color integrated chip group (for example, a chip group is formed by combining three 3*n chips), n*3 pixel units can be obtained. When combined with the backplane, the chip group used is 1 / 3n of the traditional MIP package, greatly reducing the preparation time, reducing the process and raw material costs, and at the same time greatly improving the yield. Furthermore, the pixel size applicable to the full-color integrated package of the present application can be flexibly adjusted and can be much smaller than the pixel size applicable to the traditional MIP process.

[0091] To make the objectives, technical solutions, and advantages of this application clearer, the following will describe in more detail the technical solutions in the embodiments of this application with reference to the accompanying drawings in the preferred embodiments of this application. In the drawings, the same or similar reference numerals throughout represent the same or similar components or components with the same or similar functions. The described embodiments are some, but not all, of the embodiments of this application. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain this application and should not be construed as limiting this application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in this application without creative efforts fall within the scope of protection of this application. The following will explain in detail the embodiments of this application with reference to the accompanying drawings.

[0092] In this application, some terms can be understood as having the following meanings:

[0093] Sub pixel (abbreviated as SP): A single blue light pixel, or a single green light pixel, or a single red light pixel is called a sub pixel. In this patent, a sub pixel can also be a single arbitrary wavelength.

[0094] Pixel subgroup (abbreviated as PSG): A combination formed by multiple sub pixels.

[0095] Pixel unit (abbreviated as PU): A unit including the three primary colors of blue light sub pixels, green light sub pixels, and red light sub pixels, or including other three or more different wavelengths that can form white light sub pixels.

[0096] Single-core single-color single-sub pixel chip: A single light-emitting diode chip can only emit one wavelength of light and only contains one sub pixel, such as one blue light sub pixel, or one green light sub pixel, or one red light sub pixel.

[0097] Single-core single-color multi-sub pixel chip: A single chip can only emit one wavelength of light, but contains two or more sub pixels, such as two red light sub pixels, three red light sub pixels, or more red light sub pixels.

[0098] Single-core multi-color multi-sub pixel chip: A single chip can emit multiple different wavelengths of light and contains three or more sub pixels, such as one red light sub pixel + one green light sub pixel + one blue light sub pixel, two red light sub pixels + two green light sub pixels + two blue light sub pixels, multiple blue light sub pixels + multiple red light sub pixels + multiple green light sub pixels.

[0099] Light-emitting diode chip (abbreviated as C): A solid-state semiconductor device with a light-emitting layer between a P-type electrode and an N-type electrode. It is hereinafter simply referred to as "chip" in the text.

[0100] Light-emitting diode chip group (abbreviated as CG): Composed of two or more single-core dual (single)-color multi-subpixel chips, including one or more pixel units.

[0101] Microdisplay module (abbreviated as DMB): A display device formed by electrically connecting a light-emitting diode chip group and a driving backplane.

[0102] In a first aspect, referring to Figure 1-26 As shown, the present application provides a light-emitting diode chip. The chip includes an N-type electrode 102, a P-type electrode 104, and a light-emitting layer 113 disposed between the N-type electrode 102 and the P-type electrode 104; the light-emitting layer 113 is electrically conductive with the N-type electrode 102 and the P-type electrode 104 respectively;

[0103] The light-emitting layer 113 includes N light-emitting materials, and the emission wavelengths of the N light-emitting materials are different; along the thickness direction of the chip, at least one of the N light-emitting materials is stacked with the remaining light-emitting materials;

[0104] Among the several stacked light-emitting materials, at least one light-emitting material is located on the side of the remaining light-emitting materials close to the P-type electrode 104, and the light emitted by this light-emitting material is used to excite the remaining light-emitting materials to emit light;

[0105] The N light-emitting materials are used to form M subpixels arranged side by side, and among the M subpixels, at least some of the emission wavelengths are different; where N and M are both positive integers greater than or equal to 3.

[0106] It should be noted that an electric field is formed between the N-type electrode 102 and the P-type electrode 104, and the light-emitting layer 113 is disposed between the N-type electrode 102 and the P-type electrode 104, which can be understood as the light-emitting layer 113 is located in this electric field. Referring to Figure 2 、 4 、6, and 7-26, along the thickness direction of the chip, all of the light-emitting layer 113 or a part of the thickness of the light-emitting layer 113 is located between the N-type electrode 102 and the P-type electrode 104. The light-emitting layer 113 is electrically conductive with the N-type electrode 102 and the P-type electrode 104 respectively, which may mean that the light-emitting layer 113 is in contact conduction with the N-type electrode 102 and the P-type electrode 104 respectively, or the light-emitting layer 113 is electrically conductive with the N-type electrode 102 through the N-type semiconductor layer 103 and is electrically conductive with the P-type electrode 104 through the P-type semiconductor layer 105.

[0107] Among them, the light-emitting layer 113 includes N light-emitting materials, where N is a positive integer greater than or equal to 3. In the following text, multiple light-emitting materials and N light-emitting materials have the same meaning. For example, on the basis that the N light-emitting materials are not equal, the N light-emitting materials may include a first light-emitting material 113-1 that emits blue light, a second light-emitting material 113-2 that emits green light, a third light-emitting material 113-3 that emits red light, an (n - 1)th light-emitting material 113-(n - 1) that emits purple light, and an nth light-emitting material 113-n that emits the remaining wavelengths that are not equal to the wavelengths of the above-mentioned lights. In other embodiments, the emission wavelengths of the above light-emitting materials can also be adjusted, and the present application does not limit this. Among them, n is a positive integer greater than or equal to 1 and less than or equal to N.

[0108] Among the N light-emitting materials, along the thickness direction of the chip, at least one light-emitting material is stacked on the side of the remaining light-emitting materials closer to the P-type electrode 104. Among the stacked light-emitting materials, the light emitted by the at least one light-emitting material can be used to excite the remaining light-emitting materials to emit light. Refer to Figure 2 、 4 As shown in 6, the first light-emitting material 113-1 is stacked on the side of the second light-emitting material 113-2 to the nth light-emitting material 113-n closer to the P-type electrode 104, and the light emitted by the first light-emitting material 113-1 can be used to excite the second light-emitting material 113-2 to the nth light-emitting material 113-n to emit light. Among them, the light-emitting mechanism of the first light-emitting material 113-1 is electroluminescence, and the light-emitting mechanisms of the second light-emitting material 113-2 to the nth light-emitting material 113-n are all photoluminescence.

[0109] The above light-emitting materials can form M sub-pixels arranged side by side on the chip, and M is also a positive integer greater than or equal to 3. Refer to Figure 1 、 3 As shown in 5, the chip includes a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3... an mth sub-pixel SPm. Among them, m is a positive integer greater than or equal to 1 and less than or equal to M. For example, the first light-emitting material 113-1 corresponds to the first sub-pixel SP1, and the first sub-pixel SP1 is a blue photon sub-pixel. The second light-emitting material 113-2 corresponds to the second sub-pixel SP2, and the second sub-pixel SP2 is a green photon sub-pixel. The third light-emitting material 113-3 corresponds to the third sub-pixel SP3, and the third sub-pixel SP3 is a red photon sub-pixel.

[0110] In the present application, "side by side" or "arranged side by side" may refer to being arranged along a direction perpendicular to the thickness direction of the chip. That is, located at the same thickness position of the chip; it may also refer to being on the same layer of the chip, and having a dislocation in the thickness direction of the chip can also be considered side by side or arranged side by side.

[0111] Taking a single-core three-color three sub-pixels as an example, the chip may include a first sub-pixel, a second sub-pixel, and a third sub-pixel with different emission wavelengths. The first sub-pixel, the second sub-pixel, and the third sub-pixel are any three of multiple wavelength sub-pixels such as red photon sub-pixels, green photon sub-pixels, blue photon sub-pixels, purple photon sub-pixels, and ultraviolet photon sub-pixels.

[0112] In this application, a light-emitting diode chip is formed by combining multiple sub-pixels with unequal emission wavelengths, that is, a single-core multi-color multi-sub-pixel arrangement is adopted. Compared with the related art that uses a single sub-pixel to form a chip, this application can flexibly adjust the size of the light-emitting diode chip, reduce the transfer difficulty and alignment difficulty in the mass transfer operation. Moreover, it can effectively reduce the number of light-emitting diode chips required for a display product with the same emission area and the same pixel density, thereby reducing the complexity of the mass transfer operation and the manufacturing cost. In this way, the yield of ultra-high density pixel display products can also be improved.

[0113] In some embodiments, M is greater than or equal to N. Refer to Figure 1-6 As shown, M can be equal to N, that is, one light-emitting material forms one sub-pixel. M can also be greater than N, that is, in the manufacturing process, one light-emitting material can form two or more sub-pixels with equal emission wavelengths.

[0114] In the chip of this application, among several stacked light-emitting materials, the emission wavelength of the light-emitting material close to the P-type electrode 104 is less than that of the light-emitting material far from the P-type electrode 104. During the operation of the chip, after the N-type electrode 102 is energized, electrons can be provided, and after the P-type electrode 104 is energized, holes can be provided. Among them, the holes and electrons can migrate to the positions corresponding to each light-emitting material, and after the holes and electrons recombine, light with the wavelength corresponding to the light-emitting material can be emitted. Based on the fact that the extension length of the holes is less than that of the electrons, the diffusion length of the holes determines the combination position of the holes and electrons. The light-emitting material with a smaller emission wavelength is arranged closer to the P-type electrode 104 side relative to the light-emitting material with a larger emission wavelength. In this way, the holes can migrate to the light-emitting material with a smaller emission wavelength to ensure the emission of this light-emitting material. The light emitted by this light-emitting material can further excite the light-emitting material with a smaller emission wavelength and closer to the N-type electrode 102 side to emit light.

[0115] If so, the light-emitting material with a smaller emission wavelength is disposed closer to the N-type electrode 102, and the light-emitting material with a larger emission wavelength is disposed closer to the P-type electrode 104. In this way, there is a possibility that holes cannot migrate to the position where the light-emitting material with a smaller emission wavelength is located, resulting in the inability of this light-emitting material to emit light. Moreover, the light emitted by the light-emitting material with a larger emission wavelength cannot excite the light-emitting material with a smaller emission wavelength to emit light, affecting the light extraction performance of the chip. Therefore, in the present application, the light-emitting material with a smaller emission wavelength is disposed on the side closer to the P-type electrode 104, which can enable the light-emitting material of the chip to emit light normally, thereby ensuring the light extraction performance of the chip.

[0116] In the chip of the present application, among the N light-emitting materials, the light-emitting material with the smallest emission wavelength is stacked on the side closer to the P-type electrode 104 of the remaining light-emitting materials. In this way, it can be ensured that when the chip is operating, electrons and holes can recombine at the position where the light-emitting material with the smallest emission wavelength is located, thereby ensuring that this light-emitting material can achieve electroluminescence. Moreover, the light-emitting material with the smallest emission wavelength can also be used to excite the remaining light-emitting materials to perform photoluminescence.

[0117] In the chip of the present application, referring to Figure 2 , 4 , 6, 7, and Figure 8-16 as shown, at least a part of each light-emitting material is electrically connected to the N-type electrode 102.

[0118] Referring to Figure 2 , 4 , 6, 7, and Figure 8-10 as shown, among the multiple light-emitting materials, except for the light-emitting material with the smallest emission wavelength, the remaining light-emitting materials are arranged side by side;

[0119] The light-emitting material with the smallest emission wavelength includes a first part and a second part connected to each other. The first part is stacked with the remaining light-emitting materials; the side of the first part closer to the P-type electrode 104 is electrically connected to the P-type electrode 104, and different positions on the side of the first part closer to the N-type electrode 102 respectively correspond to different light-emitting materials arranged side by side;

[0120] The second part is arranged side by side with the remaining light-emitting materials, and the side of the second part and the remaining light-emitting materials closer to the N-type electrode 102 are both electrically connected to the N-type electrode 102; the multiple light-emitting materials arranged side by side respectively correspond to multiple sub-pixels.

[0121] It should be noted that the luminescent material with the smallest emission wavelength can be the first luminescent material 113-1, and the remaining luminescent materials can be the second luminescent material 113-2, the third luminescent material 113-3... the nth luminescent material 113-n. The first part of the first luminescent material 113-1 can be the part extending in the direction perpendicular to the chip thickness, and the second part can be the part extending in the chip thickness direction. The first part can be electrically connected to the P-type electrode 104 respectively, and is stacked on the side of the second luminescent material 113-2, the third luminescent material 113-3... the nth luminescent material 113-n close to the P-type electrode 104. The second part can be arranged side by side with the remaining luminescent materials.

[0122] The first luminescent material 113-1 correspondingly forms the first sub-pixel, the second luminescent material 113-2 correspondingly forms the second sub-pixel, the third luminescent material 113-3 correspondingly forms the third sub-pixel... the nth luminescent material 113-n correspondingly forms the mth sub-pixel.

[0123] In some embodiments, the same luminescent material can correspondingly form multiple sub-pixels. For example, the first luminescent material 113-1 can form two sub-pixels with equal emission wavelengths.

[0124] When the chip works as described above, when the thickness of the first part of the first luminescent material 113-1 is small, holes and electrons can combine in the first luminescent material 113-1, thereby realizing the electroluminescence of the first luminescent material 113-1. The holes can also pass through the first luminescent material 113-1 and enter the second luminescent material 113-2, the third luminescent material 113-3... the nth luminescent material 113-n, realizing the electroluminescence of the second luminescent material 113-2, the third luminescent material 113-3... the nth luminescent material 113-n. Of course, the light emitted by the first luminescent material 113-1 can also excite the second luminescent material 113-2, the third luminescent material 113-3... the nth luminescent material 113-n to emit light, realizing the photoluminescence of the second luminescent material 113-2, the third luminescent material 113-3... the nth luminescent material 113-n.

[0125] When the thickness of the first part of the first luminescent material 113-1 is large, the holes cannot pass through the first luminescent material 113-1 and enter the second luminescent material 113-2, the third luminescent material 113-3... the nth luminescent material 113-n, so that the second luminescent material 113-2, the third luminescent material 113-3... the nth luminescent material 113-n can only be excited to emit light by the light emitted by the first luminescent material 113-1.

[0126] Refer to Figure 7As shown, the chip of the present application further includes a hole blocking layer 115, and the hole blocking layer 115 is disposed at least between the light-emitting material closest to the P-type electrode 104 and the light-emitting material stacked adjacent to the light-emitting material closest to the P-type electrode 104. That is, the hole blocking layer 115 can be disposed between the first light-emitting material 113-1 and the second light-emitting material 113-2, the third light-emitting material 113-3... the nth light-emitting material 113-n stacked with the first light-emitting material 113-1. In this way, holes cannot pass through the hole blocking layer 115 and enter the second light-emitting material 113-2, the third light-emitting material 113-3... the nth light-emitting material 113-n either. The second light-emitting material 113-2, the third light-emitting material 113-3... the nth light-emitting material 113-n can only achieve photoluminescence through the light emitted by the first light-emitting material 113-1.

[0127] Referring to Figure 8-10 As shown, the chip of the present application further includes a reflective layer 107, and the reflective layer 107 is located on the backlight side of the light-emitting diode chip. The reflective layer 107 of the present application is disposed on the backlight side, which can ensure that the light is emitted from the light-emitting side. The reflective layer 107 shown in the figure is located on the side of the N-type electrode 102 facing away from the P-type electrode 104, and the side of the P-type electrode 104 facing away from the N-type electrode 102 forms the light-emitting side of the light-emitting diode chip. The reflective layer 107 can be a metal layer or a Bragg reflective layer 107.

[0128] Continuing to refer to Figure 8-10 As shown, the chip of the present application further includes a plurality of filter layers 117 with different filtering wavelengths. The plurality of filter layers 117 are arranged side by side on the light-emitting side of the light-emitting diode chip, and each filter layer 117 corresponds to each sub-pixel one by one. The filter layer 117 is disposed on the side of the P-type electrode 104 facing away from the N-type electrode 102. The second filter layer 117b CF2 corresponds to the second sub-pixel of the second light-emitting material 113-2, the third filter layer 117c CF3 corresponds to the third sub-pixel formed by the third light-emitting material 113-3... the nth filter layer 117CFn corresponds to the mth sub-pixel formed by the nth light-emitting material 113-n.

[0129] It should be noted that the filter layer 117 can be a color filter, or a Bragg reflective layer (or, Distributed Bragg Reflector, abbreviated as DBR). The Bragg reflective layer can also filter the wavelength of the passing light, so as to emit light with different wavelengths. The Bragg reflective layer can be alternately stacked with two materials of aluminum nitride and gallium nitride, or alternately stacked with two materials of titanium oxide and silicon oxide, or alternately stacked with two materials of silicon oxide and silicon nitride. Optionally, the thickness of the Bragg reflective layer is 2-6 microns. In other embodiments, this thickness value can be adjusted according to needs, and the present application does not limit it.

[0130] In the chip of the present application, the driving methods of multiple sub-pixels of the chip can be independent driving and synchronous driving.

[0131] Referring to Figure 1 As shown, the first sub-pixel, the second sub-pixel, the third sub-pixel... the mth sub-pixel share the N-type electrode 102 and the P-type electrode 104. When the N-type electrode 102 and the P-type electrode 104 are energized, each sub-pixel can emit light synchronously, and the driving mode is synchronous driving.

[0132] Referring to Figure 3 and 4 As shown, the P-type electrode 104 includes M sub-P-type electrodes 104 that are separated from each other. One side of the M sub-pixels close to the N-type electrode 102 is electrically connected to the N-type electrode 102, and one side of the M sub-pixels close to the P-type electrode 104 is electrically connected to the M sub-P-type electrodes 104 in a one-to-one correspondence.

[0133] It should be noted that Figure 3 and 4 As shown in

[0134] Referring to Figure 5 and 6 As shown, the N-type electrode 102 includes M sub-N-type electrodes 102 that are separated from each other. One side of the M sub-pixels close to the P-type electrode 104 is electrically connected to the P-type electrode 104, and one side of the M sub-pixels close to the N-type electrode 102 is electrically connected to the M sub-N-type electrodes 102 in a one-to-one correspondence.

[0135] It should be noted that Figure 5 and 6 As shown in

[0136] Referring to Figure 3-7 , Figure 9 and Figure 10As shown, the chip of the present application further includes an isolation structure 114, and the isolation structure 114 is located between any two adjacent sub-pixels. The isolation structure 114 is located between the second part arranged side by side, the second light-emitting material 113-2, the third light-emitting material 113-3... the nth light-emitting material 113-n. Based on the fact that different regions in the first part respectively correspond to the second light-emitting material 113-2, the third light-emitting material 113-3... the nth light-emitting material 113-n, the isolation structure 114 can also be located between different regions in the first part.

[0137] Exemplarily, referring to Figure 10 As shown, when the N-type electrode 102 includes M sub-N-type electrodes 102 that are separated from each other, the isolation structure 114 can also be located between adjacent sub-N-type electrodes 102.

[0138] Exemplarily, referring to Figure 4 As shown, when the P-type electrode 104 includes M sub-P-type electrodes 104 that are separated from each other, the isolation structure 114 can also be located between adjacent sub-P-type electrodes 104.

[0139] Exemplarily, referring to Figure 10 As shown, when a plurality of reflective layers 107 are respectively located on the side of a plurality of discrete sub-N-type electrodes 102 facing away from the P-type electrode 104, the isolation structure 114 can also be located between adjacent reflective layers 107.

[0140] In the present application, the isolation structure 114 may only include a channel (Channel, abbreviated as CN), that is, the channel may not be filled with the isolation material 114a. The channel can spatially isolate the structures to be isolated. Combining Figure 7 and Figure 8 As shown, the channel CN is filled with an electrically insulating isolation material 114a (referring to Figure 22 and 23 As shown), such as silicon nitride or silicon oxide, etc. In some embodiments, the electrically insulating isolation material 114a may also have a light-shielding effect, such as a black organic material, etc. In this way, the mixing of light between the first sub-pixel and the second sub-pixel can be reduced or avoided, and the light-emitting effect of the light-emitting diode chip can be improved. In other embodiments, the isolation structure 114 may also be an ion implantation layer, a structure with an electrically isolating effect and a light-blocking effect formed by an ion implantation process. In the following embodiments, the isolation structure 114 is the same as above and will not be elaborated later.

[0141] It should be noted that a chip without an isolation structure 114 and with a synchronous driving method can achieve multi-spectral or full-spectral light output, and is usually used in the lighting field.

[0142] In the chip of the present application, referring to Figure 11-16As shown, except for the luminescent material closest to the N-type electrode 102, the remaining luminescent materials each include a first part and a second part that are interconnected;

[0143] In the thickness direction of the light-emitting diode chip, the first parts of the remaining luminescent materials are stacked;

[0144] In a direction intersecting the thickness direction of the light-emitting diode chip, the second parts of the remaining luminescent materials and the luminescent material closest to the N-type electrode 102 are arranged side by side in sequence and respectively correspond to different sub-pixels.

[0145] It should be noted that the luminescent material closest to the N-type electrode 102 is the nth luminescent material 113-n, and the remaining luminescent materials include the first luminescent material 113-1, the second luminescent material 113-2... and the (n-1)th luminescent material 113-(n-1).

[0146] Among the first luminescent material 113-1, the second luminescent material 113-2... and the (n-1)th luminescent material 113-(n-1), the first part is the part extending in a direction intersecting the chip thickness direction, and the second part is the part extending in the chip thickness direction. The first parts of the respective luminescent materials are stacked in the thickness direction of the chip, and the luminescent material with the smallest emission wavelength is located on the side of the remaining luminescent materials closer to the P-type electrode 104. When the N-type electrode 102 and the P-type electrode 104 are energized, the luminescent material with the smallest emission wavelength emits electroluminescence. When the holes provided by the P-type electrode 104 can enter the remaining luminescent materials, the remaining luminescent materials emit photoluminescence and electroluminescence. When the holes provided by the P-type electrode 104 cannot enter the remaining luminescent materials, the remaining luminescent materials emit photoluminescence. Among them, the nth luminescent material 113-n is stacked on the side of the (n-1)th luminescent material 113-(n-1) closer to the N-type electrode 102.

[0147] Among the first luminescent material 113-1, the second luminescent material 113-2... and the (n-1)th luminescent material 113-(n-1), the second parts of the respective luminescent materials can correspond to different sub-pixels. For example: the second part of the first luminescent material 113-1 corresponds to the first sub-pixel, the second part of the second luminescent material 113-2 corresponds to the second sub-pixel, and the sub-pixel of the nth luminescent material corresponds to the mth sub-pixel. The same luminescent material can correspond to form multiple sub-pixels. For example: the second part of the first luminescent material 113-1 corresponds to two sub-pixels with equal emission wavelengths. Among them, the nth luminescent material 113-n is arranged side by side with the second parts of the respective luminescent materials and is also used to correspond to at least one sub-pixel.

[0148] Refer to Figure 12As shown, in the above-mentioned chip, a reflective layer 107 and a light filtering layer 117 may also be included. The reflective layer 107 may be located on the side of the N-type electrode 102 facing away from the P-type electrode 104, such that the side of the P-type electrode 104 facing away from the N-type electrode 102 forms a light emitting side, and correspondingly, the light filtering layer 117 is disposed on this light emitting side. The light filtering layer 117 may include a second light filtering layer 117b CF2, a third light filtering layer 117c CF3... an nth light filtering layer 117CFn. The second light filtering layer 117b CF2 corresponds to the second sub-pixel of the second light emitting material 113-2, the third light filtering layer 117c CF3 corresponds to the third sub-pixel formed by the third light emitting material 113-3... the nth light filtering layer 117CFn corresponds to the mth sub-pixel formed by the nth light emitting material 113-n.

[0149] Referring to Figure 11 and 12 As shown, the driving method of multiple sub-pixels of the chip is synchronous driving. Referring to Figure 13 and 14 As shown, the P-type electrode 104 includes a first sub-P-type electrode, a second sub-P-type electrode, a third sub-P-type electrode... an mth sub-P-type electrode, and the driving method of multiple sub-pixels of the chip is independent driving. Referring to Figure 14 and 16 As shown, the N-type electrode 102 includes a first sub-N-type electrode, a second sub-N-type electrode, a third sub-N-type electrode... an mth sub-N-type electrode, and the driving method of multiple sub-pixels of the chip is independent driving.

[0150] In the chip of this embodiment, an isolation structure 114 (not shown in the figure) may be provided between each sub-pixel. The isolation structure 114 may be located between the second parts of each light emitting material arranged side by side, and may further be located between each region of the first part of each light emitting material corresponding to each sub-pixel. When the P-type electrode 104 of the chip includes multiple discrete P-type electrodes 104, the isolation structure 114 may be located between the sub-P-type electrodes 104 corresponding to each sub-pixel. When the N-type electrode 102 of the chip includes multiple discrete N-type electrodes 102, the isolation structure 114 may be located between the sub-N-type electrodes 102 corresponding to each sub-pixel. The isolation structure 114 may also be located between the light filtering layers 117 corresponding to each sub-pixel, and between the reflective layers 107.

[0151] In the chip of this embodiment, a hole blocking layer 115 (not shown in the figure) may be provided between each stacked light emitting material. The hole blocking layer 115 may be provided at least between the first light emitting material 113-1 and the light emitting material stacked with the second light emitting material 113-2. Referring to Figure 11As shown, the material of the second light-emitting layer 113 is stacked with the first light-emitting material 113-1, and the hole blocking layer 115 is disposed therebetween. In other embodiments, if the third light-emitting material 113-3 is stacked with the first light-emitting material 113-1, the hole blocking layer 115 may also be disposed therebetween. Of course, the hole blocking layer 115 may further be disposed between other stacked light-emitting materials. For example, between the stacked second light-emitting material 113-2 and the third light-emitting material 113-3.

[0152] Based on the above Figure 11-16 embodiment, in some other embodiments, some of the light-emitting materials may only include the first part and not the second part. For example, based on the Figure 11 structure shown, the first light-emitting material 113-1 may only include the first part and not the second part. The remaining light-emitting materials may include the first part and the second part.

[0153] Based on the above Figure 11-16 embodiment, in some other embodiments, some of the light-emitting materials may only include the second part and not the first part. For example, based on the Figure 11 structure shown, the second light-emitting material 113-2 may only include the second part and not the first part. The remaining light-emitting materials may include the first part and the second part.

[0154] Referring to Figure 17-26 shown, among the multiple light-emitting materials, except for the light-emitting material with the smallest emission wavelength, the remaining light-emitting materials are stacked along the thickness direction of the light-emitting diode chip.

[0155] In this chip, the light-emitting material with the smallest emission wavelength is stacked on the side of the remaining light-emitting materials close to the P-type electrode 104. That is, the first light-emitting material 113-1 is stacked on the side of the remaining light-emitting materials close to the P-type electrode 104. The first light-emitting material 113-1 can emit light by electroluminescence. The light emitted by the first light-emitting material 113-1 can excite the remaining light-emitting materials to emit light, and the remaining light-emitting materials emit light by photoluminescence. Of course, if the holes provided by the P-type electrode 104 and the electrons provided by the N-type electrode 102 can migrate into the remaining light-emitting materials, the remaining light-emitting materials can also emit light by electroluminescence.

[0156] Among the remaining light-emitting materials, along the direction from the P-type electrode 104 to the N-type electrode 102, the emission wavelengths of the remaining light-emitting materials gradually increase. That is, along the direction from the P-type electrode 104 to the N-type electrode 102, the wavelengths of the second light-emitting material 113-2, the third light-emitting material 113-3... the nth light-emitting material 113-n gradually increase and are arranged in sequence. In this way, the light emitted by the light-emitting material on the side close to the P-type electrode 104 can excite the light-emitting material on the side far from the P-type electrode 104 to emit light.

[0157] In some other embodiments, along the direction from the P-type electrode 104 to the N-type electrode 102, the remaining light-emitting materials may also not be arranged in the order of the emission wavelengths. For example, the second light-emitting material 113-2 with a smaller emission wavelength may also be located on the side closer to the N-type electrode 102 of the third light-emitting material 113-3 with a larger emission wavelength.

[0158] In the chip of this embodiment, among the light-emitting materials arranged in layers, different regions arranged along the direction intersecting the thickness of the light-emitting diode chip respectively correspond to different sub-pixels.

[0159] Referring to Figure 18 and 19 As shown, in the above chip, a reflective layer 107 and a filter layer 117 may also be included. The reflective layer 107 may be located on the side of the N-type electrode 102 facing away from the P-type electrode 104, so that the side of the P-type electrode 104 facing away from the N-type electrode 102 forms a light-emitting side, and the filter layer 117 is disposed on this light-emitting side. The filter layer 117 may include a second filter layer 117b CF2, a third filter layer 117c CF3... an nth filter layer 117CFn. The second filter layer 117b CF2 corresponds to the second sub-pixel of the second light-emitting material 113-2, the third filter layer 117c CF3 corresponds to the third sub-pixel formed by the third light-emitting material 113-3... the nth filter layer 117CFn corresponds to the mth sub-pixel formed by the nth light-emitting material 113-n.

[0160] Referring to Figure 17 As shown, the driving method of the multiple sub-pixels of this chip is synchronous driving. Referring to Figure 18 As shown, the P-type electrode 104 includes a first sub-P-type electrode, a second sub-P-type electrode, a third sub-P-type electrode... an mth sub-P-type electrode, and the driving method of the multiple sub-pixels of the chip is independent driving. Referring to Figure 19 As shown, the N-type electrode 102 includes a first sub-N-type electrode, a second sub-N-type electrode, a third sub-N-type electrode... an mth sub-N-type electrode, and the driving method of the multiple sub-pixels of the chip is independent driving.

[0161] In the chip of this embodiment, referring to Figure 22 and 23As shown, an isolation structure 114 can be provided between each sub-pixel. The isolation structure 114 can be located between different regions of each light-emitting material. When the P-type electrode 104 of the chip includes a plurality of discrete P-type electrodes 104, the isolation structure 114 can be located between the sub-P-type electrodes 104 corresponding to each sub-pixel. When the N-type electrode 102 of the chip includes a plurality of discrete N-type electrodes 102, the isolation structure 114 can be located between the sub-N-type electrodes 102 corresponding to each sub-pixel. The isolation structure 114 can also be located between the filter layers 117 corresponding to each sub-pixel and between the reflective layers 107.

[0162] In the chip of this embodiment, a hole blocking layer 115 (not shown in the figure) can be provided between the stacked light-emitting materials. The hole blocking layer 115 can be provided at least between the first light-emitting material 113-1 and the light-emitting material stacked with the second light-emitting material 113-2. Refer to Figure 17 As shown, the second light-emitting layer 113 material is stacked with the first light-emitting material 113-1, and the hole blocking layer 115 is provided therebetween. In other embodiments, if the third light-emitting material 113-3 is stacked with the first light-emitting material 113-1, the hole blocking layer 115 can also be provided therebetween. Of course, the hole blocking layer 115 can also be further provided between other stacked light-emitting materials. For example, between the stacked second light-emitting material 113-2 and the third light-emitting material 113-3.

[0163] Refer to Figure 24 to 26 As shown, in the chip of the present application, among the stacked light-emitting materials, several light-emitting materials form a light-emitting material group, and the light-emitting layer 113 includes a plurality of light-emitting material groups; along the P-type electrode 104 to the N-type electrode 102, the plurality of light-emitting material groups are arranged in sequence. Figure 24 to 26 What is shown in is the light-emitting material group Group1……Group n.

[0164] It should be noted that the number of light-emitting material groups can be 2 groups, 3 groups or more groups. In different groups, the arrangement and quantity of the light-emitting materials can be the same or different.

[0165] Among them, in the light-emitting material group closest to the P-type electrode 104, the light-emitting wavelength of the light-emitting material closest to the P-type electrode 104 can be the smallest. That is, Figure 24 in, the light-emitting wavelength of the first light-emitting material 113-1 located closest to the P-type electrode 104 is the smallest. The light emitted by this light-emitting material can excite the remaining light-emitting materials in the same light-emitting material group, or can also excite the light-emitting materials in the remaining light-emitting material groups.

[0166] Refer to Figure 24As shown, in the above-mentioned chip, a reflective layer 107 and a light filtering layer 117 may also be included. The reflective layer 107 may be located on the side of the N-type electrode 102 away from the P-type electrode 104, such that the side of the P-type electrode 104 away from the N-type electrode 102 forms a light-emitting side, and the corresponding light filtering layer 117 is disposed on this light-emitting side. The light filtering layer 117 may include a first light filtering layer 117a CF1, a second light filtering layer 117b CF2, a third light filtering layer 117c CF3... an nth light filtering layer 117CFn. The first light filtering layer 117a CF1 and the second light filtering layer 117b CF2 correspond to the second sub-pixels of the second light-emitting material 113-2, the third light filtering layer 117c CF3 corresponds to the third sub-pixels formed by the third light-emitting material 113-3... the nth light filtering layer 117CFn corresponds to the mth sub-pixels formed by the nth light-emitting material 113-n.

[0167] Continue to refer to Figure 24 As shown, the driving method of the multiple sub-pixels of this chip is synchronous driving. Refer to Figure 25 As shown, the P-type electrode 104 includes a first sub-P-type electrode, a second sub-P-type electrode, a third sub-P-type electrode... an mth sub-P-type electrode, and the driving method of the multiple sub-pixels of the chip is independent driving. Refer to Figure 26 As shown, the N-type electrode 102 includes a first sub-N-type electrode, a second sub-N-type electrode, a third sub-N-type electrode... an mth sub-N-type electrode, and the driving method of the multiple sub-pixels of the chip is independent driving.

[0168] In the chip of this embodiment, refer to Figure 25 and 26 As shown, an isolation structure 114 may be provided between each sub-pixel. The isolation structure 114 may be located between different regions of each light-emitting material in each light-emitting material group. When the P-type electrode 104 of the chip includes multiple discrete P-type electrodes 104, the isolation structure 114 may be located between the sub-P-type electrodes 104 corresponding to each sub-pixel. When the N-type electrode 102 of the chip includes multiple discrete N-type electrodes 102, the isolation structure 114 may be located between the sub-N-type electrodes 102 corresponding to each sub-pixel. The isolation structure 114 may also be located between the light filtering layers 117 corresponding to each sub-pixel, and between the reflective layers 107.

[0169] In the chip of this embodiment, a hole blocking layer 115 (not shown in the figure) may be provided between the stacked light-emitting materials. The hole blocking layer 115 may be provided at least between the first light-emitting material 113-1 of the same light-emitting material group and the light-emitting material stacked with the second light-emitting material 113-2. Refer to Figure 24As shown, in the light-emitting material group near the P-type electrode 104, the material of the second light-emitting layer 113 is stacked with the first light-emitting material 113-1, and the hole-blocking layer 115 is disposed therebetween. In other embodiments, if the third light-emitting material 113-3 is stacked with the first light-emitting material 113-1, the hole-blocking layer 115 may also be disposed therebetween. Of course, the hole-blocking layer 115 may further be disposed between other stacked light-emitting materials. For example, between the stacked second light-emitting material 113-2 and the third light-emitting material 113-3. Of course, the hole-blocking layer 115 may also be disposed between adjacent light-emitting material groups.

[0170] The chip of each of the above embodiments may further include an N-type semiconductor layer 103 and a P-type semiconductor layer 105. The N-type semiconductor and the P-type semiconductor are respectively located on opposite sides in the thickness direction of the light-emitting layer 113. The N-type electrode 102 is electrically connected to the light-emitting layer 113 through the N-type semiconductor, and the P-type electrode 104 is electrically connected to the light-emitting layer 113 through the P-type semiconductor.

[0171] When the N-type electrode 102 includes M discrete sub-N-type electrodes 102, the isolation structure 114 is located between adjacent sub-N-type electrodes 102, and at least a part of the isolation structure 114 extends into the P-type semiconductor layer 105. By way of example, with reference to Figure 20 and 22 As shown, the isolation structure 114 extends into the P-type semiconductor.

[0172] When the P-type electrode 104 includes M discrete sub-P-type electrodes 104, the isolation structure 114 is located between adjacent sub-P-type electrodes 104, and at least a part of the isolation structure 114 extends into the N-type semiconductor layer 103. By way of example, with reference to Figure 21 and 23 As shown, the isolation structure 114 extends into the N-type semiconductor.

[0173] The above setting of the isolation structure 114 can not only reduce the process difficulty, but also improve the isolation effect of the isolation structure 114 on each sub-pixel. It should be noted that the solution in which the isolation structure 114 extends into the P-type semiconductor or the N-type semiconductor can also be applied to the chip structures of the above other embodiments.

[0174] In the embodiments of the above chip, in the independent driving mode, each sub-pixel corresponds to each separate sub-N-type electrode 102 or sub-P-type electrode 104. In some other embodiments, in the independently driven chip, a part of the sub-pixels may also share the discrete sub-N-type electrodes 102 or sub-P-type electrodes 104. Specifically:

[0175] As a first implementable embodiment, the N-type electrode 102 includes m discrete sub-N-type electrodes 102, and the P-type electrode 104 includes M discrete sub-P-type electrodes 104; one side of the M sub-pixels close to the P-type electrode 104 is electrically connected to each sub-P-type electrode 104 in a one-to-one correspondence, and one side of the M sub-pixels close to the N-type electrode 102 is electrically connected to the m sub-N-type electrodes 102; m is less than M, and a partial number of sub-pixels share one sub-N-type electrode 102.

[0176] Referring to Figure 27 as shown, sub-pixel G and sub-pixel B share one sub-N-type electrode 102N1, sub-pixel G is electrically connected to sub-P-type electrode 104P11, and sub-pixel B is electrically connected to sub-P-type electrode 104P21. Two sub-pixels R share another sub-N-type electrode 102N2, and the two sub-pixels R are respectively electrically connected to sub-P-type electrode 104P22 and sub-P-type electrode 104P12. In this way, the sub-pixels sharing one sub-N-type electrode 102 have higher emission uniformity.

[0177] As a second implementable embodiment, the P-type electrode 104 includes m discrete sub-P-type electrodes 104, and the N-type electrode 102 includes M discrete sub-N-type electrodes 102; one side of the M sub-pixels close to the N-type electrode 102 is electrically connected to each sub-N-type electrode 102 in a one-to-one correspondence, and one side of the M sub-pixels close to the P-type electrode 104 is electrically connected to the m sub-P-type electrodes 104; m is less than M, and a partial number of sub-pixels share one sub-P-type electrode 104.

[0178] Referring to Figure 28 as shown, sub-pixel G and sub-pixel B share one sub-P-type electrode 104P1, sub-pixel G is electrically connected to sub-N-type electrode 102N11, sub-pixel B is electrically connected to sub-N-type electrode 102N21, and two sub-pixels R share another sub-P-type electrode 104P2. The two sub-pixels R are respectively electrically connected to sub-N-type electrode 102P22 and sub-N-type electrode 102P12. In this way, the emission uniformity of the sub-pixels sharing one sub-P-type electrode 104 is higher.

[0179] Referring to Figure 29 - Figure 41 as shown, in some embodiments of the chip of the present application, the M sub-pixels form a pixel subgroup. For example, referring to Figure 29 as shown, sub-pixel B, sub-pixel G, and sub-pixel R together form a chip. Referring to Figure 30 and Figure 31 as shown, the arrangement order of sub-pixel B, sub-pixel G, and sub-pixel R can be changed. Figure 29-31 The number of sub-pixels of a chip shown can be 3. Referring to Figure 32 as shown, the number of sub-pixels in a chip can also be 4, or referring to Figure 33 and34 As shown, the number of sub-pixels in a chip can be 5. In other embodiments, the number of sub-pixels in the chip can be more (for example Figure 41 as shown, the chip includes 8 sub-pixels), and the arrangement of each sub-pixel can be flexibly adjusted.

[0180] In some other embodiments, M sub-pixels form multiple pixel sub-groups, and in the direction intersecting the thickness direction of the light-emitting diode chip, the multiple pixel sub-groups are arranged in an array. For example, referring to Figure 36-42 as shown, sub-pixel B, sub-pixel G, and sub-pixel R can form a pixel sub-group, and the chip includes multiple pixel sub-groups arranged in an array. The arrangement of sub-pixel B, sub-pixel G, and sub-pixel R in different pixel sub-groups can be the same or different. For example, referring to Figure 38 as shown, a pixel sub-group can include four sub-pixels. For example, referring to Figure 40 and Figure 41 as shown, a pixel sub-group can include 5 sub-pixels.

[0181] As an implementable embodiment, among the multiple sub-pixels of the above pixel sub-group, the emission wavelengths of the multiple sub-pixels are not equal to each other, or the multiple sub-pixels include at least two sub-pixels with equal emission wavelengths.

[0182] For example, referring to Figure 29-31 as shown, the sub-pixels of a pixel sub-group are sub-pixel B, sub-pixel G, and sub-pixel R respectively. Referring to Figure 33 as shown, sub-pixel G1 and sub-pixel G2 can represent sub-pixels with different emission wavelengths. Or, referring to Figure 32 as shown, the sub-pixels of a pixel sub-group can include sub-pixel B, sub-pixel G, and two sub-pixels R. Referring to Figure 34 as shown, the sub-pixels of a pixel sub-group can include sub-pixel B, sub-pixel G, and three sub-pixels R.

[0183] In the chip of the present application, M sub-pixels form multiple pixel units, and the multiple pixel units are arranged in an array along the direction intersecting the thickness direction of the light-emitting diode chip;

[0184] One pixel unit includes Y sub-pixels, and the Y sub-pixels include X types of wavelengths; X is a positive integer greater than or equal to 3, and Y is a positive integer greater than or equal to X.

[0185] It should be noted that, referring to Figure 29-31 as shown, a chip includes three sub-pixels, the three sub-pixels form a pixel unit, and the three sub-pixels are respectively 3 types of wavelengths. In this embodiment, both X and Y are 3. On this basis, referring to Figure 36-38As shown, a multi-color multi-subpixel chip includes 3*a subpixels. Among these subpixels, there are 3 wavelengths and a pixel units are included. In this embodiment, X is 3 and Y is 3*a.

[0186] Referring to Figure 32 As shown, a chip includes four subpixels. The four subpixels form a pixel unit, and the four subpixels include 3 wavelengths. In this embodiment, X is 3 and Y is 4. On this basis, referring to Figure 39 As shown, a multi-color multi-subpixel chip includes 4*a subpixels. Among these subpixels, there are 3 wavelengths and a pixel units are included. In this embodiment, X is 3 and Y is 4*a.

[0187] Referring to Figure 33 As shown, a chip includes five subpixels. The five subpixels form a pixel unit, and the five subpixels include 4 wavelengths (taking the example that the emission wavelengths of subpixel G1 and subpixel G2 are different). In this embodiment, X is 4 and Y is 5. On this basis, referring to Figure 40 As shown, a multi-color multi-subpixel chip includes 5*a subpixels. Among these subpixels, there are 4 wavelengths and a pixel units are included. In this embodiment, X is 4 and Y is 5*a.

[0188] Referring to Figure 34 As shown, a chip includes five subpixels. The five subpixels form a pixel unit, and the five subpixels include 3 wavelengths. In this embodiment, X is 3 and Y is 5. On this basis, referring to Figure 41 As shown, a multi-color multi-subpixel chip includes 5*a subpixels. Among these subpixels, there are 3 wavelengths and a pixel units are included. In this embodiment, X is 3 and Y is 5*a.

[0189] In the above embodiments, when Y is greater than X, in one of the pixel units, the emission wavelengths of at least some of the subpixels are equal.

[0190] According to the above method, pixel units with different structures can be designed in the chip to achieve a diversified chip structure, adjust the light mixing effect of the chip, and thus achieve a chip with a flexible structure and a rich light emission effect.

[0191] As a realizable embodiment, in the chip of the embodiments of the present application, all the subpixels in the same pixel unit are only for the use of the pixel unit to which they belong. Referring to Figure 29-31 As shown, three subpixels in the same chip can form a pixel unit, and all the subpixels are only for the use of this pixel unit. Referring to Figure 32As shown, the chip includes 2 sub-pixels R, 1 sub-pixel B, and 1 sub-pixel G. 1 sub-pixel R, 1 sub-pixel B, and 1 sub-pixel G can form a complete pixel unit, and it is only used for this pixel unit. In this way, a complete full-color pixel unit can be formed in the chip, ensuring more convenient use of the chip.

[0192] It should be noted that in two adjacent pixel units, for example, the first pixel unit and the second pixel unit. When the sub-pixels in the first pixel unit have insufficient light emission brightness, some or all of the sub-pixels in the adjacent second pixel unit can be borrowed flexibly to complete the light emission of the second pixel unit. That is, the sub-pixels borrowed in the first pixel unit can be used for the light emission of the second pixel unit instead of the light emission of the first pixel unit. In this way, the structural flexibility and light output effect of the chip can be improved. Among them, the first pixel unit can also borrow the light emission of the second pixel unit for other reasons, and this application does not limit this.

[0193] As another implementable embodiment, in the chip of the embodiment of the present application, two sub-pixels are shared by adjacent pixel units, and the total number of sub-pixels of a single chip is a*(2X - 2), where a is a positive integer greater than or equal to 1. Refer to Figure 35 As shown, the sub-pixel R and the sub-pixel B in the same chip are shared by the pixel unit PU1 and the pixel unit PU2. The number of sub-pixels in this chip is 8. In this chip, X is 4 and a is 2. Among them, a is the number of combinations of sub-pixels. For example, in the illustrated chip, the sub-pixel B, the sub-pixel G, the sub-pixel R, and the sub-pixel G together form a combination, and there are two combinations in this chip, so a takes the value of 2.

[0194] In the same chip, some sub-pixels are shared to form different pixel units, which can ensure the flexibility of the chip structure and meet diverse display requirements.

[0195] In some embodiments, the size of the light-emitting diode chip is greater than or equal to 50 microns. The size of the pixel sub-group of this chip can also be greater than or equal to 50 microns. For example, it can be 50 - 100 microns, or 100 - 150 microns, or greater than 150 microns. Of course, in some embodiments, the size of this light-emitting diode chip can also be less than 50 microns. The light-emitting diode chip can be selected with different sizes according to different usage scenarios.

[0196] In some embodiments, the shape of the light-emitting diode chip is any one of a rectangle, a square, a circle, an ellipse, a triangle, a rhombus, a parallelogram, and a polygon with more than four sides; among them, the shapes of different sub-pixels are the same or different. That is, the shape of the first sub-pixel B and the second sub-pixel G can both be Figure 28 the rectangle shown in

[0197] When multiple light-emitting diode chips form a light-emitting diode chip group, the shapes of different light-emitting diode chips can be the same or different.

[0198] In some embodiments, the size range of the sub-pixels is 0.001 - 200 microns. When the size of the sub-pixel is 0.001 micron - 0.1 micron, the sub-pixel size is at the nanoscale and is a nano LED. During the preparation of the nano LED, the arrangement method of a single-core multi-color multi-sub-pixel in this application can be referred to, which helps to increase the size of a single chip of the nano LED containing multiple sub-pixels, so that the size of a single chip is close to or falls within the size range of the LED chips that can be operated by the current mass transfer process, thereby reducing the operation difficulty in the preparation process of the nano LED and improving its operability.

[0199] In some other embodiments, taking a light-emitting diode chip with 3*3 combined sub-pixels applied to a large TV as an example, the size of a single sub-pixel can be 30 microns, and the distance between two adjacent sub-pixels is 10 microns. The length and width of the light-emitting diode chip are both 110 microns, and its size can be measured as 110*110 microns. A light-emitting diode chip with such a size can use the packaging process of a mini LED.

[0200] The sizes of the light-emitting diode chip and the sub-pixels will vary according to the usage scenario of the light-emitting diode chip. Below, exemplary descriptions are made for the sizes of the light-emitting diode chip and the sub-pixels in different usage scenarios.

[0201] When the light-emitting diode chip is applied to display products such as home TVs and desktop computers, when the pixel density is 50 - 150, the size (pitch) of the pixel unit composed of several sub-pixels in multiple light-emitting diode chips can be 150 - 700 microns, the size (sub pitch) of the sub-pixels in the light-emitting diode chip can be less than 250 microns, and the size of the light-emitting diode chip can be greater than 100 microns.

[0202] When the light-emitting diode chip is applied to display products such as laptops and tablets, when the pixel density is 150 - 250, the size of the sub-pixels can be less than 70 microns, the size of the pixel unit is 100 - 200 microns, and the size of the light-emitting diode chip can be greater than 60 microns.

[0203] When the light-emitting diode chip is applied to display products such as mobile phones and electronic watches, when the pixel density is greater than 300, the size of the sub-pixels can be less than 30 microns, the size of the pixel unit is less than 100 microns, and the size of the light-emitting diode chip can be greater than 50 microns.

[0204] Based on this, the light-emitting diode chip provided by the embodiments of the present application adopts an arrangement mode of single-core multi-color and multi-sub-pixels. The sizes of the sub-pixels and the light-emitting diode chip have a relatively large range, which can be applicable to different usage scenarios and increase the applicability of the light-emitting diode chip.

[0205] In some embodiments, the shape of the sub-pixel is any one of a rectangle, a square, a circle, an ellipse, a triangle, a rhombus, a parallelogram, and a polygon with more than four sides.

[0206] In some embodiments, the sizes of different sub-pixels are equal or unequal. The size of the sub-pixel affects its light-emitting area. That is, the light-emitting areas of different sub-pixels can be equal or unequal. The sizes of different sub-pixels can be adjusted according to the brightness attenuation of the sub-pixels. For example, if the brightness attenuation rate of a certain sub-pixel is relatively large, the size of this sub-pixel can be appropriately increased to ensure uniform light output requirements. The sizes of different sub-pixels can also be adjusted according to whether there is a sharing situation between different pixel units (Pixel unit, abbreviated as PU). For example, as shown in Figure 58 As shown, sub-pixel (B) and sub-pixel (R) are shared by two pixel units respectively during the formation of pixel units PU1 and PU2, sub-pixel (G) is not shared and belongs entirely to pixel unit PU1. Therefore, the sizes of sub-pixel (B) and sub-pixel (R) are larger than the size of sub-pixel (G). In this way, the luminous brightness of the shared sub-pixels in each pixel unit can be ensured.

[0207] It should be noted that the above-mentioned "size" can be understood as the extension length of a certain extension direction of the sub-pixel. For example, it can be the length or width of a rectangular sub-pixel, or the major axis length or minor axis length of an elliptical sub-pixel, or the diameter of a circular sub-pixel, etc.

[0208] Referring to Figure 43 As shown, the chip provided by the embodiments of the present application further includes a buffer layer 101, an N-type semiconductor layer 103, a P-type semiconductor layer 105, a current spreading layer 106, a reflective layer 107, and a first insulating layer 108. The buffer layer 101 and the N-type semiconductor layer 103 are stacked, the light-emitting layer 113 is disposed on the side of the N-type semiconductor layer 103 away from the buffer layer 101, and the P-type semiconductor layer 105 is disposed on the side of the light-emitting layer 113 away from the buffer layer 101. The current spreading layer 106 is in contact with the surface of the P-type semiconductor layer 105 away from the buffer layer 101, the N-type electrode 102 is in contact with the N-type semiconductor layer 103, and the P-type electrode 104 is in contact with the P-type semiconductor layer 105 and the current spreading layer 106. The first insulating layer 108 is disposed on the side of the current spreading layer 106 away from the buffer layer 101.

[0209] The light-emitting layer 113 includes a first light-emitting material 113-1, a second light-emitting material 113-2, and a third light-emitting material 113-3 that are sequentially stacked along the P-type electrode 104 to the N-type electrode 102.

[0210] Optionally, continuing to refer to Figure 43 As shown, the reflective layer 107 can be disposed on the side of the light-emitting layer 113 facing away from the buffer layer 101. In this way, the light-emitting direction of the light-emitting diode chip is towards the direction away from the buffer layer 101, that is, the downward arrow in the figure. The first filter layer 117a, the second filter layer 117b, and the third filter layer 117c are arranged side by side at the bottom of the buffer layer 101. The structure of this chip is a thin-film flip-chip structure.

[0211] Optionally, referring to Figure 43 As shown, the reflective layer 107 is disposed on the side of the first insulating layer 108 facing away from the buffer layer 101, and a second insulating layer 109 is further disposed on the side of the reflective layer 107 facing away from the buffer layer 101. The second insulating layer 109 can protect the reflective layer 107.

[0212] Among them, the material of the buffer layer 101 can be one or more of gallium nitride, aluminum gallium nitride, and aluminum indium gallium nitride, and the thickness of the buffer layer 101 can be 10 - 40 nanometers. The material of the N-type semiconductor layer 103 can be N-type doped gallium nitride, and the material of the P-type semiconductor layer 105 can be P-type doped gallium nitride. The material of the current spreading layer 106 can be a transparent conductive material (indium tin oxide, ITO) or silver, etc., and its function is to improve the distribution ability of the P-type electrode 104 and make the holes as evenly distributed as possible in the region where the P-type semiconductor layer 105 is located. The material of the first insulating layer 108 can be silicon oxide or silicon nitride.

[0213] Referring to Figure 44 As shown, the light-emitting diode chip provided by the embodiment of the present application can further include a substrate 100, and the substrate 100 can be disposed on the side of the buffer layer 101 facing away from the light-emitting layer 113. The material of the substrate 100 can be one or more composites of sapphire, gallium nitride, aluminum nitride, silicon, and silicon carbide. This chip is a front-mounted structure. Specifically, the reflective layer 107 is located on the side of the substrate 100 facing away from the light-emitting layer 113, and the filter layer 117 is located on the side of the light-emitting layer 113 facing away from the substrate 100. That is, in the figure, the reflective layer 107 is located at the bottom of the substrate 100, and the filter layer 117 is located on the top of the first insulating layer 108. The upper side of the chip is the light-emitting side.

[0214] Referring to Figure 45As shown, the light-emitting diode chip provided by the embodiment of the present application further includes a substrate 100, and the substrate 100 is disposed on the side of the buffer layer 101 away from the light-emitting layer 113. The structure of this chip is a flip-chip structure, and the lower side is the light-emitting side. Specifically, the reflective layer 107 is located on the side of the first light-filtering layer 117a away from the light-emitting layer 113, and the light-filtering layer 117 is located on the side of the substrate 100 away from the light-emitting layer 113. That is, in the figure, the reflective layer 107 is located on the top of the first insulating layer 108, and the light-filtering layer 117 is located on the bottom of the substrate 100.

[0215] Referring to Figure 46 As shown, the chip provided by the embodiment of the present application may further include a bonding substrate 100, a bonding layer 111, an N-type semiconductor layer 103, a P-type semiconductor layer 105, and a reflective layer 107.

[0216] The bonding substrate 100 and the bonding layer 111 are sequentially disposed on the P-type electrode 104. The P-type semiconductor layer 105 is disposed on the side of the bonding layer 111 away from the bonding substrate 100 and is in contact with the bonding layer 111; the light-emitting layer 113 is disposed on the side of the P-type semiconductor layer 105 away from the bonding substrate 100, the N-type semiconductor layer 103 is disposed on the side of the light-emitting layer 113 away from the bonding substrate 100, and the N-type electrode 102 contacts the side of the N-type semiconductor layer 103 away from the bonding substrate 100; the reflective layer 107 is disposed on the side of the P-type semiconductor layer 105 close to the bonding substrate 100. The light-emitting layer 113 includes a first light-emitting material 113-1, a second light-emitting material 113-2, and a third light-emitting material 113-3 that are sequentially stacked along the P-type electrode 104 to the N-type electrode 102. A first insulating layer 108 is disposed on the top of the N-type semiconductor layer 103.

[0217] It should be noted that Figure 46 the light-emitting direction is the upward direction indicated by the arrow in the figure, forming a light-emitting diode chip with a vertical front-mounted structure. The first light-filtering layer 117a, the second light-filtering layer 117b, and the third light-filtering layer 117c are arranged side by side at the bottom of the first insulating layer 108.

[0218] Combined with Figure 43-46 As shown, the chip provided by the embodiment of the present application further includes a light-blocking layer 116. The light-blocking layer 116 is located on the light-emitting side of the light-emitting diode chip and is located between two adjacent sub-pixels. The light-blocking layer 116 may be located between the first light-filtering layer 117a and the second light-filtering layer 117b, or may be located between the second light-filtering layer 117b and the third light-filtering layer 117c. The light-blocking layer 116 may be a black resin material and has the function of absorbing light and blocking light. The light-blocking layer 116 is located between two adjacent sub-pixels, which can avoid the problem of light mixing between the two sub-pixels and ensure the light-emitting effect of the light-emitting diode chip.

[0219] Second aspect, an embodiment of the present application provides a method for manufacturing a light-emitting diode chip, and this manufacturing method can be used to manufacture the above-mentioned light-emitting diode chip.

[0220] As the first manufacturing method of the light-emitting diode chip, referring to Figure 47 as shown, this manufacturing method includes:

[0221] Providing a substrate 100 ( Figure 47 (a)); sequentially forming a buffer layer 101, an N-type semiconductor layer 103, and a third light-emitting material 113-3 on the substrate 100 through an epitaxial growth process ( Figure 47 (b)); forming a second light-emitting material 113-2 on a partial surface of the third light-emitting material 113-3 through an epitaxial growth process ( Figure 47 (c)); forming a first light-emitting material 113-1 covering another partial surface of the third light-emitting material 113-3 through an epitaxial growth process ( Figure 47 (d)); forming a P-type semiconductor layer 105 covering the first light-emitting material 113-1, the second light-emitting material 113-2, and the third light-emitting material 113-3 through an epitaxial growth process ( Figure 47 (e)). Then performing conventional chip processes to obtain a single-core multi-color multi-sub-pixel chip.

[0222] On the basis of the above, continuing to refer to Figure 47 as shown, this manufacturing method includes forming an isolation structure 114 ( Figure 47 (f)). Then performing conventional chip processes to obtain a single-core multi-color multi-sub-pixel chip.

[0223] As the second manufacturing method of the light-emitting diode chip, referring to Figure 48 as shown, this manufacturing method includes:

[0224] Providing a substrate 100 ( Figure 48 (a)); sequentially forming a buffer layer 101, an N-type semiconductor layer 103, and a third light-emitting material 113-3 on the substrate 100 through an epitaxial growth process ( Figure 48 (b)); forming a second light-emitting material 113-2 on a partial surface of the third light-emitting material 113-3 through an epitaxial growth process ( Figure 48 (c)); forming a first light-emitting material 113-1 on a partial surface of the second light-emitting material 113-2 through an epitaxial growth process ( Figure 48 (d)); forming a P-type semiconductor layer 105 covering the first light-emitting material 113-1, the second light-emitting material 113-2, and the third light-emitting material 113-3 through an epitaxial growth process ( Figure 48 (e)). Then performing conventional chip processes to obtain a single-core multi-color multi-sub-pixel chip.

[0225] Based on the above, continue to refer to Figure 48 as shown, the manufacturing method includes forming an isolation structure 114 ( Figure 48 (f)). Then perform conventional chip processes to obtain a single-core multi-color multi-sub-pixel chip.

[0226] As the third manufacturing method of the light-emitting diode chip, refer to Figure 49 as shown, the manufacturing method includes:

[0227] Provide a substrate 100 ( Figure 49 (a)); sequentially form a buffer layer 101, an N-type semiconductor layer 103, a third light-emitting material 113-3, a second light-emitting material 113-2, a first light-emitting material 113-1, and a P-type semiconductor layer on the substrate 100 through an epitaxial growth process ( Figure 49 (b)); form a step ( Figure 49 (c)); form a patterned current spreading layer ( Figure 49 (d)); form a patterned first insulating layer covering the current spreading layer, with a part of the first insulating layer located at the step ( Figure 49 (e)); form a patterned reflective layer 107 covering the first insulating layer ( Figure 49 (f)); form a patterned second insulating layer 109 covering the reflective layer 107 ( Figure 49 (g)); form an N-type electrode 102 and a P-type electrode 104 ( Figure 49 (h)); form a first filter layer 117a, a second filter layer 117b, and a third filter layer 117c on the side of the substrate 100 facing away from the reflective layer 107 ( Figure 49 (i)).

[0228] As the fourth manufacturing method of the light-emitting diode chip, refer to Figure 50 as shown, the manufacturing method includes:

[0229] Provide a substrate 100 ( Figure 50 (a)); sequentially form a buffer layer 101, an N-type semiconductor layer 103, a third light-emitting material 113-3, a second light-emitting material 113-2, a first light-emitting material 113-1, and a P-type semiconductor layer 105 on the substrate 100 through an epitaxial growth process ( Figure 50 (b)); form a step and a channel (an isolation structure 114 without filling the isolation material 114a) ( Figure 50 (c)); form a patterned current spreading layer 106 ( Figure 50 (d)); form a patterned first insulating layer 108 covering the current spreading layer 106, with a part of the first insulating layer 108 located at the step ( Figure 50 (e)); form a patterned reflective layer 107 covering the first insulating layer 108 ( Figure 50(f)); Form a patterned second insulating layer 109 covering the reflective layer 107( Figure 50 (g)); Form an N-type electrode 102 and a P-type electrode 104( Figure 50 (h)); Form a first light filtering layer 117a, a second light filtering layer 117b, and a third light filtering layer 117c on the side of the substrate 100 facing away from the reflective layer 107( Figure 50 (i)).

[0230] As the fifth method for fabricating a light-emitting diode chip, as shown in Figure 51 the fabrication method includes:

[0231] Form a substrate 100 through a deposition process Figure 51 (a)); Sequentially form a buffer layer 101, an N-type semiconductor layer 103, a third light-emitting material 113-3, a second light-emitting material 113-2, a first light-emitting material 113-1, and a P-type semiconductor layer 105 on the substrate 100 through an epitaxial growth process Figure 51 (b)); Form a step and a channel (an isolation structure 114 without filling an isolation material 114a) Figure 51 (c)); Form a patterned current spreading layer 106 Figure 51 (d)); Form a patterned first insulating layer 108 covering the current spreading layer 106, with a part of the first insulating layer 108 located at the step Figure 51 (e)); Form a patterned reflective layer 107 covering the first insulating layer 108 Figure 51 (f)); Form a patterned second insulating layer 109 covering the reflective layer 107 Figure 51 (g)); Form an N-type electrode 102 and a P-type electrode 104 Figure 51 (h)); Form a first light filtering layer 117a, a second light filtering layer 117b, and a third light filtering layer 117c on the side of the substrate 100 facing away from the reflective layer 107 Figure 51 (i)).

[0232] Combined with Figure 43-46 as shown, the chip provided by the embodiment of the present application further includes a color conversion layer 112, and the color conversion layer 112 is disposed on the light-emitting side of a part of the light-emitting diode chips and is correspondingly disposed with at least a part of the regions of the sub-pixels.

[0233] It should be noted that the positive projection of the color conversion layer 112 on the plane where the corresponding sub-pixel is located may cover all regions of a single sub-pixel or only cover a part of the regions of a single sub-pixel. The material of the color conversion layer 112 may be a quantum dot material, a phosphor material, etc. Using the color conversion layer 112 can adjust the light-emitting wavelength of the light-emitting diode chip and enrich the types of its light-emitting wavelengths.

[0234] Referring toFigure 46 As shown, taking the chip of the upright structure as an example, the light emission wavelengths of the sub-pixels corresponding to the first filter layer 117a, the second filter layer 117b and the third filter layer 117c are different, and the color conversion layer 112 is located at the light emission layer of the first filter layer 117a and is opposite to a part of the first filter layer 117a, so that part of the light emission of the first filter layer 117a can be converted into light of other emission wavelengths except the light transmission wavelength of the first filter layer 117a, the second filter layer 117b and the third filter layer 117c. Therefore, the chip can emit light of multiple emission wavelengths.

[0235] In a third aspect, an embodiment of the present application provides a light-emitting diode chip set, comprising a plurality of the above-mentioned light-emitting diode chips, wherein the plurality of light-emitting diode chips are arranged in an array along a thickness direction intersecting the light-emitting diode chips.

[0236] Reference Figure 52 As shown, multiple chips can be arranged in an array in a plane formed by the x-direction and the y-direction, for example, chip C1, chip C2, chip C3 and chip C4. The x-direction and the y-direction can intersect each other, and in some embodiments, the two can be perpendicular to each other. Multiple chips can be arranged only along the x-direction, such as chip C1 and chip C2. Multiple chips can also be arranged only along the y-direction, such as chip C1 and chip C3. The arrangement of the chipset provided in the present application can be flexibly adjusted.

[0237] Reference Figure 52 As shown, in the chipset of the present application, the sub-pixels in a single chip can form a complete pixel unit. For example, in chip C1, sub-pixel B, sub-pixel G and sub-pixel R can form a pixel unit.

[0238] In the chipset of the present application, pixels of multiple chips can form a complete pixel unit.

[0239] As a first achievable implementation method, refer to Figure 64 As shown, in two adjacent LED chips, the entire area of ​​the sub-pixel of one LED chip and the entire area of ​​the sub-pixel of the other LED chip together form a pixel unit. For example, the sub-pixel B in chip C1 and the sub-pixel G and sub-pixel R in chip C3 together form a pixel unit.

[0240] As a second achievable implementation method, refer to Figure 58-61 As shown, in two adjacent LED chips, a partial area of ​​the sub-pixel of one LED chip and a partial area of ​​the sub-pixel of another LED chip together form a pixel unit. Figure 58Among them, a partial area of the sub-pixel R and the sub-pixel G in the chip C1 and a partial area of the sub-pixel B in the chip C2 together form a pixel unit PU2. Among them, the sub-pixel R of the chip C1 can also be used to form the pixel unit PU1, and the sub-pixel B of the chip C2 can also be used to form the pixel unit PU3. Therefore, the sub-pixel R and the sub-pixel B are sub-pixels shared by two pixel units respectively. Figure 59 Compared with Figure 58 , the arrangement of the sub-pixels in the two chips is different, but the sub-pixels shared are still the sub-pixel R and the sub-pixel B.

[0241] Referring to Figure 60 as shown, the sub-pixels shared can also be the sub-pixel G and the sub-pixel R. Referring to Figure 61 as shown, the sub-pixels shared can also be the sub-pixel G and the sub-pixel B.

[0242] Referring to Figure 53 to Figure 57 as shown, in the light-emitting diode chip group provided by the embodiment of the present application, two adjacent light-emitting diode chips are both irregular in shape. One of the two adjacent light-emitting diode chips has a convex area, and the other has a concave area; the convex area and the concave area are in a matching shape and are spliced with each other.

[0243] It should be noted that the convex area can be a cube, a cone, a hemisphere or other irregular shapes, and the convex area and the concave area are in a matching shape and are spliced with each other. The respective numbers of the convex area and the concave area can be 1, 2 or more, and the numbers of both are equal. For example, the adjacent light-emitting diode chips can include a first light-emitting diode chip and a second light-emitting diode chip.

[0244] It should be noted that taking Figure 53-55 as an example, the first light-emitting diode chip C1 and the second light-emitting diode chip C2 are both in a stepped shape. The convex area of the step of the first light-emitting diode chip C1 is spliced with the concave area of the step of the second light-emitting diode chip C2 in this way for splicing. In this way, the first light-emitting diode chip C1 and the second light-emitting diode chip C2 are completed in splicing.

[0245] Among them, referring to Figure 53 and Figure 54 as shown, the sizes of the sub-pixels in the first light-emitting diode chip C1 are the same. In the present application, by splicing the convex area and the concave area in alignment with each other, a structure similar to a "mortise and tenon structure" can be formed, so as to facilitate the self-alignment assembly of different light-emitting diode chips, reduce the alignment difficulty, and improve the preparation efficiency and yield.

[0246] The shape of the spliced light-emitting diode chips can also be a convex shape or a concave shape( Figure 54 as shown); or, in the stepped light-emitting diode chips, the sizes of different sub-pixels are different(Figure 55 as shown); alternatively, the light-emitting diode chip has a serrated edge ( Figure 56 as shown); or, the light-emitting diode chip has an arc-shaped edge ( Figure 57 as shown).

[0247] In some other embodiments, referring to Figure 58 to Figure 63 as shown, in the combined chips of the light-emitting diode chip group, the shapes of different light-emitting diode chips may also be the same and are regular shapes.

[0248] In the chip group provided in the embodiments of the present application, a plurality of light-emitting diode chips form a plurality of chip groups arranged in an array and a plurality of pixel units arranged in an array; in the same light-emitting diode chip, the pitch between adjacent sub-pixels is d1; the pitch between adjacent chip groups is d2; the pitch between adjacent pixel units is d3; the pitch between adjacent light-emitting diode chips is d4; any one of d1, d2, d3, and d4 is equal, or d1, d2, d3, and d4 are not equal to each other pairwise.

[0249] Referring to Figure 52 as shown, in the chip group, along the y direction, the size of sub-pixel B of chip C1, and the sum of the pitch between sub-pixel B and sub-pixel G is the first size. The size of sub-pixel B is a, the pitch between sub-pixel B and sub-pixel G is b, the first size = a + b, and the first size is the sub-pitch of sub-pixel B.

[0250] In chip C1, the size of sub-pixel G, and the sum of the pitch between sub-pixel G and sub-pixel R is the second size. The size of sub-pixel G is c, the pitch between sub-pixel G and sub-pixel R is d, the second size = c + d, and the second size is the sub-pitch of sub-pixel G.

[0251] In chip C1, the size of sub-pixel R, and the sum of the pitch between sub-pixel R of chip C1 and sub-pixel B of chip C2 is the third size. The size of sub-pixel R is e, the pitch between sub-pixel R of chip C1 and sub-pixel B of chip C2 is f, the third size = e + f, and the third size is the sub-pitch of sub-pixel R.

[0252] Optionally, the first size, the second size, and the third size are all equal; the first size, the second size, and the third size may also be all not equal. Among them, the sum of the first size, the second size, and the third size may be the pitch of the pixel unit composed of sub-pixel B, sub-pixel G, and sub-pixel R of chip C1.

[0253] Similarly, in chip C2, the pixel unit formed by sub-pixel B, sub-pixel G, and sub-pixel R also has a pixel size. The pixel sizes of chip C1 and chip C2 may be equal or not equal.

[0254] Continue to refer to Figure 52 Along the first direction x, in the chip group CG1, the size of the sub-pixel B of the chip C1 is a'. The distance between the sub-pixel B of the chip C1 and the sub-pixel B of the chip C3 is g.

[0255] The sum of a' and g can be the pixel size of the pixel unit in the chip C1 along the first direction x. The sum of a, b, c, d, e, and f can be the pixel size of the pixel unit along the second direction y. The sum of m and n and the sum of a, b, c, d, e, and f can be equal or unequal.

[0256] When the number of sub-pixels of the chip group along the first direction x is 1, along the first direction x, the sum of the size of the chip and the distance between the chip groups can be flexibly adjusted, that is, Figure 52 The sum of a' and g shown in can be flexibly adjusted. In this way, it is possible to adapt to display panels with different pixel sizes.

[0257] Among them, in each light-emitting diode chip, the distance between two adjacent sub-pixels can be d1. The distance between adjacent chip groups can be d2. The distance between adjacent pixel units can be d3. The distance between two adjacent light-emitting diode chips can be d4. d1, d2, d3, and d4 can all be equal. In this way, the arrangement regularity of each sub-pixel, each light-emitting diode chip, each light-emitting diode chip group, and each pixel unit can be effectively improved, and the light-emitting uniformity can be improved.

[0258] Or, d1, d2, d3, and d4 can be pairwise different. That is, d1 can be not equal to d2, can be not equal to d3, and can be not equal to d4; d2 can be not equal to d3 and can be not equal to d4; d3 can be not equal to d4. Among them, d3 can be determined by the PPI of the full-color display screen prepared by the light-emitting diode chip group, and the flexible adjustment of d3 can achieve efficient layout for various applications from a watch to a large-size TV.

[0259] In the fourth aspect, referring to Figure 65 and 66 As shown, an embodiment of the present application provides a display module, including a driving backplane 200 and the light-emitting diode chip group of the above embodiment. The light-emitting diode chip group is disposed on the driving backplane 200 and is electrically connected to the driving backplane 200.

[0260] It should be noted that the driving backplane 200 can be a TFT (Thin Film Transistor) driving backplane 200 or a CMOS (Complementary Metal Oxide Semiconductor) driving backplane 200.

[0261] It should be noted that, as a first implementable embodiment, referring to Figure 65 As shown, there are multiple light-emitting diode chip groups, and the multiple light-emitting diode chip groups are arranged in an array on the driving backplane 200. The driving backplane 200 can provide driving current for the multiple light-emitting diode chip groups, so as to drive the multiple light-emitting diode chip groups to emit light. Figure 65 The light-emitting diode chip group CG1 and the light-emitting diode chip group CG2 are shown arranged on the driving backplane 200. In some embodiments, there may also be 3, 4 or more light-emitting diode chip groups, and the multiple light-emitting diode chip groups are arranged in an array.

[0262] Both the light-emitting diode chip group CG1 and the light-emitting diode chip group CG2 include a light-emitting diode chip C1 and a light-emitting diode chip C2. Each light-emitting diode chip includes a pixel sub-group, and the pixel sub-group includes three sub-pixels. In some embodiments, the number of light-emitting diode chips in the light-emitting diode chip group, the number of pixel sub-groups and sub-pixels in the light-emitting diode chip can all be adjusted, and this embodiment does not limit this.

[0263] As a second implementable embodiment, referring to Figure 66 As shown, the driving backplane 200 includes a driving substrate 201 and multiple driving units 202. One driving unit 202 is correspondingly electrically connected to one light-emitting diode chip group, and the multiple driving units 202 are all electrically connected to the driving substrate 201. The driving unit 202 and the driving substrate 201 can also be TFT and CMOS.

[0264] One driving unit 202 and one light-emitting diode chip group can form a microdisplay module. Figure 66 The microdisplay modules DBM1 and DBM2 are shown, both of which are electrically connected to the driving substrate 201. The driving substrate 201 can provide driving current for the driving units 202 in the microdisplay module, so as to drive the light-emitting diode chip group to emit light through the driving unit 202. In some embodiments, the number of microdisplay modules can be 3, 4, 5 or more, and this embodiment does not limit the specific value of this number.

[0265] Figure 66As shown, a light-emitting diode chip group CG1 and a light-emitting diode chip group CG2 are respectively electrically connected to two different driving units 202, and both of the two driving units 202 are electrically connected to a driving substrate 201. The light-emitting diode chip group CG1 and the light-emitting diode chip group CG2 both include a light-emitting diode chip C1 and a light-emitting diode chip C2. Each light-emitting diode chip includes a pixel subgroup, and the pixel subgroup includes three sub-pixels. In this embodiment, the number of light-emitting diode chip groups, the number of light-emitting diode chips in the light-emitting diode chip group, the number of pixel subgroups and sub-pixels in the light-emitting diode chip can all be adjusted, and this embodiment does not limit this either.

[0266] In a fifth aspect, an embodiment of the present application provides a full-color display screen, and the full-color display screen can be manufactured by encapsulating the above-mentioned display module.

[0267] In a sixth aspect, an embodiment of the present application provides an electronic device, and the electronic device includes the above-mentioned full-color display screen. The electronic device can be a television, an electronic watch, an e-book, a desktop computer, a laptop computer, a tablet computer, a mobile phone, an AR device (Augmented Reality), or a VR device (Virtual Reality), etc. When the light-emitting diode chip of the electronic device includes an ultraviolet pixel, the electronic device can also be an ultraviolet curing lamp or an ultraviolet detection lamp, etc.

[0268] In the description of the embodiments of the present application, it should be understood that, unless otherwise clearly specified and limited, the terms "installation", "connection", and "connection" should be understood in a broad sense. For example, it can be a fixed connection, or an indirect connection through an intermediate medium, and it can be the communication inside two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations. The orientation or positional relationship indicated by the terms "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application. In the description of the present application, "a plurality of" means two or more, unless otherwise specifically and precisely defined.

[0269] In the description and claims of this application and the above-mentioned drawings, the terms "first", "second", "third", "fourth", etc. (if any) are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of the present application described herein can be implemented, for example, in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0270] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit them. Although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features. And these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A light emitting diode chip, characterized in that: It includes an N-type electrode, a P-type electrode, and a light-emitting layer disposed between the N-type electrode and the P-type electrode; the light-emitting layer is electrically connected to the N-type electrode and the P-type electrode respectively; The light-emitting layer includes N light-emitting materials, and the light-emitting wavelengths of the N light-emitting materials are different; along the thickness direction of the light-emitting diode chip, at least one of the N light-emitting materials is stacked with the remaining light-emitting materials; Among the stacked plurality of light-emitting materials, at least one light-emitting material is located on a side of the remaining light-emitting materials close to the P-type electrode, and the light emitted by the light-emitting material is used to excite the remaining light-emitting materials to emit light; The N light-emitting materials are used to form M sub-pixels arranged side by side, and among the M sub-pixels, at least some of the sub-pixels have different light-emitting wavelengths; wherein N and M are both positive integers greater than or equal to 3.

2. The light emitting diode chip according to claim 1, characterized in that: The M is greater than or equal to the N.

3. The light emitting diode chip according to claim 1, characterized in that: Among the stacked light-emitting materials, the light-emitting wavelength of the light-emitting material close to the P-type electrode is smaller than the light-emitting wavelength of the light-emitting material far from the P-type electrode.

4. The light emitting diode chip according to claim 1, characterized in that: Among the N light-emitting materials, the light-emitting material with the smallest light-emitting wavelength is stacked on a side of the remaining light-emitting materials close to the P-type electrode.

5. The light emitting diode chip according to claim 4, characterized in that: At least a portion of each of the light-emitting materials is electrically connected to the N-type electrode.

6. The light emitting diode chip according to claim 5, characterized in that: The remaining luminescent materials are arranged side by side; The light-emitting material with the smallest light-emitting wavelength includes a first part and a second part connected to each other, and the first part is stacked with the rest of the light-emitting materials; a side of the first part close to the P-type electrode is electrically connected to the P-type electrode, and different positions of a side of the first part close to the N-type electrode correspond to different light-emitting materials arranged side by side; The second portion is arranged side by side with the rest of the light-emitting materials, and the second portion and the rest of the light-emitting materials are both electrically connected to the N-type electrode on one side close to the N-type electrode; The plurality of light-emitting materials arranged side by side correspond to the plurality of sub-pixels respectively.

7. The light emitting diode chip according to claim 5, characterized in that: Except for the light-emitting material closest to the N-type electrode, the rest of the light-emitting materials include a first part and a second part connected to each other; Along the thickness direction of the light emitting diode chip, the remaining first part of the light emitting material is stacked; Along a thickness direction intersecting the light emitting diode chip, the rest of the second portion of the light emitting material and the light emitting material closest to the N-type electrode are arranged side by side in sequence and correspond to different sub-pixels respectively.

8. The light emitting diode chip according to claim 4, characterized in that: The rest of the light emitting materials are stacked along the thickness direction of the light emitting diode chip.

9. The light emitting diode chip according to claim 4, characterized in that: In the stacked light-emitting materials, different regions arranged along a direction intersecting the thickness of the light-emitting diode chip correspond to different sub-pixels respectively.

10. The light emitting diode chip according to claim 5, characterized in that: In stacking a plurality of the luminescent materials, a plurality of the luminescent materials form a luminescent material group, and the luminescent layer includes a plurality of the luminescent material groups; Along the direction from the P-type electrode to the N-type electrode, a plurality of the light-emitting material groups are arranged in sequence.

11. The light emitting diode chip according to any one of claims 1 to 10, characterized in that: The N-type electrode includes M separate sub-N-type electrodes, the side of the M sub-pixels close to the P-type electrode is electrically connected to the P-type electrode, and the side of the M sub-pixels close to the N-type electrode is electrically connected to the M sub-N-type electrodes one by one; Alternatively, the P-type electrode includes M separate sub-P-type electrodes, and the sides of the M sub-pixels close to the N-type electrode are electrically connected to the N-type electrode, and the sides of the M sub-pixels close to the P-type electrode are electrically connected to the M sub-P-type electrodes one by one.

12. The light emitting diode chip according to any one of claims 1 to 10, characterized in that: The N-type electrode includes m mutually separate sub-N-type electrodes, a side of the M sub-pixels close to the P-type electrode is electrically connected to the P-type electrode, and a side of the M sub-pixels close to the N-type electrode is electrically connected to the m sub-N-type electrodes; m is less than M, and a part of the sub-pixels share one sub-N-type electrode; Or, the P-type electrode includes m separate sub-P-type electrodes, a side of the M sub-pixels close to the N-type electrode is electrically connected to the N-type electrode, and a side of the M sub-pixels close to the P-type electrode is electrically connected to the m sub-P-type electrodes; m is less than M, and a part of the sub-pixels share one sub-P-type electrode.

13. The light emitting diode chip according to any one of claims 1 to 10, characterized in that: Also included is an isolation structure, wherein the isolation structure is located between any two adjacent sub-pixels; The isolation structure includes a channel; or, the isolation structure includes a channel and an isolation material disposed in the channel; or, the isolation structure is an ion implantation layer.

14. The light emitting diode chip according to claim 13, characterized in that: It also includes an N-type semiconductor layer and a P-type semiconductor layer, wherein the N-type semiconductor and the P-type semiconductor are respectively located on opposite sides of the light-emitting layer in the thickness direction, the N-type electrode is electrically connected to the light-emitting layer through the N-type semiconductor, and the P-type electrode is electrically connected to the light-emitting layer through the P-type semiconductor; When the N-type electrode includes M separate sub-N-type electrodes, the isolation structure is located between adjacent sub-N-type electrodes, and at least a portion of the isolation structure extends into the P-type semiconductor layer; When the P-type electrode includes M separate sub-P-type electrodes, the isolation structure is located between adjacent sub-P-type electrodes, and at least a portion of the isolation structure extends into the N-type semiconductor layer.

15. The light emitting diode chip according to any one of claims 1 to 10, characterized in that: It also includes a plurality of filter layers with different filtering wavelengths, the plurality of filter layers are arranged side by side on the light emitting side of the light emitting diode chip, and each of the filter layers corresponds to each of the sub-pixels one by one.

16. The light emitting diode chip according to any one of claims 1 to 10, characterized in that: It also includes a hole blocking layer, which is at least arranged between the light-emitting material closest to the P-type electrode and the light-emitting material adjacent to the light-emitting material layer closest to the P-type electrode.

17. The light emitting diode chip according to claim 16, characterized in that: The hole blocking layer is also located between any two adjacent light-emitting materials among the stacked light-emitting materials.

18. The light emitting diode chip according to any one of claims 1 to 10, characterized in that: The M sub-pixels form a pixel subgroup; Alternatively, the M sub-pixels form a plurality of pixel subgroups, and the plurality of pixel subgroups are arranged in an array in a direction intersecting the thickness direction of the light emitting diode chip.

19. The light emitting diode chip according to claim 18, characterized in that: Among the plurality of sub-pixels in the pixel subgroup, light-emitting wavelengths of the plurality of sub-pixels are different from each other, or the plurality of sub-pixels include at least two sub-pixels with the same light-emitting wavelength.

20. The light emitting diode chip according to any one of claims 1 to 10, characterized in that: M sub-pixels form a plurality of pixel units, and the plurality of pixel units are arranged in an array along a thickness direction intersecting the light-emitting diode chip; One pixel unit includes Y sub-pixels, and the Y sub-pixels include X wavelengths; X is a positive integer greater than or equal to 3, and Y is a positive integer greater than or equal to X.

21. The light emitting diode chip according to claim 20, characterized in that: When Y is greater than X, in one pixel unit, at least a portion of the sub-pixels have the same light emission wavelength.

22. The light emitting diode chip according to claim 20, characterized in that: All the sub-pixels in the same pixel unit are only used by the pixel unit to which they belong.

23. The light emitting diode chip according to claim 20, characterized in that: Two adjacent pixel units share two sub-pixels, and the number of all sub-pixels in a single chip is a*(2X-2), where a is a positive integer greater than or equal to 1.

24. The light emitting diode chip according to any one of claims 1 to 10, characterized in that: The invention also comprises a reflective layer, wherein the reflective layer is located at the backlight side of the light emitting diode chip.

25. The light emitting diode chip according to any one of claims 1 to 10, characterized in that: It also includes a light-blocking layer, which is located on the light-emitting side of the light-emitting diode chip and between two adjacent sub-pixels.

26. The light emitting diode chip according to any one of claims 1 to 10, characterized in that: The size of the light emitting diode chip is greater than or equal to 50 microns; And / or, the shape of the light-emitting diode chip is any one of a rectangle, a square, a circle, an ellipse, a triangle, a rhombus, a parallelogram and a polygon with more than four sides; and / or, the sub-pixel has a size ranging from 0.001 to 200 micrometers; And / or, the sub-pixel has a shape of any one of a rectangle, a square, a circle, an ellipse, a triangle, a rhombus, a parallelogram and a polygon with more than four sides; And / or, the shapes of different sub-pixels are the same or different; And / or, sizes of different sub-pixels are equal or different.

27. The light emitting diode chip according to any one of claims 1 to 10, characterized in that: It also includes a buffer layer, an N-type semiconductor layer, a P-type semiconductor layer, a current spreading layer, a reflective layer and a first insulating layer; The buffer layer and the N-type semiconductor layer are stacked, the light-emitting layer is arranged on a side of the N-type semiconductor layer away from the buffer layer, and the P-type semiconductor layer is arranged on a side of the light-emitting layer away from the buffer layer; The current spreading layer is in contact with a side of the P-type semiconductor layer away from the buffer layer, the N-type electrode is in contact with the N-type semiconductor layer, and the P-type electrode is in contact with the P-type semiconductor layer and the current spreading layer; The first insulating layer is arranged on a side of the current spreading layer away from the buffer layer; The reflective layer is arranged on a side of the buffer layer away from the light-emitting layer, or the reflective layer is arranged on a side of the first insulating layer away from the buffer layer, and a second insulating layer is further arranged on the side of the reflective layer away from the buffer layer.

28. The light emitting diode chip according to claim 27, characterized in that: It also includes a substrate, which is arranged on a side of the buffer layer away from the light-emitting layer; When the reflective layer is disposed on a side of the buffer layer away from the light-emitting layer, the reflective layer is disposed on a side of the substrate away from the buffer layer.

29. The light emitting diode chip according to any one of claims 1 to 10, characterized in that: Also includes a bonding substrate, a binding layer, an N-type semiconductor layer, a P-type semiconductor layer and a reflective layer; The bonding substrate and the binding layer are sequentially arranged on the P-type electrode, and the P-type semiconductor layer is arranged on a side of the binding layer away from the bonding substrate and in contact with the binding layer; The light emitting layer is arranged on a side of the P-type semiconductor layer away from the bonding substrate, the N-type semiconductor layer is arranged on a side of the light emitting layer away from the bonding substrate, and the N-type electrode contacts the side of the N-type semiconductor layer away from the bonding substrate; The reflective layer is arranged on a side of the P-type semiconductor layer close to the bonding substrate.

30. The light emitting diode chip according to any one of claims 1 to 10, characterized in that: It also includes a color conversion layer, which is arranged on the light-emitting side of a portion of the light-emitting diode chip and corresponds to at least a portion of the sub-pixel area.

31. A light emitting diode chipset, characterized in that: It comprises a plurality of light emitting diode chips as claimed in any one of claims 1 to 30, wherein the plurality of light emitting diode chips are arranged in an array along a thickness direction intersecting the light emitting diode chips.

32. The light emitting diode chipset according to claim 31, characterized in that: In two adjacent LED chips, the entire area of ​​the sub-pixel of one LED chip and the entire area of ​​the sub-pixel of the other LED chip together form a pixel unit.

33. The light emitting diode chipset according to claim 32, characterized in that: In two adjacent LED chips, a partial area of ​​the sub-pixel of one LED chip and a partial area of ​​the sub-pixel of another LED chip together form a pixel unit.

34. The light emitting diode chip set according to any one of claims 31 to 33, characterized in that: The two adjacent light-emitting diode chips are both of special shapes; one of the two adjacent light-emitting diodes has a protruding area, and the other has a concave area; the protruding area and the concave area are matched in shape and fit together.

35. The light emitting diode chip set according to any one of claims 31 to 33, characterized in that: The plurality of light-emitting diode chips form a plurality of chip groups arranged in an array and a plurality of pixel units arranged in an array; in the same light-emitting diode chip, the spacing between adjacent sub-pixels is d1; the spacing between adjacent chip groups is d2; the spacing between adjacent pixel units is d3; and the spacing between adjacent light-emitting diode chips is d4; d1, d2, d3 and d4 are all equal, or d1, d2, d3 and d4 are not equal to each other.

36. A display module, characterized in that: It comprises a driving backplane and a light-emitting diode chipset as described in any one of claims 31-35, wherein the light-emitting diode chipset is arranged on the driving backplane and electrically connected to the driving backplane.

37. The display module according to claim 36, characterized in that: There are multiple light emitting diode chip groups; A plurality of the light emitting diode chip groups are arranged in an array on the driving backplane; Alternatively, the driving backplane includes a driving substrate and a plurality of driving units, one of the driving units is electrically connected to one of the light emitting diode chipsets, and the plurality of driving units are electrically connected to the driving substrate.

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