Full-color Micro LED display device and preparation method thereof

Abstract

The invention discloses a full-color Micro LED display device and a preparation method thereof, the device comprises a plurality of groups of display units, each display unit comprises a first N-GaN layer, a blue light LED light-emitting layer, a first P-GaN layer, a first insulating layer, a second N-GaN layer, a green light LED light-emitting layer, a second P-GaN layer, a second insulating layer, a third N-GaN layer, a red light LED light-emitting layer, a third P-GaN layer and a passivation layer, the side walls cover the first N-GaN layer, the blue light LED light-emitting layer, the first P-GaN layer, the first insulating layer, the second N-GaN layer, the green light LED light-emitting layer, the second P-GaN layer, the second insulating layer, the third N-GaN layer, the red light LED light-emitting layer and the third P-GaN layer; the upper surfaces of the first N electrode, the second N electrode, the third N electrode, the first P-type reflecting electrode, the second P-type reflecting electrode and the third P-type reflecting electrode are flush in height; and the CMOS driver covers the upper surface of the bonding layer and is electrically connected with the first N electrode, the second N electrode, the third N electrode, the first P-type reflecting electrode, the second P-type reflecting electrode and the third P-type reflecting electrode.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a full-color Micro LED display device and a preparation method thereof. Background Art

[0002] Gallium nitride is a semiconductor material with excellent electrical properties and thermal stability, and is very suitable for manufacturing high-brightness and high-efficiency Micro LEDs. The gallium nitride Micro LED has a high luminous efficiency, can significantly reduce energy consumption, and at the same time provides a high enough brightness to meet the requirements of full-color display. The gallium nitride Micro LED has high stability and can operate stably for a long time without easily malfunctioning, which is particularly important for full-color display devices that need to operate for a long time.

[0003] In the prior art, in order to achieve full-color Micro LED display, it is often necessary to fabricate devices on three wafers with different light-emitting colors, and then achieve three-color integration by bonding wafers with different emission wavelengths. This method has a complex process, high cost, low yield, and long production cycle. Or through a single epitaxial wafer, by changing the magnitude of the current to change the emission wavelength, so as to achieve full-color display. This method has a limited wavelength change range, only covering the range from green to red, or from cyan to red, and the displayed color gamut is insufficient. Summary of the Invention

[0004] Object of the Invention: In order to overcome the deficiencies of the prior art, the object of the present invention is to provide a full-color Micro LED display device, and another object of the present invention is to provide a preparation method of a full-color Micro LED display device.

[0005] To solve the above technical problems, the present invention provides a full-color Micro LED display device, including a plurality of groups of display units, and the display unit includes:

[0006] A first N-GaN layer, and the side of the first N-GaN layer has a first step;

[0007] A blue light LED light-emitting layer, covering the upper surface of the non-step region of the first N-GaN layer;

[0008] A first P-GaN layer, covering the upper surface of the blue light LED light-emitting layer, and the side of the first P-GaN layer has a second step;

[0009] A first insulating layer, covering the upper surface of the non-step region of the first P-GaN layer;

[0010] A second N-GaN layer, covering the upper surface of the first insulating layer, and the side of the second N-GaN layer has a third step;

[0011] A green light LED light-emitting layer covering the upper surface of the non-step region of the second N-GaN layer;

[0012] A second P-GaN layer covering the upper surface of the green light LED light-emitting layer, with a fourth step on the side of the second P-GaN layer;

[0013] A second insulating layer covering the upper surface of the non-step region of the second P-GaN layer;

[0014] A third N-GaN layer covering the upper surface of the second insulating layer, with a fifth step on the side of the third N-GaN layer;

[0015] A red light LED light-emitting layer covering the upper surface of the non-step region of the third N-GaN layer;

[0016] A third P-GaN layer covering the upper surface of the red light LED light-emitting layer;

[0017] A passivation layer covering the sidewalls of the first N-GaN layer, blue light LED light-emitting layer, first P-GaN layer, first insulating layer, second N-GaN layer, green light LED light-emitting layer, second P-GaN layer, second insulating layer, third N-GaN layer, red light LED light-emitting layer, and third P-GaN layer;

[0018] A first conductive layer covering the upper surface of the second step;

[0019] A second conductive layer covering the upper surface of the fourth step;

[0020] A third conductive layer covering the upper surface of the third P-GaN layer;

[0021] A first N electrode located on the first step and extending away from the first N-GaN layer;

[0022] A second N electrode located on the third step and extending away from the first N-GaN layer;

[0023] A third N electrode located on the fifth step and extending away from the first N-GaN layer;

[0024] A first P-type reflective electrode covering the first conductive layer and extending away from the first N-GaN layer;

[0025] A second P-type reflective electrode covering the second conductive layer and extending away from the first N-GaN layer;

[0026] A third P-type reflective electrode covering the third conductive layer and extending away from the first N-GaN layer;

[0027] The upper surfaces of the first N electrode, the second N electrode, the third N electrode, the first P-type reflective electrode, the second P-type reflective electrode, and the third P-type reflective electrode are flush.

[0028] The bonding layer fills the gaps between the first N electrode, the second N electrode, the third N electrode, the first P-type reflective electrode, the second P-type reflective electrode, the third P-type reflective electrode, and the passivation layer and coats the first N electrode, the second N electrode, the third N electrode, the first P-type reflective electrode, the second P-type reflective electrode, the third P-type reflective electrode, and the passivation layer.

[0029] The CMOS driver covers the upper surface of the bonding layer and is electrically connected to the first N electrode, the second N electrode, the third N electrode, the first P-type reflective electrode, the second P-type reflective electrode, and the third P-type reflective electrode.

[0030] Preferably, the bonding layer includes a first bonding layer and a second bonding layer stacked from bottom to top;

[0031] The portions of the first N electrode, the second N electrode, the third N electrode, the first P-type reflective electrode, the second P-type reflective electrode, and the third P-type reflective electrode located within the second bonding layer are respectively the first N-type contact electrode, the second N-type contact electrode, the third N-type contact electrode, the first P-type contact electrode, the second P-type contact electrode, and the third P-type contact electrode in sequence.

[0032] Preferably, the first insulating layer is undoped AlGaN; and / or the second insulating layer is undoped AlGaN.

[0033] Preferably, the first insulating layer is two or more layers of Al x1 Ga 1-x1 N, where 0 < x1 ≤ 1, and the Al compositions x1 of different AlGaN sub-layers are not equal; and / or the second insulating layer is two or more layers of Al x2 Ga 1-x2 N, where 0 < x2 ≤ 1, and the Al compositions x2 of different AlGaN sub-layers are not equal.

[0034] Preferably, the first insulating layer is an Al x1 Ga 1-x1 N / Al y1 Ga 1-y1 N superlattice structure, where 0 < x1 ≤ 1, 0 < y1 ≤ 1, and x1 ≠ y1; and / or the second insulating layer is an Al x2 Ga 1-x2 N / Al y2 Ga 1-y2 N superlattice structure, where 0 < x2 ≤ 1, 0 < y2 ≤ 1, and x2 ≠ y2.

[0035] The first insulating layer superlattice structure has 2 - 20 groups with a total thickness of 30 - 500 nm; the second insulating layer superlattice structure has 2 - 20 groups with a total thickness of 30 - 500 nm.

[0036] Preferably, the pixel size of the display unit is 1 μm - 500 μm.

[0037] Based on the same inventive concept, the present invention also provides a method for manufacturing a full-color Micro LED display device, including:

[0038] Forming a first component, including the following steps:

[0039] Step 11, providing a silicon substrate, and epitaxially growing a nucleation layer, a buffer layer, a first N-GaN layer, a blue light LED light-emitting layer, a first P-GaN layer, a first insulating layer, a second N-GaN layer, a green light LED light-emitting layer, a second P-GaN layer, a second insulating layer, a third N-GaN layer, a red light LED light-emitting layer, and a third P-GaN layer on the surface of the silicon substrate in sequence;

[0040] Step 12, forming steps, including:

[0041] The first etching, etching a part of each layer on the first N-GaN layer and a part of the first N-GaN layer along the thickness direction of the first component to form a first step on the side of the first N-GaN layer;

[0042] The second etching, etching a part of each layer on the first P-GaN layer and a part of the first P-GaN layer along the thickness direction of the first component to form a second step on the side of the first P-GaN layer;

[0043] The third etching, etching a part of each layer on the second N-GaN layer and a part of the second N-GaN layer along the thickness direction of the first component to form a third step on the side of the second N-GaN layer;

[0044] The fourth etching, etching a part of each layer on the second P-GaN layer and a part of the second P-GaN layer along the thickness direction of the first component to form a fourth step on the side of the second P-GaN layer;

[0045] The fifth etching, etching a part of each layer on the third N-GaN layer and a part of the third N-GaN layer along the thickness direction of the first component to form a fifth step on the side of the third N-GaN layer;

[0046] Step 13: Form a passivation layer that covers the sidewalls of the first N-GaN layer, the blue LED light-emitting layer, the first P-GaN layer, the first insulating layer, the second N-GaN layer, the green LED light-emitting layer, the second P-GaN layer, the second insulating layer, the third N-GaN layer, the red LED light-emitting layer, and the third P-GaN layer;

[0047] Step 14: Form a first conductive layer that covers the upper surface of the second step; form a second conductive layer that covers the upper surface of the fourth step; form a third conductive layer that covers the upper surface of the third P-GaN layer;

[0048] Step 15: Provide a first N-type sub-electrode that is located on the first step and extends away from the first N-GaN layer; provide a second N-type sub-electrode that is located on the third step and extends away from the first N-GaN layer; provide a third N-type sub-electrode that is located on the fifth step and extends away from the first N-GaN layer;

[0049] Step 16: Provide a first P-type sub-electrode that covers the first conductive layer and extends away from the first N-GaN layer; provide a second P-type sub-electrode that covers the second conductive layer and extends away from the first N-GaN layer; provide a third P-type sub-electrode that covers the third conductive layer and extends away from the first N-GaN layer;

[0050] Step 17: Form a first bonding layer that fills the gaps between the first N-type sub-electrode, the second N-type sub-electrode, the third N-type sub-electrode, the first P-type sub-electrode, the second P-type sub-electrode, the third P-type sub-electrode, and the passivation layer;

[0051] Step 18: Planarize the first bonding layer;

[0052] Form a second component, including the following steps:

[0053] Step 21: Provide a CMOS driver and form a second bonding layer above the CMOS driver;

[0054] Step 22: Etch the second bonding layer along the thickness direction of the second bonding layer to form six vias that penetrate the second bonding layer;

[0055] Step 23: Place a first N-type contact electrode, a second N-type contact electrode, a third N-type contact electrode, a first P-type contact electrode, a second P-type contact electrode, and a third P-type contact electrode in the vias respectively;

[0056] Bond the first component and the second component, including the following steps:

[0057] Step 31, horizontally transpose the second component, align and bond the first N-type sub-electrode with the first N-type contact electrode, the second N-type sub-electrode with the second N-type contact electrode, the third N-type sub-electrode with the third N-type contact electrode, the first P-type sub-electrode with the first P-type contact electrode, the second P-type sub-electrode with the second P-type contact electrode, and the third P-type sub-electrode with the third P-type contact electrode, and form a first N electrode, a second N electrode, a third N electrode, a first P-type reflective electrode, a second P-type reflective electrode, and a third P-type reflective electrode respectively;

[0058] Step 32, remove the silicon substrate, the nucleation layer, and the buffer layer to obtain the full-color Micro LED display device.

[0059] Preferably, after step 12, P-type Mg doping activation is further performed on the first component, and the doping concentration > 5E18 cm -3 .

[0060] Preferably, step 16 includes: step 161, set a first P-type sub-electrode thin film layer covering the first conductive layer, a second P-type sub-electrode thin film layer covering the second conductive layer, and a third P-type sub-electrode thin film layer covering the third conductive layer;

[0061] Step 162, set a first P-type sub-electrode extension perpendicular to the first P-type sub-electrode thin film layer on the first P-type sub-electrode thin film layer, a second P-type sub-electrode extension perpendicular to the second P-type sub-electrode thin film layer on the second P-type sub-electrode thin film layer, and a third P-type sub-electrode extension perpendicular to the third P-type sub-electrode thin film layer on the third P-type sub-electrode thin film layer;

[0062] The first P-type sub-electrode thin film layer and the first P-type sub-electrode extension together constitute the first P-type sub-electrode, the second P-type sub-electrode thin film layer and the second P-type sub-electrode extension together constitute the second P-type sub-electrode, and the third P-type sub-electrode thin film layer and the third P-type sub-electrode extension together constitute the third P-type sub-electrode.

[0063] Working principle: By simplifying the etching process, relaxing the requirements for etching precision, and introducing an electrical isolation layer, the device manufacturing process has been highly simplified and its performance improved. The present invention ingeniously uses two layers of undoped AlGaN materials as the electrical isolation layer, i.e., the insulating layer, to construct an efficient isolation structure between N-type GaN and P-type GaN, thereby achieving independent and stable electrical control between full-color Micro LEDs. Compared with the traditional manufacturing process, it is no longer necessary to precisely etch the material to the interface between N-type GaN and P-type GaN. This change has greatly relaxed the requirements for etching precision. Since both the N-type and P-type material layers maintain a relatively large thickness, even if there are certain errors during the etching process, it will not have a significant impact on the ohmic contact between the electrode and the material, thereby improving the yield and reliability of the entire device manufacturing. On this basis, each electrode can be flexibly and precisely placed on the P-type or N-type layer through material etching without excessive concern about the specific etching depth, which makes the manufacturing process of the electrode simpler and more efficient. At the same time, the addition of two layers of undoped AlGaN materials not only achieves effective electrical isolation but also ensures that full-color Micro LEDs can operate independently without interference and emit light independently, thereby improving the performance and stability of the LED device.

[0064] Advantages: Compared with the prior art, the present invention has the following remarkable features:

[0065] 1. Three light-emitting wavelengths are integrated within one epitaxial wafer, and they can be grown in one growth by epitaxial growth, without the need to be repeatedly placed in an epitaxial machine (MOCVD / MBE) for regrowth, and without the need to bond and integrate wafers with three different light-emitting wavelengths (RGB three colors) to realize multiple light-emitting materials, greatly simplifying the device manufacturing process.

[0066] 2. During the manufacturing process of the electrode, it is not necessary to precisely control the etching depth of the material, highly simplifying the device manufacturing process and improving the yield of device manufacturing. Electrical isolation between the three colors of full-color Micro LEDs is achieved through the addition of two layers of undoped insulating layers. Each electrode can be placed on the P-GaN layer or N-GaN layer through material etching. Since the N / P-type material layers have a relatively large thickness, compared with precisely etching to the interface between the N-GaN layer and the P-GaN layer, the control of the material etching depth does not need to be very strict, reducing the complexity of device manufacturing.

[0067] 3. The devices with three light-emitting wavelengths within one wafer can be controlled separately, the control of the light-emitting wavelength is more precise, the color mixing range is wider, and a larger color gamut is achieved. And the shape of each electrode is relatively perpendicular, and the process steps are simple. Description of the Drawings

[0068] In the accompanying drawings, each identical or nearly identical component shown in different drawings is represented by a similar reference numeral. For clarity, not every component in every drawing is labeled. The drawings are not necessarily drawn to scale; instead, the emphasis is on showing the various aspects of the technologies and devices described herein.

[0069] Figure 1 The structural schematic diagram of the product obtained in Step 11 of the present invention is shown;

[0070] Figure 2 The structural schematic diagram of the product obtained in Step 12 of the present invention is shown;

[0071] Figure 3 The structural schematic diagram of the product obtained in Step 13 of the present invention is shown;

[0072] Figure 4 The structural schematic diagram of the product obtained in Step 14 of the present invention is shown;

[0073] Figure 5 The structural schematic diagram of the product obtained in Step 15 of the present invention is shown;

[0074] Figures 6a - 6b The structural schematic diagram of the product obtained in Step 16 of the present invention is shown;

[0075] Figure 7 The structural schematic diagram of the product obtained in Step 17 of the present invention is shown;

[0076] Figures 8 - 9 The structural schematic diagram of the product obtained in Step 21 of the present invention is shown;

[0077] Figure 10 The structural schematic diagram of the product obtained in Step 22 of the present invention is shown;

[0078] Figure 11 The structural schematic diagram of the product obtained in Step 23 of the present invention is shown;

[0079] Figure 12 The structural schematic diagram of the product obtained in Step 31 of the present invention is shown;

[0080] Figure 13 The structural schematic diagram of the product obtained in Step 32 of the present invention is shown.

[0081] Among them, the description of the reference numerals is as follows:

[0082] 10 - Substrate, 20 - Nucleation layer, 30 - Buffer layer, 40 - First N-GaN layer, 50 - Blue LED light-emitting layer, 60 - First P-GaN layer, 70 - First insulating layer, 80 - Second N-GaN layer, 90 - Green LED light-emitting layer, 100 - Second P-GaN layer, 110 - Second insulating layer, 120 - Third N-GaN layer, 130 - Red LED light-emitting layer, 140 - Third P-GaN layer, 150 - Passivation layer, 161 - First conductive layer, 162 - Second conductive layer, 163 - Third conductive layer, 171 - First N-type sub-electrode, 172 - Second N-type sub-electrode, 173 - Third N-type sub-electrode, 181 - First P-type sub-electrode includes 1811 - First P-type sub-electrode thin film layer and 1812 - First P-type sub-electrode extension, 182 - Second P-type sub-electrode includes 1821 - Second P-type sub-electrode thin film layer and 1822 - Second P-type sub-electrode extension, 183 - Third P-type sub-electrode includes 1831 - Third P-type sub-electrode thin film layer and 1832 - Third P-type sub-electrode extension, 190 - First bonding layer, 210 - CMOS driver, 220 - Second bonding layer, 230 - Through hole, 171' - First N-type contact electrode, 172' - Second N-type contact electrode, 173' - Third N-type contact electrode, 181' - First P-type contact electrode, 182' - Second P-type contact electrode, 183' - Third P-type contact electrode. Detailed implementation manners

[0083] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this invention will be more complete and comprehensive, and the concept of the example embodiments will be fully conveyed to those skilled in the art. Like reference numerals in the figures denote like or similar structures, and thus their repetitive description will be omitted.

[0084] The words expressing positions and directions described in the present invention are illustrative with reference to the drawings, but can be changed according to needs, and all changes are included in the protection scope of the present invention.

[0085] The present invention provides a method for manufacturing a full-color Micro LED display device, including manufacturing a first component, manufacturing a second component, and bonding the first component and the second component.

[0086] Specifically, for manufacturing the first component, the preparation of the epitaxial structure can be completed by using an MOCVD epitaxial growth device, and the steps are as follows:

[0087] Step 11: Provide a silicon substrate 10, and sequentially epitaxially grow a nucleation layer 20, a buffer layer 30, a first N-GaN layer 40, a blue LED light-emitting layer 50, a first P-GaN layer 60, a first insulating layer 70, a second N-GaN layer 80, a green LED light-emitting layer 90, a second P-GaN layer 100, a second insulating layer 110, a third N-GaN layer 120, a red LED light-emitting layer 130, and a third P-GaN layer 140 on the surface of the silicon substrate 10, as Figure 1 shown.

[0088] Grow a 200-nm AlN nucleation layer 20 on the substrate 10 under the temperature condition of 950 - 1150 °C and the pressure condition of 50 - 100 torr.

[0089] Grow a 0.2 - 1-μm AlGaN buffer layer 30 on the nucleation layer 20 under the temperature condition of 980 - 1180 °C and the pressure condition of 50 - 100 torr.

[0090] Grow a 0.5 - 2.0-μm first N-GaN layer 40 on the buffer layer 30 under the temperature condition of 1100 - 1200 °C and the pressure condition of 200 - 300 torr.

[0091] Grow a 90 - 150-nm blue LED light-emitting layer 50 on the first N-GaN layer 40 under the temperature condition of 760 - 800 °C and the pressure condition of 400 - 500 torr. The blue LED light-emitting layer 50 is a multi-quantum well structure.

[0092] Grow a 50 - 100-nm first P-GaN layer 60 on the blue LED light-emitting layer 50 under the temperature condition of 900 - 1000 °C and the pressure condition of 200 - 300 torr.

[0093] Grow a 5 - 20-nm first insulating layer 70 on the first P-GaN layer 60 under the temperature condition of 900 - 1000 °C and the pressure condition of 40 - 200 torr. The material of the first insulating layer 70 is undoped AlGaN, and the Al component can be adjusted. The undoped AlGaN material is a relatively good insulating material to achieve electrical isolation of the three colors of the full-color Micro LED light-emitting device; the material of the first insulating layer 70 can also be two or more layers of Al x1 Ga 1-x1 N, where 0 < x1 ≤ 1, and the Al components x1 of different AlGaN sub-layers are not equal. The warping of the wafer is adjusted by changing the Al component of the AlGaN layer. Preferably, 2 - 10 layers are used, and the total thickness of the insulating layer is 30 - 300 nm to increase the thickness and insulation of the insulating layer; the material of the first insulating layer 70 can also be Al x1 Ga 1-x1 N / Al y1Ga 1-y1 GaN superlattice, where 0 < x1 ≤ 1, 0 < y1 ≤ 1, x1 ≠ y1. By controlling the thickness of each layer in the superlattice, compressive stress or tensile stress can be generated to adjust the wafer in a more convex or more concave direction. Preferably, 2 - 20 groups of such superlattices are used, and the total thickness of the insulating layer is 30 - 500 nm, increasing the thickness and insulation of the insulating layer.

[0094] Under the temperature condition of 1000 - 1200 °C and the pressure condition of 200 - 300 torr, a second N-GaN layer 80 with a thickness of 0.5 - 2.0 μm is grown on the first insulating layer 70.

[0095] Under the temperature condition of 742 - 782 °C and the pressure condition of 400 - 500 torr, a green LED light-emitting layer 90 with a thickness of 90 - 150 nm is grown on the second N-GaN layer 80. The green LED light-emitting layer 90 is a multi-quantum well structure.

[0096] Under the temperature condition of 900 - 1000 °C and the pressure condition of 200 - 300 torr, a second P-GaN layer 100 with a thickness of 50 - 100 nm is grown on the green LED light-emitting layer 90.

[0097] Under the temperature condition of 900 - 1000 °C and the pressure condition of 40 - 200 torr, a second insulating layer 110 with a thickness of 5 - 20 nm is grown on the second P-GaN layer 100. The material of the second insulating layer 110 is undoped AlGaN, and the Al component can be adjusted. The undoped AlGaN material is a relatively good insulating material to achieve electrical isolation of the three colors of the full-color Micro LED light-emitting device; the material of the second insulating layer 110 can also be two or more layers of Al x2 Ga 1-x2 N, where 0 < x2 ≤ 1, and the Al components x2 of different AlGaN sub-layers are not equal. By changing the Al component of the AlGaN layer, the adjustment of the wafer warpage is achieved. Preferably, 2 - 10 layers are used, and the total thickness of the insulating layer is 30 - 300 nm, increasing the thickness and insulation of the insulating layer; the material of the second insulating layer 110 can also be Al x2 Ga 1-x2 N / Al y2 Ga 1-y2 N superlattice, where 0 < x2 ≤ 1, 0 < y2 ≤ 1, x2 ≠ y2. By controlling the thickness of each layer in the superlattice, compressive stress or tensile stress can be generated to adjust the wafer in a more convex or more concave direction. Preferably, 2 - 20 groups of such superlattices are used, and the total thickness of the insulating layer is 30 - 500 nm, increasing the thickness and insulation of the insulating layer.

[0098] The third N-GaN layer 120 with a thickness of 0.5 - 2.0 μm is grown on the second insulating layer 110 under the temperature condition of 1000 - 1200 °C and the pressure condition of 200 - 300 torr.

[0099] The red LED light-emitting layer 130 with a thickness of 90 - 150 nm is grown on the third N-GaN layer 120 under the temperature condition of 702 - 742 °C and the pressure condition of 400 - 500 torr. The red LED light-emitting layer 130 has a multi-quantum well structure.

[0100] The third P-GaN layer 140 with a thickness of 50 - 100 nm is grown on the red LED light-emitting layer 130 under the temperature condition of 900 - 1000 °C and the pressure condition of 200 - 300 torr.

[0101] Three kinds of light-emitting wavelengths are integrated in the epitaxial wafer, which is formed by one-time epitaxial growth. There is no need to put it into the MOCVD machine for regrowth multiple times, and there is no need to adopt the bonding and integration between wafers with three different light-emitting wavelengths (RGB three colors). The related light-emitting material and device manufacturing processes are greatly simplified.

[0102] Step 12: Form steps, including the first etching, etching a part of each layer on the first N-GaN layer 40 and a part of the first N-GaN layer 40 along the thickness direction of the first component to form a first step on the side of the first N-GaN layer 40; the second etching, etching a part of each layer on the first P-GaN layer 60 and a part of the first P-GaN layer 60 along the thickness direction of the first component to form a second step on the side of the first P-GaN layer 60; the third etching, etching a part of each layer on the second N-GaN layer 80 and a part of the second N-GaN layer 80 along the thickness direction of the first component to form a third step on the side of the second N-GaN layer 80; the fourth etching, etching a part of each layer on the second P-GaN layer 100 and a part of the second P-GaN layer 100 along the thickness direction of the first component to form a fourth step on the side of the second P-GaN layer 100; the fifth etching, etching a part of each layer on the third N-GaN layer 120 and a part of the third N-GaN layer 120 along the thickness direction of the first component to form a fifth step on the side of the third N-GaN layer 120.

[0103] Coat the obtained product in Step 11 with photoresist, and perform exposure and development using a mask to form a pattern to be etched. Use ion etching technology to etch the epitaxial layer according to the photolithography pattern to remove the unnecessary parts, etch until the first N-GaN layer 40, and form a first step on the side of the first N-GaN layer 40. The etched thickness of the first N-GaN layer 40 is less than the thickness of the first N-GaN layer 40. The same steps are used to etch and form the second to fifth steps. Generally, shallow etching is used when etching and forming the second and fourth steps. The order of etching to form each step can be changed. For example, the first step can be etched last. After etching is completed, as Figure 2 shown.

[0104] After forming the sidewalls by etching, P-type activation can be carried out in an N 2 atmosphere at a high temperature of 600 - 700 °C. The formation of the sidewalls is conducive to the diffusion of H atoms from the sidewalls, thereby activating Mg doping, and the doping concentration > 5E18 cm -3 .

[0105] Step 13, form a passivation layer 150, and the passivation layer 150 covers the sidewalls of the first N-GaN layer 40, the blue LED light-emitting layer 50, the first P-GaN layer 60, the first insulating layer 70, the second N-GaN layer 80, the green LED light-emitting layer 90, the second P-GaN layer 100, the second insulating layer 110, the third N-GaN layer 120, the red LED light-emitting layer 130, and the third P-GaN layer.

[0106] Deposit the passivation layer 150 by chemical vapor deposition (CVD) or physical vapor deposition (PVD) method. Taking the CVD method as an example, use trimethylaluminum (TMAl), nitrogen (N 2 ) and ammonia (NH 3 ) as reaction gases, with a deposition temperature of 900 - 1000 °C, an aluminum source gas flow rate of 100 - 150 sccm, a nitrogen (N 2 ) gas flow rate of 15000 - 25000 sccm, an ammonia (NH 3 ) gas flow rate of 250 - 350 sccm, and a reaction time of 4 - 6 min, etc. to obtain a uniform and dense 50-nm passivation layer 150.

[0107] After forming the AlN passivation layer 150, photolithography and etching processes are required to form the required patterns and windows, as Figure 3 shown.

[0108] The main function of the passivation layer 150 is to protect the Micro LED device from damage by the external environment, such as oxidation, moisture, dust, etc., and at the same time improve the light extraction efficiency and performance of the Micro LED.

[0109] Step 14: Form a first conductive layer 161 that covers the upper surface of the second step; form a second conductive layer 162 that covers the upper surface of the fourth step; form a third conductive layer 163 that covers the upper surface of the third P-GaN layer 140.

[0110] Using a physical vapor deposition (PVD) process, deposit a 50-200 nm conductive thin film on the product obtained in step 13. Then, through a dry etching process, remove the excess conductive thin film to form the required first conductive layer 161, second conductive layer 162, and third conductive layer 163. Then, perform an annealing treatment at a temperature between 400-500 °C to eliminate the stress and defects in the conductive thin film and improve the stability and performance of the film layer. As Figure 4 shown.

[0111] Step 15: Set a first N-type sub-electrode 171 that is located on the first step and extends away from the first N-GaN layer 40; set a second N-type sub-electrode 172 that is located on the third step and extends away from the first N-GaN layer 40; set a third N-type sub-electrode 173 that is located on the fifth step and extends away from the first N-GaN layer 40.

[0112] The first N-type sub-electrode 171 is perpendicular to the first step, the second N-type sub-electrode 172 is perpendicular to the third step, and the third N-type sub-electrode 173 is perpendicular to the fifth step. As Figure 5 shown, the electrode material can be a metal or metal alloy such as gold (Au), platinum (Pt), titanium (Ti), etc.

[0113] Step 16: Set a first P-type sub-electrode 181 that covers the first conductive layer 161 and extends away from the first N-GaN layer 40; set a second P-type sub-electrode 182 that covers the second conductive layer 162 and extends away from the first N-GaN layer 40; set a third P-type sub-electrode 183 that covers the third conductive layer 163 and extends away from the first N-GaN layer 40.

[0114] This step is completed in two sub-steps:

[0115] Step 161: Form an electrode thin film layer, as Figure 6aAs shown, an electrode thin film layer with a thickness of 30 - 300 nm is formed on the surface of the product obtained in Step 15 using a vacuum electron beam evaporation device. The excess electrode thin film layer is etched away to form a first P-type sub-electrode thin film layer 1811, a second P-type sub-electrode thin film layer 1821, and a third P-type sub-electrode thin film layer 1831. The material of the electrode thin film layer can be silver (Ag), aluminum (Al), or gold (Au), which have high reflectivity and can form good adhesion with the first conductive layer 161, the second conductive layer 162, and the third conductive layer 163.

[0116] Step 162: Form a P-type sub-electrode extension, as Figure 6b shown. A first P-type sub-electrode extension 1812 perpendicular to the first P-type sub-electrode thin film layer 1811 is provided on the first P-type sub-electrode thin film layer 1811; a second P-type sub-electrode extension 1822 perpendicular to the second P-type sub-electrode thin film layer 1821 is provided on the second P-type sub-electrode thin film layer 1821; a third P-type sub-electrode extension 1832 perpendicular to the third P-type sub-electrode thin film layer 1831 is provided on the third P-type sub-electrode thin film layer 1831.

[0117] The first P-type sub-electrode thin film layer 1811 and the first P-type sub-electrode extension 1812 together constitute the first P-type sub-electrode 181, the second P-type sub-electrode thin film layer 1821 and the second P-type sub-electrode extension 1822 together constitute the second P-type sub-electrode 182, and the third P-type sub-electrode thin film layer 1831 and the third P-type sub-electrode extension 1832 together constitute the third P-type sub-electrode 183.

[0118] Step 17: Form a first bonding layer 190, and the first bonding layer 190 fills the gaps between the first N-type sub-electrode 171, the second N-type sub-electrode 172, the third N-type sub-electrode 173, the first P-type sub-electrode 181, the second P-type sub-electrode 182, the third P-type sub-electrode 183, and the passivation layer 150.

[0119] The first bonding layer 190 with a material of SiO 2 is deposited by plasma enhanced chemical vapor deposition (PECVD) process. The deposition temperature is 300 - 500 °C and it is deposited in the gaps between the first N-type sub-electrode 171, the second N-type sub-electrode 172, the third N-type sub-electrode 173, the first P-type sub-electrode 181, the second P-type sub-electrode 182, the third P-type sub-electrode 183, and the passivation layer 150, as Figure 7 shown.

[0120] Step 18: Planarize the first bonding layer 190.

[0121] Use chemical mechanical polishing (CMP) or other planarization techniques to improve the surface quality of the first bonding layer 190.

[0122] Specifically, to prepare the second component and form a CMOS driving circuit, the following steps are included:

[0123] Step 21: Provide a CMOS driver 210, and form a second bonding layer 220 above the CMOS driver 210.

[0124] As Figures 8 - 9 shown, deposit the second bonding layer 220 by PECVD process, with a deposition temperature of 300 - 500 °C, to form a second bonding layer 220 with a thickness of 0.1 - 1 μm and a material of SiO 2 .

[0125] Step 22: Etch the second bonding layer 220 along the thickness direction of the second bonding layer 220 to form six vias 230 penetrating through the second bonding layer 220.

[0126] Coat a photoresist on the upper surface of the second bonding layer 220, and use a mask for exposure and development to form a pattern to be etched. Use ion etching technology to etch the second bonding layer 220 according to the photolithography pattern to form six vias 230 penetrating through the second bonding layer 220, as Figure 10 shown.

[0127] Step 23: Place a first N-type contact electrode 171', a second N-type contact electrode 172', a third N-type contact electrode 173', a first P-type contact electrode 181', a second P-type contact electrode 182', and a third P-type contact electrode 183' in the vias 230 respectively. As Figure 11 shown.

[0128] Specifically, to bond the first component and the second component, the following steps are included:

[0129] Step 31: Horizontally transpose the second component, align and bond the first N-type sub-electrode 171 with the first N-type contact electrode 171', the second N-type sub-electrode 172 with the second N-type contact electrode 172', the third N-type sub-electrode 173 with the third N-type contact electrode 173', the first P-type sub-electrode 181 with the first P-type contact electrode 181', the second P-type sub-electrode 182 with the second P-type contact electrode 182', and the third P-type sub-electrode 183 with the third P-type contact electrode 183' respectively, and form a first N electrode, a second N electrode, a third N electrode, a first P-type reflective electrode, a second P-type reflective electrode, and a third P-type reflective electrode respectively.

[0130] Using an alignment device, such as a microscope, a laser alignment system, etc., align the first N-type sub-electrodes 171 on the first bonding layer 190 and the second bonding layer 220 with the first N-type contact electrodes 171', the second N-type sub-electrodes 172 with the second N-type contact electrodes 172', the third N-type sub-electrodes 173 with the third N-type contact electrodes 173', the first P-type sub-electrodes 181 with the first P-type contact electrodes 181', the second P-type sub-electrodes 182 with the second P-type contact electrodes 182', and the third P-type sub-electrodes 183 with the third P-type contact electrodes 183'. Bond the first component and the second component at a low temperature below 350 °C, such as Figure 12 as shown

[0131] Step 32, remove the silicon substrate 10, the nucleation layer 20, and the buffer layer 30 to obtain the full-color Micro LED display device

[0132] Adopt a chemical solution or a physical method, such as laser lift-off, mechanical lift-off, etc., to remove the silicon substrate 10. When removing the silicon substrate 10, the nucleation layer 20 and the buffer layer 30 will also be removed together to obtain a full-color Micro LED display device, such as Figure 13 as shown

[0133] Devices with three emission wavelengths of blue light, green light, and red light can be controlled separately, enabling a display with a larger color gamut. The light of the three emitted wavelengths exits from the first N-GaN layer 40. The emitted red light is not absorbed by the green light and blue light emitting layers, and the emitted green light is not absorbed by the blue light emitting layer, achieving a high light extraction efficiency. The pixel size of the display unit is 1 μm - 500 μm

[0134] Example 1

[0135] A method for preparing a full-color Micro LED display device includes the following steps

[0136] Prepare the first component. The preparation of the epitaxial structure can be completed using a MOCVD epitaxial growth device. The steps are as follows

[0137] Step 11, provide a silicon substrate 10, and sequentially epitaxially grow a nucleation layer 20, a buffer layer 30, a first N-GaN layer 40, a blue light LED emitting layer 50, a first P-GaN layer 60, a first insulating layer 70, a second N-GaN layer 80, a green light LED emitting layer 90, a second P-GaN layer 100, a second insulating layer 110, a third N-GaN layer 120, a red light LED emitting layer 130, and a third P-GaN layer 140 on the surface of the silicon substrate 10, such as Figure 1 as shown

[0138] Specifically, at a temperature of 1100 °C and a pressure of 50 torr, a 200-nm AlN nucleation layer 20 is grown on the substrate 10.

[0139] At a temperature of 1180 °C and a pressure of 75 torr, a 1-μm AlGaN buffer layer 30 is grown on the nucleation layer 20.

[0140] At a temperature of 1150 °C and a pressure of 200 torr, a 0.5-μm first N-GaN layer 40 is grown on the buffer layer 30.

[0141] At a temperature of 780 °C and a pressure of 400 torr, a 90-nm blue LED multi-quantum well light-emitting layer 50 is grown on the first N-GaN layer 40.

[0142] At a temperature of 950 °C and a pressure of 200 torr, a 50-nm first P-GaN layer 60 is grown on the blue LED light-emitting layer 50.

[0143] At a temperature of 900 °C and a pressure of 100 torr, a 10-nm first insulating layer 70 is grown on the first P-GaN layer 60. The material of the first insulating layer 70 is undoped Al 0.3 Ga 0.7 N.

[0144] At a temperature of 1150 °C and a pressure of 200 torr, a 0.5-μm second N-GaN layer 80 is grown on the first insulating layer 70.

[0145] At a temperature of 762 °C and a pressure of 400 torr, a 90-nm green LED light-emitting layer 90 is grown on the second N-GaN layer 80.

[0146] At a temperature of 950 °C and a pressure of 200 torr, a 50-nm second P-GaN layer 100 is grown on the green LED light-emitting layer 90.

[0147] At a temperature of 900 °C and a pressure of 100 torr, a 10-nm second insulating layer 110 is grown on the second P-GaN layer 100. The material of the second insulating layer 110 is undoped Al 0.3 Ga 0.7 N.

[0148] At a temperature of 1150 °C and a pressure of 200 torr, a 0.5-μm third N-GaN layer 120 is grown on the second insulating layer 110.

[0149] The 90 nm red light LED light emitting layer 130 is grown on the third N-GaN layer 120 under the temperature condition of 722 °C and the pressure condition of 400 torr.

[0150] The 50 nm third P-GaN layer 140 is grown on the red light LED light emitting layer 130 under the temperature condition of 950 °C and the pressure condition of 200 torr.

[0151] Step 12, forming steps, including the first etching, etching a part of each layer on the first N-GaN layer 40 and a part of the first N-GaN layer 40 along the thickness direction of the first component, and forming a first step on the side of the first N-GaN layer 40; the second etching, etching a part of each layer on the first P-GaN layer 60 and a part of the first P-GaN layer 60 along the thickness direction of the first component, and forming a second step on the side of the first P-GaN layer 60; the third etching, etching a part of each layer on the second N-GaN layer 80 and a part of the second N-GaN layer 80 along the thickness direction of the first component, and forming a third step on the side of the second N-GaN layer 80; the fourth etching, etching a part of each layer on the second P-GaN layer 100 and a part of the second P-GaN layer 100 along the thickness direction of the first component, and forming a fourth step on the side of the second P-GaN layer 100; the fifth etching, etching a part of each layer on the third N-GaN layer 120 and a part of the third N-GaN layer 120 along the thickness direction of the first component, and forming a fifth step on the side of the third N-GaN layer 120.

[0152] A photoresist is coated on the product obtained in step 11, and exposure and development are carried out using a mask template to form a pattern to be etched. The epitaxial layer is etched according to the photolithographic pattern using ion etching technology to remove unnecessary parts, and etching is carried out until the first N-GaN layer 40, and a first step is formed on the side of the first N-GaN layer 40. The etched thickness of the first N-GaN layer 40 is less than the thickness of the first N-GaN layer 40. The same steps are used to etch and form the second to fifth steps, and shallow etching is used when etching and forming the second and fourth steps. The etching is completed, as Figure 2 shown.

[0153] After the sidewalls are formed by etching, P-type activation is carried out in an N 2 atmosphere at a high temperature of 650 °C. The formation of the sidewalls is conducive to the diffusion of H atoms from the sidewalls, thereby activating Mg doping.

[0154] Step 13, form a passivation layer 150 that covers the sidewalls of the first N-GaN layer 40, the blue LED light-emitting layer 50, the first P-GaN layer 60, the first insulating layer 70, the second N-GaN layer 80, the green LED light-emitting layer 90, the second P-GaN layer 100, the second insulating layer 110, the third N-GaN layer 120, the red LED light-emitting layer 130, and the third P-GaN layer 140.

[0155] The CVD method uses an aluminum source, nitrogen gas (N 2 ) and ammonia gas (NH 3 ) as reaction gases, with a deposition temperature of 950 °C, an aluminum source gas flow rate of 120 sccm, a nitrogen gas (N 2 ) gas flow rate of 20,000 sccm, an ammonia gas (NH 3 ) gas flow rate of 300 sccm, a reaction time of 5 min, etc. to obtain a uniform and dense 50-nm passivation layer 150. Then, photolithography and etching processes are carried out to form the required patterns and windows, as Figure 3 shown.

[0156] Step 14, form a first conductive layer 161 that covers the upper surface of the second step; form a second conductive layer 162 that covers the upper surface of the fourth step; form a third conductive layer 163 that covers the upper surface of the third P-GaN layer 140.

[0157] Using a physical vapor deposition (PVD) process, deposit a 60-nm conductive thin film on the product obtained in Step 13. Then, through a dry etching process, remove the excess conductive thin film to form the required first conductive layer 161, second conductive layer 162, and third conductive layer 163. Then, perform an annealing treatment at 450 °C to eliminate the stress and defects in the conductive thin film and improve the stability and performance of the film layer. As Figure 4 shown.

[0158] Step 15, set a first N-type sub-electrode 171 that is located on the first step and extends away from the first N-GaN layer 40; set a second N-type sub-electrode 172 that is located on the third step and extends away from the first N-GaN layer 40; set a third N-type sub-electrode 173 that is located on the fifth step and extends away from the first N-GaN layer 40.

[0159] The first N-type sub-electrode 171 is perpendicular to the first step, the second N-type sub-electrode 172 is perpendicular to the third step, and the third N-type sub-electrode 173 is perpendicular to the fifth step, as Figure 5 shown. Among them, the electrode material is titanium (Ti).

[0160] Step 16: Set the first P-type sub-electrode 181, where the first P-type sub-electrode 181 covers the first conductive layer 161 and extends away from the first N-GaN layer 40; set the second P-type sub-electrode 182, where the second P-type sub-electrode 182 covers the second conductive layer 162 and extends away from the first N-GaN layer 40; set the third P-type sub-electrode 183, where the third P-type sub-electrode 183 covers the third conductive layer 163 and extends away from the first N-GaN layer 40.

[0161] This step is completed in two sub-steps:

[0162] Step 161: Form an electrode thin film layer, as Figure 6a shown. Use a vacuum electron beam evaporation device to form an electrode thin film layer with a thickness of 60 nm on the surface of the product obtained in step 15. Etch away the excess electrode thin film layer to form the first P-type sub-electrode thin film layer 1811, the second P-type sub-electrode thin film layer 1821, and the third P-type sub-electrode thin film layer 1831. The material of the electrode thin film layer is aluminum (Al).

[0163] Step 162: Form P-type sub-electrode extension parts, as Figure 6b shown. Set a first P-type sub-electrode extension part 1812 perpendicular to the first P-type sub-electrode thin film layer 1811 on the first P-type sub-electrode thin film layer 1811; set a second P-type sub-electrode extension part 1822 perpendicular to the second P-type sub-electrode thin film layer 1821 on the second P-type sub-electrode thin film layer 1821; set a third P-type sub-electrode extension part 1832 perpendicular to the third P-type sub-electrode thin film layer 1831 on the third P-type sub-electrode thin film layer 1831.

[0164] The first P-type sub-electrode thin film layer 1811 and the first P-type sub-electrode extension part 1812 together constitute the first P-type sub-electrode 181, the second P-type sub-electrode thin film layer 1821 and the second P-type sub-electrode extension part 1822 together constitute the second P-type sub-electrode 182, and the third P-type sub-electrode thin film layer 1831 and the third P-type sub-electrode extension part 1832 together constitute the third P-type sub-electrode 183.

[0165] Step 17: Form a first bonding layer 190, where the first bonding layer 190 fills the gaps between the first N-type sub-electrode 171, the second N-type sub-electrode 172, the third N-type sub-electrode 173, the first P-type sub-electrode 181, the second P-type sub-electrode 182, the third P-type sub-electrode 183, and the passivation layer 150.

[0166] Deposit a material of SiO by plasma enhanced chemical vapor deposition (PECVD) process 2The first bonding layer 190, with a deposition temperature of 350 °C, is deposited in the gaps between the first N-type sub-electrode 171, the second N-type sub-electrode 172, the third N-type sub-electrode 173, the first P-type sub-electrode 181, the second P-type sub-electrode 182, the third P-type sub-electrode 183, and the passivation layer 150, as Figure 7 shown.

[0167] Step 18, planarize the first bonding layer 190.

[0168] Use chemical mechanical polishing (CMP) planarization technology to improve the surface quality of the first bonding layer 190.

[0169] Prepare the second component, and form a CMOS drive circuit, including the following steps:

[0170] Step 21, provide a CMOS driver 210, and form a second bonding layer 220 above the CMOS driver 210.

[0171] As Figures 8 - 9 shown, the second bonding layer 220 is deposited by PECVD process, with a deposition temperature of 350 °C, to form a second bonding layer 220 with a thickness of 0.5 μm and a material of SiO 2 2.

[0172] Step 22, etch the second bonding layer 220 along the thickness direction of the second bonding layer 220 to form six vias 230 penetrating through the second bonding layer 220.

[0173] Coat a photoresist on the upper surface of the second bonding layer 220, and use a mask for exposure and development to form a pattern to be etched. Use ion etching technology to etch the second bonding layer 220 according to the photolithography pattern to form six vias 230 penetrating through the second bonding layer 220, as Figure 10 shown.

[0174] Step 23, place the first N-type contact electrode 171', the second N-type contact electrode 172', the third N-type contact electrode 173', the first P-type contact electrode 181', the second P-type contact electrode 182', and the third P-type contact electrode 183' in the vias 230 respectively. As Figure 11 shown.

[0175] Specifically, bonding the first component and the second component includes the following steps:

[0176] Step 31: Horizontally transpose the second component, align and bond the first N-type sub-electrode 171 with the first N-type contact electrode 171', the second N-type sub-electrode 172 with the second N-type contact electrode 172', the third N-type sub-electrode 173 with the third N-type contact electrode 173', the first P-type sub-electrode 181 with the first P-type contact electrode 181', the second P-type sub-electrode 182 with the second P-type contact electrode 182', and the third P-type sub-electrode 183 with the third P-type contact electrode 183' respectively, and form the first N electrode, the second N electrode, the third N electrode, the first P-type reflective electrode, the second P-type reflective electrode, and the third P-type reflective electrode respectively.

[0177] Use a microscope to align the first N-type sub-electrode 171 and the first N-type contact electrode 171', the second N-type sub-electrode 172 and the second N-type contact electrode 172', the third N-type sub-electrode 173 and the third N-type contact electrode 173', the first P-type sub-electrode 181 and the first P-type contact electrode 181', the second P-type sub-electrode 182 and the second P-type contact electrode 182', and the third P-type sub-electrode 183 and the third P-type contact electrode 183' on the first bonding layer 190 and the second bonding layer 220. Bond the first component and the second component at a low temperature below 350 °C, as Figure 12 shown.

[0178] Step 32: Remove the silicon substrate 10, the nucleation layer 20, and the buffer layer 30 to obtain the full-color Micro LED display device.

[0179] Use a chemical solution to remove the silicon substrate 10. When removing the silicon substrate 10, the nucleation layer 20 and the buffer layer 30 will also be removed together to obtain the full-color Micro LED display device, as Figure 13 shown.

[0180] Example 2

[0181] Other steps of this example are the same as those of Example 1. The difference is that at a temperature of 900 °C and a pressure of 100 torr, a first insulating layer 70 with a total thickness of 180 nm is grown on the first P-GaN layer 60, and the number of growth layers is 3. The structure of the first insulating layer 70 is Al 0.2 Ga 0.8 N: 20 nm / Al 0.15 Ga 0.85 N: 20 nm / Al 0.1 Ga 0.9 N: 20 nm. At a temperature of 900 °C and a pressure of 100 torr, a second insulating layer 110 with a total thickness of 180 nm is grown on the second P-GaN layer 100, and the number of growth layers is 3. The structure of the second insulating layer 110 is Al 0.2 Ga0.8 N: 20 nm / Al 0.15 Ga 0.85 N: 20 nm / Al 0.1 Ga 0.9 N: 20 nm, with 3 growth layers.

[0182] Example 3

[0183] This example is the same as Example 1 in other steps. The difference is that at a temperature of 900 °C and a pressure of 100 torr, a first insulating layer 70 with a total thickness of 180 nm is grown on the first P-GaN layer 60. The growth layer number is 3 layers, and the structure of the first insulating layer 70 is Al 0.15 Ga 0.85 N: 20 nm / Al 0.1 Ga 0.9 N: 20 nm / Al 0.05 Ga 0.95 N: 20 nm. At a temperature of 900 °C and a pressure of 100 torr, a second insulating layer 110 with a total thickness of 180 nm is grown on the second P-GaN layer 100. The growth layer number is 3 layers, and the structure of the second insulating layer 110 is Al 0.15 Ga 0.85 N: 20 nm / Al 0.1 Ga 0.9 N: 20 nm / Al 0.05 Ga 0.95 N: 20 nm, with 3 growth layers.

[0184] Example 4

[0185] This example is the same as Example 1 in other steps. The difference is that at a temperature of 900 °C and a pressure of 100 torr, a first insulating layer 70 with a total thickness of 250 nm is grown on the first P-GaN layer 60. The structure of the first insulating layer 70 is (AlN: 5 nm / Al 0.2 Ga 0.8 N: 20 nm) x 10 superlattice. At a temperature of 900 °C and a pressure of 100 torr, a 250-nm second insulating layer 110 is grown on the second P-GaN layer 100. The structure of the second insulating layer 110 is (AlN: 5 nm / Al 0.2 Ga 0.8 N: 20 nm) x 10 superlattice.

[0186] Example 5

[0187] This embodiment is the same as the other steps of Embodiment 1, except that at a temperature of 900 °C and a pressure of 100 torr, a first insulating layer 70 with a total thickness of 250 nm is grown on the first P-GaN layer 60. The structure of the first insulating layer 70 is (AlN: 5 nm / Al 0.15 Ga 0.85 N: 20 nm) x 10 superlattice. At a temperature of 900 °C and a pressure of 100 torr, a second insulating layer 110 with a thickness of 250 nm is grown on the second P-GaN layer 100. The structure of the second insulating layer 110 is (AlN: 5 nm / Al 0.15 Ga 0.85 N: 20 nm) x 10 superlattice.

[0188] Embodiment 6

[0189] This embodiment is the same as the other steps of Embodiment 1, except that at a temperature of 900 °C and a pressure of 100 torr, a first insulating layer 70 with a total thickness of 250 nm is grown on the first P-GaN layer 60. The structure of the first insulating layer 70 is (AlN: 5 nm / Al 0.1 Ga 0.9 N: 20 nm) x 10 superlattice. At a temperature of 900 °C and a pressure of 100 torr, a second insulating layer 110 with a thickness of 250 nm is grown on the second P-GaN layer 100. The structure of the second insulating layer 110 is (AlN: 5 nm / Al 0.1 Ga 0.9 N: 20 nm) x 10 superlattice.

[0190] The in-chip emission wavelength uniformity STD variance and warpage Wrap / Bow of the full-color Micro LED display devices of Embodiments 1-6 are respectively tested. The results are shown in Table 1:

[0191] Table 1

[0192]

[0193]

[0194] It can be seen from the data in Table 1 that the material and Al component of the first insulating layer 70 and the second insulating layer 110 will significantly affect the in-chip emission wavelength uniformity STD variance and warpage Wrap / Bow of the full-color Micro LED display device. In Embodiments 1, 2, and 4, the materials of the first insulating layer 70 and the second insulating layer 110 change from single-layer Al 0.3 Ga 0.7 N to three-layer Al 0.2 Ga 0.8 N / Al 0.15 Ga0.85 N / Al 0.1 Ga 0.9 N, and then to 10 groups of AlN / Al 0.2 Ga 0.8 N. The overall STD variance of the uniformity of the in-chip emission wavelength gradually decreases, the adjustment effect on warping gradually improves, and the warping value becomes smaller; from Examples 2 and 3 and Examples 4 - 6, it can be seen that the Al component of the first insulating layer 70 and the second insulating layer 110 gradually becomes smaller, and compressive stress or tensile stress will be generated during the process of becoming smaller, thereby making the warping value of the display unit smaller and greatly reducing the risk of wafer cracking. The embodiments of the present invention further illustrate that when reducing the etching complexity, using an insulating layer can also achieve the effect of reducing the warping value of the full-color Micro LED display unit.

[0195] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention without departing from the principles and purposes of the present invention. All such changes should fall within the protection scope of the claims of the present invention.

Claims

1. A full-color Micro LED display device, characterized in that: It comprises several groups of display units, wherein the display units include: A first N-GaN layer, wherein a side edge of the first N-GaN layer has a first step; A blue LED light-emitting layer covering the upper surface of the non-step region of the first N-GaN layer; A first P-GaN layer covers the upper surface of the blue LED light-emitting layer, and a side edge of the first P-GaN layer has a second step; a first insulating layer, covering an upper surface of the first P-GaN layer in a non-step region; a second N-GaN layer covering an upper surface of the first insulating layer, wherein a side edge of the second N-GaN layer has a third step; A green LED light-emitting layer covering the upper surface of the second N-GaN layer in the non-step region; A second P-GaN layer covers the upper surface of the green LED light-emitting layer, and a side edge of the second P-GaN layer has a fourth step; a second insulating layer, covering an upper surface of the second P-GaN layer in a non-step region; a third N-GaN layer, covering an upper surface of the second insulating layer, wherein a side edge of the third N-GaN layer has a fifth step; A red LED light-emitting layer covering the upper surface of the non-step region of the third N-GaN layer; A third P-GaN layer, covering the upper surface of the red LED light-emitting layer; A passivation layer covering the first N-GaN layer, the blue LED light-emitting layer, the first P-GaN layer, the first insulating layer, the second N-GaN layer, the green LED light-emitting layer, the second P-GaN layer, the second insulating layer, the third N-GaN layer, the red LED light-emitting layer, and the sidewalls of the third P-GaN layer; a first conductive layer, covering an upper surface of the second step; a second conductive layer, covering an upper surface of the fourth step; a third conductive layer, covering an upper surface of the third P-GaN layer; A first N-electrode, located on the first step and extending back toward the first N-GaN layer; a second N-electrode, located on the third step and extending back toward the first N-GaN layer; a third N-electrode, located on the fifth step and extending back toward the first N-GaN layer; a first P-type reflective electrode, covering the first conductive layer and extending back toward the first N-GaN layer; a second P-type reflective electrode, covering the second conductive layer and extending back toward the first N-GaN layer; a third P-type reflective electrode, covering the third conductive layer and extending back toward the first N-GaN layer; The upper surfaces of the first N-electrode, the second N-electrode, the third N-electrode, the first P-type reflective electrode, the second P-type reflective electrode, and the third P-type reflective electrode are flush with each other; a bonding layer, filling the gaps between the first N electrode, the second N electrode, the third N electrode, the first P-type reflective electrode, the second P-type reflective electrode, the third P-type reflective electrode, and the passivation layer, and covering the first N electrode, the second N electrode, the third N electrode, the first P-type reflective electrode, the second P-type reflective electrode, the third P-type reflective electrode, and the passivation layer; A CMOS driver covers the upper surface of the bonding layer and is electrically connected to the first N-electrode, the second N-electrode, the third N-electrode, the first P-type reflective electrode, the second P-type reflective electrode, and the third P-type reflective electrode.

2. The full-color Micro LED display device according to claim 1, characterized in that: The bonding layer includes a first bonding layer and a second bonding layer stacked from bottom to top; The parts of the first N-electrode, the second N-electrode, the third N-electrode, the first P-type reflective electrode, the second P-type reflective electrode, and the third P-type reflective electrode located in the second bonding layer are respectively the first N-type contact electrode, the second N-type contact electrode, the third N-type contact electrode, the first P-type contact electrode, the second P-type contact electrode, and the third P-type contact electrode.

3. The full-color Micro LED display device according to claim 1, characterized in that: The first insulating layer is non-doped AlGaN; and / or The second insulating layer is non-doped AlGaN.

4. The full-color Micro LED display device according to claim 1, characterized in that: The first insulating layer is two or more layers of Al x1 Ga 1-x1 N, where 0<x1≤1, the Al composition x1 of different AlGaN sublayers is not equal; and / or The second insulating layer is two or more layers of Al x2 Ga 1-x2 N, where 0<x2≤1, and the Al components x2 of different AlGaN sublayers are not equal.

5. The full-color Micro LED display device according to claim 1, characterized in that: The first insulating layer is Al x1 Ga 1-x1 N / A y1 Ga 1-y1 N superlattice structure, wherein 0<x1≤1, 0<y1≤1, x1≠y1; and / or The second insulating layer is Al x2 Ga 1-x2 N / A y2 Ga 1-y2 N superlattice structure, where 0<x2≤1, 0<y2≤1, x2≠y2.

6. The full-color Micro LED display device according to claim 5, characterized in that: The first insulating layer superlattice structure consists of 2-20 groups with a total thickness of 30-500 nm; the second insulating layer superlattice structure consists of 2-20 groups with a total thickness of 30-500 nm.

7. The full-color Micro LED display device according to claim 1, characterized in that: The pixel size of the display unit is 1 μm-500 μm.

8. The method for preparing a full-color Micro LED display device according to claim 1, characterized in that: The following steps are involved: Forming a first component comprises the following steps: Step 11, providing a silicon substrate, and epitaxially growing a nucleation layer, a buffer layer, a first N-GaN layer, a blue LED light-emitting layer, a first P-GaN layer, a first insulating layer, a second N-GaN layer, a green LED light-emitting layer, a second P-GaN layer, a second insulating layer, a third N-GaN layer, a red LED light-emitting layer, and a third P-GaN layer in sequence on the surface of the silicon substrate; Step 12, forming a step, includes: A first etching step is performed to etch a portion of each layer on the first N-GaN layer and a portion of the first N-GaN layer along a thickness direction of the first component to form a first step on a side of the first N-GaN layer; A second etching step is performed to etch a portion of each layer on the first P-GaN layer and a portion of the first P-GaN layer along the thickness direction of the first component to form a second step on the side of the first P-GaN layer; A third etching step is performed to etch a portion of each layer on the second N-GaN layer and a portion of the second N-GaN layer along the thickness direction of the first component to form a third step on the side of the second N-GaN layer; A fourth etching step is performed to etch a portion of each layer on the second P-GaN layer and a portion of the second P-GaN layer along the thickness direction of the first component to form a fourth step on the side of the second P-GaN layer; A fifth etching step is performed to etch a portion of each layer on the third N-GaN layer and a portion of the third N-GaN layer along the thickness direction of the first component to form a fifth step on the side of the third N-GaN layer; Step 13, forming a passivation layer, wherein the passivation layer covers the side walls of the first N-GaN layer, the blue LED light-emitting layer, the first P-GaN layer, the first insulating layer, the second N-GaN layer, the green LED light-emitting layer, the second P-GaN layer, the second insulating layer, the third N-GaN layer, the red LED light-emitting layer, and the third P-GaN layer; Step 14, forming a first conductive layer, the first conductive layer covers the upper surface of the second step; forming a second conductive layer, the second conductive layer covers the upper surface of the fourth step; forming a third conductive layer, the third conductive layer covers the upper surface of the third P-GaN layer; Step 15, providing a first N-type sub-electrode, the first N-type sub-electrode is located on the first step and extends back to the first N-GaN layer; providing a second N-type sub-electrode, the second N-type sub-electrode is located on the third step and extends back to the first N-GaN layer; providing a third N-type sub-electrode, the third N-type sub-electrode is located on the fifth step and extends back to the first N-GaN layer; Step 16, providing a first P-type sub-electrode, wherein the first P-type sub-electrode covers the first conductive layer and extends back to the first N-GaN layer; providing a second P-type sub-electrode, wherein the second P-type sub-electrode covers the second conductive layer and extends back to the first N-GaN layer; providing a third P-type sub-electrode, wherein the third P-type sub-electrode covers the third conductive layer and extends back to the first N-GaN layer; Step 17, forming a first bonding layer, wherein the first bonding layer fills the gaps between the first N-type sub-electrode, the second N-type sub-electrode, the third N-type sub-electrode, the first P-type sub-electrode, the second P-type sub-electrode, the third P-type sub-electrode, and the passivation layer; Step 18, planarizing the first bonding layer; Forming the second component comprises the following steps: Step 21, providing a CMOS driver, and forming a second bonding layer above the CMOS driver; Step 22, etching the second bonding layer along the thickness direction of the second bonding layer to form six through holes penetrating the second bonding layer; Step 23, placing a first N-type contact electrode, a second N-type contact electrode, a third N-type contact electrode, a first P-type contact electrode, a second P-type contact electrode, and a third P-type contact electrode in the through hole respectively; Bonding the first component and the second component comprises the following steps: Step 31, horizontally transposing the second component, aligning and bonding the first N-type sub-electrode with the first N-type contact electrode, the second N-type sub-electrode with the second N-type contact electrode, the third N-type sub-electrode with the third N-type contact electrode, the first P-type sub-electrode with the first P-type contact electrode, the second P-type sub-electrode with the second P-type contact electrode, and the third P-type sub-electrode with the third P-type contact electrode, and respectively forming a first N-electrode, a second N-electrode, a third N-electrode, a first P-type reflective electrode, a second P-type reflective electrode, and a third P-type reflective electrode; Step 32, removing the silicon substrate, the nucleation layer, and the buffer layer to obtain the full-color Micro LED display device.

9. The method for preparing a full-color Micro LED display device according to claim 8, characterized in that: After step 12, the first component is further activated by P-type Mg doping, with a doping concentration of >5E18cm -3 .

10. The method for preparing a full-color Micro LED display device according to claim 8, characterized in that: The step 16 comprises: Step 161, providing a first P-type sub-electrode thin film layer covering the first conductive layer, a second P-type sub-electrode thin film layer covering the second conductive layer, and a third P-type sub-electrode thin film layer covering the third conductive layer; Step 162, providing a first P-type sub-electrode extension portion perpendicular to the first P-type sub-electrode thin layer on the first P-type sub-electrode thin layer, providing a second P-type sub-electrode extension portion perpendicular to the second P-type sub-electrode thin layer on the second P-type sub-electrode thin layer, and providing a third P-type sub-electrode extension portion perpendicular to the third P-type sub-electrode thin layer on the third P-type sub-electrode thin layer; The first P-type sub-electrode thin film layer and the first P-type sub-electrode extension portion together constitute a first P-type sub-electrode, the second P-type sub-electrode thin film layer and the second P-type sub-electrode extension portion together constitute a second P-type sub-electrode, and the third P-type sub-electrode thin film layer and the third P-type sub-electrode extension portion together constitute a third P-type sub-electrode.

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