Display panel

Abstract

The invention discloses a display panel, and the display panel comprises a plurality of laminated structures, and each laminated structure comprises a light-emitting device and a pixel electrode which are stacked in a first direction; the common electrode layer is positioned on one side, far away from the pixel electrode, of the plurality of laminated structures; the reflecting layer at least covers a part of area of the side surface of the laminated structure and a part of area of the first surface, and the first surface is the surface, away from the corresponding light-emitting device, of the pixel electrode; the reflecting layer is provided with a plurality of first through holes in one-to-one correspondence with the plurality of laminated structures, and the first through holes are exposed out of the other part of area of the first surface; the silicon-based back plate is positioned on one side, far away from the pixel electrode, of the reflecting layer; the silicon-based backboard comprises a plurality of driving circuits which are in one-to-one correspondence with the plurality of laminated structures; and the connecting structures are connected with the pixel electrodes and the driving circuit through the first through holes.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a display panel. Background Art

[0002] In recent years, silicon-based light-emitting diode (LED) micro-displays are often applied in the field of near-eye display virtual reality (VR) / augmented reality (AR).

[0003] Due to the characteristic that the LED itself has the ability to withstand large currents, the silicon-based LED technical solution is also known as the ultimate solution in the field of micro-displays.

[0004] However, as the LED gradually transitions to micro-display, the size of the LED becomes smaller and smaller, and correspondingly its light efficiency also becomes smaller, which directly affects the light extraction efficiency of the silicon-based LED micro-display.

[0005] In view of this, how to improve the light extraction efficiency of the silicon-based LED micro-display has become a technical problem to be solved urgently. Summary of the Invention

[0006] Embodiments of the present invention provide a display panel to solve the technical problem that the light extraction efficiency of the silicon-based LED micro-display in the prior art is not high.

[0007] In a first aspect, to solve the above technical problem, embodiments of the present invention provide a display panel, including:

[0008] A plurality of stacked structures, where the stacked structure includes a light-emitting device and a pixel electrode stacked along a first direction;

[0009] A common electrode layer located on a side of the plurality of stacked structures away from the pixel electrode;

[0010] A reflective layer covering at least a part of the side surface and a part of the first surface of the stacked structure, where the first surface is the surface of the pixel electrode away from the corresponding light-emitting device; the reflective layer has a plurality of first through-holes corresponding to the plurality of stacked structures one by one, and the first through-holes expose another part of the first surface;

[0011] A silicon-based backplane located on a side of the reflective layer away from the pixel electrode; the silicon-based backplane includes a plurality of driving circuits corresponding to the plurality of stacked structures one by one;

[0012] A plurality of connection structures, where the connection structures connect the pixel electrode and the driving circuit through the first through-holes.

[0013] A possible implementation manner, in which the cross-sectional pattern of the stacked structure in a plane perpendicular to the silicon-based backplane is an inverted trapezoid, and there is a first spacer region between any two adjacent stacked structures, and the reflective layer also covers the first spacer region.

[0014] A possible implementation manner, in which the display panel further includes:

[0015] A protective layer located between the reflective layer and the plurality of stacked structures; the shape of the protective layer is the same as that of the reflective layer, the protective layer includes a second through hole corresponding to the first through hole, the orthographic projection of the second through hole on the reflective layer is located within the first through hole, and there is a gap between the edge of the second through hole and the edge of the first through hole, and a part of the connection structure is filled in the second through hole.

[0016] A possible implementation manner, in which the reflective layer is a distributed Bragg reflector.

[0017] A possible implementation manner, in which the material of the reflective layer includes metal.

[0018] A possible implementation manner, in which the cross-sectional pattern of the stacked structure in a plane perpendicular to the silicon-based backplane is a regular trapezoid, and the light-emitting device includes a second semiconductor layer, an active layer, and a first semiconductor layer stacked along the first direction, and the reflective layer includes:

[0019] A first sub-reflective layer covering a part of the region of the first surface, and the plurality of first through holes are located in the first sub-reflective layer; a second sub-reflective layer located on the side of the plurality of stacked structures away from the silicon-based backplane; the second sub-reflective layer covers at least the side surfaces of the active layer and the first semiconductor layer, and the second spacer regions between any two adjacent pixel electrodes.

[0020] A possible implementation manner, in which the second sub-reflective layer also covers a part of the region of the second surface, the second surface is the surface of the stacked structure close to the common electrode layer, the second sub-reflective layer includes a first opening, and the first opening exposes another part of the region of the second surface, and the common electrode layer is connected to the stacked structure through the first opening.

[0021] A possible implementation manner, in which the display panel further includes:

[0022] A protective layer located between the second sub-reflective layer and the stacked structures; the protective layer covers at least the side surfaces of the stacked structures.

[0023] A possible implementation manner, in which the protective layer also covers the second spacer regions.

[0024] A possible implementation, the display panel further includes:

[0025] An auxiliary electrode layer, located on a side of the common electrode layer away from the silicon-based backplane;

[0026] The second sub-reflection layer is reused as the auxiliary electrode layer.

[0027] A possible implementation, the second sub-reflection layer is located on a side of the common electrode layer close to the stacked structure, and the second sub-reflection layer is made of a metal material.

[0028] A possible implementation, the display panel further includes:

[0029] An auxiliary electrode layer, located on a side of the common electrode layer away from the silicon-based backplane;

[0030] The auxiliary electrode layer has a plurality of third openings penetrating through the auxiliary electrode layer, and the plurality of third openings correspond to the plurality of stacked structures one by one; a positive projection of the third opening on the silicon-based backplane is located within a positive projection of the corresponding stacked structure on the silicon-based backplane.

[0031] A possible implementation, the display panel further includes:

[0032] A plurality of light extraction structures, located on a side of the common electrode layer away from the silicon-based backplane; the plurality of light extraction structures correspond to the plurality of stacked structures one by one, and the light extraction structure covers the corresponding stacked structure. Description of the Drawings

[0033] Figure 1 A schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0034] Figure 2 A schematic structural diagram of a silicon-based backplane provided by an embodiment of the present invention;

[0035] Figure 3 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0036] Figure 4 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0037] Figure 5 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0038] Figure 6 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0039] Figure 7Schematic diagram of another display panel provided by an embodiment of the present invention;

[0040] Figure 8 Schematic diagram of another display panel provided by an embodiment of the present invention;

[0041] Figure 9 Schematic diagram of another display panel provided by an embodiment of the present invention;

[0042] Figure 10 Schematic diagram of another display panel provided by an embodiment of the present invention;

[0043] Figure 11 Schematic diagram of another display panel provided by an embodiment of the present invention;

[0044] Figures 12 - 14 Schematic diagram of another display panel provided by an embodiment of the present invention;

[0045] Figure 15 Partial top view of a display panel provided by an embodiment of the present invention;

[0046] Figure 16 and Figure 17 Schematic diagram of the fabrication of a display panel provided by an embodiment of the present invention;

[0047] Figure 18 A fabrication provided by an embodiment of the present invention Figure 15 Schematic diagram of the display substrate in;

[0048] Figure 19 Schematic diagram of a substrate structure provided by an embodiment of the present invention;

[0049] Figure 20 Schematic diagram of a patterned original stack provided by an embodiment of the present invention;

[0050] Figure 21 Schematic diagram of the formation of a bonding layer provided by an embodiment of the present invention;

[0051] Figure 22 Schematic diagram of another formation of a display substrate provided by an embodiment of the present invention;

[0052] Figure 23 Schematic diagram of the formation of a reflective layer provided by an embodiment of the present invention;

[0053] Figure 24 Schematic diagram of the formation of an auxiliary electrode layer provided by an embodiment of the present invention;

[0054] Figure 25 Schematic diagram of the formation of a light extraction structure provided by an embodiment of the present invention.

[0055] Reference numerals:

[0056] Stacked structure 1, light-emitting device 11, pixel electrode 12, first surface 12a, common electrode layer 3, reflective layer 4, first via hole H1, connection structure 5, first sub-connection structure 51, second sub-connection structure 52, inner layer structure 51', outer layer structure 52', silicon-based backplane 6, first semiconductor layer 111, active layer 112, second semiconductor layer 113, protective layer 7, first sub-protective layer 71, second sub-protective layer 72, auxiliary electrode layer 8, third opening K3, first sub-reflective layer 41, second sub-reflective layer 42, first opening K1, second opening K2, light extraction structure 9, second surface 11a, first spacer M1, second spacer M2;

[0057] Substrate SU, well region WL, gate GATE, doped region DR, first connection pad P, second connection pad com, wiring layer TL, first wiring layer TL1, second wiring layer TL2, driving circuit 61;

[0058] Display substrate A, base A0, bonding layer J, original stack 01, initial light-emitting device 11', bottom film layer 111', substrate substrate A01, AlGaN layer A02, GaN buffer layer A03, hard mask layer B, photoresist PR, second metal layer 42', first metal layer 08, third semiconductor layer J1, outer metal layer J2, inner metal layer J3, light extraction layer 09, third via hole H3. Detailed implementation manners

[0059] An embodiment of the present invention provides a display panel to solve the technical problem that the light extraction efficiency of a silicon-based LED microdisplay is not high in the prior art.

[0060] It should be understood that the specific structures and functional details disclosed in the embodiments of the present invention are only representative and are for the purpose of describing the exemplary embodiments of the present application. However, the present application can be specifically implemented in many alternative forms or combinations and should not be construed as being limited only to the embodiments set forth herein.

[0061] In the description of the present application, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, unless otherwise specified, the meaning of "a plurality" is two or more. In addition, the term "comprising" and any variations thereof are intended to cover non-exclusive inclusion.

[0062] The terms used in this application are only for describing specific embodiments and are not intended to limit the exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms "a" and "an" used herein are also intended to include the plural. It should also be understood that the terms "comprises" and / or "comprising" specify the presence of the stated features, integers, steps, operations, units, and / or components, and do not preclude the presence or addition of one or more other features, integers, steps, operations, units, components, and / or combinations thereof.

[0063] To make the above objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described below in conjunction with the drawings and embodiments. However, the exemplary embodiments can be implemented in various forms and should not be construed as limited to the embodiments described herein; on the contrary, these embodiments are provided to make the present invention more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings represent the same or similar structures, and thus the repeated description thereof will be omitted. The words expressing positions and directions described in the present invention are all illustrated by taking the drawings as examples, but can be changed according to needs, and all the changes are included in the protection scope of the present invention. The drawings of the present invention are only used to illustrate the relative positional relationship and do not represent the actual proportion.

[0064] It should be noted that specific details are set forth in the following description to facilitate a thorough understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar generalizations without departing from the spirit of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed below. The subsequent description of the specification is the preferred embodiment for implementing the present application, but the description is for the purpose of illustrating the general principles of the present application and is not intended to limit the scope of the present application. The protection scope of the present application shall be defined by the appended claims.

[0065] The following specifically describes a display panel provided by an embodiment of the present invention in conjunction with the drawings.

[0066] Please refer to Figure 1 a schematic structural diagram of a display panel provided by an embodiment of the present invention, the display panel includes:

[0067] a plurality of stacked structures 1, the stacked structure 1 includes a light-emitting device 11 and a pixel electrode 12 stacked along a first direction Y; the first direction Y is the direction in which the pixel electrode 12 points to the light-emitting device 11;

[0068] a common electrode layer 3, located on a side of the plurality of stacked structures 1 away from the pixel electrode 22;

[0069] The reflective layer 4 covers at least a partial area of the side surface of the stacked structure 1 and a partial area of the first surface 12a, where the first surface 12a is the surface of the pixel electrode 12 away from the corresponding light-emitting device 11; the reflective layer 4 has a plurality of first through-holes H1 corresponding one-to-one to the plurality of stacked structures 1, and the first through-holes H1 expose another partial area of the first surface 12a; for example, if the top view shape of the stacked structure 1 is rectangular, the stacked structure 1 includes side surfaces corresponding to 4 sides, and the reflective layer 4 covers a partial area of the side surfaces corresponding to these 4 sides of the stacked structure 1 and a partial area of the first surface 12a; again, if the top view shape of the stacked structure 1 is a regular hexagon, the stacked structure 1 includes side surfaces corresponding to 6 sides, and the reflective layer 4 covers a partial area of the side surfaces corresponding to these 6 sides of the stacked structure 1 and a partial area of the first surface 2a. In this way, the reflective layer 4 can not only emit the light emitted from the stacked structure 1 towards the pixel electrode 12 from the common electrode layer 3 side, but also reflect the light emitted from the side surface of the stacked structure 1, so that these lights are finally emitted from the common electrode layer 3 side, thus effectively improving the light extraction efficiency of the display panel.

[0070] The silicon-based backplane 6 is located on the side of the plurality of reflective layers 4 away from the pixel electrode 12; the silicon-based backplane 6 includes a plurality of driving circuits ( Figure 1 not shown in the figure) corresponding one-to-one to the plurality of stacked structures 1. A plurality of first through-holes H1 corresponding one-to-one to the plurality of stacked structures 1 are provided on the reflective layer 4, and the first through-holes H1 are overlapped with the pixel electrode 12, so that the connection structure 5 can pass through the first through-holes H1 to connect the pixel electrode 12 and the driving circuit in the silicon-based backplane 6, enabling the display panel to work normally.

[0071] A plurality of connection structures 5, the connection structure 5 connects the pixel electrode 12 and the driving circuit through the first through-hole H1; the connection structure 5 can be made of a conductive material, such as it can be made of copper, indium tin oxide (ITO), or can also be made of a combination of multiple metal materials, such as Figure 1 as shown in the figure, the connection structure 5 is composed of an inner layer structure 51' and an outer layer structure 52' covering the inner layer structure 51', the inner layer structure 51' can be made of copper, and the outer layer structure 52' can be made of thallium nitride (TaN).

[0072] A plurality of first through-holes H1 corresponding one-to-one to the plurality of stacked structures 1 are provided on the reflective layer 4, and the first through-holes H1 are overlapped with the pixel electrode 12, so that the connection structure 5 can pass through the first through-holes H1 to connect the pixel electrode 12 and the driving circuit in the silicon-based backplane 6, enabling the display panel to work normally.

[0073] The light-emitting device 11 includes: a first semiconductor layer 111, an active layer 112, and a second semiconductor layer 113 which are stacked; the first semiconductor layer 111 is located on the side of the active layer 112 close to the common electrode layer 3 and is connected to the common electrode layer 3, and the second semiconductor layer 113 is located on the side of the active layer 112 close to the pixel electrode 12 and is connected to the pixel electrode 12.

[0074] The first semiconductor layer 111 may be an n-type nitride semiconductor layer containing In x Al y Ga 1-x-y N (0 ≤ x < 1, 0 ≤ y < 1, 0 ≤ x + y < 1), and the n-type impurity may be silicon. For example, the first semiconductor layer 111 may contain n-type GaN. The second semiconductor layer 113 may be a p-type nitride semiconductor layer containing In x Al y Ga 1-x-y N (0 ≤ x < 1, 0 ≤ y < 1, 0 ≤ x + y < 1), and the p-type impurity may be magnesium. For example, the second semiconductor layer 113 may be a single-layer structure, but in some exemplary embodiments, it may have a multi-layer structure containing different components. The active layer 112 may have a multi-quantum well (MQW) structure, in which the quantum well layer and the quantum barrier layer are alternately stacked with each other. For example, the quantum well layer and the quantum barrier layer may respectively include In x Al y Ga 1-x-y N (0 ≤ x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ x + y ≤ 1) of different components. In one example, the quantum well layer may include In x Ga 1-x N (0 < x ≤ 1) component, and the quantum barrier layer may include GaN or AlGaN. The active layer 12 is not limited to the MQW structure and may have a single quantum well (SQW) structure.

[0075] An electrical signal can be applied to the light-emitting device 11 through the pixel electrode 12 and the common electrode layer 3, and the light-emitting device 11, the pixel electrode 12, and the common electrode layer 3 can form a light-emitting diode (LED). In the embodiments provided by the present invention, there is no particular limitation on the type of the light-emitting diode. For example, an LED with a quantum well junction, an LED with a columnar structure, an LED with a double heterojunction, etc. may be used. The LED may be a structure with its size miniaturized to the order of hundreds of micrometers. For example, the area of the region where the light-emitting diode emits light is preferably 1 mm 2 Hereinafter, more preferably 10000 μm 2 Hereinafter, further preferably 3000 μm 2 Hereinafter, further preferably 700 μm 2Hereinafter, it can even be 200 μm 2 or less.

[0076] Please refer to Figure 2 FIG. is a schematic structural diagram of a silicon-based backplane provided by an embodiment of the present invention. The silicon-based backplane 6 includes a substrate SU and a driving circuit 61 formed thereon by semiconductor processes. The material of the substrate SU is single crystal silicon. The driving circuit 61 includes a pixel circuit and a peripheral circuit, both of which may include a plurality of transistors. Specifically, a well region WL can be formed in a silicon substrate by doping. The well region WL has two doped regions DR distributed at intervals. Taking one well region WL as an example: A gate GATE is provided on one side of the silicon-based backplane 6, and the orthographic projection of the gate GATE on the silicon-based backplane 6 is located between the two doped regions DR. The well region WL and the gate GATE can form a transistor. The doped regions DR of the well region WL are respectively the first pole and the second pole of the transistor, and the well region WL between the two doped regions DR is the channel region of the transistor.

[0077] Figure 1 A part of each connection structure 5 in [ ] is located in the silicon-based backplane 6. A part of the connection structure 5 located in the silicon-based backplane 6 can become a first connection pad P. The display panel further includes a common connection structure ( Figure 1 not shown in the figure), and the common connection structure is connected to the common electrode layer 3 ( Figure 1 not shown). A part of the common connection structure is located in the silicon-based backplane 6. A part of the common connection structure located in the silicon-based backplane 6 can be called a second connection pad com. As Figure 2 shown, the substrate SU further includes a circuit pattern connected to the first connection pad P and the second connection pad com to connect a plurality of LEDs in series and / or in parallel with each other. The circuit pattern can be composed of traces in a trace layer TL. The trace layer TL includes a first trace layer TL1 and a second trace layer TL2.

[0078] In the embodiment provided by the present invention, by setting the stacked structure 1 in the display panel to include light-emitting devices 11 stacked along the first direction Y, and setting a reflective layer 4, the reflective layer 4 covers at least a part of the side surface region and a part of the first surface 12a of the stacked structure 1. The first surface 12a is the surface of the pixel electrode 12 away from the corresponding light-emitting device 11. In this way, the reflective layer 4 can be used to reflect the light emitted by each stacked structure 1 towards the pixel electrode 2 side and the light emitted from the side surface of the stacked structure 1, so that these lights are all emitted from the side of the common electrode layer 3, thereby effectively improving the light extraction efficiency of the display panel.

[0079] Please refer to Figure 3A schematic structural diagram of another display panel provided by an embodiment of the present invention. The cross-sectional pattern of the stacked structure 1 in a plane perpendicular to the silicon-based backplane 6 is an inverted trapezoid. There is a first spacer M1 between any two adjacent stacked structures 1, and the reflective layer 4 also covers the first spacer M1.

[0080] When the cross-sectional pattern of the stacked structure 1 in a plane perpendicular to the silicon-based backplane 6 is an inverted trapezoid, allowing the reflective layer 4 to also cover the first spacer M1 between any two adjacent stacked structures 1 can prevent damage to the common electrode layer 3 during etching in the first spacer M1.

[0081] Please refer to Figure 4 A schematic structural diagram of another display panel provided by an embodiment of the present invention. The display panel further includes:

[0082] A protective layer 7, located between the reflective layer 4 and the plurality of pixel electrodes 2; the shape of the protective layer 7 is the same as that of the reflective layer 4. The protective layer 7 includes a second through-hole H2 corresponding to the first through-hole H1. The orthographic projection of the second through-hole in the reflective layer 4 is located within the first through-hole H1, and there is a gap between the edge of the second through-hole H2 and the edge of the first through-hole H1. A part of the connection structure 5 is filled in the second through-hole H2.

[0083] Since it is inevitable to cause damage to the side surface of the light-emitting device 11 when etching to form the stacked structure 1, and the damage to the side surface of the light-emitting device 11 will cause non-radiative recombination of electrons and holes in the side surface region of the active layer 12, affecting the light-emitting efficiency. In the present invention, by providing a protective layer 7 with the same shape as the reflective layer 4 between the stacked structure 1 and the reflective layer 4, the protective layer 7 can completely cover the side surface of the stacked structure 1, preventing subsequent processes from contaminating the side surface of the light-emitting device 11, thereby reducing non-radiative recombination in the active layer 12 of the light-emitting device 11 and improving the light-emitting efficiency of the light-emitting device 11. In addition, when the reflective layer 4 contains a conductive material, the protective layer 7 can also be used to prevent conduction between non-adjacent film layers in the stacked structure 1. And having the orthographic projection of the second through-hole H2 of the protective layer 7 in the reflective layer 4 located within the first through-hole H1 and a gap between the edge of the first through-hole H1 and the edge of the second through-hole H2 can effectively prevent the connection structure 5 from contacting the reflective layer 4.

[0084] Please continue to refer to Figure 3 , the protective layer 7 includes:

[0085] A first sub-protective layer 71, located on the side of the stacked structure 1 close to the reflective layer 4; the first sub-protective layer 71 is formed by an atomic layer deposition process;

[0086] A second sub-protective layer 72, located on the side of the first sub-protective layer 71 close to the reflective layer 4; the second through-hole H2 penetrates through the first sub-protective layer 71 and the second sub-protective layer 72.

[0087] The first sub-protective layer 71 may be a protective layer 7 formed by atomic layer deposition (ALD). The atomic layer deposition process can ensure that the first sub-protective layer 71 isolates the stacked structure 1 and the reflective layer 4, and the obtained first sub-protective layer 71 has a relatively thin thickness, hardly affecting the state size of the light-emitting diode. In addition, atomic layer deposition is a chemical adsorption and self-limiting reaction, and no plasma is generated during the deposition process, so that the side surface of the active layer 12 can be prevented from being bombarded and damaged by the plasma.

[0088] The material used for the first sub-protective layer 71 may be Al 2 O 3 , and the Al 2 O 3 layer formed by the ALD process has high density, no pinholes, excellent three-dimensional conformal properties, good coverage of the side surface of the stacked structure 1, and can better isolate the stacked structure 1 and the reflective layer 4.

[0089] The material used for the second sub-protective layer 72 may be silicon oxide (SiO), so that the second sub-protective layer 72 can be used to protect the first sub-protective layer 71 from being damaged in the subsequent etching process.

[0090] In some embodiments, the reflective layer 4 may be a distributed Bragg reflector. For example, the reflective layer 4 in Figure 1 and Figure 3 can be set as a distributed Bragg reflector.

[0091] In other embodiments, the material of the reflective layer 4 includes metals, especially metal materials with a reflectivity greater than 99%, and may be one or a combination of metals or alloy layers such as silver (Ag), aluminum (Al), nickel (Ni), titanium (Ti), titanium tungsten (TiW), chromium (Cr), aluminum copper (AlCu), platinum (Pt), gold (Au), etc.

[0092] In other embodiments, the reflective layer 4 may also be a stacked structure composed of a transparent conductive layer - a metal reflective layer - a transparent conductive layer. The transparent conductive layer may be composed of indium tin oxide (ITO), so that the ITO can be used to protect the metal reflective layer and improve the lattice matching degree between the reflective layer 4 and the semiconductor layer.

[0093] Please refer to Figure 5 which is a schematic structural diagram of another display panel provided by an embodiment of the present invention. The display panel further includes:

[0094] An auxiliary electrode layer 8, located on the side of the common electrode layer 3 away from the silicon-based backplane 6; the auxiliary electrode layer 8 may be composed of a metal material;

[0095] The auxiliary electrode layer 8 has a plurality of third openings K3 penetrating through the auxiliary electrode layer 8, and the plurality of third openings K3 correspond to the plurality of stacked structures 1 one by one; the orthographic projection of the third openings K3 on the silicon-based backplane 6 is located within the orthographic projection of the corresponding stacked structure 1 on the silicon-based backplane 6.

[0096] By providing the auxiliary electrode layer 8 having a plurality of third openings K3 on the side of the common electrode layer 3 away from the silicon-based backplane 6, and making the plurality of third openings K3 correspond to the plurality of stacked structures 1 one by one, the orthographic projection of the third openings K3 on the silicon-based backplane 6 is located within the orthographic projection of the corresponding stacked structure 1 on the silicon-based backplane 6, and the auxiliary electrode layer 8 overlaps with the side surface of the corresponding stacked structure 1, the entire auxiliary electrode layer 8 can be made into a metal mesh, which is beneficial to reducing the voltage drop of the stacked structure 1 operating in a high-current scenario through the metal mesh, thereby improving the display effect. Moreover, since the auxiliary electrode layer 8 is made of a metal material and the metal material is opaque, the auxiliary electrode layer 8 can also be used to prevent the problem of light crosstalk between adjacent stacked structures 1 and improve the display effect.

[0097] Please refer to Figure 6 For the structural schematic diagram of another display panel provided by an embodiment of the present invention, the cross-sectional pattern of the stacked structure 1 in the plane perpendicular to the silicon-based backplane 6 is a regular trapezoid, and the light-emitting device 11 includes a second semiconductor layer 13, an active layer 12, and a first semiconductor layer 11 stacked along the first direction Y, and the reflective layer 4 includes:

[0098] A first sub-reflective layer 41 covering a part of the region of the first surface 2a, and a plurality of first through holes H1 are located in the first sub-reflective layer 41;

[0099] A second sub-reflective layer 42 is located on the side of the plurality of stacked structures 1 away from the silicon-based backplane 6; the second sub-reflective layer 42 covers at least the side surfaces of the active layer 12 and the first semiconductor layer 11, and the second spacer region M2 between any two adjacent pixel electrodes 12.

[0100] When the cross-sectional pattern of the stacked structure 1 in the plane perpendicular to the silicon-based backplane 6 is a regular trapezoid, by providing the first sub-reflective layer 41 on the side of the plurality of stacked structures 1 close to the silicon-based backplane 6, the first sub-reflective layer 41 can be used to reflect the light rays directed to the side where the pixel electrode 12 is located; and by providing the second sub-reflective layer 42 on the side of the plurality of stacked structures 1 away from the silicon-based backplane 6 and making the second sub-reflective layer 42 cover at least the side surfaces of the active layer 12 and the first semiconductor layer 11, the second sub-reflective layer 42 can be used to reflect at least most of the light rays from the side surfaces of the stacked structure 1, so that the light rays reflected by the first sub-reflective layer 41 and the second sub-reflective layer 42 finally exit from the side of the common electrode layer 3, thereby improving the light-emitting efficiency of the display panel.

[0101] Please continue to refer to Figure 6, ideally, the second sub-reflection layer 42 exactly covers the side surface of the stacked structure 1. However, when manufacturing the second sub-reflection layer 42, usually after patterning to form the stacked structure 1, a whole second sub-reflection layer 42 is fabricated on the side of the light-emitting device 1 away from the pixel electrode 12, and the second sub-reflection layer 42 is etched to expose the side of the light-emitting device 11 away from the pixel electrode 12. When etching the second sub-reflection layer 42, there is usually a problem of alignment error, which may cause the second sub-reflection layer 42 to fail to cover some areas of the first semiconductor layer 111 due to the alignment error.

[0102] It can be understood that the main material of the first semiconductor layer is GaN, and its refractive index is between 2.2 and 2.5; the material of the first sub-protective layer 71 is Al 2 O 3 , with a refractive index of 1.67; the material of the second sub-protective layer 72 is SiO, with a refractive index of 1.45. Even if there are areas in the stacked structure that are not covered by the reflection layer, the large-angle light emitted by the light-emitting device cannot be emitted due to total reflection, and the small-angle light emitted by the light-emitting device will be blocked by the part of the reflection layer between adjacent stacked structures. Therefore, the emitted light rays of adjacent stacked structures will not interfere with each other.

[0103] Please refer to Figure 7 for the structural schematic diagram of another display panel provided by an embodiment of the present invention. The second sub-reflection layer 42 also covers a part of the second surface 11a. The second surface 11a is the surface of the stacked structure 1 close to the common electrode layer 3. The second sub-reflection layer 42 includes a first opening K1, and the first opening K1 exposes another part of the second surface 11a. The common electrode layer 3 is connected to the stacked structure 1 through the first opening K1. Since the first opening K1 of the second sub-reflection layer 42 exposes a part of the second surface 11a, the orthographic projection of the first opening K1 on the second surface 11a is located in the second surface 11a. In this way, even if there is an alignment error when manufacturing the second opening K2, it can ensure that the second sub-reflection layer 42 covers the side surface of the stacked structure 1, thereby improving the light extraction efficiency of the display panel.

[0104] In some embodiments, the first sub-reflection layer 41 and the second sub-reflection layer 42 can be Bragg reflectors.

[0105] Please refer to Figure 8 for the structural schematic diagram of another display panel provided by an embodiment of the present invention. The display panel further includes:

[0106] A protective layer 7, located between the second sub-reflection layer 42 and the stacked structure 1; the protective layer 7 at least covers the side surface of the stacked structure 1.

[0107] Such as Figure 8As shown, when the second sub-reflection layer 42 has a first opening K1, the protective layer 7 has a second opening K2 in the area covered by the first opening K1. The second opening K2 exposes at least a part of the second surface 11a, and the common electrode layer 3 is connected to a part of the second surface 11a exposed through the second opening K2.

[0108] By providing a protective layer 7 between the second sub-reflection layer 42 and the stacked structure 1 and covering at least the side surface of the stacked structure 1, the side surface of the stacked structure 1 can be protected by the protective layer 7 from damage during the manufacturing process, thereby improving the light-emitting efficiency of the stacked structure 1.

[0109] Please refer to Figure 9 which is a schematic structural diagram of another display panel provided by an embodiment of the present invention. The protective layer 7 also covers the second spacer M2, so that it is not necessary to etch the protective layer 7 in the second spacer M2, enabling the protective layer 7 to completely cover the side surface of the stacked structure 1.

[0110] Please continue to refer to Figure 9 , the protective layer 7 includes a first sub-protective layer 71 and a second sub-protective layer 72. The second sub-protective layer 72 is located between the first sub-protective layer 71 and the second sub-reflection layer 42. The material composition and functions of the first sub-protective layer 71 and the second sub-protective layer 72 can refer to the first sub-protective layer 71 and the second sub-protective layer 72 described above, and will not be elaborated here. Figure 4 in the above, and will not be elaborated here.

[0111] Figure 8 , Figure 9 The first sub-reflection layer 41 in the above can be a distributed Bragg reflector. In addition to being a distributed Bragg reflector, the second sub-reflection layer 42 can also be composed of a metal. When the second sub-reflection layer 42 is composed of a metal, not only can the second sub-reflection layer 42 reflect the light emitted from the side surface of the stacked structure 1, but the second sub-reflection layer 42 can also be used as a part of the common electrode layer 3, thereby reducing the resistance of the common electrode layer 3. In addition, the second sub-reflection layer 42 can also be used to prevent the problem of light crosstalk between adjacent stacked structures 1.

[0112] Please continue to refer to Figure 8 , Figure 9 , the second sub-reflection layer 42 is located on the side of the common electrode layer 3 close to the stacked structure 1 and is composed of a metal material. In this way, not only can the second sub-reflection layer 42 reflect the light emitted from the side surface 1b of the stacked structure 1, but the second sub-reflection layer 42 can also be used to reduce the resistance of the common electrode layer 3.

[0113] Please refer to Figure 10 which is a schematic structural diagram of another display panel provided by an embodiment of the present invention. The display panel further includes:

[0114] The auxiliary electrode layer 8 is located on the side of the common electrode layer 3 away from the silicon-based backplane 6;

[0115] The auxiliary electrode layer 8 has a plurality of third openings K3 penetrating through the auxiliary electrode layer 8, and the plurality of third openings K3 correspond to the plurality of stacked structures 1 one by one; the orthographic projection of the third opening K3 on the silicon-based backplane 6 is located within the orthographic projection of the corresponding stacked structure 1 on the silicon-based backplane 6.

[0116] The material used for the auxiliary electrode layer 8 can be a metal material.

[0117] By providing the auxiliary electrode layer 8 on the side of the common electrode layer 3 away from the silicon-based backplane 6, and making the auxiliary electrode layer 8 have a plurality of third openings K3 penetrating through the auxiliary electrode layer 8, and the orthographic projection of the third opening K3 on the silicon-based backplane 6 is located within the orthographic projection of the corresponding stacked structure 1 on the silicon-based backplane 6, the voltage drop in the display area can be reduced by using the auxiliary electrode layer 8 in a high-current working scenario, thereby improving the display effect.

[0118] Please refer to Figure 11 For another structural schematic diagram of the display panel provided by the embodiment of the present invention, the display panel further includes:

[0119] The auxiliary electrode layer 8 is located on the side of the common electrode layer 3 away from the silicon-based backplane 6;

[0120] The second sub-reflection layer 42 is reused as the auxiliary electrode layer 8.

[0121] Since when the second sub-reflection layer 42 is reused as the auxiliary electrode layer 8, the second sub-reflection layer 42 is located on the side of the common electrode layer 3 away from the silicon-based backplane 6, if the protective layer 7 and the common electrode layer 3 cover the second spacer M2, it will only ensure that the second sub-reflection layer 42 covers at least the side surfaces of the first semiconductor layer 11 and the active layer 12; of course, it is also possible to make the protective layer 7 and the common electrode layer 3 not cover the second spacer M2, so that the second sub-reflection layer 42 can cover the side surfaces of the stacked structure 1.

[0122] When the second sub-reflection layer 42 is located on the side of the common electrode layer 3 away from the silicon-based backplane 6, by reusing the second sub-reflection layer 42 as the auxiliary electrode layer 8, it can not only use the second sub-reflection layer 42 to cover at least the side surfaces of the first semiconductor layer 11 and the active layer 12 and reflect most of the light emitted from the side surfaces of the stacked structure 1 at least, but also use the second sub-reflection layer 42 to reduce the voltage drop in the display area and prevent color crosstalk between adjacent stacked structures, thereby improving the display effect.

[0123] Please refer to Figures 12 - 14 For another structural schematic diagram of the display panel provided by the embodiment of the present invention.

[0124] The display panel further includes:

[0125] A plurality of light extraction structures 9 are located on the side of the common electrode layer 3 away from the silicon-based backplane 6; the plurality of light extraction structures 9 correspond to the plurality of stacked structures 1 one by one, and the light extraction structure 9 covers the corresponding stacked structure 1.

[0126] As Figures 12 - 14 shown, the longitudinal cross-sectional shape of the light extraction structure 9 can be semi-circular or semi-elliptical, which can increase the light extraction area and refract and converge the side light of the stacked structure 1 to the center of the corresponding pixel.

[0127] The light extraction structure 9 can be made of silicon oxide (SiO) or other lens materials, which is not limited herein.

[0128] Please refer to Figure 15 a partial top view of a display panel provided by an embodiment of the present invention. Figure 15 is Figure 12 the corresponding partial top view. The partial top views of the display panels of the remaining structures are similar thereto and will not be described in detail herein.

[0129] It should be understood that Figures 12 - 14 only shows the combination of the light extraction structure 9 and Figure 4 , Figures 10 - 11 . Actually, the light extraction structure 9 can also be provided in the display panel of any of the foregoing structures, which will not be described in detail herein.

[0130] Based on the same inventive concept, an embodiment of the present invention provides a method for manufacturing a display panel. Please refer to Figure 16 and Figure 17 a manufacturing schematic diagram of a display panel provided by an embodiment of the present invention. The manufacturing method includes:

[0131] S10: Provide a silicon-based backplane 6; the silicon-based backplane 6 includes a plurality of driving circuits ( Figures 16 - 17 not shown in the figure) and a second sub-connection structure 52 connected to the driving circuit 61; the structure of the silicon-based backplane 6 can refer to Figure 2 , and the second sub-connection structure 52 can be Figure 2 the first connection pad P or the second connection pad com in

[0132] S11: Form a display substrate A; the display substrate A includes: a substrate A0, a plurality of stacked structures 1 and a reflective layer 4; the stacked structure 1 includes a light-emitting device 11 and a pixel electrode 12 stacked along a first direction Y, and the reflective layer 4 covers at least a part of the side surface area and a part of the area of the first surface 12a of the stacked structure 1; the reflective layer 4 has a plurality of first through holes H1 corresponding to the plurality of stacked structures 1 one by one, and the first through holes H1 expose another part of the area of the first surface 12a; the first direction Y is the direction in which the pixel electrode 12 points to the light-emitting device 11;

[0133] S12: Bond the silicon-based backplane 6 to the display substrate A, and remove the substrate A0; wherein, the display substrate A includes a common electrode layer 3 on the side of the plurality of stacked structures 1 away from the plurality of pixel electrodes 2, or the display substrate A does not include the common electrode layer 3, and the common electrode layer 3 is formed after the silicon-based backplane 6 is bonded to the display substrate A. After the silicon-based backplane 6 is bonded to the display substrate A, the first sub-connection structure 51 and the second sub-connection structure 52 are bonded to form the connection structure 5.

[0134] The silicon-based backplane 6 and the display substrate A can be directly bonded through the first sub-connection structure 51 and the second sub-connection structure 52, as Figure 16 shown; the silicon-based backplane 6 and the display substrate A can also be bonded in a hybrid bonding manner. When using hybrid bonding, as Figure 15 shown, the display substrate A includes a bonding layer J facing the silicon-based backplane 6, and correspondingly, the silicon-based backplane 6 also includes a bonding layer J facing the display substrate A (not shown in Figure 15 , which can be referred to the side of the display substrate A); their bonding layers J both include metal patterns (for the display substrate A, that is, the first sub-connection structure 51 and the sub-connection structure corresponding to the common electrode layer 6 (not shown), and for the silicon-based backplane 6, that is Figure 2 the first connection pad P and the second connection pad com in 2 ), and an insulating pattern (one of SiO

[0135] As Figure 15 shown, if the display substrate A does not include the common electrode layer 3, then after the display substrate A is bonded to the silicon-based backplane 6 and the substrate A0 is removed; step S13 needs to be further performed: forming a common electrode layer 3 on the side of the stacked structure 1 away from the silicon-based backplane 6. If the display substrate A further includes other film layers on the side of the common electrode layer 3 away from the silicon-based backplane 6, they also need to be formed layer by layer after the common electrode layer 3 is formed;

[0136] As Figure 16 shown, if the display substrate A includes the common electrode layer 3, then the display substrate A can be obtained after the display substrate A is bonded to the silicon-based backplane 6 and the substrate is removed.

[0137] Please refer to Figure 18 A schematic diagram of a display substrate provided by an embodiment of the present invention, which can be specifically implemented in the following manner: Figure 15 S20: Form the substrate A0;

[0138] S20: Form the substrate A0;

[0139] Please refer toFigure 19 The figure is a schematic structural diagram of a substrate provided by an embodiment of the present invention. The substrate A0 may be composed of a substrate A01, an AlGaN layer A02 on one side of the substrate A01, and a GaN buffer layer A03 on the side of the AlGaN layer A02 away from the substrate A01. In this way, when performing step S21, the GaN buffer layer A03 can be lattice-matched with the original semiconductor stack 01. The substrate A01 may be made of sapphire material or other insulating materials, and there is no specific limitation.

[0140] S21: Grow the original stack 01 on one side of the substrate A0;

[0141] The film layer structure of the original stack 01 is the same as that of the stack structure 1 in the foregoing Figure 1 and will not be elaborated here.

[0142] S22: Pattern the original stack 01 to obtain a plurality of initial light-emitting structures 11' and a plurality of pixel electrodes 2; among them, the etching depth h of the bottom film layer 111' closest to the substrate A0 in the plurality of initial light-emitting structures 11' is less than the thickness d of the bottom film layer 111'; the bottom film layer 111' is the Figure 1 film layer where the first semiconductor layer 111 in the foregoing is located; that is, there are a plurality of grooves M in the bottom film layer 111', the depth of the grooves M in the bottom film layer 111' is h, and the value range of the width CD of the grooves M is 0.5 μm to 1 μm; when removing the substrate A0 in the foregoing Figure 13 , a part of the film thickness of the bottom film layer 111' is removed. The part of the film thickness is less than the maximum thickness (i.e., d) of the bottom film layer 111' and greater than or equal to the minimum thickness (i.e., d - h) of the bottom film layer 111', and a plurality of light-emitting devices 11 can be obtained.

[0143] The patterning of the original stack 01 can be performed using a hard mask, as Figure 20 shown in the figure which is a schematic diagram of patterning the original stack provided by an embodiment of the present invention.

[0144] S31: Form a hard mask layer B on the side of the original stack 01 away from the substrate A0;

[0145] The material used for the hard mask layer B may be silicon oxide.

[0146] S32: Thin the substrate A0 to adapt to the processing thickness of the exposure machine.

[0147] S33: Coat a photoresist PR on the side of the hard mask layer B away from the substrate A0, and pattern the photoresist PR using a yellow light process;

[0148] S34: Pattern the hard mask layer B and the original stack 01 using a dry etching process to obtain the patterned hard mask layer B, a plurality of initial light-emitting devices 11', and a plurality of pixel electrodes 12;

[0149] S35: Remove the hard mask layer B.

[0150] S23: Form a reflective layer 4 on the side of the plurality of pixel electrodes 2 away from the substrate A0; wherein, the reflective layer 4 has a plurality of first through holes H1 penetrating through the reflective layer 4, and the plurality of first through holes H1 correspond to the plurality of pixel electrodes 2 one by one;

[0151] The reflective layer 4 can be a three-layer structure composed of an ITO layer - a metal layer - an ITO layer, and the metal layer can be made of silver, aluminum, etc.; the reflective layer 4 can also be composed of a distributed Bragg reflector. Figure 19 The reflective layer 4 shown in is constructed by a distributed Bragg reflector.

[0152] Before forming the reflective layer 4, a Figure 4 protective layer 7 in can also be formed on the side of the plurality of pixel electrodes 12 away from the substrate A0. The film layer structure of the protective layer 7 can refer to the introduction of the relevant embodiments and will not be elaborated here. Figure 4 For details, please refer to the relevant embodiments and will not be elaborated here.

[0153] S24: On the side of the reflective layer 4 away from the substrate A0, form a bonding layer J; wherein, the bonding layer J includes a second sub-connection structure 52.

[0154] Please refer to Figure 21 which is a schematic diagram of forming a bonding layer provided by an embodiment of the present invention.

[0155] S241: On the side of the reflective layer 4 away from the substrate A0, form a third semiconductor layer J1;

[0156] S242: At the position corresponding to the first through hole H1, etch the third semiconductor layer J1 to form a third through hole H3 that penetrates through the film layer where the third semiconductor layer J1 is located to the pixel electrode 2. The orthographic projection of the third through hole H3 on the reflective layer 4 is located within the first through hole H1;

[0157] The third semiconductor layer J1 and the film layer between the third semiconductor layer J1 and the pixel electrode 2 can be etched using a dry etching method. For example, if the display panel is the display panel in Figure 4 , when etching, the protective layer 7 also needs to be etched (i.e., the third through hole H3 needs to penetrate through the third semiconductor layer J1 and the protective layer 7).

[0158] S243: On the side of the third semiconductor layer J1 away from the substrate A0, form an outer metal layer J2;

[0159] The outer metal layer J2 can be formed using a sputtering process, and the outer metal layer J2 can use TaN.

[0160] S244: Form an inner metal layer J3 on the side of the outer metal layer J2 away from the substrate A0.

[0161] The inner metal layer J3 can be formed using a sputtering process. The inner metal layer J3 can be made of copper. The formation of the inner metal layer J3 usually involves first depositing a copper seed layer and then performing thick copper plating using an electroplating process.

[0162] S245: Remove the outer metal layer J2 and the inner metal layer J3 outside the third through hole H3 to obtain an inner structure 51' and an outer structure 52'.

[0163] The part of the outer metal layer J2 and the inner metal layer J3 outside the third through hole H3 can be removed using a mask grinding process, so as to obtain the first sub-connection structure 51.

[0164] Please refer to Figure 22 Another schematic diagram for forming a display substrate provided by an embodiment of the present invention can be realized through the following steps:

[0165] S41: Form a substrate A0; the substrate A0 can adopt the structure in Figure 19 or be composed of sapphire, and there is no specific limitation.

[0166] S42: Sequentially form a bonding layer J, a first sub-reflection layer 41, and an original stack 01 on one side of the substrate A0; among them, the first sub-reflection layer 41 includes a plurality of first through holes H1, and the bonding layer J includes a plurality of first sub-connection structures 51 corresponding one-to-one to the plurality of first through holes H1.

[0167] S43: Pattern the original stack 01 to obtain a plurality of light-emitting devices 11 and a plurality of pixel electrodes 12; the plurality of pixel electrodes 12 correspond one-to-one to the plurality of first through holes H1, and the first sub-connection structure 51 is connected to the pixel electrode 12 corresponding to the first through hole H1 in the corresponding first through hole H1.

[0168] S44: Form a protective layer 7 on the side of the plurality of stack structures 1 away from the substrate A0; then perform S45 or S51

[0169] Please refer to Figure 23 A schematic diagram for forming a reflection layer provided by an embodiment of the present invention can be realized through the following steps:

[0170] S51: Form a second metal layer 42' on the side of the protective layer 7 away from the substrate A0.

[0171] S52: Pattern the second metal layer 42' to obtain a second sub-reflection layer 42; among them, the second sub-reflection layer 42 at least covers the side surfaces of the first semiconductor layer 11 and the active layer 12.

[0172] After forming the protective layer 7, the protective layer 7 may not be patterned first. It can be like Figure 21 In the same way as in , after forming the second metal layer 42', the second metal layer 42' and the protective layer 7 are patterned using the same etching process, and the first opening K1 and the second opening K2 exposing the second surface 11a are formed simultaneously.

[0173] Execute S45 after executing S52.

[0174] S45: Form a common electrode layer 3 on the side of the protective layer 7 away from the substrate A0; wherein, the common electrode layer 3 is connected to the plurality of stacked structures 1 through the first opening K1 and the second opening K2.

[0175] Please refer to Figure 24 A schematic diagram of forming an auxiliary electrode layer provided by an embodiment of the present invention is shown, which is specifically implemented through the following steps:

[0176] S61: After forming the common electrode layer 3 on the side of the protective layer 7 away from the substrate A0, form a first metal layer 08 on the side of the common electrode layer 3 away from the substrate A0;

[0177] The first metal layer 08 can be formed by electron beam evaporation.

[0178] S62: Pattern the first metal layer 08 to obtain an auxiliary electrode layer 8; the auxiliary electrode layer 8 has a plurality of third openings K3 penetrating through the auxiliary electrode layer 8, and the plurality of third openings K3 correspond to the plurality of stacked structures 1 one by one; the orthographic projection of the third opening K3 on the silicon-based backplane 6 is located within the orthographic projection of the corresponding stacked structure 1 on the silicon-based backplane 6, and the auxiliary electrode layer 8 overlaps with the side surface 1b of the corresponding stacked structure 1.

[0179] The first metal layer 08 can be patterned by blue film and lift-off to obtain the auxiliary electrode layer 8.

[0180] Please refer to Figure 25 A schematic diagram of forming a light extraction structure provided by an embodiment of the present invention.

[0181] S71: Form a light extraction layer 09 on the side of the auxiliary electrode layer 8 away from the stacked structure 1;

[0182] The light extraction layer 09 can be grown on the side of the auxiliary electrode layer 8 away from the stacked structure 1 by vapor deposition.

[0183] S72: Form a photoresist PR on the side of the light extraction layer 09 away from the stacked structure 1, and pattern the photoresist PR;

[0184] The patterned photoresist PR can be hemispherical.

[0185] S73: Patterning the light extraction layer 09 to obtain a plurality of light extraction structures 9.

[0186] The fabrication method of the light extraction structure 9 on other display panels or display substrates A can refer to the above fabrication method, which will not be elaborated here one by one.

[0187] The display panel can be: an Organic Light Emitting Diode (OLED) display panel, a Quantum Dot Light Emitting Diodes (QLED) display panel, a Micro Light Emitting Diodes (Micro LED) display panel, etc. The present invention does not make specific limitations thereto.

[0188] Although the preferred embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications to these embodiments once they learn the basic creative concepts. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications falling within the scope of the present invention.

[0189] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these modifications and variations.

Claims

1. A display panel, characterized in that: include: A plurality of stacked structures, wherein the stacked structures include light emitting devices and pixel electrodes stacked along a first direction; A common electrode layer, located at a side of the plurality of stacked structures away from the pixel electrode; a reflective layer covering at least a portion of the side surface of the stacked structure and a portion of the first surface, wherein the first surface is a surface of the pixel electrode away from the corresponding light-emitting device; the reflective layer has a plurality of first through holes corresponding to the plurality of stacked structures one by one, and the first through holes expose another portion of the first surface; A silicon-based backplane is located on a side of the reflective layer away from the pixel electrode; the silicon-based backplane includes a plurality of driving circuits corresponding to the plurality of stacked structures; A plurality of connection structures are provided, wherein the connection structures connect the pixel electrode and the driving circuit through the first through hole.

2. The display panel according to claim 1, wherein: The cross-sectional shape of the stacked structure on a plane perpendicular to the silicon-based backplane is an inverted trapezoid, and a first spacing region is provided between any two adjacent stacked structures, and the reflective layer also covers the first spacing region.

3. The display panel according to claim 2, wherein: The display panel further includes: A protective layer is located between the reflective layer and the multiple stacked structures; the shape of the protective layer is the same as that of the reflective layer, the protective layer includes a second through hole corresponding to the first through hole, the orthographic projection of the second through hole on the reflective layer is located in the first through hole, and there is a gap between the edge of the second through hole and the edge of the first through hole, and a part of the connection structure is filled in the second through hole.

4. The display panel according to claim 2 or 3, characterized in that: The reflective layer is a distributed Bragg reflector.

5. The display panel according to claim 3, wherein: The material of the reflective layer includes metal.

6. The display panel according to claim 1, wherein: The cross-sectional shape of the stacked structure on a plane perpendicular to the silicon-based backplane is a regular trapezoid, the light-emitting device comprises a second semiconductor layer, an active layer and a first semiconductor layer stacked along the first direction, and the reflective layer comprises: The first sub-reflection layer covers a portion of the first surface, and the plurality of first through holes are located in the first sub-reflection layer; the second sub-reflection layer is located on a side of the plurality of stacked structures away from the silicon-based backplane; the second sub-reflection layer at least covers the side surfaces of the active layer and the first semiconductor layer, and a second spacing area between any two adjacent pixel electrodes.

7. The display panel according to claim 6, wherein: The second sub-reflective layer also covers a portion of the second surface, where the second surface is a surface of the stacked structure close to the common electrode layer. The second sub-reflective layer includes a first opening, which exposes another portion of the second surface. The common electrode layer is connected to the stacked structure through the first opening.

8. The display panel according to claim 6 or 7, characterized in that: The display panel further includes: The protective layer is located between the second sub-reflection layer and the stacked structure; the protective layer at least covers the side surface of the stacked structure.

9. The display panel according to claim 8, wherein: The protection layer also covers the second spacer area.

10. The display panel according to claim 8, wherein: The display panel further includes: An auxiliary electrode layer, located on a side of the common electrode layer away from the silicon-based backplane; The second sub-reflection layer is reused as the auxiliary electrode layer.

11. The display panel according to claim 8, wherein: The second sub-reflection layer is located on a side of the common electrode layer close to the stacked structure, and the second sub-reflection layer is made of a metal material.

12. The display panel according to any one of claims 1 to 3 and 5 to 7, characterized in that: The display panel further includes: An auxiliary electrode layer, located on a side of the common electrode layer away from the silicon-based backplane; The auxiliary electrode layer has a plurality of third openings penetrating the auxiliary electrode layer, and the plurality of third openings correspond one-to-one to the plurality of stacked structures; the orthographic projections of the third openings on the silicon-based backplane are located within the orthographic projections of the corresponding stacked structures on the silicon-based backplane.

13. The display panel according to any one of claims 1 to 3 and 5 to 7, characterized in that: The display panel further includes: A plurality of light extraction structures are located on a side of the common electrode layer away from the silicon-based backplane; the plurality of light extraction structures correspond to the plurality of stacked structures one by one, and the light extraction structures cover the corresponding stacked structures.

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