Display panel and electronic device

Abstract

The invention provides a display panel and an electronic device. The display panel includes a display area including a first area having a first light transmittance and a second area having a second light transmittance higher than the first light transmittance, a plurality of first pixels, a plurality of second pixels, a first power portion, a second power portion, and a cathode insulating layer, each of the plurality of first pixels is configured to provide light to the first region and includes a first cathode, and each of the plurality of second pixels is configured to provide light to the second region and includes a second cathode overlapping the first cathode in plan view and electrically insulated from the first cathode, the first power portion is connected to the first cathode and configured to supply a first power voltage to the first cathode, the second power portion is connected to the second cathode and configured to supply a second power voltage different from the first power voltage to the second cathode, and the cathode insulating layer is between the first cathode and the second cathode.

Description

Technical Field

[0001] Aspects of some embodiments of the present disclosure relate to a display panel. Background Art

[0002] An electronic device may be a device including various electronic components such as a display panel for displaying an image, an input sensing unit for detecting an external input, and an electronic module. The electronic components may be electrically connected to each other through signal lines arranged in various ways. The display panel includes a light-emitting element that generates light.

[0003] The input sensing unit may include a detection electrode for detecting an external input. The electronic module may include a camera, an infrared sensor, a proximity sensor, or the like. The electronic module may be positioned under the display panel.

[0004] The above information disclosed in this background art section is only for enhancing the understanding of the background, and thus the information discussed in this background art section does not necessarily constitute the prior art. Summary of the Invention

[0005] Aspects of some embodiments of the present disclosure relate to a display panel, and for example, to a display panel having relatively improved overall display quality in a display area.

[0006] Aspects of some embodiments of the present disclosure include a display panel that can relatively improve the display quality of a display area on which an electronic module is positioned.

[0007] According to some embodiments of the present disclosure, the display panel includes a display area, a plurality of first pixels, a plurality of second pixels, a first power part, a second power part, and a cathode insulating layer. The display area includes a first area having a first light transmittance (e.g., which may refer to the first display area mentioned hereinafter) and a second area having a second light transmittance higher than the first light transmittance (e.g., which may refer to the second display area mentioned hereinafter). Each of the plurality of first pixels provides light to the first area and includes a first cathode. Each of the plurality of second pixels provides light to the second area and includes a second cathode that overlaps the first cathode in a plane (or in a plan view) and is electrically insulated from the first cathode. The first power part is connected to the first cathode and supplies a first power voltage to the first cathode. The second power part is connected to the second cathode and supplies a second power voltage different from the first power voltage to the second cathode. The cathode insulating layer is between the first cathode and the second cathode.

[0008] According to some embodiments, a hole passing through the first cathode and the cathode insulating layer may be defined in the second area, and the second cathode may pass through the first cathode and the cathode insulating layer through the hole to be connected to the second power part.

[0009] According to some embodiments, the hole may be at the edge of the first region.

[0010] According to some embodiments, the display panel may further include dummy pixels provided in the second region, and the hole may overlap the dummy pixels in a plane (or in a plan view).

[0011] According to some embodiments, the holes may be provided as a plurality such that a plurality of holes are included, and the plurality of holes may be arranged along the edge of the second region.

[0012] According to some embodiments, the second cathode may be spaced apart from the first region in a plane (or in a plan view).

[0013] According to some embodiments, the second cathode may overlap the first region and the second region in a plane (or in a plan view).

[0014] According to some embodiments, the second power voltage may have a voltage level lower than that of the first power voltage.

[0015] According to some embodiments, the first power section may include a first power line in a peripheral region adjacent to the display region and a first power auxiliary line branched from the first power line and extending from the peripheral region to the first region to be electrically connected to the first cathode. According to some embodiments, the second power section may include a second power line in the peripheral region and a second power auxiliary line branched from the second power line and extending from the peripheral region to the second region to be electrically connected to the second cathode.

[0016] According to some embodiments, the hole and the second power auxiliary line may overlap each other in a plane (or in a plan view).

[0017] According to some embodiments, the second power auxiliary line may extend through the first region so as to have a minimum distance between the second region and the peripheral region.

[0018] According to some embodiments, the display panel may further include a base layer on which the first power line and the second power line are positioned and a first insulating layer on the base layer. According to some embodiments, the first cathode may be on the first insulating layer.

[0019] According to some embodiments, the display panel may further include a first anode on the base layer and overlapping the first region, a second anode on the base layer and overlapping the second region, and an organic layer on the base layer and including an emission layer. The second power auxiliary line may be in the same layer as the second anode.

[0020] According to some embodiments of the present disclosure, a display panel includes a display area including a first area having a first light transmittance and a second area adjacent to the first area and having a second light transmittance higher than the first light transmittance, a first anode in the first area, a second anode in the second area, an organic layer including an emission layer on the first anode and the second anode, a first cathode in the first area, a second cathode in the second area, in a different layer from the first cathode and electrically insulated from the first cathode, a first power part connected to the first cathode, and a second power part connected to the second cathode. According to some embodiments, a hole may be defined in the second area and passing through the first cathode, and the second cathode may pass through the first cathode through the hole to be connected to the second power part.

[0021] According to some embodiments, the display panel may further include a cathode insulating layer between the first cathode and the second cathode. The hole may also pass through the cathode insulating layer, and the second cathode may pass through the first cathode and the cathode insulating layer through the hole to be connected to the second power part.

[0022] According to some embodiments, the display panel may further include a peripheral area adjacent to the display area. According to some embodiments, the first power part may include a first power line in the peripheral area and a first power auxiliary line branched from the first power line and extending from the peripheral area to the first area to be electrically connected to the first cathode. According to some embodiments, the second power part may include a second power line in the peripheral area and a second power auxiliary line branched from the second power line and extending from the peripheral area to the second area to be electrically connected to the second cathode.

[0023] According to some embodiments, the hole and the second power auxiliary line may overlap each other in a plane (or in a plan view).

[0024] According to some embodiments, the display panel may further include a base layer on which the first power line and the second power line are located and a first insulating layer on the base layer. According to some embodiments, the first cathode may be on the first insulating layer.

[0025] According to some embodiments, the first anode and the second anode may be on the base layer, and the second power auxiliary line may be in the same layer as the second anode.

[0026] According to some embodiments, the first power part may supply a first power voltage to the first cathode, and the second power part may supply a second power voltage having a voltage level lower than the first power voltage to the second cathode. Description of the Drawings

[0027] According to some embodiments of the present disclosure, the accompanying drawings are included to provide a further understanding of the embodiments, and the accompanying drawings are incorporated into and constitute a part of this specification. The accompanying drawings illustrate aspects of some embodiments of the present disclosure and, together with the description, are used to explain the characteristics of some embodiments of the present disclosure. In the accompanying drawings:

[0028] Figure 1A is a perspective view of an electronic device according to some embodiments of the present disclosure;

[0029] Figure 1B is an exploded perspective view of an electronic device according to some embodiments of the present disclosure;

[0030] Figure 2 is a block diagram of an electronic device according to some embodiments of the present disclosure;

[0031] Figure 3A is a plan view of a display panel according to some embodiments of the present disclosure;

[0032] Figure 3B is a plan view of a display panel according to some embodiments of the present disclosure;

[0033] Figure 4A is an enlarged plan view showing a part of a first display area according to some embodiments of the present disclosure;

[0034] Figure 4B is an enlarged plan view showing a part of a second display area according to some embodiments of the present disclosure;

[0035] Figure 4C is an enlarged plan view showing a part of a second display area according to some embodiments of the present disclosure;

[0036] Figure 5A is an equivalent circuit diagram of a first red pixel according to some embodiments of the present disclosure;

[0037] Figure 5B is an equivalent circuit diagram of a second red pixel according to some embodiments of the present disclosure;

[0038] Figure 6 is a plan view of a display panel according to some embodiments of the present disclosure;

[0039] Figures 7A to 7D is a cross-sectional view of a display panel according to some embodiments of the present disclosure;

[0040] Figure 8 is a plan view of a display panel according to some embodiments of the present disclosure;

[0041] Figure 9Ais an enlarged plan view of a portion of a display panel according to some embodiments of the present disclosure;

[0042] Figure 9B and Figure 9C is an enlarged cross-sectional view of a portion of a display panel according to some embodiments of the present disclosure;

[0043] Figure 10A and Figure 10B is an enlarged plan view of a portion of a display panel according to some embodiments of the present disclosure; and

[0044] Figure 11A and Figure 11B is a plan view of a display panel according to some embodiments of the present disclosure. Detailed Embodiments

[0045] In this specification, it will be understood that when an element (or region, layer, portion, etc.) is referred to as being "on", "connected to", or "coupled to" another element, it can be directly positioned on the other element, directly connected or coupled to the other element, or a third intervening element can be positioned between the elements. Additionally, herein, the expression "A component is on B region" may mean that A component overlaps B region in a plan view.

[0046] Throughout the specification, like reference numerals or symbols refer to like elements. Further, in the drawings, for an effective description of the technical content, the thickness, ratio, and size of the elements are exaggerated. The term "and / or" includes one or more combinations that can be defined by the relevant elements.

[0047] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the teachings of the present invention, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element. Unless the context clearly indicates otherwise, the singular forms as used herein are also intended to include the plural forms.

[0048] In addition, terms such as "below", "beneath", "on", and "above" are used to explain the relationship of the elements shown in the drawings. The terms are relative concepts and are explained based on the directions shown in the drawings.

[0049] It will also be understood that when terms such as "includes" or "has" are used herein, they specify the presence of the stated features, numbers, steps, operations, elements, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, parts, or combinations thereof.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0051] Hereinafter, a display panel and a method for manufacturing a display panel according to some embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0052] Figure 1A is a perspective view of an electronic device according to some embodiments of the present disclosure. Figure 1B is an exploded perspective view of an electronic device according to some embodiments of the present disclosure. Figure 2 is a block diagram of an electronic device according to some embodiments of the present disclosure.

[0053] Referring to Figures 1A to 2 , the electronic device DD may be a device that is activated in response to an electrical signal. The electronic device DD may include various embodiments. For example, the electronic device DD may include a computer (such as a tablet computer, a laptop computer), a smart TV, or the like. In Figures 1A to 2 , a smart phone is shown as an example of the electronic device DD, but the embodiments according to the present disclosure are not limited thereto.

[0054] The electronic device DD may display an image IM on a display surface FS parallel to each of a first direction DR1 and a second direction DR2 in a third direction DR3. The display surface FS on which the image IM is displayed may correspond to the front surface of the electronic device DD and may correspond to the front surface FS of the window 100. Hereinafter, the same reference numerals are used for the display surface FS and the front surface of the electronic device DD and the front surface FS of the window 100. The image IM may include not only a moving image (e.g., a video image) but also a still image (e.g., a static image). Figure 1A A clock window and application icons are shown as examples of the image IM.

[0055] In Figure 1AIn [the device], the front surface (or top surface) and the rear surface (or bottom surface) of each component are defined based on the direction in which the image IM is displayed. The front surface and the rear surface may face each other in the third direction DR3, and the direction orthogonal to each of the front surface and the rear surface may be parallel to the third direction DR3. At the same time, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative concepts and may be changed to other directions.

[0056] The electronic device DD may include a window 100, a display module 200, a driving circuit part 300, a housing 400, and an electronic module 500. According to some embodiments, the window 100 and the housing 400 may be coupled to each other to provide the appearance of the electronic device DD.

[0057] The window 100 may include an optically transparent insulating material. For example, the window 100 may include glass or plastic. The window 100 may have a single-layer or multi-layer structure. For example, the window 100 may include a plurality of plastic films coupled to each other by an adhesive, or may include a glass substrate and a plastic film coupled to each other by an adhesive.

[0058] The window 100 may be divided into a transmissive area TA and a border area BZA in a plane or in a plan view. Herein, the phrase "in a plane" or "in a plan view" may mean a state when observed in the third direction DR3. In addition, the "thickness direction" may mean the third direction DR3.

[0059] The transmissive area TA may be an optically transparent area. When compared with the transmissive area TA, the border area BZA may be an area having a relatively low light transmittance. The border area BZA may define the shape of the transmissive area TA. The border area BZA may be adjacent to the transmissive area TA and surround the transmissive area TA.

[0060] The border area BZA may have a color (e.g., a set or predetermined color). The border area BZA may cover the peripheral area NAA of the display module 200 to prevent the peripheral area NAA from being visible from the outside. However, this is shown as an example, and according to some embodiments of the present disclosure, the border area BZA may be omitted in the window 100.

[0061] The display module 200 may be positioned below the window 100. The term "below" used herein may mean a direction opposite to the direction in which the display module 200 provides an image. The display module 200 may display the image IM and detect a user input TC. The display module 200 has a front surface IS including an active area AA and a peripheral area NAA. The active area AA may be an area activated in response to an electrical signal.

[0062] According to some embodiments, the active area AA may be an area on which an image IM is displayed, and may also be an area through which a user input TC is detected. The transmissive area TA at least overlaps with the active area AA. For example, the transmissive area TA overlaps with the front surface or at least a part of the active area AA. Thus, the user can see the image IM or provide the user input TC through the transmissive area TA.

[0063] The non-active area NAA may be an area covered by the border area BZA. The non-active area NAA is adjacent to the active area AA (e.g., in the periphery of the active area AA or outside the coverage area of the active area AA). The non-active area NAA may surround the active area AA. A driving circuit, driving lines, or the like for driving the active area AA may be positioned in the non-active area NAA.

[0064] According to some embodiments, the display module 200 is assembled in a flat state in which the active area AA and the non-active area NAA face the window 100. However, this is shown as an example, and a part of the non-active area NAA may be bendable. Here, since a part of the non-active area NAA faces the rear surface of the electronic device DD, the surface area of the border area BZA on the front surface of the electronic device DD may be relatively reduced. Alternatively, the display module 200 may be assembled in a state in which a part of the active area AA is also bendable. Alternatively, according to some embodiments of the present disclosure, the non-active area NAA may be omitted in the display module 200.

[0065] The active area AA of the display module 200 may include a plurality of display areas. The plurality of display areas may have different light transmittances. According to some embodiments, the active area AA of the display module 200 includes a first display area DA1 and a second display area DA2. The second display area DA2 may have a higher light transmittance than the first display area DA1.

[0066] The driving circuit part 300 may be electrically connected to the display module 200. The driving circuit part 300 may include a main circuit board MB and a flexible film CF.

[0067] The flexible film CF is electrically connected to the display module 200. The flexible film CF may be connected to a pad PD positioned in the non-active area NAA of the display module 200. The flexible film CF provides an electrical signal for driving the display module 200. The electrical signal may be generated by the flexible film CF or by the main circuit board MB. The main circuit board MB may include various driving circuits for driving the display module 200, a connector for supplying power, or the like.

[0068] The electronic module 500 may include a first electronic module 501 and a second electronic module 502. The first electronic module 501 and the second electronic module 502 may overlap with the second display area DA2 on a plane (or in a plane view). The first electronic module 501 and the second electronic module 502 may be positioned below the display module 200. The first electronic module 501 and the second electronic module 502 may receive external inputs sent through the second display area DA2, or may output signals through the second display area DA2. That is, since the second display area DA2 has a higher light transmittance than the first display area DA1, the electronic module 500 may easily send and / or receive signals through the second display area DA2.

[0069] The housing 400 is coupled to the window 100. The housing 400 is coupled to the window 100 to provide an internal space (e.g., within the housing 400 and between the bottom surface of the housing 400 and the window 100). The display module 200 and the electronic module 500 may be accommodated in the internal space.

[0070] The housing 400 may include a material having relatively high rigidity. For example, the housing 400 may include glass, plastic, or metal, or include a plurality of frames and / or plates made of a combination thereof. The housing 400 can stably protect the components of the electronic device DD accommodated in the internal space from damage caused by external impacts.

[0071] Referring Figure 2 , the electronic device DD may include a display module 200, a power supply module PM, a first electronic module EM1, and a second electronic module EM2. The display module 200, the power supply module PM, the first electronic module EM1, and the second electronic module EM2 may be electrically connected to each other.

[0072] The display module 200 may include a display panel 210 and an input sensing part 220.

[0073] The display panel 210 may be a component that generates an image IM. The image IM generated by the display panel 210 is displayed on the front surface IS and is visible to the outside of the user through the transmissive area TA in the third direction DR3.

[0074] The input sensing part 220 may detect a user input TC applied from the outside. For example, the input sensing part 220 may detect a user input TC provided to the window 100. The user input TC may include various types of external inputs, such as a part of the user's body (e.g., the user's finger), light, heat, a pen (or stylus), or pressure. In Figure 1AIn this case, the user input TC is shown as the user's hand applied to the front surface FS. However, this is shown as an example, and the user input TC can be provided in various types as described above. The electronic device DD can also detect the user input TC applied to the side surface or the rear surface of the electronic device DD according to the structure of the electronic device DD, but the embodiments according to the present disclosure are not limited to any one embodiment.

[0075] The power supply module PM supplies power required for the overall operation of the electronic device DD. The power supply module PM may include a typical battery module.

[0076] The first electronic module EM1 and the second electronic module EM2 may include various functional modules for operating the electronic device DD.

[0077] The first electronic module EM1 can be directly mounted on the motherboard electrically connected to the display module 200, or mounted on a separate board to be electrically connected to the motherboard through a connector or the like.

[0078] The first electronic module EM1 may include a control module CM, a wireless communication module TM, an image input module IIM, a sound input module AIM, a memory MM, and an external interface IF. Some of the modules can also be electrically connected to the motherboard through a flexible circuit board without being mounted on the motherboard.

[0079] The control module CM controls the overall operation of the electronic device DD. The control module CM can be a microprocessor. For example, the control module CM activates or deactivates the display module 200. The control module CM can control other modules such as the image input module IIM or the sound input module AIM based on the touch signal received from the display module 200.

[0080] The wireless communication module TM can send wireless signals to / receive wireless signals from another terminal using Bluetooth or WiFi channels. The wireless communication module TM can use a general communication channel to send / receive audio signals. The wireless communication module TM may include a transmitter TM1 that modulates and transmits the signal to be sent and a receiver TM2 that demodulates the signal to be received.

[0081] The image input module IIM processes the image signal to convert the image signal into image data that can be displayed on the display module 200. The sound input module AIM receives an external sound signal through a microphone in a recording mode, an audio recognition mode, etc., and converts the external sound signal into electrical audio data.

[0082] The external interface IF can be used as an interface for connecting to an external charger, a wired / wireless data port, a card (e.g., a memory card and a SIM / UIM card) slot, or the like.

[0083] The second electronic module EM2 may include a sound output module AOM, a light emitting module LM, a light receiving module LRM, a camera module CMM, etc. Components may be directly mounted on the motherboard, or mounted on a separate board to be electrically connected to the display module 200 through a connector or the like, or electrically connected to the first electronic module EM1.

[0084] The sound output module AOM converts sound data received from the wireless communication module TM or sound data stored in the memory MM, and outputs the converted result to the outside.

[0085] The light emitting module LM generates and outputs light. The light emitting module LM may output infrared rays. The light emitting module LM may include an LED element. The light receiving module LRM may detect infrared rays. When infrared rays having a certain level (e.g., a set or predetermined level) or a higher level are detected, the light receiving module LRM may be activated. The light receiving module LRM may include a CMOS element. After the infrared light (i.e., infrared rays) generated by the light emitting module LM is output, the infrared light may be reflected by an external object (e.g., a user's finger or face), and the reflected infrared light may be incident on the light receiving module LRM. The camera module CMM may capture an external image.

[0086] Each of the first electronic module 501 and the second electronic module 502 according to some embodiments may include at least one of the components of the first electronic module EM1 and / or the second electronic module EM2. For example, each of the first electronic module 501 and the second electronic module 502 may include at least one of a sound output module AOM, a light emitting module LM, a light receiving module LRM, a camera module CMM, and a thermal detection module. The first electronic module 501 and the second electronic module 502 may detect an external object received through the second display area DA2 (shown in Figure 1B ), or provide a sound signal such as voice or light such as infrared rays to the outside through the second display area DA2.

[0087] Figure 3A is a plan view of a display panel according to some embodiments of the present disclosure.

[0088] Referring to Figure 1B and Figure 3A , a first display area DA1 and a second display area DA2 may be defined in the display panel 210. The first display area DA1 and the second display area DA2 may correspond to the active area AA of the display module 200.

[0089] The electronic module 500 may be positioned below the second display area DA2. The light transmittance of the second display area DA2 may be greater than that of the first display area DA1. Accordingly, the electronic module 500 may transmit and / or receive signals through the second display area DA2. To increase the light transmittance, some components of the second display area DA2 may be omitted. For example, some of the pixels positioned in the second display area DA2 may be removed and / or spaced relatively farther apart.

[0090] The first display area DA1 and the second display area DA2 may be adjacent to each other. The second display area DA2 may have a rectangular shape, and at least one side defining the second display area DA2 may be adjacent to the first display area DA1. Figure 3A Aspects of some embodiments of the present disclosure are shown in which three sides are adjacent to the first display area DA1 and the remaining side is not adjacent to the first display area DA1. However, embodiments according to the present disclosure are not limited thereto. Further, according to some embodiments, when viewed in a plane (or in a plan view), the second display area DA2 may be defined on an upper portion of the display panel 210.

[0091] A first pixel PX1 may be positioned in the first display area DA1, and a second pixel PX2 may be positioned in the second display area DA2. The first pixel PX1 and the second pixel PX2 may be pixels that generate light. The number of the first pixel PX1 and the number of the second pixel PX2 in the same surface area may be different from each other. For example, the number of the second pixel PX2 may be less than the number of the first pixel PX1. Accordingly, the light transmittance of the second display area DA2 may be greater than that of the first display area DA1. Further, the resolution of the second display area DA2 may be less than the resolution of the first display area DA1.

[0092] The first pixel PX1 and the second pixel PX2 may have substantially the same components. Components of the first pixel PX1 and the second pixel PX2 will be described with reference to the accompanying drawings later.

[0093] Figure 3B is a plan view of a display panel according to some embodiments of the present disclosure.

[0094] In the description with reference to Figure 3B the components described with reference to Figure 3A are indicated by like reference numerals, and some repeated descriptions thereof may be omitted.

[0095] With reference to Figure 1B and Figure 3B in the display panel 210, a first display area DA1a and a second display area DA2a may be defined. The electronic module 500 may be positioned below the second display area DA2a. The second display area DA2a may be surrounded by the first display area DA1a.

[0096] Figure 3A and Figure 3B shows an example in which the number of the second display regions DA2a is one, but embodiments according to the present disclosure are not limited thereto. That is, according to some embodiments, two or more second display regions DA2a may be provided. In this case, the two or more second display regions DA2a may have the same light transmittance. However, embodiments according to the present disclosure are not limited thereto. That is, the two or more second display regions DA2a may have different transmittances (e.g., light transmittances) from each other.

[0097] Figure 4A is an enlarged plan view showing a part of a first display region according to some embodiments of the present disclosure. Figure 4B is an enlarged plan view showing a part of a second display region according to some embodiments of the present disclosure. Figure 4C is an enlarged plan view showing a part of a second display region according to some embodiments of the present disclosure.

[0098] Referring to Figure 3A and Figure 4A , a plurality of first pixels PX1 may be positioned in the first display region DA1. The first pixels PX1 may be arranged to be spaced apart from each other in a first direction DR1 and a second direction DR2.

[0099] The plurality of first pixels PX1 may include a plurality of red pixels PX_R1, a plurality of green pixels PX_G1 and PX_G2, and a plurality of blue pixels PX_B1. The plurality of first pixels PX1 may be grouped into a plurality of first pixel groups PG1. For example, each of the first pixel groups PG1 may include one first red pixel PX_R1, two first green pixels PX_G1 and PX_G2, and one first blue pixel PX_B1. Each of the first pixels PX1 in the first pixel group PG1 (e.g., pixel region PXA) may include an emission region EA and a non-emission region NEA. According to some embodiments, the emission region EA may have a rectangular shape, but is not limited thereto. A first light-emitting element LD1 (shown in Figure 5A ) may be positioned in the emission region EA, and transistors T1 to T7 (shown in Figure 5A ) for driving the first light-emitting element LD1 (shown in Figure 5A ) may be positioned in the non-emission region NEA.

[0100] The plurality of first pixel groups PG1 may be positioned in a first region A1 of the first display region DA1. The first region A1 may mean a unit area. For example, the first region A1 may have a surface area of about 1 inch × about 1 inch.

[0101] The first pixel group PG1 may be arranged in a matrix shape within the first region A1. For example, a plurality of first pixel groups PG1 may be arranged to be spaced apart from each other in a first direction DR1 and a second direction DR2.

[0102] The first region A1 in which 18 first pixel groups PG1 are arranged is shown. However, for the convenience of explanation, the first region A1 is merely illustrative and is not limited thereto according to the embodiments of the present disclosure. The number of first pixel groups PG1 located in the first region A1 may be increased.

[0103] Referring to Figure 3A and Figure 4B , a plurality of second pixels PX2 may be located in the second region A2 of the second display area DA2. The second region A2 may include a plurality of pixel regions PXA each having a plurality of second pixels PX2 located therein and a plurality of opening regions OA1. Pixels may be substantially not arranged in the opening regions OA1. That is, the opening regions OA1 may be regions in which some components of the second pixels PX2 (e.g., the second light-emitting element LD2 shown in Figure 5B ) are removed. Therefore, in a unit area, the resolution of the first display area DA1 may be greater than the resolution of the second display area DA2.

[0104] The second pixel PX2 may have the same structure as the first pixel PX1. A plurality of second pixels PX2 may be grouped into a plurality of second pixel groups PG2. For example, each of the second pixel groups PG2 may include one second red pixel PX_R2, two second green pixels PX_G3 and PX_G4, and one second blue pixel PX_B2. Each of the pixel regions PXA may include an emission region EA and a non-emission region NEA. According to some embodiments, the emission region EA may have a rectangular shape, but is not limited thereto. The second light-emitting element LD2 (shown in Figure 5B ) may be located in the emission region EA, and the transistors T1 to T7 (shown in Figure 5B ) for driving the second light-emitting element LD2 may be located in the non-emission region NEA.

[0105] The second region A2 may be defined as a unit area similar to the first region A1. That is, the second region A2 and the first region A1 may have the same surface area.

[0106] Four second pixel groups PG2 may be located in the second region A2. In the second region A2, a portion other than the pixel regions PXA in which the second pixel groups PG2 are located may be defined as the opening regions OA1. Each of the opening regions OA1 may be an optical path through which light provided from the outside is transmitted. Therefore, a sensor located in the second display area DA2 may recognize the light transmitted through the opening regions OA1 to detect user input information.

[0107] In the second region A2, the total surface area of the plurality of pixel regions PXA may be smaller than the total surface area of the plurality of opening regions OA1.

[0108] Referring to Figure 4C , two second pixel groups PG2 may be positioned in the second region A2. In the second region A2, a portion other than the pixel regions PXA in which the second pixel groups PG2 are positioned may be defined as an opening region OA2. Figure 4C The opening region OA2 of the second region A2 shown in Figure 4B may have a larger surface area than the opening region OA1 of the second region A2 shown in

[0109] Figure 5A is an equivalent circuit diagram of a first red pixel according to some embodiments of the present disclosure. Although Figure 5A various components are shown in

[0110] Referring to Figure 5A , the first red pixel PX_R1 may include a plurality of transistors T1 to T7, a capacitor CP, and a first light-emitting element LD1. The plurality of transistors T1 to T7 and the capacitor CP may control the amount of current flowing through the first light-emitting element LD1 in response to a data signal and a scan signal.

[0111] Each of the plurality of transistors T1 to T7 may include an input electrode (or source electrode), an output electrode (or drain electrode), and a control electrode (or gate electrode). For convenience, herein, one of the input electrode and the output electrode is defined as the first electrode, and the other is defined as the second electrode.

[0112] The first electrode of the first transistor T1 may be connected to a driving power line EVDL via a fifth transistor T5. The driving power line EVDL may be a line through which a driving power voltage ELVDD is supplied. The second electrode of the first transistor T1 is connected to the anode of the first light-emitting element LD1 via a sixth transistor T6.

[0113] The first transistor T1 may control the amount of current flowing through the first light-emitting element LD1 according to the voltage applied to the control electrode of the first transistor T1.

[0114] The second transistor T2 may be connected between the data line DL1 and the first electrode of the first transistor T1. The control electrode of the second transistor T2 is connected to the second scan line SLW1. When the second scan signal is provided to the second scan line SLW1, the second transistor T2 may be turned on to electrically connect the data line DL1 to the first electrode of the first transistor T1.

[0115] The third transistor T3 may be connected between the second electrode of the first transistor T1 and the control electrode of the first transistor T1. The control electrode of the third transistor T3 is connected to the second scan line SLW1. When the second scan signal is provided to the second scan line SLW1, the third transistor T3 may be turned on to electrically connect the second electrode of the first transistor T1 to the control electrode of the first transistor T1. Thus, when the third transistor T3 is turned on, the first transistor T1 is diode-connected.

[0116] The fourth transistor T4 is connected between the node ND and the initialization voltage line VIL. The control electrode of the fourth transistor T4 is connected to the first scan line SLI1. The node ND may be the node to which the control electrodes of the fourth transistor T4 and the first transistor T1 are connected. When the first scan signal is provided to the first scan line SLI1, the fourth transistor T4 may be turned on to supply the initialization voltage Vint to the node ND. Here, the first scan signal may be a signal generated earlier than the second scan signal. For example, the first scan signal may be the same signal as the signal applied to the second scan line SLW1 of the pixels in the previous row.

[0117] The fifth transistor T5 may be connected between the driving power line EVDL and the first electrode of the first transistor T1. The sixth transistor T6 may be connected between the second electrode of the first transistor T1 and the anode of the first light-emitting element LD1. The control electrodes of the fifth transistor T5 and the sixth transistor T6 are connected to the first emission control line EL1.

[0118] The seventh transistor T7 is connected between the initialization voltage line VIL and the anode of the first light-emitting element LD1. The control electrode of the seventh transistor T7 is connected to the third scan line SLB1. When the third scan signal is provided to the third scan line SLB1, the seventh transistor T7 may be turned on to supply the initialization voltage Vint to the anode of the first light-emitting element LD1. For example, the third scan signal may be the same signal as the signal applied to the second scan line SLW1 of the pixels in the next row.

[0119] In addition, Figure 5A It is shown that the control electrode of the seventh transistor T7 is connected to the third scan line SLB1, but the embodiments according to the present disclosure are not limited thereto. According to some embodiments, the control electrode of the seventh transistor T7 may be connected to the second scan line SLW1.

[0120] Figure 5A An embodiment is shown in which the first transistor T1 to the seventh transistor T7 are PMOS transistors, but embodiments according to the present disclosure are not limited thereto. According to some embodiments, some or all of the first transistor T1 to the seventh transistor T7 are provided as NMOS transistors.

[0121] The capacitor CP is positioned between the driving power line EVDL and the node ND. The capacitor CP stores a voltage corresponding to the data signal. In response to the voltage stored in the capacitor CP, when the fifth transistor T5 and the sixth transistor T6 are turned on, the amount of current flowing through the first transistor T1 can be determined.

[0122] The first light-emitting element LD1 can be electrically connected to the sixth transistor T6 and the first source power line EVSL1. The first anode of the first light-emitting element LD1 can be connected to the sixth transistor T6, and the first cathode of the first light-emitting element LD1 can be connected to the first source power line EVSL1. The first source power voltage ELVSS1 can be applied to the first source power line EVSL1. The first source power voltage ELVSS1 has a level lower than the driving power voltage ELVDD. Accordingly, the first light-emitting element LD1 can emit light in response to a voltage corresponding to the difference between the signal transmitted through the sixth transistor T6 and the first source power voltage ELVSS1. Herein, the source power voltage may also be simply referred to as the power voltage.

[0123] According to some embodiments, the structure of the first red pixel PX_R1 is not limited to Figure 5A the structure shown therein. According to some embodiments, the first red pixel PX_R1 can be implemented in various forms for allowing the first light-emitting element LD1 to emit light.

[0124] Figure 5B is an equivalent circuit diagram of a second red pixel according to some embodiments of the present disclosure. Although Figure 5B various components are shown therein, embodiments according to the present disclosure are not limited thereto. For example, according to some embodiments, without departing from the spirit and scope of embodiments according to the present disclosure, the second red pixel may include additional components or fewer components.

[0125] Referring to Figure 5A the components described are indicated by like reference numerals or symbols, and their description is omitted.

[0126] Referring to Figure 5A and Figure 5B , the second red pixel PX_R2 may include a plurality of transistors T1 to T7, a capacitor CP, and a second light-emitting element LD2. The plurality of transistors T1 to T7 and the capacitor CP can control the amount of current flowing through the second light-emitting element LD2 in response to a data signal and a scan signal.

[0127] Specifically, different from the first cathode of the first light-emitting element LD1, the second cathode of the second light-emitting element LD2 may be connected to the second source power line EVSL2 to receive the second source power voltage ELVSS2. According to some embodiments, the second source power voltage ELVSS2 may have a voltage level lower than that of the first source power voltage ELVSS1. As an example, when the first source power voltage ELVSS1 is -6V, the second source power voltage ELVSS2 may have a voltage less than -6V, and the second source power voltage ELVSS2 may have a voltage of -6.7V.

[0128] Accordingly, the second light-emitting element LD2 may emit light in response to a voltage corresponding to the difference between the signal transmitted through the sixth transistor T6 and the second source power voltage ELVSS2. That is, even when a signal having the same level as the signal input to the first cathode of the first light-emitting element LD1 is transmitted to the second anode of the second light-emitting element LD2, the driving current of the second light-emitting element LD2 increases due to the difference between the second source power voltage ELVSS2 and the first source power voltage ELVSS1. Accordingly, under the same input signal, the second light-emitting element LD2 may emit light having a higher luminance than the first light-emitting element LD1. As a result, the sharpness of the second display area DA2 may be relatively improved.

[0129] In addition, as described in more detail below, according to some embodiments, the first source power line EVSL1 and the second source power line EVSL2 are separated from the first common cathode CCE1 (see Figure 6 ) and the second common cathode CCE2 (see Figure 6 ) such that the first source power voltage ELVSS1 received by the first light-emitting element LD1 through the first source power line EVSL1 is provided to be different from the second source power voltage ELVSS2 received by the second light-emitting element LD2 through the second source power line EVSL2.

[0130] Accordingly, the first source power line EVSL1 and the second source power line EVSL2 may not be provided integrally to prevent or reduce a voltage loss that occurs when the same source power voltage is supplied to the first light-emitting element LD1 and the second light-emitting element LD2. That is, since the first source power line EVSL1 and the second source power line EVSL2 are separated, a voltage determined in consideration of the voltage drop (IR-DROP) value of the line may be supplied to each of the lines. Accordingly, the power consumption of the electronic device DD (see Figure 1A ) may be relatively reduced.

[0131] For example, when the voltage drop value of the first source power line EVSL1 is greater than the voltage drop value of the second source power line EVSL2, for the second source power voltage ELVSS2 supplied to the second source power line EVSL2, the voltage drop value of the second source power line EVSL2 rather than the voltage drop value of the first source power line EVSL1 may be considered.

[0132] In addition, since separate power lines and cathodes are used, the voltage drop values of some lines can be reduced to reduce the level of the driving voltage supplied to each of the lines. Accordingly, the power consumption of the electronic device DD (see Figure 1A ) can be further relatively reduced.

[0133] Figure 6 is a plan view of a display panel according to some embodiments of the present disclosure. For example, Figure 6 is a plan view showing a line layout of a display panel according to some embodiments of the present disclosure.

[0134] Referring to Figure 6 , the active area AA of the display panel 210 may be an area where an image is displayed, and its peripheral area NAA may be an area where a driving circuit, driving lines, or the like are positioned. In Figure 6 , the active area AA of the display panel 210 includes a first display area DA1 and a second display area DA2.

[0135] According to some embodiments, the second display area DA2 may be surrounded by the first display area DA1, but the embodiments according to the present disclosure are not limited to the embodiments shown in the drawings. For example, only a part of the second display area DA2 may be surrounded by the first display area DA1, and the remaining part may be surrounded by the peripheral area NAA. However, the embodiments according to the present disclosure are not limited thereto.

[0136] In addition, the second display area DA2 is shown as having a rectangular shape in the drawings, but the embodiments according to the present disclosure are not limited thereto. For example, the second display area DA2 may have a circular shape, an oval shape, another polygonal shape, an irregular shape, and the like.

[0137] The first common cathode CCE1 is positioned in the first display area DA1, and the second common cathode CCE2 is positioned in the second display area DA2. The first common cathode CCE1 and the second common cathode CCE2 may be arranged to be spaced apart from each other and electrically insulated.

[0138] The first common cathode CCE1 may be defined by connecting Figure 3A and Figure 5AAn electrode provided by commonly connecting the first cathodes of the first light-emitting elements LD1 provided in the first pixel PX1 as shown. That is, the first cathodes of the plurality of first light-emitting elements LD1 can be provided integrally and provided in the form of a single body electrode like the second common cathode CCE2.

[0139] The second common cathode CCE2 can be defined as an electrode provided by commonly connecting the second cathodes of the second light-emitting elements LD2 provided in the second pixel PX2 as shown in Figure 3A and Figure 5B That is, the second cathodes of the plurality of second light-emitting elements LD2 can be provided integrally and provided in the form of a single body electrode like the second common cathode CCE2.

[0140] The first common cathode CCE1 and the second common cathode CCE2 can overlap each other in the second display area DA2. However, the embodiments according to the present disclosure are not limited thereto. For example, the second common cathode CCE2 can extend to the first display area DA1 so that the first common cathode CCE1 and the second common cathode CCE2 also overlap each other in the first display area DA1.

[0141] The first source power line EVSL1 electrically connected to the first common cathode CCE1 and the second source power line EVSL2 electrically connected to the second common cathode CCE2 are located in the peripheral area NAA. The first source power line EVSL1 and the second source power line EVSL2 can be arranged to surround three sides of the active area AA. The pads extending from both ends of each of the first source power line EVSL1 and the second source power line EVSL2 can be located in the peripheral area NAA where the pad PD (shown in Figure 1B ) is located.

[0142] As shown in Figure 6 , the first source power line EVSL1 can be located inside the second source power line EVSL2. That is, the phrase "located inside" used herein means that the first source power line EVSL1 is arranged to be more adjacent to the active area AA than the second source power line EVSL2.

[0143] According to some embodiments, the first source power line EVSL1 is electrically connected to the first common cathode CCE1 through the first power assist line SEVSL1 (see Figure 9A ), and the second source power line EVSL2 is electrically connected to the second common cathode CCE2 through the second power assist line SEVSL2 (see Figure 9A ).

[0144] The first power assist line SEVSL1 (see Figure 9A) can branch from the first source power line EVSL1 to extend to one side of the first display area DA1. The second power assist line SEVSL2 (see Figure 9A ) can branch from the second source power line EVSL2 to extend to one side of each of the first display area DA1 and the second display area DA2.

[0145] According to some embodiments, the second power assist line SEVSL2 (see Figure 9A ) can branch from a position of the second source power line EVSL2 so as to have a minimum distance from the second source power line EVSL2 to the second display area DA2. Further, the second power assist line SEVSL2 (see Figure 9A ) can extend in a direction in which the second source power line EVSL2 has a minimum distance to the second display area DA2.

[0146] That is, the second power assist line SEVSL2 (see Figure 9A ) can extend across the first display area DA1 such that the distance between the second display area DA2 and the peripheral area NAA is the minimum distance. However, the embodiments according to the present disclosure are not limited thereto. For example, the second power assist line SEVSL2 (see Figure 9A ) can extend in different directions.

[0147] The length and the extending direction of the second power assist line SEVSL2 (see Figure 9A ) can be changed according to the shape of the second display area DA2 based on the product design and the distance between the second display area DA2 and the peripheral area NAA. However, the embodiments according to the present disclosure are not limited thereto.

[0148] The first power assist line SEVSL1 (see Figure 9A ) can include a left power assist line and a right power assist line separated based on the second display area DA2. The first power assist line SEVSL1 (see Figure 9A ) and the second power assist line SEVSL2 (see Figure 9A ) are arranged to be spaced apart from each other and are electrically insulated from each other.

[0149] The number of the first power assist line SEVSL1 (see Figure 9A ) and the number of the second power assist line SEVSL2 (see Figure 9A ) are each not limited to the number shown in the drawings and can be less than or greater than the number shown in the drawings. However, the embodiments according to the present disclosure are not limited to any one embodiment.

[0150] As Figure 6As shown, the first common cathode CCE1 may overlap with the first display area DA1 and the second display area DA2. In addition, the first common cathode CCE1 may extend to the peripheral area NAA. The second common cathode CCE2 may overlap with the second display area DA2. In addition, the second common cathode CCE2 may overlap with the first display area DA1 and extend to the peripheral area NAA. However, the embodiments according to the present disclosure are not limited to Figure 6 the embodiments shown. For example, the first common cathode CCE1 may not overlap with the peripheral area NAA, and the second common cathode CCE2 may not overlap with the first display area DA1. The embodiments according to the present disclosure are not limited to any one embodiment.

[0151] Figures 7A to 7D is a cross-sectional view of a display panel according to some embodiments of the present disclosure. For example, Figure 7A is a cross-sectional view taken along the line I-I' shown in Figure 6 , Figure 7B is a cross-sectional view taken along the line II-II' shown in Figure 6 , and Figure 7C and Figure 7D is a cross-sectional view taken along the line III-III' shown in Figure 6 .

[0152] Referring together to Figure 7A and Figure 7B , the display panel 210 includes a base layer BS, a circuit element layer DP-CL, a light-emitting element layer DP-EDL, and a thin film encapsulation layer TFE. According to some embodiments, the base layer BS, the circuit element layer DP-CL, the light-emitting element layer DP-EDL, and the thin film encapsulation layer TFE may be sequentially stacked in the third direction DR3.

[0153] The base layer BS may be a member providing a base surface on which the circuit element layer DP-CL is positioned. The base layer BS may be a glass substrate, a metal substrate, a plastic substrate, or the like. However, the embodiments according to the present disclosure are not limited thereto, and the base layer BS may be an inorganic layer, an organic layer, or a composite material layer.

[0154] The circuit element layer DP-CL is positioned on the base layer BS. The circuit element layer DP-CL may include first to seventh transistors T1 to T7 (see Figure 5A and Figure 5B ), a capacitor CP (see Figure 5A and Figure 5B ), and the like. For convenience of explanation, Figure 7A and Figure 7B only one transistor PX-TR (hereinafter referred to as a pixel transistor) is shown. Here, the pixel transistor PX-TR may be with reference to Figure 5A andFigure 5B The described sixth transistor T6.

[0155] The circuit element layer DP-CL and the light-emitting element layer DP-EDL include a first insulating layer 10, a second insulating layer 20, a third insulating layer 30, a fourth insulating layer 40, a fifth insulating layer 50, and a sixth insulating layer 60 stacked in a third direction DR3. The first insulating layer 10 is positioned on the base layer BS. The first insulating layer 10 may include a barrier layer 11 and a buffer layer 12.

[0156] The barrier layer 11 may include an inorganic material. The barrier layer 11 may prevent or reduce the infiltration of oxygen or moisture introduced through the base layer BS into the first pixel PX1 (see Figure 3A ) and the second pixel PX2 (see Figure 3A ). The buffer layer 12 may include an inorganic material. The buffer layer 12 may supply a surface energy lower than that of the base layer BS to the first pixel PX1 and the second pixel PX2, so that the first pixel PX1 and the second pixel PX2 are stably provided on the base layer BS. In Figure 7A and Figure 7B , each of the barrier layer 11 and the buffer layer 12 is shown as a single layer. However, this is shown as an example, and each of the barrier layer 11 and the buffer layer 12 according to some embodiments of the present disclosure may be provided as multiple layers to be alternately stacked. Alternatively, one of the barrier layer 11 and the buffer layer 12 may be provided as multiple layers, or may be omitted.

[0157] The pixel transistor PX-TR may be positioned on the first insulating layer 10. The pixel transistor PX-TR includes a semiconductor pattern SP and a control electrode CE. The semiconductor pattern SP is positioned on the first insulating layer 10. The semiconductor pattern SP may include a semiconductor material. The semiconductor pattern SP may include a channel portion CHA, a source portion SSA, and a drain portion DDA. The semiconductor pattern SP may be covered by the second insulating layer 20, and the control electrode CE may be positioned on the second insulating layer 20. The control electrode CE is positioned on the second insulating layer 20 corresponding to the channel portion CHA of the semiconductor pattern SP. That is, the control electrode CE and the channel portion CHA of the semiconductor pattern SP are spaced apart from each other by the second insulating layer 20. The control electrode CE may be connected to one electrode of the capacitor CP.

[0158] The source portion SSA and the drain portion DDA of the semiconductor pattern SP may be spaced apart from each other with the channel portion CHA interposed therebetween. The source portion SSA of the semiconductor pattern SP may be utilized as the input electrode of the pixel transistor PX-TR, and the drain portion DDA of the semiconductor pattern SP may be utilized as the output electrode of the pixel transistor PX-TR.

[0159] The third insulating layer 30 is positioned on the control electrode CE and the second insulating layer 20. The second insulating layer 20 and the third insulating layer 30 may be provided with contact holes for exposing the drain portion DDA of the semiconductor pattern SP. A first connection electrode CNE1 connected to the drain portion DDA through the contact hole may be positioned on the third insulating layer 30. According to some embodiments, in Figure 7A the pixel transistor PX-TR may further include an input electrode and an output electrode respectively connected to the source portion SSA and the drain portion DDA of the semiconductor pattern SP.

[0160] The fourth insulating layer 40 is positioned on the third insulating layer 30. The fourth insulating layer 40 may include an organic material and / or an inorganic material, and may have a single-layer structure or a stacked structure.

[0161] A second connection electrode CNE2 may be positioned on the fourth insulating layer 40. The second connection electrode CNE2 may be connected to the first connection electrode CNE1. A fifth insulating layer 50 may be positioned on the second connection electrode CNE2.

[0162] The pixel transistor PX-TR according to some embodiments may be provided in various structures and is not limited to the embodiments shown in Figure 7A and Figure 7B the embodiments shown.

[0163] The light-emitting element layer DP-EDL is positioned on the circuit element layer DP-CL. The light-emitting element layer DP-EDL may include a plurality of light-emitting elements.

[0164] A first light-emitting element LD1 among the plurality of light-emitting elements is positioned on the fifth insulating layer 50. The first light-emitting element LD1 may include a first anode AE1, an emission layer EL, and a first common cathode CCE1. The first anode AE1 may pass through the fifth insulating layer 50 to be electrically connected to the pixel transistor PX-TR through the second connection electrode CNE2.

[0165] A sixth insulating layer 60 may be positioned on the fifth insulating layer 50. A pixel opening PX_OP may be defined in the sixth insulating layer 60, and the pixel opening PX_OP may expose at least a part of the first anode AE1. The sixth insulating layer 60 may be a pixel defining film.

[0166] The emission layer EL may be positioned on the first anode AE1 exposed by the pixel opening PX_OP defined in the sixth insulating layer 60. The emission layer EL may include a light-emitting material. For example, the emission layer EL may include at least one of materials that emit light having red, green, or blue. The emission layer EL may include a fluorescent material or a phosphorescent material. The emission layer EL may include an organic light-emitting material or an inorganic light-emitting material. The emission layer EL may emit light in response to the potential difference between the first anode AE1 and the first common cathode CCE1.

[0167] The first common cathode CCE1 may be positioned on the emission layer EL. The first common cathode CCE1 may be commonly provided in a plurality of first pixels PX1. The first common cathode CCE1 may have a shape corresponding to the first display area DA1. The first common cathode CCE1 may be electrically connected to the first source power line EVSL1 positioned in the peripheral area NAA.

[0168] A cathode insulating layer CCE-IL may be positioned on the first common cathode CCE1. The cathode insulating layer CCE-IL may be positioned between the first common cathode CCE1 and the second common cathode CCE2. For example, the cathode insulating layer CCE-IL may be positioned on the first common cathode CCE1 on the first display area DA1. In addition, the cathode insulating layer CCE-IL may be positioned on the second common cathode CCE2 in the second display area DA2 (see Figure 6 ).

[0169] The cathode insulating layer CCE-IL may have a shape corresponding to the first display area DA1. However, the embodiments according to the present disclosure are not limited thereto. For example, the cathode insulating layer CCE-IL may have a shape covering the whole of the second display area DA2 and a part of the first display area DA1, but the embodiments according to the present disclosure are not limited thereto.

[0170] The cathode insulating layer CCE-IL may separate the first common cathode CCE1 and the second common cathode CCE2 from each other so that the first common cathode CCE1 and the second common cathode CCE2 are electrically insulated from each other.

[0171] The second common cathode CCE2 may be positioned on the cathode insulating layer CCE-IL. The second common cathode CCE2 will be described in detail later.

[0172] According to some embodiments of the present disclosure, the first source power line EVSL1 and the first connection electrode CNE1 are positioned in the same layer. When the pixel transistor PX-TR includes an input electrode and an output electrode, the first source power line EVSL1 is positioned in the same layer as the input electrode and the output electrode of the pixel transistor PX-TR. Each of the fourth insulating layer 40 and the fifth insulating layer 50 is provided with a first contact portion 41 and a second contact portion 51 for exposing the first source power line EVSL1. The first contact portion 41 and the second contact portion 51 may be defined as areas where the fourth insulating layer 40 and the fifth insulating layer 50 are open to a region corresponding to the first source power line EVSL1.

[0173] A first bridging electrode BE11 is positioned on the first source power line EVSL1 exposed through the first contact portion 41 and the second contact portion 51. The first bridging electrode BE11 may be the above-mentioned first power assist line SEVSL1 (see Figure 9A) portion. The first bridging electrode BE11 may include a first sub - bridging electrode BE11_1 and a second sub - bridging electrode BE11_2.

[0174] The first sub - bridging electrode BE11_1 is positioned on the first source power line EVSL1 and the fourth insulating layer 40. That is to say, the first sub - bridging electrode BE11_1 and the second connection electrode CNE2 may be positioned in the same layer. The first sub - bridging electrode BE11_1 is in direct contact with the first source power line EVSL1 exposed through the first contact portion 41.

[0175] The second sub - bridging electrode BE11_2 is positioned on the first sub - bridging electrode BE11_1 and the fifth insulating layer 50. That is to say, the second sub - bridging electrode BE11_2 and the first anode AE1 may be positioned in the same layer. The second sub - bridging electrode BE11_2 is in direct contact with the first sub - bridging electrode BE11_1 exposed through the second contact portion 51.

[0176] In a plane (or in a plane view), the first source power line EVSL1 partially overlaps with the first bridging electrode BE11, and the first common cathode CCE1 partially overlaps with the first bridging electrode BE11. The first common cathode CCE1 may overlap with the first bridging electrode BE11 in the peripheral area NAA.

[0177] According to some embodiments of the present disclosure, the fifth insulating layer 50 may be omitted. In the structure in which the fifth insulating layer 50 is omitted, the first bridging electrode BE11 may only include the second sub - bridging electrode BE11_2. In this case, the second sub - bridging electrode BE11_2 may be in direct contact with the first source power line EVSL1.

[0178] The sixth insulating layer 60 is provided with a third contact portion 61 for exposing the second sub - bridging electrode BE11_2. The first common cathode CCE1 positioned on the sixth insulating layer 60 may be in direct contact with the second sub - bridging electrode BE11_2 in the third contact portion 61.

[0179] As Figure 7A shown, between the first source power line EVSL1 and the first display area DA1, there may be positioned the first scan line SLI1, the second scan line SLW1, and the third scan line SLB1 of the first pixel PX1 and the second pixel PX2 (see Figure 5A and Figure 5B)The connected scan driver GDC. That is, the first source power line EVSL1 and the second source power line EVSL2 can be located outside the scan driver GDC. Here, the phrase "located outside..." means that the first source power line EVSL1 and the second source power line EVSL2 are located farther from the active area AA than the scan driver GDC. The scan driver GDC may include a signal line GDC-SL and a transistor GDC-TR for driving.

[0180] Referring to Figure 7C , the second light-emitting element LD2 is located on the fifth insulating layer 50. The second light-emitting element LD2 may include a second anode AE2, an emission layer EL, and a second common cathode CCE2. The second anode AE2 may pass through the fifth insulating layer 50 to be electrically connected to the pixel transistor PX-TR through the second connection electrode CNE2. The emission layer EL may emit light in response to the potential difference between the second anode AE2 and the second common cathode CCE2.

[0181] Figure 7D Illustrated is a case where the second light-emitting element LD2 is different from that shown in Figure 7C according to some embodiments of the present disclosure and the second light-emitting element LD2 is dummy. Referring to Figure 7D , the second anode AE2 may be electrically insulated from the pixel transistor PX-TR (see Figure 7C ).

[0182] Referring to Figure 7C and Figure 7D , the second common cathode CCE2 may be located on the cathode insulating layer CCE-IL. The second common cathode CCE2 may be located on the cathode insulating layer CCE-IL to be electrically insulated from the first common cathode CCE1.

[0183] In addition, the second common cathode CCE2 may be located on the emission layer EL. The second common cathode CCE2 may be provided commonly in a plurality of second pixels PX2 (shown in Figure 3A ). The second common cathode CCE2 may have a shape corresponding to the second display area DA2. However, the embodiments of the present disclosure are not limited thereto. For example, the second common cathode CCE2 may have a shape corresponding to the whole of the second display area DA2 and a part of the first display area DA1, but is not limited thereto according to the embodiments of the present disclosure. The second common cathode CCE2 may be electrically connected to the second source power line EVSL2 located in the peripheral area NAA.

[0184] According to some embodiments of the present disclosure, before forming the second common cathode CCE2, the first common cathode CCE1 may be formed, and then a portion of the first common cathode CCE1 that overlaps with the emission layer EL of the second light-emitting element LD2 may be removed. Thereafter, a cathode insulating layer CCE-IL and the second common cathode CCE2 may be formed. Here, the first common cathode CCE1 may be removed by a laser drilling method, and the embodiments according to the present disclosure are not limited thereto.

[0185] However, the embodiments according to the present disclosure are not limited thereto. For example, after forming the first common cathode CCE1 and the cathode insulating layer CCE-IL, a portion of the first common cathode CCE1 and a portion of the cathode insulating layer CCE-IL that each overlap with the emission layer EL of the second light-emitting element LD2 may be removed to form the second common cathode CCE2 thereon, and the embodiments according to the present disclosure are not limited to any one embodiment.

[0186] According to some embodiments of the present disclosure, the second source power line EVSL2 and the first connection electrode CNE1 are located in the same layer. Each of the fourth insulating layer 40 and the fifth insulating layer 50 is provided with a fourth contact portion 42 and a fifth contact portion 52 for exposing the second source power line EVSL2. The fourth contact portion 42 and the fifth contact portion 52 may be defined as regions where the fourth insulating layer 40 and the fifth insulating layer 50 are open corresponding to the second source power line EVSL2.

[0187] A second bridging electrode BE2 is located on the second source power line EVSL2 exposed through the fourth contact portion 42 and the fifth contact portion 52. The second bridging electrode BE2 may be a portion of the second power assist line SEVSL2 (see Figure 9A ). The second bridging electrode BE2 includes a third sub-bridging electrode BE2_1 and a fourth sub-bridging electrode BE2_2.

[0188] The third sub-bridging electrode BE2_1 is located on the second source power line EVSL2 and the fourth insulating layer 40. That is, the third sub-bridging electrode BE2_1 and the second connection electrode CNE2 may be located in the same layer. The third sub-bridging electrode BE2_1 is in direct contact with the second source power line EVSL2 exposed through the fourth contact portion 42.

[0189] The fourth sub-bridging electrode BE2_2 is located on the third sub-bridging electrode BE2_1 and the fifth insulating layer 50. That is, the fourth sub-bridging electrode BE2_2 and the second anode AE2 may be located in the same layer. The fourth sub-bridging electrode BE2_2 may be in direct contact with the third sub-bridging electrode BE2_1 exposed through the fifth contact portion 52.

[0190] On a plane (or in a plane view), a second source power line EVSL2 partially overlaps with a second bridging electrode BE2, and a second common cathode CCE2 partially overlaps with the second bridging electrode BE2. The second bridging electrode BE2 may also partially overlap with a first source power line EVSL1 in a region adjacent to the second display area DA2. The second common cathode CCE2 may overlap with the second bridging electrode BE2 in the peripheral area NAA.

[0191] According to some embodiments of the present disclosure, the fifth insulating layer 50 may be omitted. In a structure in which the fifth insulating layer 50 is omitted, the second bridging electrode BE2 may include only a fourth sub-bridging electrode BE2_2. In this case, the fourth sub-bridging electrode BE2_2 may be in direct contact with the second source power line EVSL2.

[0192] A sixth insulating layer 60 is provided with a sixth contact portion for exposing the fourth sub-bridging electrode BE2_2. The second common cathode CCE2 positioned on the sixth insulating layer 60 may be in direct contact with the fourth sub-bridging electrode BE2_2 in the sixth contact portion.

[0193] As Figure 7C shown, the scan driver GDC may not be positioned between the first source power line EVSL1 and the first display area DA1.

[0194] In addition, as Figure 4B and Figure 7C shown, the pixel transistor PX-TR and the second light-emitting element LD2 may not be positioned in the opening area OA1 of the second display area DA2. Only the base layer BS and the first insulating layer 10 to the sixth insulating layer 60 may be present in the opening area OA1. The second common cathode CCE2 may be removed or retained in the opening area OA1. In Figure 7C , the opening area OA may correspond to Figure 4B the opening area OA1 in Figure 4C and either the opening area OA2 in

[0195] Referring to Figures 7A to 7D , a thin film encapsulation layer TFE may be positioned on the light-emitting element layer DP-EDL to seal the first light-emitting element LD1 and the second light-emitting element LD2. The thin film encapsulation layer TFE may entirely cover the active area AA. The thin film encapsulation layer TFE may cover a partial area of the peripheral area NAA.

[0196] The thin film encapsulation layer TFE may include a first inorganic layer 71, an organic layer 72, and a second inorganic layer 73 stacked in a third direction DR3. In Figures 7A to 7DIn [the figure], each of the first inorganic layer 71, the organic layer 72, and the second inorganic layer 73 is shown as a single layer. However, this is shown as an example. For example, at least one of the first inorganic layer 71, the organic layer 72, and the second inorganic layer 73 may be provided as multiple layers or omitted, and the embodiments according to the present disclosure are not limited to any one embodiment.

[0197] The first inorganic layer 71 may cover the first common cathode CCE1 and the second common cathode CCE2. The first inorganic layer 71 may prevent or reduce the infiltration of contaminants such as external moisture or oxygen into the first light-emitting element LD1 and the second light-emitting element LD2. For example, the first inorganic layer 71 may include silicon nitride, silicon oxide, or a compound as a composition thereof. The first inorganic layer 71 may be formed by a deposition process.

[0198] The organic layer 72 may be positioned on the first inorganic layer 71 in contact with the first inorganic layer 71. The organic layer 72 may provide a flat surface on the first inorganic layer 71. For example, the organic layer 72 may provide a flat surface.

[0199] The unevenness formed on the top surface of the first inorganic layer 71, particles present on the first inorganic layer 71, or similar situations may be covered by the organic layer 72 to block the influence of the surface state of the top surface of the first inorganic layer 71 on the components formed on the organic layer 72. In addition, the organic layer 72 may relieve the stress between the layers in contact with each other. The organic layer 72 may include an organic substance and may be formed by a solution process such as spin coating, slot coating, or inkjet printing.

[0200] The second inorganic layer 73 is positioned on the organic layer 72 to cover the organic layer 72. The second inorganic layer 73 may be formed more stably on a relatively flat surface compared to when it is positioned on the first inorganic layer 71. The second inorganic layer 73 may seal the moisture or the like discharged from the organic layer 72 to prevent or reduce the introduction of moisture to the outside. The second inorganic layer 73 may include silicon nitride, silicon oxide, or a compound as a composition thereof. The second inorganic layer 73 may be formed by a deposition process.

[0201] The display panel 210 may further include a first dam portion DMP1 and a second dam portion DMP2 positioned in the peripheral area NAA. As Figure 7A and Figure 7B shown, the first dam portion DMP1 and the second dam portion DMP2 may have a multilayer structure. The second dam portion DMP2 may be positioned outside the first dam portion DMP1. The first dam portion DMP1 includes a first lower dam DM1-L, a first intermediate dam DM1-M, and a first upper dam DM1-U. The second dam portion DMP2 includes a second lower dam DM2-L, a second intermediate dam DM2-M, and a second upper dam DM2-U.

[0202] The first lower dam DM1-L and the second lower dam DM2-L may be formed synchronously with the fifth insulating layer 50. The first intermediate dam DM1-M and the second intermediate dam DM2-M are respectively provided on the first lower dam DM1-L and the second lower dam DM2-L. The first intermediate dam DM1-M and the second intermediate dam DM2-M may be formed synchronously with the sixth insulating layer 60. The first upper dam DM1-U and the second upper dam DM2-U are respectively provided on the first intermediate dam DM1-M and the second intermediate dam DM2-M.

[0203] The first dam portion DMP1 and the second dam portion DMP2 may be provided in a closed-loop shape to the peripheral region NAA so as to surround the active region AA. Thus, during the formation of the organic layer 72 of the thin film encapsulation layer TFE, the first dam portion DMP1 and the second dam portion DMP2 prevent or reduce the diffusion of the liquid organic material to the outside. The organic layer 72 may be formed by coating a liquid organic material on the first inorganic layer 71 using an inkjet method. Here, the first dam portion DMP1 and the second dam portion DMP2 may set the boundary of the region where the liquid organic material is located.

[0204] According to some embodiments of the present disclosure, the first dam portion DMP1 may partially overlap with the first source power line EVSL1. Figure 7A and Figure 7B A structure in which two dam portions DMP1 and DMP2 are provided is shown, but the embodiments according to the present disclosure are not limited thereto. That is, the display panel 210 may provide only one of the first dam portion DMP1 and the second dam portion DMP2. In addition, Figure 7A and Figure 7B A structure in which the first dam portion DMP1 and the second dam portion DMP2 are spaced apart from each other is shown, but the embodiments according to the present disclosure are not limited thereto. For example, the first dam portion DMP1 and the second dam portion DMP2 may be connected to each other. In addition, a structure in which each of the first dam portion DMP1 and the second dam portion DMP2 has a three-layer film structure is shown, but each of the first dam portion DMP1 and the second dam portion DMP2 may have a two-layer structure.

[0205] Figures 6 to 7D A structure in which the first source power line EVSL1 and the second source power line EVSL2 do not overlap with each other in a plane (or in a plan view) is shown. That is, the first source power line EVSL1 and the second source power line EVSL2 are located in the same layer and are arranged to be spaced apart from each other in a plane (or in a plan view). However, the embodiments according to the present disclosure are not limited thereto. That is, the first source power line EVSL1 and the second source power line EVSL2 may be located in different layers from each other and are arranged to overlap with each other in a plane (or in a plan view).

[0206] Figure 8is a plan view of a display panel according to some embodiments of the present disclosure. For example, Figure 8 is a plan view showing a line layout of a display panel showing some embodiments different from the embodiments described with reference to Figure 6 In the description with reference to Figure 8 the components described with reference to Figures 6 to 7D are indicated by similar reference numerals, and their descriptions are omitted.

[0207] With reference to Figure 8 , the active area AA of the display panel 210 includes a first display area DA1 and a second display area DA2. A first common cathode CCE1 is positioned in the first display area DA1, and a second common cathode CCE2 is positioned in the second display area DA2. The first common cathode CCE1 and the second common cathode CCE2 may be arranged to be spaced apart from each other and electrically insulated.

[0208] The first common cathode CCE1 may be defined as an electrode provided by commonly connecting the first cathodes of the first light-emitting elements LD1 provided in the first pixel PX1 shown in Figure 3A and Figure 5A . That is, the first cathodes of the first light-emitting elements LD1 may be provided integrally to be provided in the form of a single body electrode like the first common cathode CCE1.

[0209] The second common cathode CCE2 may be defined as an electrode provided by commonly connecting the second cathodes of the second light-emitting elements LD2 provided in the second pixel PX2 shown in Figure 3A and Figure 5A . That is, the second cathodes of the second light-emitting elements LD2 may be provided integrally to be provided in the form of a single body electrode like the second common cathode CCE2.

[0210] A first source power line EVSL1 electrically connected to the first common cathode CCE1 and a second source power voltage ELVSS2 electrically connected to the second common cathode CCE2 are positioned in the peripheral area NAA. The first source power line EVSL1 and the second source power line EVSL2 may be arranged to surround three sides of the active area AA. Pads extending from both ends of each of the first source power line EVSL1 and the second source power line EVSL2 may be positioned in the peripheral area NAA where the pads PD (shown in Figure 1B ) of the display panel 210 are positioned.

[0211] The first source power line EVSL1 may be positioned inside the second source power line EVSL2. The first source power line EVSL1 is electrically connected to the first common cathode CCE1, and the second source power line EVSL2 is electrically connected to the second common cathode CCE2.

[0212] Different from the display panel 210 according to some embodiments as shown in Figure 6 , the display panel 210 according to some embodiments as shown in Figure 8 may include a second display area DA2 having a circular shape in a plane (or in a plan view). The second display area DA2 may be surrounded by the first display area DA1.

[0213] The first common cathode CCE1 may overlap with the first display area DA1 and the second display area DA2. The second common cathode CCE2 may overlap with the second display area DA2. In addition, the second common cathode CCE2 may overlap with the first display area DA1.

[0214] Figure 9A is an enlarged plan view of a part of a display panel according to some embodiments of the present disclosure. Figure 9B and Figure 9C is an enlarged cross-sectional view of a part of a display panel according to some embodiments of the present disclosure. For example, Figure 9A is a schematic plan view showing some of the lines overlapping with the first display area and the second display area according to some embodiments of the present disclosure. Figure 9B is along Figure 9A the cross-sectional view taken along the line IV-IV' shown in Figure 9C is a cross-sectional view of a display panel according to some embodiments different from the embodiments shown and described with reference to Figure 9B For example,

[0215] Referring to Figure 9A and Figure 9B , the display panel 210 according to some embodiments (see Figure 6 ) may include a first power part and a second power part.

[0216] The first power part may supply a first power voltage to the first common cathode CCE1. The first power part may include a first source power line EVSL1 and a first power auxiliary line SEVSL1. The first source power line EVSL1 may be located in the peripheral area NAA (see Figure 6 ). The first power auxiliary line SEVSL1 may branch from the first source power line EVSL1. The first power auxiliary line SEVSL1 may extend into the first display area DA1 in the peripheral area NAA (see Figure 6 ). The first power auxiliary line SEVSL1 may be electrically connected to the first common cathode CCE1.

[0217] The second power part may supply a second power voltage to the second common cathode CCE2. According to some embodiments, the second power voltage may have a voltage level lower than that of the first power voltage.

[0218] The second power part may include a second source power line EVSL2 and a second auxiliary power line SEVSL2. The second source power line EVSL2 may be positioned in the peripheral area NAA (see Figure 6 ). The second auxiliary power line SEVSL2 may branch from the second source power line EVSL2. The second auxiliary power line SEVSL2 may extend in the peripheral area NAA (see Figure 6 ) to the first display area DA1 and the second display area DA2. The second auxiliary power line SEVSL2 may be electrically connected to the second cathode (e.g., the second common cathode CCE2).

[0219] In the first display area DA1, a first pixel group PG1 may be positioned. The first pixel group PG1 may be provided as a plurality. The first pixel group PG1 may be electrically connected to the first auxiliary power line SEVSL1 in the first display area DA1. As shown in the drawings, the first pixel group PG1 may overlap with the first auxiliary power line SEVSL1.

[0220] In the second display area DA2, a second pixel group PG2 may be positioned. The second pixel group PG2 may be provided as a plurality. The second pixel group PG2 may be electrically connected to the second auxiliary power line SEVSL2 in the second display area DA2. As shown in the drawings, the second pixel group PG2 may overlap with the second auxiliary power line SEVSL2.

[0221] As shown in the drawings, the first auxiliary power line SEVSL1 and the second auxiliary power line SEVSL2 may be provided with a mesh pattern. However, the embodiments according to the present disclosure are not limited thereto. For example, only one auxiliary power line may be provided with a mesh pattern, and the embodiments according to the present disclosure are not limited to any one embodiment.

[0222] In the second display area DA2, a dummy pixel group PG2_DM may be positioned. The dummy pixel group PG2_DM may include a plurality of dummy pixels. The dummy pixel group PG2_DM may be provided as a plurality. Different from the second pixel group PG2, the dummy pixel group PG2_DM may not be electrically connected to a transistor, but is not limited thereto. For example, the dummy pixel group PG2_DM may also be electrically connected to a transistor like the second pixel group PG2, and the embodiments according to the present disclosure are not limited to any one embodiment.

[0223] The first common cathode CCE1 may overlap with the first display area DA1 and the second display area DA2. The first common cathode CCE1 may overlap with the first pixel group PG1 and the second pixel group PG2.

[0224] The second common cathode CCE2 may overlap with the second display area DA2. The second common cathode CCE2 may overlap with the second pixel group PG2 and the dummy pixel group PG2_DM. The second common cathode CCE2 may be spaced apart from the first display area DA1. However, embodiments according to the present disclosure are not limited thereto. For example, the second common cathode CCE2 may also overlap with a part of the first display area DA1, and embodiments according to the present disclosure are not limited to any one embodiment.

[0225] Holes HH may be positioned in the second display area DA2. The holes HH may be positioned in the dummy pixel group PG2_DM. The holes HH may overlap with the dummy pixels of the dummy pixel group PG2_DM in a plane (or in a plan view). However, embodiments according to the present disclosure are not limited thereto. For example, the holes HH may be positioned in an area of the second display area DA2 that does not overlap with the second pixels and the dummy pixels, and embodiments according to the present disclosure are not limited to any one embodiment.

[0226] When the holes HH are positioned in an area that does not overlap with the dummy pixels or the second pixels, the empty areas of the first display area DA1 and the second display area DA2 may be utilized. Therefore, the integration degree of components in the display panel 210 (see Figure 6 ) may be improved, and the display panel 210 (see Figure 6 ) may be capable of having an ultra-small size.

[0227] The holes HH may be provided as multiple. According to some embodiments, at least some of the holes HH may overlap with the second power assist line SEVSL2 in a plane (or in a plan view).

[0228] Some of the holes HH may be positioned at the edge of the first display area DA1 in a plane (or in a plan view). That is, some of the holes HH may be arranged adjacent to the first display area DA1. Alternatively, the holes HH may be arranged along the edge of the second display area DA2.

[0229] Referring to Figure 9B , the first power assist line SEVSL1 and the second power assist line SEVSL2 may be positioned on the fifth insulating layer 50. The first common cathode CCE1 may be positioned on the sixth insulating layer 60. A part of the first common cathode CCE1 may pass through the sixth insulating layer 60 to be electrically connected to the first power assist line SEVSL1.

[0230] The cathode insulating layer CCE-IL may be positioned on the sixth insulating layer 60. The cathode insulating layer CCE-IL may be positioned on the first common cathode CCE1. The second common cathode CCE2 may be positioned on the cathode insulating layer CCE-IL.

[0231] The thin film encapsulation layer TFE (see Figure 7AThe first inorganic layer 71 of ) may be positioned on the second common cathode CCE2.

[0232] The first power assist line SEVSL1 may be in the same layer as the first anode AE1 (see Figure 7A ). The second power assist line SEVSL2 may be in the same layer as the second anode AE2 (see Figure 7C ).

[0233] However, embodiments according to the present disclosure are not limited thereto. For example, the first power assist line SEVSL1 and the second power assist line SEVSL2 may be in different layers from each other, and embodiments according to the present disclosure are not limited to any one embodiment.

[0234] The hole HH may pass through the cathode insulating layer CCE-IL, the first common cathode CCE1, and the sixth insulating layer 60. A part of the second common cathode CCE2 may be connected to the second power part through the hole HH. A part of the second common cathode CCE2 may be electrically connected to the second power assist line SEVSL2 to be connected to the second power part.

[0235] Here, a part of the cathode insulating layer CCE-IL, the first common cathode CCE1, and the sixth insulating layer 60 may be removed by a laser drilling method, and embodiments according to the present disclosure are not limited thereto.

[0236] Referring to Figure 9C , according to some embodiments of the present disclosure, the second common cathode CCE2 may overlap with the first display area DA1. Even if the second common cathode CCE2 overlaps with the first display area DA1, the cathode insulating layer CCE-IL may be positioned between the first common cathode CCE1 and the second common cathode CCE2 so that the first common cathode CCE1 and the second common cathode CCE2 are electrically insulated from each other.

[0237] Figure 10A and Figure 10B are enlarged plan views of parts of a display panel according to some embodiments of the present disclosure (see the display panel 210 in Figure 6 ). For example, Figure 10A is a plan view showing pixels in a first area and a second area according to some embodiments of the present disclosure. Figure 10B is Figure 10A an enlarged view of the area F10b in

[0238] Referring to Figure 10A and Figure 10B , according to some embodiments of the present disclosure, the display panel 210 (see Figure 6 ) may include a first pixel group PG1, and the first pixel group PG1 includes pixels in the first display area DA1 (see Figure 9A) the first green pixels PX_G1 and PX_G2, the first blue pixel PX_B1, and the first red pixel PX_R1 arranged in one direction. The display panel 210 may include a second pixel group PG2 including second green pixels PX_G3 and PX_G4, a second blue pixel PX_B2, and a second red pixel PX_R2 arranged in one direction in a second display area DA2 (see Figure 9A ).

[0239] Here, as shown in the drawings, the area occupied by one first pixel group PG1 with respect to the entire surface area of the first display area DA1 (see Figure 9A ) may be smaller than the area occupied by one second pixel group PG2 with respect to the entire surface area of the second display area DA2 (see Figure 9A ). However, embodiments according to the present disclosure are not limited thereto. For example, the areas occupied by the first pixel group PG1 and the second pixel group PG2 may be the same, and embodiments according to the present disclosure are not limited to any one embodiment. However, also in this case, in terms of the brightness per unit pixel, the second display area DA2 may be larger than the first display area DA1.

[0240] Referring to Figure 10B , the dummy pixel group PG2_DM may be spaced apart from the second red pixel PX_R2. However, embodiments according to the present disclosure are not limited thereto. For example, the dummy pixels of the dummy pixel group PG2_DM may be spaced apart from the second blue pixel PX_B2, or the second green pixels PX_G3 or PX_G4, and embodiments according to the present disclosure are not limited to any one embodiment.

[0241] Figure 10B shows the dummy pixel group PG2_DM present in the second display area DA2 (see Figure 9A ), but embodiments according to the present disclosure are not limited thereto. For example, the dummy pixel group PG2_DM may not exist, and embodiments according to the present disclosure are not limited to any one embodiment.

[0242] The second power assist line SEVSL2 may overlap with the dummy pixels in a plane (or in a plan view). According to some embodiments, the second power assist line SEVSL2 may be spaced apart from the second red pixel PX_R2 or the first blue pixel PX_B1 in a plane (or in a plan view), but embodiments according to the present disclosure are not limited thereto. For example, the second power assist line SEVSL2 may overlap with the second red pixel PX_R2 or the first blue pixel PX_B1 in a plane (or in a plan view), and embodiments according to the present disclosure are not limited to any one embodiment.

[0243] Figure 11A andFigure 11B is a plan view of a display panel according to some embodiments of the present disclosure. For example, Figure 11A and Figure 11B are plan views respectively showing line layouts of display panels according to some embodiments different from the embodiments of the inventive concept shown in Figure 6 and Figure 8 . In the descriptions with reference to Figure 11A and Figure 11B , the components described with reference to Figure 6 and Figure 8 are indicated by like reference numerals, and their descriptions are omitted.

[0244] Referring to Figure 11A , the first source power line EVSL1 may be arranged to surround three sides of the active region AA. The second source power line EVSL2 may be arranged to surround some sides of the active region AA. The second source power line EVSL2 may be arranged to be adjacent to one side of the active region AA.

[0245] As an example, the second source power line EVSL2 may be arranged to be adjacent to one side located at a side portion of the active region AA. The second source power line EVSL2 may extend in a first direction DR1 to overlap with the first display region DA1 and the second display region DA2.

[0246] However, embodiments according to the present disclosure are not limited thereto. For example, the second source power line EVSL2 may be arranged to surround two sides of the active region AA, and embodiments according to the present disclosure are not limited to any one embodiment.

[0247] The second power assist line SEVSL2 (see Figure 9A ) may branch from a position of the second source power line EVSL2 to have a minimum distance from the second source power line EVSL2 to the second display region DA2. In addition, the second power assist line SEVSL2 (see Figure 9A ) may extend in a direction in which the second source power line EVSL2 has a minimum distance from the second display region DA2.

[0248] Referring to Figure 11B , the first source power line EVSL1 may be arranged to surround three sides of the active region AA. The second source power line EVSL2 may be arranged to surround some sides of the active region AA. The second source power line EVSL2 may be arranged to be adjacent to one side of the sides of the active region AA not surrounded by the first source power line EVSL1.

[0249] As an example, the second source power line EVSL2 may be arranged adjacent to one side located at the lower portion of the active region AA. The second source power line EVSL2 may extend in the second direction DR2 to overlap with the first display region DA1 and the second display region DA2.

[0250] In a display panel and an electronic device including the display panel according to some embodiments, the levels of the power voltages supplied to the first pixel and the second pixel may be different from each other to relatively improve the sharpness difference between the first display region and the second display region. Under the same input signal, the brightness of the light output from the second light-emitting element may be higher than the brightness of the light output from the first light-emitting element. Accordingly, the sharpness difference between the first display region and the second display region may be relatively improved, and the overall display quality may be relatively improved.

[0251] In a display panel and an electronic device including the display panel according to some embodiments, the voltage lines respectively supplying the power voltages to the first pixel and the second pixel may be separated from the first pixel and the cathode of the first pixel to provide the voltage levels of the voltages respectively supplied to the pixels as different from each other. Accordingly, a voltage having a voltage level required by the pixel may be adjusted and supplied, and the power consumption may be relatively reduced.

[0252] Although embodiments of the present invention have been described, it is to be understood that the present invention should not be limited to these embodiments, but that various changes and modifications can be made by those of ordinary skill in the art within the spirit and scope of the present invention as claimed. Accordingly, the technical scope of the present inventive concept is not limited to what is described in the detailed description of the specification, but should be determined by the claims and their equivalents.

Claims

1. A display panel, comprising: a display area, the display area including a first area having a first light transmittance and a second area adjacent to the first area and having a second light transmittance higher than the first light transmittance; a plurality of first pixels, each of the plurality of first pixels being configured to provide light to the first region and comprising a first cathode; a plurality of second pixels, each of the plurality of second pixels being configured to provide light to the second region and including a second cathode overlapping the first cathode in a plan view and electrically insulated from the first cathode; a first power portion connected to the first cathode and configured to supply a first power voltage to the first cathode; a second power portion connected to the second cathode and configured to supply a second power voltage different from the first power voltage to the second cathode; as well as A cathode insulating layer is provided between the first cathode and the second cathode.

2. The display panel according to claim 1, wherein: A hole is defined in the second region passing through the first cathode and the cathode insulating layer, and The second cathode passes through the first cathode and the cathode insulating layer through the hole to be connected to the second power portion.

3. The display panel according to claim 2, wherein: The hole is at the edge of the first area.

4. The display panel according to claim 2, further comprising a dummy pixel in the second area, in, The hole overlaps the dummy pixel in the plan view.

5. The display panel according to claim 2, wherein: The hole is provided in a plurality so as to include a plurality of holes, Wherein, the plurality of holes are arranged along an edge of the second region.

6. The display panel according to claim 1, wherein: The second cathode is spaced apart from the first region in the plan view.

7. The display panel according to claim 1, wherein: In the plan view, the second cathode overlaps the first region and the second region.

8. The display panel according to claim 1, wherein: The second power voltage has a lower voltage level than the first power voltage.

9. The display panel according to claim 2, wherein: The first power part comprises: a first power line in a peripheral area adjacent to the display area; and a first power auxiliary line branched from the first power line and extending from the peripheral region to the first region to be electrically connected to the first cathode, and The second power part comprises: a second power line, the second power line being in the peripheral area; and A second power auxiliary line is branched from the second power line and extends from the peripheral region to the second region to be electrically connected to the second cathode.

10. The display panel according to claim 9, wherein: The hole and the second power assist line overlap each other in the plan view.

11. The display panel according to claim 9, wherein: The second power auxiliary line extends through the first area so as to have a minimum distance between the second area and the peripheral area.

12. The display panel according to claim 9, further comprising: a base layer on which the first power line and the second power line are positioned; as well as a first insulating layer, the first insulating layer being on the base layer, Wherein, the first cathode is on the first insulating layer.

13. The display panel according to claim 12, further comprising: a first anode on the base layer and overlapping the first region; a second anode on the base layer and overlapping the second region; as well as an organic layer on the base layer and including an emission layer, Wherein, the second power auxiliary line and the second anode are in the same layer.

14. A display panel, comprising: a display area, the display area including a first area having a first light transmittance and a second area adjacent to the first area and having a second light transmittance higher than the first light transmittance; a first anode, the first anode being in the first region; a second anode, the second anode being in the second region; an organic layer, the organic layer comprising an emission layer on the first anode and the second anode; a first cathode, the first cathode being in the first region; a second cathode in the second region, in a different layer from the first cathode, and electrically insulated from the first cathode; a first power portion connected to the first cathode; as well as a second power portion connected to the second cathode, wherein a hole is defined in the second region and passes through the first cathode, wherein the second cathode passes through the first cathode through the hole to be connected to the second power part.

15. The display panel according to claim 14, further comprising a cathode insulating layer between the first cathode and the second cathode, in, The hole also passes through the cathode insulating layer, and The second cathode passes through the first cathode and the cathode insulating layer through the hole to be connected to the second power portion.

16. The display panel according to claim 15, further comprising a peripheral area adjacent to the display area, in, The first power part comprises: a first power line, the first power line being in the peripheral area; and a first power auxiliary line branched from the first power line and extending from the peripheral region to the first region to be electrically connected to the first cathode, and Wherein, the second power part comprises: a second power line, the second power line being in the peripheral area; and A second power auxiliary line is branched from the second power line and extends from the peripheral region to the second region to be electrically connected to the second cathode.

17. The display panel according to claim 16, wherein: The hole and the second power assisting line overlap each other in a plan view.

18. The display panel according to claim 16, further comprising: a base layer on which the first power line and the second power line are positioned; as well as a first insulating layer, the first insulating layer being on the base layer, Wherein, the first cathode is on the first insulating layer.

19. The display panel according to claim 18, wherein: The first anode and the second anode are on the base layer, and The second power assist line is on the same layer as the second anode.

20. The display panel according to claim 15, wherein: The first power portion is configured to supply a first power voltage to the first cathode, and The second power portion supplies a second power voltage having a voltage level lower than the first power voltage to the second cathode.

21. An electronic device comprising: case; an electronic module, the electronic module being arranged in the housing; as well as a display panel, the display panel being arranged to overlap the electronic module, Wherein, the display panel comprises: a display area, the display area including a first area having a first light transmittance and a second area adjacent to the first area and having a second light transmittance higher than the first light transmittance; a plurality of first pixels, each of the plurality of first pixels being configured to provide light to the first region and comprising a first cathode; a plurality of second pixels, each of the plurality of second pixels being configured to provide light to the second region and including a second cathode overlapping the first cathode in a plan view and electrically insulated from the first cathode; a first power portion connected to the first cathode and configured to supply a first power voltage to the first cathode; a second power portion connected to the second cathode and configured to supply a second power voltage different from the first power voltage to the second cathode; and A cathode insulating layer is provided between the first cathode and the second cathode.

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