DDR PHY power collapse circuit for multi-mode double data rate synchronous dynamic random access memory

Abstract

A transmitter circuit includes a first driver circuit configured to drive an input / output pad in an integrated circuit device, the first driver circuit including a thin oxide transistor, the thin oxide transistor is configured to couple the input / output pad to a first voltage rail when the transmitter circuit operates in a first mode; a gate pull-up transistor configured to couple the gate of the thin oxide transistor to the second voltage rail when the voltage of the third voltage rail collapses to 0 volt level; and a switch configured to block transmission of a gating signal to the gate of the thin oxide transistor when the voltage of the third voltage rail collapses to the zero volt level.

Description

[0001] Cross - Reference to Related Applications

[0002] This patent application claims priority to pending U.S. non - provisional application Ser. No. 17 / 973,996, filed Oct. 26, 2022, which is assigned to the assignee of the present application and is hereby incorporated by reference in its entirety as if fully set forth herein and for all applicable purposes. Technical Field

[0003] The present disclosure generally relates to interface circuits for integrated circuits and, more particularly, to driver circuits that can operate in a combined transmitter that supports multiple voltage levels and signaling schemes for memory devices. Background Art

[0004] The technology of electronic devices has experienced explosive growth in the past few years. For example, better communication, hardware, larger networks, and more reliable protocols have driven the development of cellular and wireless communication technologies. Wireless service providers are now able to offer their customers an expanding range of features and services and provide users with an unprecedented level of access to information, resources, and communication. To keep up with these service enhancements, mobile electronic devices (e.g., cellular phones, tablet devices, laptop computers, etc.) have become more powerful and complex than ever. Continuing service enhancements require process technology advancements that can provide increasing performance and transistor density for integrated circuit (IC) devices.

[0005] IC devices may include a memory interface having physical layer circuitry configured to read and write to a double - data - rate random - access memory device. In drivers that have led to and continue to lead to process technology advancements, the demand for memory interfaces that support higher data rates has grown. Changes in certain aspects of large - scale IC design and semiconductor manufacturing processes, including reducing the process minimum feature size, may create new or different sensitivities of IC devices to electrical overstress (EOS). For example, the reduction of transistor gate length, transistor gate oxide thickness, and other features may limit the voltage levels that a transistor can sustain or tolerate. Transmitter circuits in memory devices may need to support different memory standards that specify different voltage ranges and signaling schemes, which may compromise the integrity of transistors in low - voltage circuits.

[0006] Accordingly, there is a continuing need for improvements in transmitter circuits that protect transistors, including thin - oxide transistors, from EOS. Summary of the Invention

[0007] Certain aspects of the present disclosure relate to systems, apparatuses, methods, and techniques that can avoid electrical overstress that may affect transistors in the input / output circuitry of a memory device. Some examples disclosed herein are applicable to the protection of circuits operating in a mode supporting different voltage domains.

[0008] In one aspect of the present disclosure, a transmitter circuit includes: a first driver circuit configured to drive an input / output pad in an integrated circuit device, the first driver circuit including a thin-oxide transistor configured to couple the input / output pad to a first voltage rail when the transmitter circuit operates in a first mode; a gate pull-up transistor configured to couple the gate of the thin-oxide transistor to a second voltage rail when the voltage of a third voltage rail collapses to 0 volts; and a switch configured to block the transmission of a gating signal to the gate of the thin-oxide transistor when the voltage of the third voltage rail collapses to the 0 volts.

[0009] In one aspect of the present disclosure, an apparatus has components for driving an input / output pad provided in an integrated circuit device, the input / output pad including a thin-oxide transistor in a first driver circuit that is active when the apparatus operates in a first mode and is configured to couple the input / output pad to the first voltage rail when active; components for pulling the gate of the thin-oxide transistor to a second voltage rail when the voltage of a third voltage rail collapses to 0 volts; and components for blocking the transmission of a gating signal to the gate of the thin-oxide transistor when the voltage of the third voltage rail collapses to 0 volts.

[0010] In one aspect of the present disclosure, a method for operating a transmitter circuit includes: configuring a first driver circuit to drive an input / output pad in an integrated circuit device when the transmitter circuit operates in a first mode, the first driver circuit including a thin-oxide transistor configured to couple the input / output pad to a first voltage rail when the transmitter circuit operates in a first mode; configuring a gate pull-up transistor to couple the gate of the thin-oxide transistor to a second voltage rail when the voltage of a third voltage rail collapses to 0 volts; and configuring a switch to block the transmission of a gating signal to the gate of the thin-oxide transistor when the voltage of the third voltage rail collapses to 0 volts.

[0011] In some examples, the transmitter circuit has a second driver circuit configured to couple the I / O pad to the first voltage rail when the transmitter circuit operates in a second mode. The second driver circuit may be deactivated when the transmitter circuit operates in a first mode. The first driver circuit may be deactivated when the transmitter circuit operates in the second mode. When the transmitter circuit operates in the first mode, the first voltage rail may deliver power at a first voltage level, and when the transmitter circuit operates in the second mode, the first voltage rail may deliver power at a second voltage level. The magnitude of the first voltage level may be greater than the magnitude of the second voltage level. When the transmitter circuit operates in the first mode, the first voltage rail and the second voltage rail may have the same voltage level, while when the transmitter circuit operates in the second mode, the first voltage rail and the second voltage rail may have different voltage levels. In one example, a transmission gate is used to implement the switch. In some embodiments, the gating signal is provided by a circuit powered by the third voltage rail. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 Illustrates example components and interconnects in a system-on-chip (SoC) that may be adapted to implement certain aspects of the present disclosure.

[0013] Figure 2 Illustrates an example of a combined transmitter in an input / output circuit of a memory device that may operate in multiple modes.

[0014] Figure 3 Illustrates certain aspects of a hold mode in a combined transmitter that supports multiple operating modes.

[0015] Figure 4 Illustrates certain aspects of voltage collapse in a combined transmitter that supports multiple operating modes.

[0016] Figure 5 Illustrates an example of a combined transmitter in an input / output circuit of a memory device configured according to certain aspects disclosed herein.

[0017] Figure 6 Illustrates Figure 5 certain aspects of voltage collapse in the combined transmitter illustrated in

[0018] Figure 7 Is a flowchart illustrating a method for operating a transmitter circuit such as Figure 5 the combined transmitter shown in DETAILED DESCRIPTION

[0019] The detailed description set forth below in connection with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. In order to provide a thorough understanding of the various concepts, specific details are included in the detailed description. It will be apparent, however, to one of ordinary skill in the art that the concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0020] Reference will now be made to the accompanying drawings to describe several exemplary aspects of the present disclosure. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0021] The terms "computing device" and "mobile device" are used interchangeably herein to refer to any one or all of the following: servers, personal computers, smart phones, cellular phones, tablet computers, laptop computers, netbooks, ultrabooks, palmtop computers, personal digital assistants (PDAs), wireless email receivers, multimedia Internet-enabled cellular phones, global positioning system (GPS) receivers, wireless game controllers, and similar personal electronic devices that include programmable processors. While the various aspects are particularly useful in mobile devices (e.g., smart phones, laptop computers, etc.) having limited resources (e.g., processing power, battery, size, etc.), these aspects are generally useful in any computing device that may benefit from improved processor performance and reduced power consumption.

[0022] The term "multi-core processor" is used herein to refer to a single integrated circuit (IC) chip or chip package that includes two or more independent processing units or cores (e.g., CPU cores, etc.) configured to read and execute program instructions. The term "multi-processor" is used herein to refer to a system or device that includes two or more processing units configured to read and execute program instructions.

[0023] The term "system-on-a-chip" (SoC) is used herein to refer to a single integrated circuit (IC) chip that includes multiple resources and / or processors integrated on a single substrate. A single SoC may include circuitry for digital, analog, mixed-signal, and radio frequency functions. A single SoC may also include any number of general-purpose and / or special-purpose processors (e.g., digital signal processors (DSPs), modem processors, video processors, etc.), memory blocks (e.g., read-only memory (ROM), random access memory (RAM), flash memory, etc.), and resources (e.g., timers, voltage regulators, oscillators, etc.), any one or all of which may be included in one or more cores.

[0024] The memory technologies described herein may be adapted to store instructions, programs, control signals, and / or data for use by or in a computer or other digital electronic device. Any reference to terms and / or technical details related to individual memory types, interfaces, standards, or memory technologies is for illustrative purposes only and is not intended to limit the scope of the claims to a particular memory system or technology, unless specifically recited in the claim language. The complexity of mobile computing device architectures has grown and now typically includes multiple processor cores, SoCs, coprocessors, functional modules including dedicated processors (e.g., communication modem chips, GPS receivers, etc.), complex memory systems, intricate electrical interconnects (e.g., buses and / or fabrics), and many other resources that execute complex and power-intensive software applications (e.g., video streaming applications, etc.).

[0025] Certain aspects of the present disclosure are applicable to input / output (I / O) circuitry that provides an interface between a core circuit and a memory device. Many mobile devices employ synchronous dynamic random access memory (SDRAM), including low-power double data rate SDRAM, which may be referred to as low-power DDR SDRAM (LPDDR SDRAM), or in some instances as LPDDRi SDRAM, where the i describes the technology formation of the LPDDR SDRAM. Examples of LPDDR SDRAM include LPDDR2 SDRAM, LPDDR4 SDRAM, and LPDDR4X SDRAM, where LPDDR4X SDRAM may refer to a variant of LPDDR4 SDRAM that provides improved power savings capabilities over LPDDR4 SDRAM. Later generations of LPDDR SDRAM designed to operate at higher operating frequencies may employ lower voltage levels in the core of the SoC or memory device to mitigate the increased power associated with the higher operating frequencies.

[0026] The process technologies for manufacturing semiconductor devices (including IC devices) are constantly improving. The process technologies include manufacturing methods for manufacturing IC devices and defining transistor sizes, operating voltages, and switching speeds. The characteristics of the components that make up the circuits in IC devices can be referred to as technology nodes and / or process nodes. The terms "technology node", "process node", and "process technology" can be used to characterize a specific semiconductor manufacturing process and the corresponding design rules. By using smaller feature sizes to produce smaller transistors that can fabricate higher density ICs, faster and more efficient technology nodes are continuously developed. The development of transistor technology has led to a reduced gate oxide thickness and a lower operating voltage. The gate oxide thickness can be configured as a fraction of the transistor channel length. In one example, the gate oxide thickness is between 2% and 4% of the transistor channel length. As the transistor size decreases, the corresponding reduction in the gate oxide thickness reduces the maximum gate-drain operating voltage that can be used with the device.

[0027] ICs typically provide multiple voltage domains for power saving purposes. For example, a higher voltage domain provides power at a higher voltage level than a lower voltage domain. Sometimes a higher voltage domain is required to interface with external devices, while the core logic circuits can typically operate at the lower voltage levels available in the lower voltage domain. For the purposes of the present disclosure, a thick oxide transistor can refer to a transistor having a gate oxide thickness sufficient to enable the transistor to withstand and operate at the higher voltage levels in the higher voltage domain, and a thin oxide transistor can refer to a transistor having a gate oxide thickness that is insufficient to avoid electrical overload when the transistor spans the higher voltage levels in the higher voltage domain. In certain examples disclosed herein, the thin oxide transistor can be rated for a voltage of up to 0.6 volts, and the thick oxide transistor can be rated for a voltage greater than 0.6 volts, and the thick oxide transistor can be used in the higher high voltage domain that provides power at 1.2 volts.

[0028] Figure 1Illustrated are example components and interconnections in a system-on-chip (SoC) 100 that may be adapted to implement certain aspects of the present disclosure. The SoC 100 may include multiple heterogeneous processors, such as a central processing unit (CPU) 102, a modem processor 104, a graphics processor 106, and an application processor 108. Each processor 102, 104, 106, 108 may include one or more cores, and each processor / core may perform operations independently of other processors / cores. The processors 102, 104, 106, 108 may be organized in close proximity to each other (e.g., on a single substrate, die, integrated chip, etc.), such that the processors may operate at a much higher frequency / clock rate than would be possible if the signals propagated off-chip. The proximity of the cores may also allow for sharing of on-chip memory and resources (e.g., voltage rails), as well as allowing for more coordinated collaboration between the cores. As used herein, a voltage rail refers to a component through which power at a particular voltage is distributed throughout the IC.

[0029] The SoC 100 may include system components and resources 110 for managing sensor data, analog-to-digital conversion, and / or wireless data transmission, as well as for performing other specialized operations (e.g., decoding high-definition video, video processing, etc.). The system components and resources 110 may also include components such as voltage regulators, oscillators, phase-locked loops (PLLs), peripheral bridges, data controllers, system controllers, access ports, timers, and / or other similar components for supporting processors and software clients operating on a computing device. The system components and resources 110 may also include circuitry for interfacing with peripheral devices such as cameras, electronic displays, wireless communication devices, external memory chips, etc.

[0030] The SoC 100 may also include a universal serial bus (USB) or other serial bus controller 112, one or more memory controllers 114, and a centralized resource manager (CRM) 116. The SoC 100 may also include an input / output module (not illustrated) for communicating with resources external to the SoC, each of which resources may be shared by two or more internal SoC components.

[0031] The processors 102, 104, 106, 108 may be interconnected to the USB controller 112, the memory controller 114, the system components and resources 110, the CRM 116, and / or other system components via an interconnect / bus module 122, which may include reconfigurable logic gate arrays and / or implement a bus architecture. Communication may also be provided by advanced interconnects such as a high-performance on-chip network (NoC).

[0032] The interconnect / bus module 122 may include or provide a bus master system that is configured to grant exclusive control of the bus to SoC components (e.g., processors, peripherals, etc.) (e.g., transfer data in burst mode, block transfer mode, etc.) for a set duration, number of operations, number of bytes, etc. In some cases, the interconnect / bus module 122 may implement an arbitration scheme to prevent multiple master components from attempting to drive the bus simultaneously. The memory controller 114 may be a dedicated hardware module configured to manage the data stream to and from the memory 124 via the memory interface / bus 126.

[0033] The memory controller 114 may include one or more processors configured to perform read and write operations on the memory 124. Examples of processors include microprocessors, microcontrollers, digital signal processors (DSPs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout this disclosure. In some aspects, the memory 124 may be part of the SoC 100. In some aspects, the memory 124 may conform to the specifications governing the manufacture and use of one or more types of LPDDRi SDRAM.

[0034] Certain memory devices may be configured to operate in accordance with the specifications that define the operating characteristics of various types of LPDDRi SDRAM. In one example, the memory device may operate in LPDDR2 SDRAM and LPDDR4X SDRAM operating modes (which may be referred to herein as "LP2" and "LP4X" modes, respectively). The memory device includes double data rate input / output circuitry (DDRIO) that enables the memory device to communicate with corresponding I / O circuitry in the SoC 100 or another device coupled to the memory device. The DDRIO may be configured for multi-mode operation. In some instances, the transmitters of the DDRIO of a memory device that supports LP2 and LP4X operating modes may include multiple circuits that perform the same function at different voltage levels.

[0035] Figure 2An example of a transmitter 200 of a memory device DDRIO that can operate in LP2 and LP4X modes is illustrated. In the illustrated example, the transmitter 200 is coupled to an input / output pad (I / O pad 208) and uses a plurality of driver circuits to drive the input / output pad. As used herein, the term input / output pad refers to a structure that is a portion of a coupling that conducts signals between an internal circuit at the core of an IC device and an external terminal, connector, or pin of a chip package carrying the IC device. In one example, the input / output pad may be coupled to an external terminal, connector, or pin by a wire that is thermoacoustically bonded to the input / output pad. In another example, the input / output pad may be coupled to an external terminal, connector, or pin via a solder ball that contacts the input / output pad. The process technology, signaling scheme, and operating voltage used to manufacture a memory device including the transmitter 200 may determine the type of transistor gate oxide used in the transmitter 200.

[0036] In the illustrated example, I / O pad 208 is coupled to an output voltage rail (V ) through one driver circuit configured as LP2 mode pull-up circuit 202 or through another driver circuit configured as LP4X pull-up circuit 204. DDIO 210). When the transmitter 200 is configured for V DDIO In the LP2 mode of operation where 1.2 volts of power can be provided, the LP2 mode pull-up circuit 202 can be used to drive the I / O pad 208. When the transmitter 200 is configured for V DDIO In the LP4X operating mode where 0.6 volts of power can be provided, the LP4X pull-up circuit 204 can be used to drive the I / O pad 208. The illustrated LP2 mode pull-up circuit 202 is implemented using only thick oxide transistors. The use of thin oxide transistor 212 and thick oxide transistors 214, 216 0 To 216 n The illustrated LP4X pull-up circuit 204 is implemented by a combination of.

[0037] In the illustrated example, I / O pad 208 is coupled to the lowest voltage rail (i.e., V) through yet another driver circuit of pull-down circuit 206 configured for use in LP2 mode and LP4X mode. SSX 220). Using thick oxide transistor 218 0 To 218 n The combination with the thin oxide transistor 222 implements the illustrated pull-down circuit 206. For the purposes of this disclosure, the highest voltage power rail in the memory device may be referred to as V DDPX , the lowest voltage rail can be referred to as V SSX .

[0038] To operate as a combined transmitter that functions in both LP4x and LP2 modes, the DDRIO transmitter 200 needs to comply with the signaling schemes and voltage domains defined by the corresponding specifications and standards. To meet these requirements, a combination of thick-gate and thin-gate devices is used to implement the DDRIO transmitter 200. The voltage domain in which the transmitter 200 operates includes voltage rails that deliver power to various segments of the memory device. For example, V DDIO 210 is shared with the SDRAM circuit and provided to the LP2 mode pull-up circuit 202 and the LP4X pull-up circuit 204 (driver circuits) at 1.2 volts in LP2 mode and at 0.6 volts in LP4x mode. Another voltage rail (V DDA ) is shared across the physical interface (PHY) of the memory device and is used to power the pre-drivers and logic circuits coupled to the DDRIO transmitter 200. In many examples, the voltage level of V DDA is scalable and can be collapsed to improve the power efficiency of the PHY.

[0039] Conventional combined transmitters do not support V DDA collapse, where it is desired that the voltage of the V DDA voltage rail drops to the 0-volt level, which in some instances corresponds to the voltage level of V SSX . Some conventional combined transmitters support a "hold mode", where the voltage level of V DDA is scaled to a lower level or an intermediate-level voltage. In conventional transmitters, V DDA collapse is typically avoided to prevent electrical overstress (EOS) of the thin-oxide transistors in LP2 mode.

[0040] Figure 3 Illustrates certain aspects of the hold mode in a combined transmitter that supports LP4X and LP2 modes. The first timing diagram 300 illustrates entering the hold mode when the combined transmitter is operating in LP4X mode. Entering the hold mode starts at time point 308 when the voltage level of V DDA 302 drops from 0.89 volts to 0.35 volts. The highest voltage power available for the transmitter is provided by V DDPX 304 held at a constant voltage level. The voltage level of V DDIO 306 is not constrained by the voltage level of V DDPX 304 and drops from 0.6 volts to 0 volts. In LP4X mode, the maximum voltage across the thin-oxide transistor 212 when entering the hold mode is defined by the voltage applied to the gate of the thin-oxide transistor 212, which is driven by the pre-driver and logic circuits powered by V DDA 302. In the hold mode, the voltage of V DDA 302 is 0.35 volts.

[0041] The second timing diagram 320 illustrates entering the hold mode when the combined transmitter operates in the LP2 mode. During operation in the LP2 mode, certain hold mode voltages in the LP4X pull-up circuit 204 are illustrated in the circuit diagram 340. At the time point 328 where the voltage level of V DDA 322 drops from 0.89 volts to 0.35 volts, it starts to enter the hold mode. The highest voltage power available for the transmitter is provided by V DDPX 324 which is held at a constant voltage level. The voltage level of V DDIO 326 is tied to the voltage level of V DDPX 304 and is held at 1.2 volts. In the LP2 mode, the thin oxide transistor 212 is inactive and is turned off by the signal 342 which is driven to the high signaling state by the pre-driver and logic circuit powered by V DDA 322. In the hold mode, the voltage of V DDA 322 is 0.35 volts. The maximum voltage across the thin oxide transistor 212 when entering the hold mode can be calculated as 1.2 - 0.35 = 0.85 volts, which is less than the maximum voltage level of V DDA 322 and is thus within the maximum operating voltage level defined for the thin oxide transistor 212.

[0042] Figure 4 Illustrates some aspects of voltage collapse in a combined transmitter supporting LP4x and LP2 modes. The first timing diagram 400 illustrates entering voltage collapse when the combined transmitter operates in the LP4X mode. At the time point 408 where the voltage level of V DDA 402 drops from 0.89 volts to 0 volts, it starts to enter voltage collapse. The highest voltage power available for the transmitter is provided by V DDPX 404 which is held at a constant voltage level. The voltage level of V DDIO 406 is not constrained by the voltage level of V DDPX 404 and drops from 0.6 volts to 0 volts. In the LP4X mode, the maximum voltage across the thin oxide transistor 212 when entering voltage collapse is defined by the voltage applied to the gate of the thin oxide transistor 212 which is driven by the pre-driver and logic circuit powered by V DDA 402. During voltage collapse, the voltage of V DDA 402 is 0 volts.

[0043] The second timing diagram 420 illustrates entering voltage collapse when the combined transmitter operates in the LP2 mode. During voltage collapse in the LP2 mode operation, certain voltages in the LP4X pull-up circuit 204 are illustrated in the circuit diagram 440. At V DDAThe voltage collapse begins at time point 428 when the voltage level of 422 drops from 0.89 volts to 0 volts. The maximum voltage power available for the transmitter is provided by V DDPX 424. The voltage level of V DDIO 426 is tied to the voltage level of V DDPX 404 and remains at 1.2 volts. The thin-oxide transistor 212 is controlled by the signal 442 received from a pre-driver and logic circuitry powered by V DDA 422. In LP2 mode, V DDA 422 is at 0 volts during the voltage collapse, the signal 442 received from the pre-driver and logic circuitry is expected to be at 0 volts during the voltage collapse, and the thin-oxide transistor 212 then turns on. In LP4X mode, the maximum voltage (gate-drain and / or gate-source voltage) across the thin-oxide transistor 212 during the voltage collapse is expected to be 1.2 volts and may exceed the maximum operating voltage level defined for the thin-oxide transistor 212, resulting in EOS.

[0044] Certain aspects of the present disclosure provide circuits, methods, and techniques that enable a combined transmitter to avoid EOS during a voltage collapse, including when the combined transmitter is operating in LP2 mode. In one aspect, when the combined transmitter is configured to withstand a voltage collapse on V DDA and the entire PHY can enter a low-power or idle state, the overall system power efficiency can be improved.

[0045] Figure 5 An example of a DDRIO transmitter 500 configured in accordance with certain aspects disclosed herein is illustrated. The DDRIO transmitter 500 includes Figure 2 certain features of the DDRIO transmitter 200 illustrated in

[0046] and can be implemented in a memory device capable of operating in LP2 and LP4X modes. The DDRIO transmitter 500 supports voltage collapse in both LP2 mode and LP4X mode. V DDIO In the illustrated example, the transmitter 500 is coupled to an input / output pad (I / O pad 508) and uses a plurality of driver circuits to drive the input / output pad. The I / O pad 508 can be coupled to the output voltage rail DDIO 510 through one driver circuit configured as an LP2 mode pull-up circuit 502 or through another driver circuit configured as an LP4X pull-up circuit 504. In one example, when the transmitter 500 is configured for LP2 operation mode where V DDIOWhen operating in the LP4X mode that provides 0.6 volts of power, the LP4X pull-up circuit 504 can be used. The LP2 mode pull-up circuit 502 can be implemented using thick oxide transistors. In the illustrated example, a combination of a thin oxide transistor 512 and thick oxide transistors 514, 516 0 to 516 n is used to implement the LP4X pull-up circuit 504. The process technology, signaling scheme, and voltage domain including the transmitter 500 used to fabricate the memory device can determine the type of transistor oxide used in the transmitter 500.

[0047] In the illustrated example, regardless of the operating mode of the transmitter 500, the I / O pad 508 is coupled to the lowest voltage power supply rail (i.e., V SSX 518) through another driver circuit configured as a pull-down circuit 506. The pull-down circuit 506 can be implemented using thick oxide transistors.

[0048] The DDRIO transmitter 500 can operate as a combined transmitter that functions in both the LP4x and LP2 modes, and the DDRIO transmitter 500 can be configured to operate using different signaling schemes and in different voltage domains according to corresponding or relevant specifications and standards. A hybrid of thick-gate and thin-gate devices in the pull-up path can be used to implement the DDRIO transmitter 500. The voltage domain in which the transmitter 500 operates includes voltage rails that deliver power to multiple segments of the memory device. For example, V DDIO 510 is shared with the SDRAM circuit and is provided to the LP2 mode pull-up circuit 502 and the LP4X pull-up circuit 504 (driver circuits) at 1.2 volts in the LP2 mode and at 0.6 volts in the LP4x mode. Another voltage rail (V DDA ) is shared across the physical interface (PHY) of the memory device and is used to power the pre-driver and logic circuits coupled to the DDRIO transmitter 500. In many examples, the voltage level of V DDA is scalable and can be collapsed to improve the power efficiency of the PHY.

[0049] The DDRIO transmitter 500 supports voltage collapse, where it is desired that the voltage of certain voltage rails drops to 0 volts or the level of V SSX . The LP4X pull-up circuit 504 includes a thick oxide layer gate pull-up transistor 522 that is configured to pull the gate of the thin oxide transistor 512 to V DDPX 520 when the DDRIO transmitter 500 is operating in the LP2 mode. In the LP2 mode, the gate pull-up transistor 522 turns off the thin oxide transistor 512. A transmission gate circuit 524 is provided to avoid V in the LP2 modeDDPX Leakage with V DDA When the DDRIO transmitter 500 operates in the LP2 mode, the transmission gate circuit 524, which can also be referred to as the transmit gate, is deactivated, and the transmission gate circuit 524 remains deactivated when entering the voltage collapse mode.

[0050] Figure 6 Illustrates Figure 5 Certain aspects of voltage collapse during the LP4x and LP2 modes in the combined transmitter illustrated in. The first timing diagram 600 illustrates entering voltage collapse when the combined transmitter operates in the LP4X mode. Voltage collapse begins at the time point 608 when the voltage level of V DDA 602 drops from 0.89 volts to 0 volts. The highest voltage power available for the transmitter is provided by V DDPX 604 which is maintained at a constant voltage level. The voltage level of V DDIO 606 is not constrained by the voltage level of V DDPX 604 and drops from 0.6 volts to 0 volts. In the LP4X mode, the maximum voltage across the thin oxide transistor 512 when entering the voltage collapse mode is defined by the voltage applied to the gate of the thin oxide transistor 512, which is driven by a pre-driver and logic circuit powered by V DDA 602. In the voltage collapse mode, the voltage of V DDA 602 is 0 volts.

[0051] The second timing diagram 620 illustrates entering voltage collapse when the combined transmitter operates in the LP2 mode. Certain voltages in the LP4X pull-up circuit 504 during voltage collapse in the LP2 mode operation are illustrated in the circuit diagram 640. Voltage collapse begins at the time point 628 when the voltage level of V DDA 622 drops from 0.89 volts to 0 volts. The highest voltage power available for the transmitter is provided by V DDPX 626 which is maintained at a constant 1.2V voltage level. The voltage level of V DDIO 624 is tied to the voltage level of V DDPX 604 and remains at 1.2 volts.

[0052] The gate pull transistor 522 and the transmission gate circuit 524 operate to avoid otherwise affecting the EOS of the thin oxide transistor 512. In one example, the gate pull transistor 522 and the transmission gate circuit 524 are configured such that all terminals of the thin oxide transistor 512 are pulled to V DDIO 624 during the LP2 mode. In the LP2 mode, V DDIO 624 has the same voltage as V DDPX626 the same voltage, resulting in no potential or negligible potential across the thin oxide transistor 512. When the transmission gate circuit 524 is turned on, the thin oxide transistor 512 is controlled by a gating signal 642 received from a pre-driver and logic circuit powered by V DDA 622. In the LP2 mode, the transmission gate circuit 524 is turned off and the gating signal 642 is decoupled from the gate of the thin oxide transistor 512. The voltage on the gate of the thin oxide transistor 512 is then controlled by a gate pull-up transistor 522. The transmission gate circuit 524 operates as a switch and can be configured to block the transmission of the gating signal 642 to the gate of the thin oxide transistor 512.

[0053] Figure 5 and Figure 6 The circuits in are provided as examples for illustrative purposes. Certain combinations of thin oxide P-type metal oxide semiconductor (PMOS) transistors and thick oxide N-type metal oxide semiconductor (NMOS) transistors are depicted. It is envisioned that other combinations of thick oxide NMOS transistors, thin oxide NMOS transistors, thick oxide POS transistors, thick oxide PMOS transistors can be used to implement the concepts disclosed herein.

[0054] Figure 7 is a flow chart illustrating an example of a method 700 for operating a transmitter circuit in an IC device in accordance with certain aspects disclosed herein. The method may involve Figure 5 and Figure 6 the various features and aspects of the driver circuits illustrated in. At block 702, a first driver circuit is configured to drive an I / O pad in an IC device when the transmitter circuit is operating in a first mode. The first driver circuit may include a thin oxide transistor configured to couple the I / O pad to a first voltage rail when the transmitter circuit is operating in the first mode. At block 704, a gate pull-up transistor is configured to couple the gate of the thin oxide transistor to a second voltage rail when the voltage on a third voltage rail collapses to 0 volts. At block 706, a switch is configured to block the transmission of a gating signal to the gate of the thin oxide transistor when the voltage on the third voltage rail collapses to 0 volts.

[0055] In some examples, the second driver circuit is configured to couple the I / O pad to the first voltage rail when the transmitter circuit operates in the second mode. When the transmitter circuit operates in the first mode, the second driver circuit may be deactivated. When the transmitter circuit operates in the second mode, the first driver circuit may be deactivated. When the transmitter circuit operates in the first mode, the first voltage rail may deliver power at a first voltage level, and when the transmitter circuit operates in the second mode, the first voltage rail may deliver power at a second voltage level. The magnitude of the first voltage level may be greater than the magnitude of the second voltage level. When the transmitter circuit operates in the first mode, the first voltage rail and the second voltage rail may have the same voltage level, while when the transmitter circuit operates in the second mode, the first voltage rail and the second voltage rail may have different voltage levels.

[0056] In one example, the switch includes a transmit gate. In some implementations, the gating signal is provided by a circuit powered by the third voltage rail.

[0057] It should be noted that the operating steps described in any exemplary aspect herein are described for the purpose of providing examples. The described operations may be performed in many different orders other than the illustrated order. In addition, the operations described in a single operating step may actually be performed in multiple different steps. Additionally, one or more of the operating steps discussed in the exemplary aspects may be combined. It will be understood that, as will be apparent to those skilled in the art, numerous different modifications may be made to the operating steps illustrated in the flowcharts. Those skilled in the art will also understand that any of a variety of different technologies and processes may be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0058] The various operations of the above-described method can be performed by any suitable component capable of performing the corresponding functions. The component can include various hardware and / or software components and / or modules, including but not limited to circuits, application-specific integrated circuits (ASICs), or processors. Generally, in the presence of operations illustrated in the drawings, those operations can have corresponding components plus functional components with similar numbers. In some aspects, an apparatus for performing certain functions disclosed herein can include a component for driving an I / O pad provided in an IC device. In some examples, the component for driving the I / O pad includes a thin-oxide transistor in a first driver circuit that is active when the transmitter circuit operates in a first mode and is configured to couple the I / O pad to the first voltage rail when active. The apparatus can include a component for pulling the gate of the thin-oxide transistor to a second voltage rail when the voltage of a third voltage rail collapses to 0 volts, and a component for blocking the transmission of a gating signal to the gate of the thin-oxide transistor when the voltage of the third voltage rail collapses to the 0 volts.

[0059] In certain embodiments, the component for driving the I / O pad further includes a second driver circuit that is active when the transmitter circuit operates in a second mode and is configured to couple the I / O pad to the first voltage rail when active. When the transmitter circuit operates in the first mode, the second driver circuit can be deactivated. When the transmitter circuit operates in the second mode, the first driver circuit can be deactivated. When the transmitter circuit operates in the first mode, the first voltage rail can deliver power at a first voltage level, and when the transmitter circuit operates in the second mode, the first voltage rail can deliver power at a second voltage level. The magnitude of the first voltage level can be greater than the magnitude of the second voltage level. When the transmitter circuit operates in the first mode, the first voltage rail and the second voltage rail can have the same voltage level, while when the transmitter circuit operates in the second mode, the first voltage rail and the second voltage rail can have different voltage levels.

[0060] In some instances, the component for blocking the transmission of the gating signal includes a transmission gate. In certain embodiments, the gating signal is provided by a circuit powered by the third voltage rail.

[0061] In one example, a transmitter circuit provided according to certain aspects of the present disclosure has a first driver circuit configured to drive an I / O pad in an integrated circuit device, the first driver circuit including a thin-oxide transistor configured to couple the I / O pad to a first voltage rail when the transmitter circuit operates in a first mode. The transmitter circuit further has a gate pull-up transistor configured to couple the gate of the thin-oxide transistor to a second voltage rail when the voltage of a third voltage rail collapses to 0 volts; and a switch configured to block the transmission of a gating signal to the gate of the thin-oxide transistor when the voltage of the third voltage rail collapses to 0 volts.

[0062] In some embodiments, the transmitter circuit has a second driver circuit configured to couple the I / O pad to the first voltage rail when the transmitter circuit operates in a second mode. The second driver circuit may be deactivated when the transmitter circuit operates in the first mode. The first driver circuit may be deactivated when the transmitter circuit operates in the second mode. When the transmitter circuit operates in the first mode, the first voltage rail may deliver power at a first voltage level, and when the transmitter circuit operates in the second mode, the first voltage rail may deliver power at a second voltage level. The magnitude of the first voltage level may be greater than the magnitude of the second voltage level. When the transmitter circuit operates in the first mode, the first voltage rail and the second voltage rail may have the same voltage level, while when the transmitter circuit operates in the second mode, the first voltage rail and the second voltage rail may have different voltage levels. In one example, a transmission gate is used to implement the switch. In some embodiments, the gating signal is provided by a circuit powered by the third voltage rail.

[0063] Some example embodiments are described in the following numbered clauses:

[0064] 1. A transmitter circuit, the transmitter circuit comprising: a first driver circuit configured to drive an input / output pad in an integrated circuit device, the first driver circuit including a thin-oxide transistor configured to couple the input / output pad to a first voltage rail when the transmitter circuit operates in a first mode; a gate pull-up transistor configured to couple the gate of the thin-oxide transistor to a second voltage rail when the voltage of a third voltage rail collapses to 0 volts; and a switch configured to block the transmission of a gating signal to the gate of the thin-oxide transistor when the voltage of the third voltage rail collapses to the 0 volts.

[0065] 2. The transmitter circuit according to clause 1, wherein the transmitter circuit further comprises: a second driver circuit configured to couple the input / output pad to the first voltage rail when the transmitter circuit operates in a second mode.

[0066] 3. The transmitter circuit according to clause 2, wherein when the transmitter circuit operates in the first mode, the second driver circuit is deactivated, and wherein when the transmitter circuit operates in the second mode, the first driver circuit is deactivated.

[0067] 4. The transmitter circuit according to clause 2 or clause 3, wherein when the transmitter circuit operates in the first mode, the first voltage rail delivers power at a first voltage level, and wherein when the transmitter circuit operates in the second mode, the first voltage rail delivers power at a second voltage level.

[0068] 5. The transmitter circuit according to clause 4, wherein the magnitude of the first voltage level is greater than the magnitude of the second voltage level.

[0069] 6. The transmitter circuit according to any one of clauses 1 to 5, wherein when the transmitter circuit operates in the first mode, the first voltage rail and the second voltage rail have the same voltage level, and wherein when the transmitter circuit operates in the second mode, the first voltage rail and the second voltage rail have different voltage levels.

[0070] 7. The transmitter circuit according to any one of clauses 1 to 6, wherein the switch includes a transmission gate.

[0071] 8. The transmitter circuit according to any one of clauses 1 to 7, wherein the gating signal is provided by a circuit powered by the third voltage rail.

[0072] 9. An apparatus, the apparatus comprising: means for driving an input / output pad provided in an integrated circuit device, the input / output pad including a thin-oxide transistor in a first driver circuit, the first driver circuit being active when the apparatus operates in a first mode and configured to couple the input / output pad to a first voltage rail when active; means for pulling the gate of the thin-oxide transistor to a second voltage rail when the voltage of a third voltage rail collapses to 0 volts; and means for blocking the transmission of a gating signal to the gate of the thin-oxide transistor when the voltage of the third voltage rail collapses to the 0 volts.

[0073] 10. The apparatus according to clause 9, wherein the component for driving the input / output pad further comprises: a second driver circuit that is active when the apparatus operates in a second mode and is configured to couple the input / output pad to the first voltage rail when active.

[0074] 11. The apparatus according to clause 10, wherein when the apparatus operates in the first mode, the second driver circuit is deactivated, and wherein when the apparatus operates in the second mode, the first driver circuit is deactivated.

[0075] 12. The apparatus according to clause 10 or clause 11, wherein the first voltage rail delivers power at a first voltage level when the apparatus operates in the first mode, and wherein the first voltage rail delivers power at a second voltage level when the apparatus operates in the second mode.

[0076] 13. The apparatus according to clause 12, wherein the magnitude of the first voltage level is greater than the magnitude of the second voltage level.

[0077] 14. The apparatus according to any one of clauses 9 to 13, wherein when the apparatus operates in the first mode, the first voltage rail and the second voltage rail have the same voltage level, and wherein when the apparatus operates in the second mode, the first voltage rail and the second voltage rail have different voltage levels.

[0078] 15. The apparatus according to any one of clauses 9 to 14, wherein the component for blocking the transmission of the gating signal comprises a transmission gate.

[0079] 16. The apparatus according to any one of clauses 9 to 15, wherein the gating signal is provided by a circuit that is powered by the third voltage rail.

[0080] 17. A method for operating a transmitter circuit, the method comprising: configuring a first driver circuit to drive an input / output pad in an integrated circuit device when the transmitter circuit operates in a first mode, the first driver circuit including a thin-oxide transistor configured to couple the input / output pad to a first voltage rail when the transmitter circuit operates in the first mode; configuring a gate pull-up transistor to couple the gate of the thin-oxide transistor to a second voltage rail when the voltage of a third voltage rail collapses to 0 volts; and configuring a switch to block the transmission of a gating signal to the gate of the thin-oxide transistor when the voltage of the third voltage rail collapses to 0 volts.

[0081] 18. The method according to clause 17, the method further comprising: configuring a second driver circuit to couple the input / output pad to the first voltage rail when the transmitter circuit operates in a second mode.

[0082] 19. The method according to clause 18, wherein when the transmitter circuit operates in the first mode, the second driver circuit is deactivated, and wherein when the transmitter circuit operates in the second mode, the first driver circuit is deactivated.

[0083] 20. The method according to clause 18 or clause 19, wherein when the transmitter circuit operates in the first mode, the first voltage rail delivers power at a first voltage level, and wherein when the transmitter circuit operates in the second mode, the first voltage rail delivers power at a second voltage level.

[0084] 21. The method according to clause 20, wherein the magnitude of the first voltage level is greater than the magnitude of the second voltage level.

[0085] 22. The method according to any one of clauses 17 to 21, wherein when the transmitter circuit operates in the first mode, the first voltage rail and the second voltage rail have the same voltage level, and wherein when the transmitter circuit operates in the second mode, the first voltage rail and the second voltage rail have different voltage levels.

[0086] 23. The method according to any one of clauses 17 to 22, wherein the switch includes a transmit gate.

[0087] 24. The method according to any one of clauses 17 to 23, wherein the gating signal is provided by a circuit powered by the third voltage rail.

[0088] As used herein, the phrase referring to "at least one of" a list of items refers to any combination of these items (which includes a single member). For example, "at least one of a, b, or c" is intended to cover a, b, c, a-b, a-c, b-c, and a-b-c, as well as any combination having multiple identical elements (e.g., a-a, a-a-a, a-a-b, a-a-c, a-b-b, a-c-c, b-b, b-b-b, b-b-c, c-c, and c-c-c, or any other ordering of a, b, and c).

[0089] This disclosure is provided to enable any person skilled in the art to make or use various aspects of the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the spirit or scope of the disclosure. Therefore, the disclosure is not intended to be limited to the examples and designs described herein, but rather to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A transmitter circuit, the transmitter circuit comprises: A first driver circuit configured to drive an input / output pad in an integrated circuit device, the first driver circuit including a thin oxide transistor configured to couple the input / output pad to a first voltage rail when the transmitter circuit operates in a first mode; A gate pull-up transistor configured to couple the gate of the thin oxide transistor to a second voltage rail when the voltage of a third voltage rail collapses to 0 volts; and A switch configured to block the transmission of a gating signal to the gate of the thin oxide transistor when the voltage of the third voltage rail collapses to the 0 volts.

2. The transmitter circuit according to claim 1, the transmitter circuit further comprises: A second driver circuit configured to couple the input / output pad to the first voltage rail when the transmitter circuit operates in a second mode.

3. The transmitter circuit according to claim 2, wherein when the transmitter circuit operates in the first mode, the second driver circuit is deactivated, and wherein when the transmitter circuit operates in the second mode, the first driver circuit is deactivated.

4. The transmitter circuit according to claim 2, wherein when the transmitter circuit operates in the first mode, the first voltage rail delivers power at a first voltage level, and wherein when the transmitter circuit operates in the second mode, the first voltage rail delivers power at a second voltage level.

5. The transmitter circuit according to claim 4, wherein the magnitude of the first voltage level is greater than the magnitude of the second voltage level.

6. The transmitter circuit according to claim 2, wherein when the transmitter circuit operates in the first mode, the first voltage rail and the second voltage rail have the same voltage level, and wherein when the transmitter circuit operates in the second mode, the first voltage rail and the second voltage rail have different voltage levels.

7. The transmitter circuit according to claim 1, wherein the switch includes a transmission gate.

8. The transmitter circuit according to claim 1, wherein the gating signal is provided by a circuit powered by the third voltage rail.

9. A device, the device comprises: Components for driving an input / output pad provided in an integrated circuit device, the input / output pad including a thin oxide transistor in a first driver circuit that is active when the device operates in a first mode and is configured to couple the input / output pad to a first voltage rail when active; Components for pulling the gate of the thin oxide transistor to a second voltage rail when the voltage of a third voltage rail collapses to 0 volts; and Components for blocking the transmission of a gating signal to the gate of the thin oxide transistor when the voltage of the third voltage rail collapses to the 0 volts.

10. The apparatus according to claim 9, wherein the component for driving the input / output pad further comprises: A second driver circuit that is active when the apparatus operates in a second mode and is configured to couple the input / output pad to the first voltage rail when active.

11. The apparatus according to claim 10, wherein when the apparatus operates in the first mode, the second driver circuit is deactivated, and wherein when the apparatus operates in the second mode, the first driver circuit is deactivated.

12. The apparatus according to claim 10, wherein the first voltage rail delivers power at a first voltage level when the apparatus operates in the first mode, and wherein the first voltage rail delivers power at a second voltage level when the apparatus operates in the second mode.

13. The apparatus according to claim 12, wherein the magnitude of the first voltage level is greater than the magnitude of the second voltage level.

14. The apparatus according to claim 10, wherein when the apparatus operates in the first mode, the first voltage rail and the second voltage rail have the same voltage level, and wherein when the apparatus operates in the second mode, the first voltage rail and the second voltage rail have different voltage levels.

15. The apparatus according to claim 9, wherein the component for blocking the transmission of the gating signal comprises a transmission gate.

16. The apparatus according to claim 9, wherein the gating signal is provided by a circuit powered by the third voltage rail.

17. A method for operating a transmitter circuit, the method comprises: Configuring a first driver circuit to drive an input / output pad in an integrated circuit device when the transmitter circuit operates in a first mode, the first driver circuit including a thin-oxide transistor configured to couple the input / output pad to a first voltage rail when the transmitter circuit operates in the first mode; Configuring a gate pull-up transistor to couple the gate of the thin-oxide transistor to a second voltage rail when the voltage of the third voltage rail collapses to 0 volts; and Configuring a switch to block the transmission of a gating signal to the gate of the thin-oxide transistor when the voltage of the third voltage rail collapses to the 0 volts.

18. The method according to claim 17, the method further comprises: Configuring a second driver circuit to couple the input / output pad to the first voltage rail when the transmitter circuit operates in a second mode.

19. The method according to claim 18, wherein when the transmitter circuit operates in the first mode, the second driver circuit is deactivated, and wherein when the transmitter circuit operates in the second mode, the first driver circuit is deactivated.

20. The method according to claim 18, wherein when the transmitter circuit operates in the first mode, the first voltage rail delivers power at a first voltage level, and wherein when the transmitter circuit operates in the second mode, the first voltage rail delivers power at a second voltage level.

21. The method according to claim 20, wherein the magnitude of the first voltage level is greater than the magnitude of the second voltage level.

22. The method according to claim 18, wherein when the transmitter circuit operates in the first mode, the first voltage rail and the second voltage rail have the same voltage level, and wherein when the transmitter circuit operates in the second mode, the first voltage rail and the second voltage rail have different voltage levels.

23. The method according to claim 17, wherein the switch includes a transmit gate.

24. The method according to claim 17, wherein the gating signal is provided by a circuit powered by the third voltage rail.

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