A magnetic bearing suspension current redundancy control circuit and method

Abstract

The present invention relates to the technical field of magnetic levitation bearings, and provides a redundant control circuit and method for the suspension current of a magnetic bearing. The redundant control circuit includes two bridge circuits for obtaining electrical energy from a DC voltage source and supplying power to the magnetic bearing coil; the bridge circuit includes a first bridge arm and a second bridge arm; the first bridge arm includes a first power diode and two first MOS transistors connected in series in sequence, and the cathode end of the first power diode forms a first connection point for connecting to the magnetic bearing coil; the second bridge arm includes two second MOS transistors and a second power diode connected in series in sequence, and the anode end of the second power diode forms a second connection point for connecting to the magnetic bearing coil. The present invention provides a redundant control circuit for the suspension current of a magnetic bearing, which can perform redundant control on the two bridge circuits more quickly and efficiently, ensure the stability of the suspension current, and has a simple structure and control logic, and is easy to implement.

Description

Technical Field

[0001] The present invention relates to the field of magnetic levitation bearings, and specifically to a magnetic bearing suspension current redundant control circuit and method. Background Art

[0002] A magnetic bearing, that is, a magnetic levitation bearing, is a bearing device that uses a controllable electromagnetic force to achieve non-contact support for a rotating part. Compared with traditional mechanical bearings, magnetic levitation bearings have advantages such as no need for lubricating oil and no contact friction, and thus can achieve ultra-high rotational speeds, while greatly reducing power consumption, and have broad application prospects.

[0003] A continuous and stable magnetic bearing suspension current is the key to ensuring that the magnetic levitation bearing can be normally levitated and rotated. In order to ensure the stability and reliability of the magnetic bearing suspension current, on the one hand, it is necessary to conduct detailed theoretical analysis and modeling optimization on the topology circuit and key devices, and on the other hand, it is necessary to improve the fault tolerance of the topology circuit, that is, it is necessary to ensure that even if a short-circuit fault occurs in a certain semiconductor power device in the topology circuit, a continuous and stable magnetic bearing suspension current can still be output to maintain the normal suspension and operation of the magnetic levitation bearing.

[0004] In the prior art, the main method for realizing magnetic suspension current redundant control is: after collecting the actual magnetic suspension current, comparing it with a preset value, then determining whether the suspension current is abnormal, and further controlling the suspension current. This method requires a relatively complex control circuit structure, a relatively complex control process, and a large delay. Summary of the Invention

[0005] In order to solve the deficiencies in the prior art, the present invention provides a magnetic bearing suspension current redundant control circuit and method, which can perform redundant control on two bridge circuits more quickly and efficiently, ensure the stability of the suspension current, and have a simple structure and control logic, and are easy to implement.

[0006] In order to achieve the above object, the specific solution adopted by the present invention is: a magnetic bearing suspension current redundant control circuit, including two bridge circuits for obtaining electrical energy from a DC voltage source and supplying power to a magnetic bearing coil;

[0007] The bridge circuit includes a first bridge arm and a second bridge arm;

[0008] The first bridge arm includes a first power diode and two first MOS transistors connected in series in sequence, and the cathode end of the first power diode forms a first connection point for connecting to the magnetic bearing coil;

[0009] The second bridge arm includes two second MOS transistors and a second power diode connected in series in sequence, and the anode end of the second power diode forms a second connection point for connecting to the magnetic bearing coil.

[0010] As a further optimization of the above magnetic bearing suspension current redundant control circuit: the control circuit further includes a PWM unit and a control unit. The PWM unit is used to generate PWM signals corresponding to the first MOS transistor and the second MOS transistor. The PWM signals are used to directly control the first MOS transistor or the second MOS transistor. The control unit is used to generate an upper control signal according to the main circuit current of the DC voltage source and the branch current of the bridge circuit. The upper control signal is used to directly control the first MOS transistor, directly control the second MOS transistor, or adjust the PWM signal to generate a lower control signal. The lower control signal is used to directly control the first MOS transistor or directly control the second MOS transistor.

[0011] As a further optimization of the above magnetic bearing suspension current redundant control circuit: the control unit includes an upper signal generator and a J-K flip-flop. The upper signal generator is used to generate two upper control signals corresponding to the bridge circuit according to the main circuit current of the DC voltage source and the branch current of the bridge circuit. The J-K flip-flop is used to adjust the PWM signal according to the upper control signal to generate a lower control signal, and transmit the lower control signal to the first MOS transistor or the second MOS transistor.

[0012] As a further optimization of the above magnetic bearing suspension current redundant control circuit: the first bridge arm of the first bridge circuit includes a first power diode D1, a first MOS transistor Q2, and a first MOS transistor Q1 connected in series in sequence. The second bridge arm of the first bridge circuit includes a second MOS transistor Q4, a second MOS transistor Q3, and a second power diode D2 connected in series in sequence;

[0013] The first bridge arm of the second bridge circuit includes a first power diode D3, a first MOS transistor Q6, and a first MOS transistor Q5 connected in series in sequence. The second bridge arm of the second bridge circuit includes a second MOS transistor Q8, a second MOS transistor Q7, and a second power diode D4 connected in series in sequence;

[0014] The drain terminal of the first MOS transistor Q1 is connected to the cathode terminal of the second power diode D2. The source terminal of the first MOS transistor Q1 is connected to the drain terminal of the first MOS transistor Q2. The source terminal of the first MOS transistor Q2 is connected to the cathode terminal of the first power diode D1. The anode terminal of the first power diode D1 is connected to the source terminal of the second MOS transistor Q4. The drain terminal of the second MOS transistor Q4 is connected to the source terminal of the second MOS transistor Q3. The drain terminal of the second MOS transistor Q3 is connected to the anode terminal of the second power diode D2;

[0015] The drain terminal of the first MOS transistor Q5 is connected to the cathode terminal of the second power diode D4. The source terminal of the first MOS transistor Q5 is connected to the drain terminal of the first MOS transistor Q6. The source terminal of the first MOS transistor Q6 is connected to the cathode terminal of the first power diode D3. The anode terminal of the first power diode D3 is connected to the source terminal of the second MOS transistor Q8. The drain terminal of the second MOS transistor Q8 is connected to the source terminal of the second MOS transistor Q7. The drain terminal of the second MOS transistor Q7 is connected to the anode terminal of the second power diode D4;

[0016] The source terminal of the second MOS transistor Q4 is connected to the source terminal of the second MOS transistor Q8. The drain terminal of the first MOS transistor Q5 is connected to the drain terminal of the first MOS transistor Q1. The cathode terminal of the first power diode D1 is connected to the cathode terminal of the first power diode D3. The anode terminal of the second power diode D2 is connected to the anode terminal of the second power diode D4.

[0017] As a further optimization of the above magnetic bearing suspension current redundant control circuit: a first connection point is formed between the cathode terminal of the first power diode D1 and the source terminal of the first MOS transistor Q2, and between the cathode terminal of the first power diode D3 and the source terminal of the first MOS transistor Q6. A second connection point is formed between the anode terminal of the second power diode D2 and the drain terminal of the second power diode Q3, and between the anode terminal of the second power diode D4 and the drain terminal of the second MOS transistor Q7;

[0018] The first connection point is used to connect the first end of the magnetic bearing coil, and the second connection point is used to connect the second end of the magnetic bearing coil.

[0019] As a further optimization of the above magnetic bearing suspension current redundant control circuit: the drain terminal of the first MOS transistor Q1 is connected to the positive terminal of the DC voltage source V, and the source terminal of the second MOS transistor Q8 is connected to the negative terminal of the DC voltage source V.

[0020] A magnetic bearing suspension current redundant control method, based on the above magnetic bearing suspension current redundant control circuit, the method includes the following steps:

[0021] Collect the trunk current Idis of the DC voltage source and the branch currents Ibra1 and Ibra2 of the two bridge circuits;

[0022] Calculate the difference EO1 between the branch current Ibra1 and the trunk current Idis, and the difference EO2 between the branch current Ibra2 and the trunk current Idis;

[0023] The difference EO1 and the difference EO2 are respectively compared with the reference value Iref, and upper control signals Gc1 and upper control signal Gc2 are generated according to the comparison results. The upper control signal Gc1 and the upper control signal Gc2 correspond one-to-one with the bridge circuit;

[0024] Generate PWM signals corresponding to the first MOS transistor and the second MOS transistor;

[0025] Directly control the first MOS transistor or the second MOS transistor by using the upper control signal Gc1, the upper control signal Gc2 or the PWM signal, or adjust the PWM signal by using the upper control signal Gc1 and the upper control signal Gc2 to generate a lower control signal, and then directly control the first MOS transistor or the second MOS transistor by using the lower control signal.

[0026] As a further optimization of the above magnetic bearing suspension current redundancy control method: when both the difference EO1 and the difference EO2 are greater than the reference value Iref, the first upper control signal Gc1 directly controls the first MOS transistor Q1 and the second MOS transistor Q3 to be in a normally open state, and the second upper control signal Gc2 directly controls the first MOS transistor Q5 and the second MOS transistor Q7 to be in a normally open state;

[0027] Perform a logical AND operation on the PWM signal corresponding to the first MOS transistor Q2 and the second MOS transistor Q4 and the first upper control signal Gc1 to generate a lower control signal, and control the first MOS transistor Q2 and the second MOS transistor Q4 to be in a closed state;

[0028] Perform a logical AND operation on the PWM signal corresponding to the first MOS transistor Q6 and the second MOS transistor Q8 and the second upper control signal Gc2 to generate a lower control signal, and control the first MOS transistor Q6 and the second MOS transistor Q8 to be in a closed state.

[0029] As a further optimization of the above magnetic bearing suspension current redundancy control method: when the difference EO1 is less than the reference value Iref and the difference EO2 is equal to the reference value Iref, the first upper control signal Gc1 directly controls the first MOS transistor Q1 and the second MOS transistor Q3 to be in a closed state, and the second upper control signal Gc2 directly controls the first MOS transistor Q5 and the second MOS transistor Q7 to be in a normally open state;

[0030] The first MOS transistor Q6 and the second MOS transistor Q8 are controlled by the corresponding PWM signals.

[0031] As a further optimization of the above magnetic bearing suspension current redundancy control method: when the difference EO1 is equal to the reference value Iref and the difference EO2 is less than the reference value Iref, the first upper control signal Gc1 directly controls the first MOS transistor Q1 and the second MOS transistor Q3 to be in the normally open state, and the second upper control signal Gc2 directly controls the first MOS transistor Q5 and the second MOS transistor Q7 to be in the off state;

[0032] The first MOS transistor Q2 and the second MOS transistor Q4 are controlled by corresponding PWM signals.

[0033] Beneficial effects: The present invention realizes the redundant control of two bridge circuits by collecting the trunk current and the branch current and performing logical operations, which is more rapid and efficient, can ensure the stability of the suspension current, and the structure and control logic of the present invention are simple and easy to implement. Description of the Drawings

[0034] Figure 1 is the circuit diagram of the magnetic bearing suspension current redundancy control circuit of the present invention;

[0035] Figure 2 is the circuit connection schematic diagram of the J-K flip-flop;

[0036] Figure 3 is the flowchart of the magnetic bearing suspension current redundancy control method of the present invention;

[0037] Figure 4 is the magnetic bearing suspension current measurement result diagram in an experiment. Detailed Embodiments

[0038] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0039] As Figure 1 shown, a magnetic bearing suspension current redundancy control circuit includes two bridge circuits for obtaining electric energy from a DC voltage source and supplying power to a magnetic bearing coil. Figure 1 Among them, the resistor R and the inductor L are the equivalent representations of the magnetic bearing coil.

[0040] The bridge circuit includes a first bridge arm and a second bridge arm.

[0041] The first bridge arm includes a first power diode and two first MOS transistors connected in series in sequence, and the cathode end of the first power diode forms a first connection point for connecting to the magnetic bearing coil.

[0042] The second bridge arm includes two second MOS transistors and a second power diode connected in series in sequence, and the anode terminal of the second power diode forms a second connection point for connecting to the magnetic bearing coil.

[0043] In the present invention, both of the two bridge circuits can control the magnetic bearing coil and are redundant backups for each other. When one of the bridge circuits fails, the other bridge circuit can continue to provide the suspension current for the magnetic bearing coil, thereby ensuring the stable operation of the magnetic bearing. Specifically, in the two bridge circuits, the first connection point of the first bridge arm is connected to the first end of the magnetic bearing coil, and the second connection point of the second bridge arm is connected to the second end of the magnetic bearing coil, thereby forming a loop to enable the DC voltage source to supply power to the magnetic bearing coil.

[0044] Furthermore, the control circuit further includes a PWM unit and a control unit. The PWM unit is used to generate PWM signals corresponding to the first MOS transistor and the second MOS transistor. The PWM signals are used to directly control the first MOS transistor or the second MOS transistor. The control unit is used to generate an upper control signal according to the main circuit current of the DC voltage source and the branch circuit current of the bridge circuit. The upper control signal is used to directly control the first MOS transistor, directly control the second MOS transistor, or adjust the PWM signal to generate a lower control signal. The lower control signal is used to directly control the first MOS transistor or directly control the second MOS transistor. In the control circuit, the PWM signals are used to control the first MOS transistor and the second MOS transistor. By changing the states of the first MOS transistor and the second MOS transistor, the power supply state to the magnetic bearing coil is changed, thereby realizing the control of the suspension current of the magnetic bearing coil. The upper control signal is generated based on the main circuit current and the branch circuit current. The upper control signals generated by the bridge circuit in the normal state and the fault state are different. Therefore, the upper control signal can be directly used to control the first MOS transistor or the second MOS transistor, thereby controlling the states of the first MOS transistor or the second MOS transistor based on the state of the bridge circuit. In addition, the lower control signal can also be obtained by adjusting the PWM signal with the upper control signal, and the lower control signal can also control the states of the first MOS transistor or the second MOS transistor based on the state of the bridge circuit.

[0045] More specifically, the method for generating the upper control signal is as follows: calculate the difference between the main circuit current and the branch circuit current, and then compare the difference with a preset reference value. If the differences corresponding to both of the two bridge circuits are greater than the reference value, both of the two bridge circuits are operating normally at this time. If the difference corresponding to one of the bridge circuits is less than the reference value while the difference corresponding to the other bridge circuit is equal to the reference value, the bridge circuit with the difference less than the reference value has failed, and the bridge circuit with the difference equal to the reference value is operating normally.

[0046] The specific structure of the control unit is as follows: The control unit includes an upper signal generator and a J-K flip-flop. The upper signal generator is used to generate two upper control signals corresponding to the bridge circuit according to the main circuit current of the DC voltage source and the branch circuit current of the bridge circuit. The J-K flip-flop is used to adjust the PWM signal according to the upper control signal to generate a lower control signal, and transmit the lower control signal to the first MOS transistor or the second MOS transistor. It should also be noted that the structure of the upper signal generator and the specific method for generating the upper control signal are conventional techniques in the art and will not be elaborated here.

[0047] In an embodiment of the present invention, as Figure 2As shown, the J-K flip-flop is marked as U1, with the model number HEF4027BT. The circuit around the J-K flip-flop U1 includes resistors R1, R2, R3, R4, R5, R6, R7, capacitors C1, C2, C3, C4, C5, and C6. The first end of resistor R1 is connected to the positive pole of the 12V power supply, and the second end of resistor R1 is connected to pin 5 of the J-K flip-flop U1. The first end of resistor R2 is connected to the positive pole of the 12V power supply, and the second end of resistor R2 is connected to pin 11 of the J-K flip-flop U1. The first end of resistor R3 is connected to the ground of the 12V power supply, and the second end of resistor R3 is connected to pin 10 of the J-K flip-flop U1. The first end of resistor R4 is connected to the ground of the 12V power supply, and the second end of resistor R4 is connected to pin 7 of the J-K flip-flop U1. The first end of resistor R5 is connected to the ground of the 12V power supply, and the second end of resistor R5 is connected to pin 6 of the J-K flip-flop U1. The first end of resistor R6 is connected to the signal RESET_1_1, and the second end of resistor R6 is connected to pin 4 of the J-K flip-flop U1. The first end of resistor R7 is connected to the signal CTR1_1, and the second end of resistor R7 is connected to pin 3 of the J-K flip-flop U1. The first end of capacitor C1 is connected to the ground of the 12V power supply, and the second end of capacitor C1 is connected to the positive pole of the 12V power supply. The first end of capacitor C2 is connected to the ground of the 12V power supply, and the second end of capacitor C2 is connected to the signal RESET_1. The first end of capacitor C3 is connected to the ground of the 12V power supply, and the second end of capacitor C3 is connected to pin 11 of the J-K flip-flop U1. The first end of capacitor C4 is connected to the ground of the 12V power supply, and the second end of capacitor C4 is connected to the signal EO_4_L. The first end of capacitor C5 is connected to the ground of the 12V power supply, and the second end of capacitor C5 is connected to pin 5 of the J-K flip-flop U1. The first end of capacitor C6 is connected to the ground of the 12V power supply, and the second end of capacitor C6 is connected to the signal CTR1_1. Pin 1 of the J-K flip-flop U1 is connected to the signal EO_MCU, pin 2 of the J-K flip-flop U1 is connected to the signal EO_3_L, pin 7 of the J-K flip-flop U1 is connected to the signal SET_1_1, pin 9 of the J-K flip-flop U1 is connected to the signal EO_4_L, pin 14 of the J-K flip-flop U1 is connected to the signal CTR1_1, pin 15 of the J-K flip-flop U1 is connected to the signal CTR1, pin 16 of the J-K flip-flop U1 is connected to the positive pole of the 12V power supply, and pin 8 of the J-K flip-flop U1 is connected to the ground of the 12V power supply.

[0048] When the two upper control signals are normal, the 13th pin of the J-K flip-flop U1 is at low level, the 14th pin is at low level, and the 15th pin is at high level. The signal of the 15th pin will perform a logical AND operation with the PWM signals of each MOS transistor. When the signal of the 15th pin is at high level, the conduction and cutoff of each MOS transistor are completely controlled by the PWM signal. When one of the upper control signals changes, the 13th pin of the J-K flip-flop U1 on this path will change from low level to high level. At this time, the 15th pin of the J-K flip-flop U1 will change from high level to low level, and the 14th pin of the J-K flip-flop U1 will change from low level to high level. After the 15th pin of the J-K flip-flop U1 becomes low level, after the PWM signals of each MOS transistor perform a logical AND operation with it, the output signal is also low level. Then all the MOS transistors in the faulty bridge circuit will be turned off. At the same time, the 1st pin of U1 will change from high level to low level. This signal can be connected to a certain pin of the single-chip microcomputer. When the single-chip microcomputer receives the change of the signal level at this pin, it can alarm through a display module such as a screen.

[0049] As Figure 1 shown, the specific structures of the two bridge circuits are as follows.

[0050] The first bridge arm of the first bridge circuit includes a first power diode D1, a first MOS transistor Q2, and a first MOS transistor Q1 connected in series in sequence. The second bridge arm of the first bridge circuit includes a second MOS transistor Q4, a second MOS transistor Q3, and a second power diode D2 connected in series in sequence.

[0051] The first bridge arm of the second bridge circuit includes a first power diode D3, a first MOS transistor Q6, and a first MOS transistor Q5 connected in series in sequence. The second bridge arm of the second bridge circuit includes a second MOS transistor Q8, a second MOS transistor Q7, and a second power diode D4 connected in series in sequence.

[0052] The drain terminal of the first MOS transistor Q1 is connected to the cathode terminal of the second power diode D2. The source terminal of the first MOS transistor Q1 is connected to the drain terminal of the first MOS transistor Q2. The source terminal of the first MOS transistor Q2 is connected to the cathode terminal of the first power diode D1. The anode terminal of the first power diode D1 is connected to the source terminal of the second MOS transistor Q4. The drain terminal of the second MOS transistor Q4 is connected to the source terminal of the second MOS transistor Q3. The drain terminal of the second MOS transistor Q3 is connected to the anode terminal of the second power diode D2.

[0053] The drain terminal of the first MOS transistor Q5 is connected to the cathode terminal of the second power diode D4. The source terminal of the first MOS transistor Q5 is connected to the drain terminal of the first MOS transistor Q6. The source terminal of the first MOS transistor Q6 is connected to the cathode terminal of the first power diode D3. The anode terminal of the first power diode D3 is connected to the source terminal of the second MOS transistor Q8. The drain terminal of the second MOS transistor Q8 is connected to the source terminal of the second MOS transistor Q7. The drain terminal of the second MOS transistor Q7 is connected to the anode terminal of the second power diode D4.

[0054] The source terminal of the second MOS transistor Q4 is connected to the source terminal of the second MOS transistor Q8. The drain terminal of the first MOS transistor Q5 is connected to the drain terminal of the first MOS transistor Q1. The cathode terminal of the first power diode D1 is connected to the cathode terminal of the first power diode D3. The anode terminal of the second power diode D2 is connected to the anode terminal of the second power diode D4.

[0055] The specific connection manner between the two bridge circuits and the magnetic bearing coil is as follows: A first connection point is formed between the cathode terminal of the first power diode D1 and the source terminal of the first MOS transistor Q2, and between the cathode terminal of the first power diode D3 and the source terminal of the first MOS transistor Q6. A second connection point is formed between the anode terminal of the second power diode D2 and the drain terminal of the second MOS transistor Q3, and between the anode terminal of the second power diode D4 and the drain terminal of the second MOS transistor Q7. The first connection point is used to connect the first end of the magnetic bearing coil, and the second connection point is used to connect the second end of the magnetic bearing coil.

[0056] The connection manner between the two bridge circuits and the DC voltage source V is as follows: The drain terminal of the first MOS transistor Q1 is connected to the positive terminal of the DC voltage source V, and the source terminal of the second MOS transistor Q8 is connected to the negative terminal of the DC voltage source V.

[0057] As Figure 3 shown, a magnetic bearing suspension current redundancy control method is based on the above magnetic bearing suspension current redundancy control circuit, and the method includes S1 to S5.

[0058] S1. Collect the trunk current Idis of the DC voltage source and the branch currents Ibra1 and Ibra2 of the two bridge circuits.

[0059] S2. Calculate the difference EO1 between the branch current Ibra1 and the trunk current Idis, and the difference EO2 between the branch current Ibra2 and the trunk current Idis.

[0060] S3. Compare the difference EO1 and the difference EO2 with a preset reference value Iref respectively, and generate a higher-level control signal Gc1 and a higher-level control signal Gc2 according to the comparison results. The higher-level control signal Gc1 and the higher-level control signal Gc2 correspond to the bridge circuits one by one.

[0061] S4. Generate PWM signals corresponding to the first MOS transistor and the second MOS transistor.

[0062] S5. Use the upper control signal Gc1, the upper control signal Gc2, or the PWM signal to directly control the first MOS transistor or the second MOS transistor, or use the upper control signal Gc1 and the upper control signal Gc2 to adjust the PWM signal to generate a lower control signal, and then use the lower control signal to directly control the first MOS transistor or the second MOS transistor.

[0063] Specifically, when controlling the first MOS transistor or the second MOS transistor, it is divided into the following three cases.

[0064] In the first case, when both the difference EO1 and the difference EO2 are greater than the reference value Iref, the first upper control signal Gc1 directly controls the first MOS transistor Q1 and the second MOS transistor Q3 to be in the normally open state, and the second upper control signal Gc2 directly controls the first MOS transistor Q5 and the second MOS transistor Q7 to be in the normally open state. The PWM signal corresponding to the first MOS transistor Q2 and the second MOS transistor Q4 and the first upper control signal Gc1 are subjected to a logical AND operation to generate a lower control signal, and control the first MOS transistor Q2 and the second MOS transistor Q4 to be in the off state. The PWM signal corresponding to the first MOS transistor Q6 and the second MOS transistor Q8 and the second upper control signal Gc2 are subjected to a logical AND operation to generate a lower control signal, and control the first MOS transistor Q6 and the second MOS transistor Q8 to be in the off state.

[0065] More specifically, in the first case, the two branch currents are equal and equal to half of the trunk current. At this time, both the first upper control signal Gc1 and the second upper control signal Gc2 are at a high level. After the PWM signal and the first upper control signal Gc1 or the second upper control signal Gc2 are subjected to a logical AND operation, the generated lower control signal is consistent with the PWM signal. Therefore, the first MOS transistor Q2, the second MOS transistor Q4, the first MOS transistor Q6, and the second MOS transistor Q8 are all controlled by their respective PWM signals.

[0066] In the second case, when the difference EO1 is less than the reference value Iref and the difference EO2 is equal to the reference value Iref, the first upper control signal Gc1 directly controls the first MOS transistor Q1 and the second MOS transistor Q3 to be in the off state, and the second upper control signal Gc2 directly controls the first MOS transistor Q5 and the second MOS transistor Q7 to be in the normally open state.

[0067] The first MOS transistor Q6 and the second MOS transistor Q8 are controlled by the corresponding PWM signals.

[0068] In the third case, when the difference EO1 is equal to the reference value Iref and the difference EO2 is less than the reference value Iref, the first upper control signal Gc1 directly controls the first MOS transistor Q1 and the second MOS transistor Q3 to be in the normally open state, and the second upper control signal Gc2 directly controls the first MOS transistor Q5 and the second MOS transistor Q7 to be in the off state.

[0069] The first MOS transistor Q2 and the second MOS transistor Q4 are controlled by corresponding PWM signals.

[0070] In order to verify the actual effect of the present invention, the following experiment was conducted.

[0071] In the experiment, the voltage of the voltage source was set to 300V DC, and the given current was 30A. It should be noted that in this experiment, the given current was indirectly reflected in the form of a given voltage, and the ratio of the given voltage to the given current was 1:3. For example, if the given voltage was 0.5V, it meant the given current was 1.5A. In this experiment, one of the MOS transistors was artificially damaged to cause a fault in the control circuit, and the measurement results of the magnetic bearing suspension current are as Figure 4 shown. As can be seen from Figure 4 it, when the control circuit fails, the magnetic bearing suspension current has a slight fluctuation, with a fluctuation amplitude of 1.9A and a duration of 110uS. This fluctuation amplitude and duration can be basically ignored.

[0072] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A magnetic bearing suspension current redundant control circuit, characterized in that It includes two bridge circuits for obtaining electrical energy from a DC voltage source and supplying power to the magnetic bearing coils; The bridge circuit includes a first bridge arm and a second bridge arm; The first bridge arm includes a first power diode and two first MOS transistors connected in series in sequence, and the cathode end of the first power diode forms a first connection point for connecting to the magnetic bearing coil; The second bridge arm includes two second MOS transistors and a second power diode connected in series in sequence, and the anode end of the second power diode forms a second connection point for connecting to the magnetic bearing coil; The first bridge arm of the first bridge circuit includes a first power diode D1, a first MOS transistor Q2, and a first MOS transistor Q1 connected in series in sequence, and the second bridge arm of the first bridge circuit includes a second MOS transistor Q4, a second MOS transistor Q3, and a second power diode D2 connected in series in sequence; The first bridge arm of the second bridge circuit includes a first power diode D3, a first MOS transistor Q6, and a first MOS transistor Q5 connected in series in sequence, and the second bridge arm of the second bridge circuit includes a second MOS transistor Q8, a second MOS transistor Q7, and a second power diode D4 connected in series in sequence; The drain end of the first MOS transistor Q1 is connected to the cathode end of the second power diode D2, the source end of the first MOS transistor Q1 is connected to the drain end of the first MOS transistor Q2, the source end of the first MOS transistor Q2 is connected to the cathode end of the first power diode D1, the anode end of the first power diode D1 is connected to the source end of the second MOS transistor Q4, the drain end of the second MOS transistor Q4 is connected to the source end of the second MOS transistor Q3, and the drain end of the second MOS transistor Q3 is connected to the anode end of the second power diode D2; The drain end of the first MOS transistor Q5 is connected to the cathode end of the second power diode D4, the source end of the first MOS transistor Q5 is connected to the drain end of the first MOS transistor Q6, the source end of the first MOS transistor Q6 is connected to the cathode end of the first power diode D3, the anode end of the first power diode D3 is connected to the source end of the second MOS transistor Q8, the drain end of the second MOS transistor Q8 is connected to the source end of the second MOS transistor Q7, and the drain end of the second MOS transistor Q7 is connected to the anode end of the second power diode D4; The source end of the second MOS transistor Q4 is connected to the source end of the second MOS transistor Q8, the drain end of the first MOS transistor Q5 is connected to the drain end of the first MOS transistor Q1, the cathode end of the first power diode D1 is connected to the cathode end of the first power diode D3, and the anode end of the second power diode D2 is connected to the anode end of the second power diode D4.

2. The magnetic bearing suspension current redundancy control circuit according to claim 1, characterized in that, The control circuit further includes a PWM unit and a control unit. The PWM unit is configured to generate PWM signals corresponding to the first MOS transistor and the second MOS transistor, and the PWM signals are used to directly control the first MOS transistor or the second MOS transistor. The control unit is configured to generate a higher-level control signal based on the main circuit current of the DC voltage source and the branch circuit current of the bridge circuit, and the higher-level control signal is used to directly control the first MOS transistor, directly control the second MOS transistor, or adjust the PWM signals to generate a lower-level control signal, and the lower-level control signal is used to directly control the first MOS transistor or directly control the second MOS transistor.

3. The redundant control circuit for the suspension current of a magnetic bearing according to claim 2, wherein The control unit includes a higher-level signal generator and a J-K flip-flop. The higher-level signal generator is configured to generate two higher-level control signals corresponding to the bridge circuit based on the main circuit current of the DC voltage source and the branch circuit current of the bridge circuit. The J-K flip-flop is configured to adjust the PWM signals according to the higher-level control signals to generate lower-level control signals, and transmit the lower-level control signals to the first MOS transistor or the second MOS transistor.

4. A magnetic bearing suspension current redundancy control circuit according to claim 1, characterized in that, A first connection point is formed between the cathode terminal of the first power diode D1 and the source terminal of the first MOS transistor Q2, and between the cathode terminal of the first power diode D3 and the source terminal of the first MOS transistor Q6. A second connection point is formed between the anode terminal of the second power diode D2 and the drain terminal of the second MOS transistor Q3, and between the anode terminal of the second power diode D4 and the drain terminal of the second MOS transistor Q7. The first connection point is used to connect the first end of the magnetic bearing coil, and the second connection point is used to connect the second end of the magnetic bearing coil.

5. The redundant control circuit for suspension current of a magnetic bearing according to claim 2, wherein The drain terminal of the first MOS transistor Q1 is connected to the positive terminal of the DC voltage source V, and the source terminal of the second MOS transistor Q8 is connected to the negative terminal of the DC voltage source V.

6. A magnetic bearing suspension current redundancy control method, characterized in that, Based on a magnetic bearing suspension current redundancy control circuit as claimed in claim 1, the method includes the following steps: Collect the main circuit current Idis of the DC voltage source and the branch circuit currents Ibra1 and Ibra2 of the two bridge circuits; Calculate the difference EO1 between the branch circuit current Ibra1 and the main circuit current Idis, and the difference EO2 between the branch circuit current Ibra2 and the main circuit current Idis; Compare the differences EO1 and EO2 with a reference value Iref respectively, and generate a higher-level control signal Gc1 and a higher-level control signal Gc2 according to the comparison results. The higher-level control signal Gc1 and the higher-level control signal Gc2 correspond to the bridge circuits one by one; Generate PWM signals corresponding to the first MOS transistor and the second MOS transistor; Use the higher-level control signal Gc1, the higher-level control signal Gc2 or the PWM signals to directly control the first MOS transistor or the second MOS transistor, or use the higher-level control signal Gc1 and the higher-level control signal Gc2 to adjust the PWM signals to generate lower-level control signals, and then use the lower-level control signals to directly control the first MOS transistor or the second MOS transistor.

7. The magnetic bearing suspension current redundancy control method according to claim 6, wherein When both the difference EO1 and the difference EO2 are greater than the reference value Iref, the first upper control signal Gc1 directly controls the first MOS transistor Q1 and the second MOS transistor Q3 to be in the normally open state, and the second upper control signal Gc2 directly controls the first MOS transistor Q5 and the second MOS transistor Q7 to be in the normally open state; The PWM signals corresponding to the first MOS transistor Q2 and the second MOS transistor Q4 and the first upper control signal Gc1 are subjected to a logical AND operation to generate a lower control signal, and control the first MOS transistor Q2 and the second MOS transistor Q4 to be in the off state; The PWM signals corresponding to the first MOS transistor Q6 and the second MOS transistor Q8 and the second upper control signal Gc2 are subjected to a logical AND operation to generate a lower control signal, and control the first MOS transistor Q6 and the second MOS transistor Q8 to be in the off state.

8. The magnetic bearing suspension current redundancy control method according to claim 6, wherein When the difference EO1 is less than the reference value Iref and the difference EO2 is equal to the reference value Iref, the first upper control signal Gc1 directly controls the first MOS transistor Q1 and the second MOS transistor Q3 to be in the off state, and the second upper control signal Gc2 directly controls the first MOS transistor Q5 and the second MOS transistor Q7 to be in the normally open state; The first MOS transistor Q6 and the second MOS transistor Q8 are controlled by the corresponding PWM signals.

9. A magnetic bearing suspension current redundancy control method according to claim 6, characterized in that, When the difference EO1 is equal to the reference value Iref and the difference EO2 is less than the reference value Iref, the first upper control signal Gc1 directly controls the first MOS transistor Q1 and the second MOS transistor Q3 to be in the normally open state, and the second upper control signal Gc2 directly controls the first MOS transistor Q5 and the second MOS transistor Q7 to be in the off state; The first MOS transistor Q2 and the second MOS transistor Q4 are controlled by the corresponding PWM signals.

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