Decoupling method of thermal effect in hydrogenated amorphous oxide semiconductor transistor hcd test

Abstract

The application discloses a decoupling method for thermal effect in amorphous oxide semiconductor transistor HCD test, and belongs to the technical field of semiconductor transistor test. The amorphous oxide semiconductor transistor device is divided into multiple test batches; the devices of the same test batch are divided into an HCD group and a BTI group; all the devices are subjected to HCD test, the test conditions of the devices of different test batches are different, the V ds >0 of the HCD group in each test batch, while the V ds =0 of the BTI group; the electrical parameters of the devices after being subjected to the voltage application under each test condition are extracted to draw a transfer characteristic curve, and the threshold voltage variation of the to-be-tested device is obtained by using the threshold voltage variation of the devices of the HCD group after being subjected to the voltage application and the threshold voltage variation of the devices of the BTI group after being subjected to the voltage application. The application fills the blank of the HCD effect quantitative evaluation method of small-size amorphous oxide semiconductor devices, and provides an important reference for DRAM array circuit design.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor transistor testing, and particularly relates to a decoupling method for thermal effects in HCD testing of amorphous oxide semiconductor transistors. BACKGROUND

[0002] The miniaturization process of a conventional silicon-based 1T1C structure has gone through 18nm, 1x, 1y and 1a technology nodes, and currently faces a huge bottleneck near the 10nm node. Oxide semiconductor is regarded as a key technology for further miniaturization and substantial reduction of area overhead of dynamic random access memory (DRAM) due to low off-state current and low overall process temperature and process compatibility. However, oxide semiconductor material will have to face new stability problems when applied to the field of DRAM. For example, in a 2T0C DRAM, the write transistor and the read transistor simultaneously experience V gs and V ds stress in the write and read stages, respectively, that is, are damaged by hot carrier degradation (HCD) effect, which may cause transistor performance degradation and failure of the overall DRAM device unit.

[0003] For amorphous oxide semiconductor transistor devices, small-size amorphous oxide semiconductor transistors (gate length / gate width <100nm) have more complex HCD behaviors while having the potential to continue the DRAM miniaturization path. Therefore, a comprehensive, systematic and scientific evaluation method has not been established for small-size devices damaged by HCD effect, making it more difficult to design the circuit of a DRAM array. SUMMARY

[0004] The application proposes a decoupling method for thermal effects in HCD testing of amorphous oxide semiconductor transistors aiming at the HCD effect damage of small-size amorphous oxide semiconductor devices.

[0005] The technical solution of the application is as follows:

[0006] A decoupling method for thermal effects in HCD testing of amorphous oxide semiconductor transistors, characterized in that it specifically comprises the following steps:

[0007] 1) Selecting a plurality of amorphous oxide semiconductor transistors of the same type as the devices to be tested, dividing the devices to be tested into a plurality of test batches, and dividing the devices in each test batch into an HCD group and a BTI group;

[0008] 2) performing "voltage application-measurement-voltage application-…-voltage application-measurement" HCD testing on the devices to be tested, wherein the voltage application is to apply a drain-source voltage V ds between the source and drain electrodes of the devices and a gate-source voltage V gs; wherein different test batches of devices apply different test conditions, including temperature, humidity, bending stress, and V gs with peak, frequency, and duty cycle of V ds ; all devices in each test batch are tested under the same test conditions, except that the HCD group is under V ds > 0, while the BTI group is under V ds = 0;

[0009] 3) extracting the test results of the device under test in step 2), drawing a transfer characteristic curve according to the electrical parameters of the device after being stressed under each test condition, extracting the threshold voltage variation of the HCD group device after being stressed, and the threshold voltage variation of the BTI group device after being stressed, and obtaining the threshold voltage variation caused by the thermal effect of the device under test by the following formula:

[0010] ΔV th,热效应 = ΔV th,HCD - ΔV th,BTI .

[0011] Further, the electrical parameters include V th , I on , SS, g m , DIBL, or I off .

[0012] Further, the amorphous oxide semiconductor transistor device is a back gate structure, a top gate structure, a double gate structure, and a three-dimensional fin gate structure, a surround gate structure, a ring channel structure, a stacked nanosheet structure, or a vertical channel structure.

[0013] Further, the channel layer of the amorphous oxide semiconductor transistor device is ITO, ln2O3, IGZO, IAZO, ITZO, CAAC-IGZO, IZO, ZnO, IWO, ITWO, or a multi-doped or composite layered channel oxide semiconductor based on the above materials.

[0014] Further, the channel length of the channel layer of the amorphous oxide semiconductor transistor device is 5-10000 nm, and the channel width is 10-10000 nm.

[0015] Further, the number of devices in the HCD group and the BTI group in each test batch is more than 100.

[0016] Further, the stress is a direct current, alternating current, or pulse voltage.

[0017] The present application has the beneficial effect of filling the gap in the quantitative evaluation method of the HCD effect of small-sized amorphous oxide semiconductor devices, and providing an important reference for the design of DRAM array circuits based on amorphous oxide semiconductors. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 An amorphous oxide semiconductor transistor device under test with a back-gate structure is shown, where 1 is the substrate, 2 is the back-gate electrode, 3 is the high-κ dielectric layer, 4 is the channel layer, 5 is the source electrode, and 6 is the drain electrode. A drain-source voltage V is applied between the source and drain electrodes. ds A gate-source voltage V is applied between the gate and source electrodes. gs .

[0019] Figure 2 This illustrates V during the i-th "pressure-measurement" cycle of the reliability test using DC pressure in a specific embodiment of the present invention. gs and V ds The waveforms are shown in Figure (a) and Figure (b) respectively.

[0020] Figure 3 The document illustrates the threshold voltage extraction process of the device after applying pressure and the test results under different conditions in a specific embodiment of the present invention. (a) shows the transfer characteristic curves of the device after different pressure application times under the same test conditions, and extracts I from each transfer characteristic curve. d Reaching the threshold current I th Gate-source voltage V at time gs (a) is the threshold voltage corresponding to the transfer characteristic curve; (b) shows the relationship between the change in threshold voltage and the pressure application time under different test conditions.

[0021] Figure 4 The process of decoupling thermal effects is demonstrated in a specific embodiment of the present invention. Detailed Implementation

[0022] The thermal effect decoupling method for amorphous oxide semiconductor transistors based on HCD testing provided by the present invention is described below with reference to the accompanying drawings and through embodiments. In the following description, many details are set forth to provide a thorough understanding of the invention; however, the invention can be implemented in many other ways than those described. Therefore, the present invention is not limited to the embodiments disclosed below.

[0023] like Figure 1 As shown, a specific embodiment of the present invention takes a back-gate amorphous oxide semiconductor transistor (AOS) device as an example to perform HCD testing on the AOS transistor under test, that is, applying a Vc between the gate and source of the back-gate AOS transistor device. gs Apply V between drain and source ds .

[0024] The thermal effect decoupling method for amorphous oxide semiconductor transistors of the present invention includes the following steps:

[0025] In step S01, the field-effect transistors to be tested are divided into multiple test batches. This invention does not restrict the method of dividing the test batches. The transistors under test within the same test batch must be divided into HCD group and BTI group. For example, the transistors under test within the same test batch can be equally divided into HCD group and BTI group. This invention also does not restrict the method of dividing the HCD and BTI groups.

[0026] In step S02, all devices undergo a "pressure-measurement-pressure-...-pressure-measurement" HCD test, with different test conditions for different batches. Test conditions include temperature, humidity, bending stress, and V... gs With V ds The peak value, frequency, and duty cycle, for example, using a DC waveform during the pressure application phase, varying the temperature of the device under test, and applying V to the device during the pressure application phase. ds and V gs .

[0027] All devices in each test batch, except V, were subjected to stress during the stress phase. ds All other test conditions except for the waveform are the same, namely, the pressure phase V of the HCD group. ds >0, while BTI group V ds =0. The waveforms of both in a single "pressure-measurement" process are as follows: Figure 2 As shown, Figure (a) shows the waveform of the HCD group, V ds >0; while Figure (b) shows the waveform of the BTI group, V ds =0.

[0028] In step S03, a transfer characteristic curve is plotted based on the electrical parameters of the device under test under each test condition, and the threshold voltage of the device after applying pressure is extracted. Taking the fixed current method for extracting the threshold voltage as an example... Figure 3 (a) Shows the transfer characteristic curves of the HCD group after different pressure times under the same test conditions, and extracts I from each transfer characteristic curve. d Reaching the threshold current I th Gate-source voltage V at time gs That is, the threshold voltage corresponding to the transfer characteristic curve. Figure 3 (b) shows the relationship between the change in threshold voltage and the pressure application time under different test conditions in the HCD test.

[0029] In step S04, the threshold voltage changes of the HCD group and BTI group during the test time are extracted using the following formula:

[0030] ΔV th,热效应 =ΔV th,HCD -ΔV th,BTI

[0031] likeFigure 4 As shown, the threshold voltage change caused by the thermal effect of the device is decoupled from the HCD test results. Although the overall HCD test results of the device under test meet the failure criteria within the test time range, the decoupling of the thermal effect by this invention can effectively determine that the dominant effect in the HCD test results of the device is the BTI effect.

[0032] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A method for decoupling thermal effects in HCD testing of amorphous oxide semiconductor transistors, characterized in that, Specifically, the steps include the following: 1) Select multiple amorphous oxide semiconductor transistors of the same type as devices under test, divide the devices under test into several test batches, and divide the devices in each test batch into HCD group and BTI group; 2) Perform a "pressure-measurement-pressure-…-pressure-measurement" HCD test on the device under test. The pressure is achieved by applying a drain-source voltage V between the source and drain electrodes of the device. ds A gate-source voltage V is applied between the gate and source electrodes. gs Different test batches of devices are subjected to different test conditions, including temperature, humidity, bending stress, and V. gs With V ds The peak value, frequency, and duty cycle; the test conditions for all devices in each test batch are consistent, except for the stress phase V of the HCD group. ds >0, while BTI group V ds =0; 3) Extract the test results of the device under test from step 2). Plot the transfer characteristic curve based on the electrical parameters of the device after applying pressure under each test condition. Extract the threshold voltage change of the HCD group device and the threshold voltage change of the BTI group device after applying pressure. Calculate the threshold voltage change caused by the thermal effect of the device under test using the following formula: 。 2. The decoupling method for thermal effects in HCD testing of amorphous oxide semiconductor transistors as described in claim 1, characterized in that, The electrical parameters include V th I on SS, g m DIBL or I off .

3. The decoupling method for thermal effects in HCD testing of amorphous oxide semiconductor transistors as described in claim 1, characterized in that, The amorphous oxide semiconductor transistor device is a back gate structure, a top gate structure, a dual gate structure, and a three-dimensional fin gate structure, a surrounding gate structure, a ring channel structure, a stacked nanosheet structure, or a vertical channel structure.

4. The decoupling method for thermal effects in HCD testing of amorphous oxide semiconductor transistors as described in claim 3, characterized in that, The channel layer of the amorphous oxide semiconductor transistor device is ITO, ln2O3, IGZO, IAZO, ITZO, CAAC-IGZO, IZO, ZnO, IWO, ITWO, or a multi-doped or composite stacked channel oxide semiconductor based on the above materials.

5. The decoupling method for thermal effects in HCD testing of amorphous oxide semiconductor transistors as described in claim 4, characterized in that, The amorphous oxide semiconductor transistor device has a channel length of 5~10000 nm and a channel width of 10~10000 nm.

6. The decoupling method for thermal effects in HCD testing of amorphous oxide semiconductor transistors as described in claim 1, characterized in that, The number of devices in both the HCD group and the BTI group in the test batch exceeded 100.

7. The decoupling method for thermal effects in HCD testing of amorphous oxide semiconductor transistors as described in claim 1, characterized in that, The pressure is applied by applying a DC, AC, or pulse voltage.

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