A register encryption circuit

Abstract

The application relates to the technical field of register encryption, and particularly discloses a register encryption circuit which comprises an addressing unit, an encryption unit and a register group which are connected in sequence; the addressing unit receives an input signal, decodes the input signal and outputs an address; the encryption unit encrypts the address, outputs an encrypted address, and looks up a corresponding register group according to the encrypted address to enable the write enable of the register group. The application realizes the encryption of the write data to the special register by using the existing addressing structure.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of register encryption technology, and particularly relates to a register encryption circuit. BACKGROUND

[0002] The stored value of the register has a great influence on the function of the whole circuit and the performance of the circuit, so when it is intended to change the value of some register groups, encryption processing needs to be performed.

[0003] The conventional register encryption circuit needs to add an additional pin to separately control whether the data is written into the register group addressed by the addressing unit, and in this mode, the register group selected by the register selection unit needs to be determined, and the additional control pin increases the complexity of the circuit and also increases the manufacturing cost of the circuit. SUMMARY

[0004] In view of the above problems, the present application aims to provide a register encryption circuit which uses the existing addressing structure to achieve encryption of the write data to the special register.

[0005] The present application provides a register encryption circuit, comprising: an addressing unit, an encryption unit and a register group connected in sequence.

[0006] The addressing unit receives an input signal and outputs an address after decoding the input signal.

[0007] The encryption unit outputs an encrypted address after encrypting the address, and finds the corresponding register group according to the encrypted address to enable the write enable of the register group.

[0008] In a possible implementation manner, the addressing unit comprises a plurality of inverters and AND gates; the input ends of the AND gates are connected with the input ends or the output ends of any two inverters.

[0009] In a possible implementation manner, the register group comprises M groups of N-bit registers; each group of the register group comprises N flip-flops; M and N are positive integers.

[0010] In a possible implementation manner, the encryption unit comprises: a two-way logic gate, a flip-flop and an inverter.

[0011] In a possible implementation manner, the two-way logic gate is a three-input logic gate, comprising an input port S, an input port A0 and an input port A1.

[0012] In a possible implementation manner, the flip-flop is a 5-port logic gate, comprising an input port CLK, an input port D, an input port RN, an output port Q and an output port QN.

[0013] In a possible implementation, the signal outputted by any one of the AND gates is connected to the input port S of the two-input logic gate after being inverted; the signal outputted by the any one of the AND gates is connected to the input port A0;

[0014] The output port of the two-input logic gate is connected to the input port D of the flip-flop, and the output port Q of the flip-flop is connected to the input port A1 of the two-input logic gate.

[0015] In a possible implementation, when the signal received by the input port S is at a first level, the output port of the two-input logic gate is selected as A0;

[0016] When the signal received by the input port S is at a second level, the output port of the two-input logic gate is selected as A1.

[0017] In a possible implementation, when the signal received by the input port S is at the first level, the output port Q outputs a second level;

[0018] When the signal received by the input port S is at the second level, the output port Q outputs a first level.

[0019] In a possible implementation, when the reset signal received by the input port RN is at a first level, the output port Q of the flip-flop outputs 0, and the output port QN is the inverse value of the value of the output port Q;

[0020] When the reset signal received by the input port RN is at a second level, and the clock signal CLK received by the input port CLK changes from a first level to a second level, the value of the output port Q takes the value of the input port D, and the output port QN is the inverse value of the value of the output port Q.

[0021] The register encryption circuit provided by the present application encrypts the register group by the addressing unit itself, avoids the need to add an encryption line, and thus avoids the problem of adding an enable pin in the circuit structure. The existing addressing structure is used to encrypt the write data to the special register. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 The circuit structure diagram of the register encryption circuit provided by the embodiment of the present application is shown in the figure;

[0023] Figure 2 The circuit structure diagram of the addressing unit provided by the embodiment of the present application is shown in the figure;

[0024] Figure 3 The circuit connection diagram of the encryption unit provided by the embodiment of the present application is shown in the figure;

[0025] Figure 4 A circuit structure diagram of the encryption unit provided for the embodiment of the present application is shown in the following;

[0026] Figure 5 A circuit structure diagram of the register group provided for the embodiment of the present application is shown in the following. DETAILED DESCRIPTION

[0027] The embodiments of the present application will be further described in conjunction with the accompanying drawings and embodiments. The detailed description of the following embodiments and the accompanying drawings are used to exemplarily illustrate the principles of the present application, but cannot be used to limit the scope of the present application, i.e., the present application is not limited to the described preferred embodiments, and the scope of the present application is defined by the claims.

[0028] In the description of the present application, it should be noted that, unless otherwise specified, the meaning of "a plurality of" is two or more than two; the terms "first", "second", etc. are only used for description purposes, and cannot be understood as indicating or implying relative importance; the above terms in the present application can be understood according to the specific circumstances by those of ordinary skill in the art.

[0029] As shown in the following, Figures 1-5 The present application provides a register encryption circuit, comprising: an addressing unit, an encryption unit and a register group connected in sequence. The addressing unit receives an input signal and outputs an address after decoding the input signal; the encryption unit outputs an encrypted address after encrypting the address, and looks up the corresponding register group according to the encrypted address, to enable the write enable of the register group.

[0030] In a possible implementation, the addressing unit comprises a plurality of inverters and AND gates; the input ends of the AND gates are connected with the input ends or the output ends of any two inverters.

[0031] The addressing unit is connected with 4 address inputs ADDR<0>, ADDR<1>, ADDR<2> and ADDR<3>, and the address is input to the decoding part for decoding. Each address can take a value of 0 or 1, and there are 16 combinations of 4-bit addresses in total, which are arranged in ascending order as 00H-0FH in hexadecimal, corresponding to the addresses of 16 groups of registers. The decoding part is composed of 24 AND gates. Because of the particularity of AND logic, both inputs of the AND gate can take 0 or 1, so the AND gate has 4 inputs. Only when both inputs of the AND gate are 1, the output of the AND gate is 1. The address decoding is constructed by the particularity of AND logic, and is arranged in ascending order as 00H-0FH.

[0032] As shown in the following, Figure 2As shown, the four input signals are arranged from least significant bit to most significant bit in ADDR. <0> ~ADDR <3> ADDR_N is obtained after inverting the values ​​using an inverter. <0> ~ADDR_N <3> Two sets of data have identical data bits that are opposites of each other, such as ADDR. <0> If the value is 0, then ADDR_N <0> The value is 1.

[0033] like Figure 2 As shown in the figure, the two input signals are ADDR_N. <0> and ADDR_N <1> The two input signals are ANDed; the output is 1 only when both input signals are 1. Also, because ADDR_N <0> and ADDR_N <1> It is ADDR <0> and ADDR <1> The value obtained by the inversion operation, i.e., ADDR <0> and ADDR <1> When all values ​​are 0, the output is 1, so the output of M0 is recorded as ADDR_XX00_P.

[0034] In this notation, XX00_P represents the lower two ADDR bits of the four-bit address. <0> and ADDR <1> When all values ​​are 0, the output is 1. Similarly... Figure 2 The output of M1 is ADDR_10XX_P, where 10XX_P represents the two most significant bits of the four-bit address, ADDR. <3> and ADDR <2> When the values ​​are 1 and 0, the output is 1; otherwise, the output is 0. Following the above method, we can list all eight possible combinations where the high two and low two bits of the four-bit address output 1. The four combinations for the low two bits are ADDR_XX00_P, ADDR_XX01_P, ADDR_XX10_P, and ADDR_XX11_P. The four combinations for the high two bits are ADDR_00XX_P, ADDR_01XX_P, ADDR_10XX_P, and ADDR_11XX_P.

[0035] like Figure 2 As shown in M3, the two input signals are ADDR_XX00_P and ADDR_00XX_P, both with an input value of 1. The output after the AND operation is also 1, denoted as ADDR_0000_P. This notation indicates that when all four address bits are 0, the output of the AND logic gate M2 is 1, and the output of other input combinations is 0.

[0036] Similarly, such as Figure 2The inputs of the AND gate M2 are ADDR_XX11_P and ADDR_11XX_P, wherein ADDR_XX11_P represents that when the lower two bits ADDR<0> and ADDR<1> of the 4-bit address are both 1, the value of ADDR_XX11_P is 1. Therefore, when ADDR_XX11_P and ADDR_11XX_P are both 1, the output of the AND gate M2 is 1, and the output is recorded as ADDR_1111_P. The notation indicates that when the four-bit address is all 1, the output of the AND gate M2 is 1, and the output of the remaining input combination is 0.

[0037] According to the above rule, when the output of the addressing unit is 1, there are 16 combinations of the 4-bit address, and each combination has a unique combination method of the 4-bit address. The 16 outputs are recorded as ADDR_0000_P-ADDR_1111_P, which are used by the encryption unit. That is, among the 16 combinations of the 4-bit input address, the output of only one combination is high regardless of the change of the 4-bit input.

[0038] In practical applications, other addresses can be selected as encryption bits, and the number of address bits of the addressing unit is not limited to 4-bit addresses. Similarly, the number of registers is not limited to 16 groups.

[0039] In a possible implementation, the encryption unit includes a two-choice logic gate, a flip-flop and an inverter. The two-choice logic gate is a three-input logic gate, including an input port S, an input port A0 and an input port A1. The flip-flop is a 5-port logic gate, including an input port CLK, an input port D, an input port RN, an output port Q and an output port QN.

[0040] In a possible implementation, the signal output by any one AND gate of the addressing unit is connected to the input port S of the two-choice logic gate after being inverted; and the signal output by the above any one AND gate is connected to the input port A0.

[0041] The output port of the two-choice logic gate is connected to the input port D of the flip-flop, and the output port Q of the flip-flop is connected to the input port A1 of the two-choice logic gate. When the signal received by the input port S is a first level, the output port of the two-choice logic gate is selected as A0; when the signal received by the input port S is a second level, the output port of the two-choice logic gate is selected as A1. In the embodiment of the application, the first level is 0 and the second level is 1. When the signal received by the input port S is the first level, the output port Q outputs the second level; when the signal received by the input port S is the second level, the output port Q outputs the first level.

[0042] In one example, the output of the above structure is an enable signal of the encryption unit, and is in conjunction with each output of the above addressing unit. When the enable signal is 1, the addressing signal can normally address the register group and write data. When the enable signal is 0, the addressing signal can normally address the register group, but cannot write data. That is, only when the encryption unit is turned on, the address combination can address the corresponding register group and write data into the register group.

[0043] In one possible implementation, when the reset signal received by the input port RN is at a first level, the output port Q of the flip-flop outputs 0, and the output port QN is the negation of the value of the output port Q; when the reset signal received by the input port RN is at a second level and the clock signal CLK received by the input port CLK changes from the first level to the second level, the value of the output port Q takes the value of the input port D, and the output port QN is the negation of the value of the output port Q.

[0044] As shown in Figure 3 , in the figure, the input of the inverter logic gate N0 is ADDR_1111_P, and the output is the negation of ADDR_1111_P, denoted as ADDR_1111_N. Figure 3 When the input port S of the multiplexer N1 is 0, the output port Z takes the value of the input A0; if the input port S is 1, the output port Z takes the value of the input port A1. When the reset signal received by the input port RN of the flip-flop N2 is 0, the flip-flop N2 is in a reset state, and the output port Q is 0. The reset signal RN changes from 0 to 1 after the entire circuit is powered on for a period of time, and when the system clock CLK_SYS changes from 0 to 1, the value of the output port Q is equal to the value of the input D.

[0045] As shown in Figure 3 , the addressing signal ADDR_1111_P is connected to the A0 end of the multiplexer N1, ADDR_1111_P is negated to get ADDR_1111_N connected to the S end of the multiplexer N1, the output Z end of the multiplexer is connected to the input D end of the flip-flop N2, and the output Q end of the flip-flop N2 is connected to the A1 end of the multiplexer N1. The system clock CLK_SYS is a group of signals that alternately change between high level 1 and low level 0 with a fixed time rule.

[0046] Further, according to the above signal line connection, when ADDR_1111_P is equal to 0, ADDR_1111_N is equal to 1, the output Z of the multiplexer N1 is A1, that is, the output Q of the flip-flop N2, and because the initial value of the flip-flop N2 is 0, the output of the multiplexer N1 is 0. When the system clock CLK_SYS changes from 0 to 1, the output Q of the flip-flop is the input D, that is, 0, and the system composed of the two logic gates N1 and N2 stably outputs 0.

[0047] Further, when ADDR_1111_P is equal to 1, ADDR_1111_N is equal to 0, the output Z of the one-select logic gate N1 is A0, i.e. ADDR_1111_P is equal to 1, when the system clock CLK_SYS changes from 0 to 1, the output Q of the flip-flop is the input D, i.e. the output 1 of N1. When ADDR_1111_P changes from 1 to 0, ADDR_1111_N is equal to 1, the output of the one-select logic gate N1 changes to A1. Since the output of the flip-flop has changed to 1 when ADDR_1111_P is equal to 1, the output of the one-select logic gate N1 is still 1, i.e. the input of the flip-flop is still 1. The system composed of the two logic gates N1 and N2 outputs 1 stably. In other words, when ADDR_1111_P is equal to 1, the system composed of N1 and N2 outputs 1 stably.

[0048] Further, the output of the flip-flop N2 is named WR_EN, and the 16 outputs of the addressing unit are subjected to AND operation with WR_EN respectively. As shown in Figure 4 N3, the two inputs are ADDR_0111_P and WR_EN respectively, and the output is 1 only when the two inputs are both 1. The four-bit address combination in ADDR_0111_P is in hexadecimal mode, and the output is named SFR_07H_WR, wherein H represents hexadecimal. According to the output logic of the flip-flop N2, WR_EN is equal to 1 only when ADDR_1111_P is equal to 1. Therefore, the addressing line network ADDR_1111_P is regarded as an encryption bit.

[0049] As shown in Figure 4 , the 16 outputs of the addressing unit are subjected to AND operation with WR_EN respectively to obtain 16 outputs, which are named SFR_00H_WR-SFR_0FH_WR in hexadecimal mode.

[0050] According to the above encryption method, the whole addressing system can output 1 to the register group for next operation only after the encryption bit addressing line network ADDR_1111_P is equal to 1 first.

[0051] In a possible implementation, the register group includes M groups of N-bit registers; each group of registers includes N flip-flops; and M and N are positive integers.

[0052] As shown in Figure 5As shown, the register group has 16 groups of 8-bit registers, and each group of the register group is composed of 8 flip-flops. When the reset of the flip-flop is 1 and the clock of the flip-flop changes from 0 to 1, the data of the input port D of the flip-flop can be written. The 16 groups of registers share one group of input data DATA[7:0]. The 16 outputs SFR_00H_WR-SFR_0FH_WR of the encryption unit each correspond to one group of registers, so the register groups are named as SFR_00H-SFR_0FH in hexadecimal address.

[0053] Taking the flip-flop group Q0 as an example, the address of the group of registers is 01H, so the input ports D of the 8 flip-flops in the group of registers are DATA[0]-DATA[7] respectively, and the 8 flip-flops share one group of clock SFR_01_WR, that is, when SFR_01_WR changes from 0 to 1, the input data DATA[0]-DATA[7] are sent to the outputs SFR_01H_P<0>-SFR_01H_P<7> of the 8 flip-flops. Similarly, the remaining 15 groups of registers share 8-bit data DATA[0]-DATA[7], and the clock of each group of registers is SFR_00H_WR-SFR_0FH_WR according to their addresses. Due to the existence of the encryption bit, only when the operator addresses the highest address bit ADDR_1111_P first, the registers of other address bits can be normally written, otherwise even if the addressing unit addresses these registers, they cannot be written, so the encryption of the register writing is realized, and no extra pin is introduced.

[0054] The register encryption circuit provided by the application encrypts the register group by the addressing unit itself, avoids the need to add an encryption line, and thus avoids the problem of adding one more enable pin in the circuit structure. The encryption of the write data to the special register is realized by using the existing addressing structure.

[0055] The above is only a specific embodiment of the application, but the protection scope of the application is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the application, which should be covered within the protection scope of the application. Therefore, the protection scope of the application should be subject to the protection scope of the claims.

Claims

1. A register encryption circuit, characterized in that, include: The addressing unit, encryption unit, and register group are connected in sequence; The addressing unit receives the input signal, decodes the input signal, and outputs the address. The encryption unit encrypts the address and outputs the encrypted address, and then looks up the corresponding register group based on the encrypted address to enable write to the register group. The encryption unit includes: a two-to-one logic gate, a flip-flop, and an inverter; The two-to-one multiplexer is a three-input logic gate, including input port S, input port A0, and input port A1; the flip-flop is a five-port logic gate, including input port CLK, input port D, input port RN, output port Q, and output port QN. The signal output from any one of the AND gates of the addressing unit is inverted and then connected to the input port S of the two-to-one logic gate; the signal output from any one of the AND gates is connected to the input port A0. The output of the 2-to-1 logic gate is connected to the input port D of the flip-flop, and the output port Q of the flip-flop is connected to the input port A1 of the 2-to-1 logic gate. When the signal received by the input port S is at the first level, the output port of the two-to-one logic gate is selected as A0; When the signal received at the input port S is at the second level, the output port of the two-to-one logic gate is selected as A1; When the signal received by the input port S is at the first level, the output port Q outputs the second level; When the signal received by the input port S is at the second level, the output port Q outputs the first level; When the reset signal received by the input port RN is at the first level, the output port Q of the trigger outputs 0, and the output port QN is the inverted value of the output port Q; When the reset signal received by the input port RN is at the second level, and the clock signal CLK received by the input port CLK changes from the first level to the second level, the value of the output port Q is the value of the input port D, and the output port QN is the inverted value of the output port Q.

2. The register encryption circuit according to claim 1, characterized in that, The addressing unit includes multiple inverters and AND gates; the input of each AND gate is connected to either the input or output of any two inverters.

3. The register encryption circuit according to claim 1, characterized in that, The register group comprises M groups of N-bit registers; each register group comprises N flip-flops; M and N are positive integers.

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