A single bus communication assembly and slave device

Abstract

The embodiment of the present application provides a single bus communication component and a slave device, data communication channels adopting a SWI bus protocol and a 1-WIRE bus protocol are established by arranging a data converter, a SWI transceiver, a 1-WIRE transceiver, a SWI ROM state machine, a 1-WIRE ROM state machine, a receiving buffer and a sending buffer in the single bus communication component, and the slave device can flexibly select corresponding data communication channels according to the bus protocol adopted by a host by arranging control information in a control register of a microprocessor in the slave device, so that the versatility of the slave device is improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of computer communication, and in particular, to a single bus communication component and a slave device. BACKGROUND

[0002] With the development of technology and economy, computers are increasingly popular in people's social life and are increasingly widely used. Generally, a computer includes a host and a slave device. The host includes core components such as a central processing unit, a memory, and a hard disk, and completes most of the calculations of the computer. The slave device communicates with the host through various buses to assist the host in completing input, output, network connection, encryption, and other computing tasks.

[0003] According to the type of the bus, the bus can be divided into single bus, double bus, and multi-bus, etc. Among them, since the single bus has only one signal line, it has the advantages of fewer required connection lines, low cost, and simple hardware design. At the same time, the single bus also supports one master and multiple slaves (i.e., one host connected with multiple slave devices) communication. These advantages make the single bus widely used in the communication between slave devices such as sensors and security chips and the host.

[0004] Currently, common single buses include 1-WIRE (one wire serial communication) bus, SWI (Single Wire Interface) bus, etc. Among them, the 1-WIRE bus has been widely used, and the SWI bus is accelerating the promotion because it supports adaptive transmission, and the slave device can adapt to a larger bandwidth range according to the performance of the master device. However, it is regrettable that the slave device in the prior art can only support one type of single bus, and the versatility of the slave device is low. SUMMARY

[0005] Embodiments of the present application aim to at least partially solve one of the technical problems in the related art.

[0006] To this end, embodiments of the present application disclose a single bus communication component and a slave device to improve the versatility of the slave device.

[0007] In a first aspect, embodiments of the present application provide a single bus communication component, which is located in a slave device, and includes a data converter, a SWI transceiver, a 1-WIRE transceiver, a SWI ROM state machine, a 1-WIRE ROM state machine, a receiving buffer, a sending buffer, and a register group; wherein the register group includes a control register in which control information is stored and a state register in which state information is stored, and the control information is flexibly set by a microprocessor in the slave device as needed.

[0008] The data converter is configured to determine whether to turn on the SWI transceiver or the 1-WIRE transceiver according to the control information, and to convert high and low level signals from the single bus interface into single bit data and send the single bit data to the SWI transceiver or the 1-WIRE transceiver when the state information indicates that the slave device is in the FUNCTION stage, and to convert single bit data from the SWI transceiver or the 1-WIRE transceiver into high and low level signals and send the high and low level signals to the single bus interface.

[0009] The SWI transceiver is configured to convert single bit data sent by the data converter into parallel data according to SWI timing and send the parallel data to the receiving buffer when turned on, convert parallel data from the sending buffer into single bit data according to SWI timing and send the single bit data to the data converter, and interact with the SWI ROM state machine in the ROM stage to complete the ROM process.

[0010] The 1-WIRE transceiver is configured to convert single bit data sent by the data converter into parallel data according to 1-WIRE timing and send the parallel data to the receiving buffer when turned on, convert parallel data from the sending buffer into single bit data according to 1-WIRE timing and send the single bit data to the data converter, and interact with the 1-WIRE ROM state machine in the ROM stage to complete the ROM process.

[0011] The SWI ROM state machine is configured to receive ROM instructions from the single bus interface through the SWI transceiver to complete the ROM process.

[0012] The 1-WIRE ROM state machine is configured to receive ROM instructions from the single bus interface through the 1-WIRE transceiver to complete the ROM process.

[0013] The sending buffer is configured to store parallel data from the memory in the slave device for reading by the SWI transceiver or the 1-WIRE transceiver.

[0014] The receiving buffer is configured to store parallel data from the SWI transceiver or the 1-WIRE transceiver for the slave device to store the parallel data from the SWI transceiver or the 1-WIRE transceiver into the memory in the slave device.

[0015] In a specific embodiment of the first aspect, the data converter comprises a first data converter and a second data converter; wherein,

[0016] the first data converter is configured to determine whether the SWI transceiver is on according to the control information, and to convert high / low level signals from the single bus interface into single bit data and send to the SWI transceiver, and convert single bit data from the SWI transceiver into high / low level signals and send to the single bus interface when the status information indicates that the slave device is in the FUNCTION stage;

[0017] the second data converter is configured to determine whether the 1-WIRE transceiver is on according to the control information, and to convert high / low level signals from the single bus interface into single bit data and send to the 1-WIRE transceiver, and convert single bit data from the 1-WIRE transceiver into high / low level signals and send to the single bus interface when the status information indicates that the slave device is in the FUNCTION stage.

[0018] In an embodiment of the first aspect, the data converter is a serial data multiplexer.

[0019] In an embodiment of the first aspect, the receiving buffer comprises a first receiving buffer and a second receiving buffer, and the sending buffer comprises a first sending buffer and a second sending buffer.

[0020] the SWI transceiver is configured to convert single bit data sent by the data converter into parallel data according to SWI timing and send to the first receiving buffer when the SWI transceiver is on, convert parallel data from the first sending buffer into single bit data according to SWI timing and send to the data converter, and interact with the SWI ROM state machine in the ROM stage to complete the ROM process.

[0021] the 1-WIRE transceiver is configured to convert single bit data sent by the data converter into parallel data according to 1-WIRE timing and send to the second receiving buffer when the 1-WIRE transceiver is on, convert parallel data from the second sending buffer into single bit data according to 1-WIRE timing and send to the data converter, and interact with the 1-WIRE ROM state machine in the ROM stage to complete the ROM process.

[0022] In an embodiment of the first aspect, the SWI transceiver and the 1-WIRE transceiver use the same sending buffer, and the SWI transceiver and the 1-WIRE transceiver use the same receiving buffer.

[0023] further comprising a parallel data multiplexer.

[0024] The parallel data multiplexer is configured to transmit parallel data from the sending buffer to the SWI transceiver or the 1-WIRE transceiver, and transmit parallel data from the SWI transceiver or the 1-WIRE transceiver to the receiving buffer; wherein the parallel data multiplexer determines the data transmission direction and the data communication channel according to the control information.

[0025] In an embodiment of the first aspect, the system further comprises a DMA controller.

[0026] The DMA controller is configured to determine the data transmission direction according to the control information, when in the sending direction, the DMA controller is configured to write parallel data from the memory in the slave device to the sending buffer, and modify the state information in the state register when the sending is completed, provide a sending completion interrupt to the microprocessor, when in the receiving direction, the DMA controller is configured to write parallel data stored in the receiving buffer to the memory in the slave device, and modify the state information in the state register when the receiving is completed, provide a receiving completion interrupt to the microprocessor.

[0027] In an embodiment of the first aspect, the DMA controller is further configured to stop writing parallel data from the memory in the slave device to the sending buffer when the remaining space of the sending buffer is less than or equal to a preset size; wherein the preset size is equal to n transmission units of the memory in the slave device, and n≥2.

[0028] In an embodiment of the first aspect, the data converter is a serial data multiplexer, the SWI transceiver and the 1-WIRE transceiver use the same sending buffer, the SWI transceiver and the 1-WIRE transceiver use the same receiving buffer, and the system further comprises a DMA controller and a parallel data multiplexer.

[0029] The DMA controller is configured to determine the data transmission direction according to the control information, when in the sending direction, the DMA controller is configured to write parallel data from the memory in the slave device to the sending buffer, and modify the state information in the state register when the sending is completed, provide a sending completion interrupt to the microprocessor, when in the receiving direction, the DMA controller is configured to write parallel data stored in the receiving buffer to the memory in the slave device, and modify the state information in the state register when the receiving is completed, provide a receiving completion interrupt to the microprocessor.

[0030] The parallel data multiplexer is configured to transmit parallel data from the sending buffer to the SWI transceiver or the 1-WIRE transceiver, and transmit parallel data from the SWI transceiver or the 1-WIRE transceiver to the receiving buffer; wherein the parallel data multiplexer determines a data transmission direction and a data communication channel according to the control information.

[0031] In a specific embodiment of the first aspect, the single bus component is implemented based on an FPGA.

[0032] In a specific embodiment of the first aspect, a default mode of the control information represents turning on the 1-WIRE transceiver.

[0033] In the second aspect, the embodiments of the present application further disclose a slave device comprising the single bus communication component of any one of the first aspect.

[0034] The embodiments of the present application have the following beneficial effects:

[0035] The single bus communication component and the slave device provided by the embodiment of the present application are located in the slave device, and the single bus communication component comprises a data converter, a SWI transceiver, a 1-WIRE transceiver, a SWI ROM state machine, a 1-WIRE ROM state machine, a receiving buffer, a sending buffer and a register group; the data converter is used to determine whether the SWI transceiver or the 1-WIRE transceiver is turned on according to the control information, and is used to send the single bit data converted from the high and low level signals from the single bus interface to the SWI transceiver or the 1-WIRE transceiver when the state information indicates that the slave device is in the FUNCTION stage, and to send the high and low level signals converted from the single bit data from the SWI transceiver or the 1-WIRE transceiver to the single bus interface; the SWI transceiver is used to send the single bit data sent by the data converter to the receiving buffer after converting the single bit data into parallel data according to the SWI timing when the SWI transceiver is turned on, to send the parallel data from the sending buffer to the data converter after converting the parallel data into single bit data according to the SWI timing, and to interact with the SWI ROM state machine in the ROM stage to complete the ROM process; the 1-WIRE transceiver is used to send the single bit data sent by the data converter to the receiving buffer after converting the single bit data into parallel data according to the 1-WIRE timing when the 1-WIRE transceiver is turned on, to send the parallel data from the sending buffer to the data converter after converting the parallel data into single bit data according to the 1-WIRE timing, and to interact with the 1-WIRE ROM state machine in the ROM stage to complete the ROM process; the SWI ROM state machine is used to receive the ROM instruction from the single bus interface through the SWI transceiver to complete the ROM process; the 1-WIRE ROM state machine is used to receive the ROM instruction from the single bus interface through the 1-WIRE transceiver to complete the ROM process; the sending buffer is used to store the parallel data from the memory in the slave device for the SWI transceiver or the 1-WIRE transceiver to read; and the receiving buffer is used to store the parallel data from the SWI transceiver or the 1-WIRE transceiver for the slave device to store the parallel data from the SWI transceiver or the 1-WIRE transceiver into the memory in the slave device. The technical scheme of the embodiment of the present application establishes the data communication channels using the SWI bus protocol and the 1-WIRE bus protocol through the data converter, the SWI transceiver, the 1-WIRE transceiver, the SWI ROM state machine, the 1-WIRE ROM state machine, the receiving buffer and the sending buffer, and sets the control register, so that the slave device can flexibly select the corresponding data communication channel according to the bus protocol used by the host through the microprocessor in the slave device setting the control information in the control register, thereby improving the versatility of the slave device. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1A structural schematic diagram of a single bus communication component provided by an embodiment of the present application is shown in FIG. 1.

[0037] Figure 2 A structural schematic diagram of a slave device provided by an embodiment of the present application is shown in FIG. 2.

[0038] Figure 3 A structural schematic diagram of another single bus communication component provided by an embodiment of the present application is shown in FIG. 3.

[0039] Figure 4 A structural schematic diagram of still another single bus communication component provided by an embodiment of the present application is shown in FIG. 4.

[0040] Figure 5 A structural schematic diagram of yet another single bus communication component provided by an embodiment of the present application is shown in FIG. 5. DETAILED DESCRIPTION

[0041] In order to more clearly understand the above objectives, features and advantages of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the technical concepts of the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present application.

[0042] As mentioned in the background, the prior art slave device can only support one single bus type, and the versatility of the slave device is low. In order to solve the problem, the present application provides a single bus communication component and a slave device. The single bus communication component is configured to establish data communication channels using SWI bus protocol and 1-WIRE bus protocol by setting a data converter, an SWI transceiver, a 1-WIRE transceiver, an SWI ROM state machine, a 1-WIRE ROM state machine, a receiving buffer and a sending buffer in the single bus communication component. A control register is also set, and the control information in the control register is set by a microprocessor in the slave device, so that the slave device can flexibly select the corresponding data communication channel according to the bus protocol used by the host, thereby improving the versatility of the slave device. In actual application, the microprocessor can be an MCU (Microcontroller Unit), a DSP (Digital Signal Processor) or the like.

[0043] Before the single bus communication assembly of the embodiment of the application is described, the application scenario of the embodiment of the application is first exemplified, so that the technical solution of the embodiment of the application can be more intuitively understood. One possible scenario is that the host is a vehicle-mounted controller, the slave device is configured with a security chip (the security chip is configured with a microprocessor) providing security services such as encryption, signature, and the single bus communication assembly of the embodiment of the application, the vehicle-mounted controller and the slave device are connected through a SWI bus, and the single bus communication assembly provides data transceiving services as a transceiving module between the vehicle-mounted controller and the security chip. Another possible application scenario is a smart home system, a master controller as a host is connected to a temperature sensor, a lighting device and other slave devices through a 1-WIRE bus, and each slave device is provided with a microprocessor and the single bus communication assembly of the embodiment of the application. It should be noted that the application scenario of the embodiment of the application is only exemplarily described, and the single bus communication assembly of the embodiment of the application is not limited to the foregoing application scenario, and other hosts and slave devices provided with microprocessors can use the technical solution provided by the embodiment of the application for communication.

[0044] Further, after the application scenario of the embodiment of the application is exemplarily described, the technical solution itself is described in combination with the drawings. Referring to Figure 1 , a structure diagram of the single bus communication assembly provided by the embodiment of the application is shown, Figure 1 The single bus communication assembly shown in the figure is located in the slave device. For the convenience of description, the embodiment of the application further provides a structure diagram of a slave device using the single bus communication assembly of the embodiment of the application, which can be specifically referred to Figure 2 . The embodiment of the application will be described in more detail in combination with Figure 1 and Figure 2 .

[0045] Referring to Figure 1 , the single bus communication assembly provided by the embodiment of the application can include a data converter 10, a SWI transceiver 11, a 1-WIRE transceiver 12, a SWI ROM state machine 13, a 1-WIRE ROM state machine 14, a sending buffer 15, a receiving buffer 16 and a register group 17.

[0046] The register group 17 includes a control register in which control information is stored and a state register in which state information is stored.

[0047] In particular, the control information is information for controlling the data transceiving of the single bus communication component. In some embodiments, the control information can include a transceiving mode, a communication protocol adopted by the host, reset information, etc. The transceiving mode indicates whether data is to be transmitted or received, the communication protocol adopted by the host can be a 1-WIRE communication protocol or a SWI communication protocol, which is determined according to the communication protocol supported by an application program in the host, and the reset information is used for controlling hardware reset. In other embodiments, the control information can also include address information, data length information, etc. Of course, a corresponding address register can also be configured for the address information, and a corresponding length register can also be configured for the data length information. In actual use, the configuration of the address register and the length register or the selection of the address information and the data length information as a part of the control information is a conventional selection of the register, and thus will not be described herein.

[0048] Generally, the control information is flexibly set by the microprocessor 20 in the slave device as needed. For example, when the host adopts the 1-WIRE communication protocol, the communication protocol in the control information is set to 1-WIRE, and when the host adopts the SWI communication protocol, the communication protocol in the control information is set to SWI. Referring to Figure 2 As shown, the microprocessor is in communication connection with the register set 17 through the internal bus of the slave device. In actual application, the register set can be connected to the internal bus of the slave device by using an APB (Advanced Peripheral Bus) interface, etc.

[0049] The state information is information for describing the running state of the single bus communication component. In some embodiments, the state information can include phase information, a number of transmitted bytes, a number of received bytes, etc. The phase information indicates whether the current is in a ROM phase or a FUNCTION phase. The ROM phase is an initialization phase, and mainly performs preparation work for data transceiving, such as searching and matching of the slave device. The FUNCTION phase is a function phase, and mainly performs transceiving operation of data. In other embodiments, the state information can also include interrupt information, etc. Of course, a corresponding interrupt register can also be configured for the interrupt information. In actual use, the configuration of the interrupt register or the selection of the interrupt information as a part of the state information is a conventional selection of the register, and thus will not be described herein.

[0050] Continuing to refer to Figure 1 and Figure 2As shown, the data converter 10 is used to determine whether to turn on the SWI transceiver 11 or the 1-WIRE transceiver 12 according to the control information. Where the communication protocol in the control information is SWI, the data converter 10 determines to turn on the SWI transceiver 11; where the communication protocol in the control information is 1-WIRE, the data converter 10 determines to turn on the 1-WIRE transceiver 12. It is obvious that the data converter 10 needs to be in communication connection with the register set 17 to obtain the control information, the status information, etc.

[0051] The data converter 10 is used to convert the high-low level signal from the single bus interface into single bit data and then send to the SWI transceiver 11 or the 1-WIRE transceiver 12 when the status information represents that the slave device is in the FUNCTION stage, and convert the single bit data from the SWI transceiver 11 or the 1-WIRE transceiver 12 into high-low level signal and then send to the single bus interface. Where the single bus interface is the communication interface connected between the host and the slave device, when the SWI transceiver 11 is turned on and the status information represents that the slave device is in the FUNCTION stage, the data converter 10 converts the high-low level signal from the single bus interface into single bit data and then sends to the SWI transceiver 11, and converts the single bit data from the SWI transceiver 11 into high-low level signal and then sends to the single bus interface. When the 1-WIRE transceiver 12 is turned on and the status information represents that the slave device is in the FUNCTION stage, the data converter 10 converts the high-low level signal from the single bus interface into single bit data and then sends to the 1-WIRE transceiver 12, and converts the single bit data from the 1-WIRE transceiver 12 into high-low level signal and then sends to the single bus interface.

[0052] The SWI transceiver 11 is used to convert the single bit data sent by the data converter 10 into parallel data according to the SWI timing when turned on and then send to the receiving buffer 16, convert the parallel data from the sending buffer 15 into single bit data according to the SWI timing and then send to the data converter 10, and interact with the SWI ROM state machine 13 in the ROM stage to complete the ROM process. Where the conversion of the single bit data into parallel data according to the SWI timing and the conversion of the parallel data into single bit data according to the SWI timing are prior art and will not be described here.

[0053] 1-WIRE transceiver 12 is used to convert the single bit data sent by data converter 10 into parallel data according to 1-WIRE timing and send the parallel data to receiving buffer 16, convert the parallel data from sending buffer 15 into single bit data according to 1-WIRE timing and send the single bit data to data converter 10, and interact with 1-WIRE ROM state machine 14 in ROM phase to complete the ROM process. The conversion of single bit data into parallel data and the conversion of parallel data into single bit data according to 1-WIRE timing are prior art and will not be described here.

[0054] SWI ROM state machine 13 is used to receive the ROM instruction from the single bus interface through SWI transceiver 11 to complete the ROM process.

[0055] Specifically, the ROM instruction is from the host, and SWI ROM state machine 13 performs search, read, match and bypass and other ROM processes according to the ROM instruction. In practical applications, search and match are used in the scenario of one host connecting multiple slave devices, and a binary tree model can be used to complete the search process of the slave devices; read and bypass are used in the scenario of one host connecting one slave device. The more specific ROM process of SWI protocol can be referred to prior art and will not be described here.

[0056] 1-WIRE ROM state machine 14 is used to receive the ROM instruction from the single bus interface through 1-WIRE transceiver 12 to complete the ROM process.

[0057] Specifically, the ROM instruction is from the host, and 1-WIRE ROM state machine 14 performs search, read, match and bypass and other ROM processes according to the ROM instruction. The more specific ROM process of 1-WIRE protocol can be referred to prior art and will not be described here.

[0058] In addition, in practical applications, SWI ROM state machine 13 and 1-WIRE ROM state machine 14 can also be used to receive the bus reset signal sent by the host through the data converter to perform subsequent bus interrupt reset.

[0059] Sending buffer 15 is used to store the parallel data from the memory 21 in the slave device for SWI transceiver 11 or 1-WIRE transceiver 12 to read.

[0060] The memory 21 in the slave device can be SRAM (Static Random-Access Memory) or the like, and is connected to the internal bus of the slave device. The parallel data in the memory 21 of the slave device is sent to the sending buffer 15 by the microprocessor 20 or a DMA controller in the slave device.

[0061] The receiving buffer 16 is used to store the parallel data from the SWI transceiver 11 or the 1-WIRE transceiver 12, so that the slave device can store the parallel data from the SWI transceiver 11 or the 1-WIRE transceiver 12 into the memory in the slave device.

[0062] The parallel data in the receiving buffer is sent to the memory 21 in the slave device by the microprocessor 20 or a DMA controller in the slave device.

[0063] The single bus communication component provided by the embodiment of the present application is located in a slave device, and comprises a data converter, a SWI transceiver, a 1-WIRE transceiver, a SWI ROM state machine, a 1-WIRE ROM state machine, a receiving buffer, a sending buffer and a register group; the data converter is used for determining whether to turn on the SWI transceiver or the 1-WIRE transceiver according to control information, and is used for converting high and low level signals from a single bus interface into single bit data and then sending the single bit data to the SWI transceiver or the 1-WIRE transceiver when state information indicates that the slave device is in a FUNCTION stage, and converting single bit data from the SWI transceiver or the 1-WIRE transceiver into high and low level signals and then sending the high and low level signals to the single bus interface; the SWI transceiver is used for converting single bit data sent by the data converter into parallel data according to SWI timing and then sending the parallel data to the receiving buffer when the SWI transceiver is turned on, converting parallel data from the sending buffer into single bit data according to SWI timing and then sending the single bit data to the data converter, and is used for interacting with the SWI ROM state machine in a ROM stage to complete a ROM process; the 1-WIRE transceiver is used for converting single bit data sent by the data converter into parallel data according to 1-WIRE timing and then sending the parallel data to the receiving buffer when the 1-WIRE transceiver is turned on, converting parallel data from the sending buffer into single bit data according to 1-WIRE timing and then sending the single bit data to the data converter, and is used for interacting with the 1-WIRE ROM state machine in the ROM stage to complete the ROM process; the SWI ROM state machine is used for receiving a ROM instruction from the single bus interface through the SWI transceiver to complete the ROM process; the 1-WIRE ROM state machine is used for receiving a ROM instruction from the single bus interface through the 1-WIRE transceiver to complete the ROM process; the sending buffer is used for storing parallel data from a memory in the slave device for reading by the SWI transceiver or the 1-WIRE transceiver; and the receiving buffer is used for storing parallel data from the SWI transceiver or the 1-WIRE transceiver for storing the parallel data from the SWI transceiver or the 1-WIRE transceiver into the memory in the slave device. The technical scheme of the embodiment of the present application establishes data communication channels using a SWI bus protocol and using a 1-WIRE bus protocol through the data converter, the SWI transceiver, the 1-WIRE transceiver, the SWI ROM state machine, the 1-WIRE ROM state machine, the receiving buffer and the sending buffer; and a control register is arranged, and control information in the control register is set by a microprocessor in the slave device, so that the slave device can flexibly select a corresponding data communication channel according to a bus protocol used by a host, thereby improving the versatility of the slave device.

[0064] Further, in actual implementation, the data converter 10 can have various forms. For example, referring to Figure 3As shown in the figure, in some embodiments of the present application, the data converter 10 comprises a first data converter 101 and a second data converter 102. In this embodiment, the first data converter 101 and the second data converter 102 are respectively connected with the register group 17 to obtain control information, state information, etc.

[0065] The first data converter 101 is configured to determine whether the SWI transceiver 11 is turned on according to the control information, and to convert the high / low level signal from the single bus interface into a single bit data and send it to the SWI transceiver 11, and convert the single bit data from the SWI transceiver 11 into a high / low level signal and send it to the single bus interface when the state information indicates that the slave device is in the FUNCTION stage.

[0066] The second data converter 102 is configured to determine whether the 1-WIRE transceiver 12 is turned on according to the control information, and to convert the high / low level signal from the single bus interface into a single bit data and send it to the 1-WIRE transceiver 12, and convert the single bit data from the 1-WIRE transceiver 12 into a high / low level signal and send it to the single bus interface when the state information indicates that the slave device is in the FUNCTION stage.

[0067] Although the use of two data converters can realize the selection of the corresponding communication channel according to the actual needs, it may cause the problem of complex structure of the single bus communication component. To solve this problem, in some embodiments of the present application, the data converter 10 is a serial data multiplexer. In this embodiment, the serial data multiplexer is multiplexed by the SWI transceiver 11 and the 1-WIRE transceiver 12, and the serial data multiplexer selects to turn on the SWI transceiver 11 or the 1-WIRE transceiver 12 according to the control information. Compared with the embodiment shown in the figure, the number of data converters in the single bus communication component is reduced, and the structure is simple. Figure 3

[0068] Further, optionally, the sending buffer 15 and the receiving buffer 16 can have various forms. For example, referring to the figure, in some embodiments of the present application, the receiving buffer 16 comprises a first receiving buffer 161 and a second receiving buffer 162, and the sending buffer 15 comprises a first sending buffer 151 and a second sending buffer 152. Figure 4 In some embodiments of the present application, the first receiving buffer 161 and the second receiving buffer 162 can be implemented by FIFO in actual application.

[0069] Figure 4 ​​In the shown embodiment, the SWI transceiver 11 is configured to convert the single-bit data sent by the data converter 10 into parallel data according to the SWI timing when the SWI transceiver 11 is powered on, and send the parallel data to the first receiving buffer 161, convert the parallel data from the first sending buffer 151 into single-bit data according to the SWI timing, and send the single-bit data to the data converter 10, and interact with the SWI ROM state machine 13 in the ROM phase to complete the ROM process.

[0070] The 1-WIRE transceiver 12 is configured to convert the single-bit data sent by the data converter 10 into parallel data according to the 1-WIRE timing when the 1-WIRE transceiver 12 is powered on, and send the parallel data to the second receiving buffer 162, convert the parallel data from the second sending buffer 152 into single-bit data according to the 1-WIRE timing, and send the single-bit data to the data converter 10, and interact with the 1-WIRE ROM state machine 14 in the ROM phase to complete the ROM process.

[0071] Optionally, in some other embodiments of the present application, the SWI transceiver 11 and the 1-WIRE transceiver 12 can share the same sending buffer 15 and receiving buffer 16. Specifically, the SWI transceiver 11 and the 1-WIRE transceiver 12 use the same sending buffer 15, and the SWI transceiver 11 and the 1-WIRE transceiver 12 use the same receiving buffer 16. In this embodiment, the single bus communication assembly of the present application can further comprise a parallel data multiplexer to enable the sending buffer 15 and the receiving buffer 16 to be connected to the SWI transceiver 11 and the 1-WIRE transceiver 12 simultaneously.

[0072] Specifically, the parallel data multiplexer is configured to send the parallel data from the sending buffer 15 to the SWI transceiver 11 or the 1-WIRE transceiver 12, and send the parallel data from the SWI transceiver 11 or the 1-WIRE transceiver 12 to the receiving buffer 16. The parallel data multiplexer determines the data transmission direction and the data communication channel according to the control information, specifically, determines the data transmission direction according to the transceiving mode in the control information, and determines the data communication channel according to the communication protocol adopted by the host in the control information.

[0073] Further, considering the occupation of the slave microprocessor resources by the communication and the communication efficiency, the single bus communication assembly of the present application can further comprise a DMA controller.

[0074] In particular, the DMA controller is configured to determine the data transfer direction according to the control information, when in the sending direction, the DMA controller is configured to write the parallel data from the memory in the slave device into the sending buffer 15, and modify the state information in the state register when the sending is completed, to provide the sending completion interrupt to the microprocessor, and when in the receiving direction, the DMA controller is configured to write the parallel data stored in the receiving buffer 16 into the memory in the slave device, and modify the state information in the state register when the receiving is completed, to provide the receiving completion interrupt to the microprocessor.

[0075] In some implementations, a dedicated interrupt flag register can be provided to set the receiving completion interrupt flag and the sending completion interrupt flag.

[0076] In some implementations, the memory 21 in the slave device is connected to the internal bus of the slave device, and the DMA controller is connected to the internal bus of the slave device through an AHB interface, to realize the data interaction between the DMA controller and the memory 21 in the slave device. The internal bus of the slave device can be an AMBA bus supporting both APB and AHB interfaces, but is not limited thereto. For example, the internal bus of the slave device can also be an AXI bus, and when the DMA controller is connected to the internal bus through an AHB interface, a conversion bridge for converting the data on the AXI bus into data supporting the AHB bus protocol needs to be added, and when the register group is connected to the internal bus through an APB interface, a conversion bridge for converting the data on the AXI bus into data supporting the APB bus protocol needs to be added.

[0077] It should be noted that when the single-bus communication component includes the DMA controller, the control information in the control register can further include DMA start information, DMA enable information and DMA buffer size information. The DMA start information is used to indicate whether the DMA controller is started, the DMA enable information is used to indicate whether the DMA controller is enabled, and the DMA buffer size information is used to indicate the size of the buffer of the DMA controller.

[0078] Further, considering that the DMA controller writes the parallel data from the memory of the slave device into the sending buffer at a higher speed than the SWI transceiver 11 and the 1-WIRE transceiver 12 read the data, in some embodiments of the present embodiment, the DMA controller is further configured to stop writing the parallel data from the memory of the slave device into the sending buffer 15 when the remaining space of the sending buffer 15 is less than or equal to a preset size.

[0079] The preset size is equal to n transmission units of the memory of the slave device, and n≥2. The transmission unit is the length of data transferred by the DMA controller at one time, which can be 4 bytes, 8 bytes, etc. n is an empirical value set by a user according to needs. With this embodiment, on the one hand, the overflow of data in the sending buffer 15 caused by the mismatch between the reading speed of the DMA controller and the data reading speed of the SWI transceiver and the 1-WIRE transceiver can be avoided, and on the other hand, the DMA controller writes the parallel data from the memory of the slave device into the sending buffer 15 only when the remaining space of the sending buffer 15 is greater than the preset size, thereby reducing the operation frequency of the DMA controller and further reducing power consumption.

[0080] Further, referring to FIG. 1, Figure 5 Further, referring to FIG. 1,

[0081] Specifically, the DMA controller 18 is configured to determine the data transmission direction according to the control information. When in the sending direction, the DMA controller 18 is configured to write the parallel data from the memory of the slave device into the sending buffer 15, and modify the state information in the state register when the sending is completed, to provide a sending completion interrupt to the microprocessor. When in the receiving direction, the DMA controller is configured to write the parallel data stored in the receiving buffer 16 into the memory of the slave device, and modify the state information in the state register when the receiving is completed, to provide a receiving completion interrupt to the microprocessor.

[0082] The parallel data multiplexer 19 is configured to transmit the parallel data from the transmitting buffer 15 to the SWI transceiver 11 or the 1-WIRE transceiver 12, and transmit the parallel data from the SWI transceiver 11 or the 1-WIRE transceiver 12 to the receiving buffer 16. The parallel data multiplexer 19 determines the data transmission direction and the data communication channel according to the control information in the control register. Specifically, the parallel data multiplexer 19 determines the data transmission direction according to the transceiving mode in the control information, and determines the data communication channel according to the communication protocol adopted by the host in the control information.

[0083] Figure 5 In the illustrated embodiment, the serial data multiplexer, the transmitting buffer and the receiving buffer are multiplexed by the SWI transceiver 11 and the 1-WIRE transceiver 12, which reduces the complexity of the single bus communication component. In addition, by configuring the DMA controller, the burden of the microprocessor in the slave device is reduced, and the communication efficiency is improved.

[0084] Further, the single bus communication component in the embodiments of the present application can be implemented based on a programmable logic device, for example, the single bus communication component in the embodiments of the present application can be implemented based on an FPGA (Field Programmable Gate Array). However, the embodiments of the present application are not limited thereto, for example, the single bus communication component in the embodiments of the present application can be implemented based on a CPLD (Complex Programmable logic device), or based on a fixed logic device.

[0085] In order to avoid the configuration of the control information by the host using various communication protocols, in some embodiments of the present application, the default mode of the control information in the control register represents the connection of the 1-WIRE transceiver. Of course, in other embodiments, the default mode of the control information in the control register represents the connection of the SWI transceiver, or there is no default mode, which is not limited in the embodiments of the present application.

[0086] Corresponding to the foregoing embodiments of the single bus communication component, the embodiments of the present application also include a slave device comprising the single bus communication component according to any of the foregoing embodiments.

[0087] Those skilled in the art can clearly understand that the technical solutions in the embodiments of the present application can be implemented by means of software plus necessary universal hardware platforms. Based on such an understanding, the technical solutions in the embodiments of the present application can be embodied in the form of a software product, and the computer software product can be stored in a storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, and the like, and includes a plurality of instructions to cause a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the schemes described in the various embodiments of the present application or some parts of the embodiments.

[0088] The various embodiments in the specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other. In the case of no conflict, the embodiments of the present application and the features in the embodiments can be combined with each other, and each embodiment mainly describes the difference from other embodiments.

[0089] The terms "first", "second", "third", "fourth" and the like in the specification of the present application and claims, and the above-described drawings (if any) are used to distinguish similar objects, and do not have to be used to describe a particular order or sequence. It should be understood that the data used in this way can be exchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0090] The above-described embodiments of the present application do not constitute a limitation on the scope of protection of the present application. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A single bus communication assembly, characterized by, The single bus communication component is located in a slave device, and comprises a data converter, a SWI transceiver, a 1-WIRE transceiver, a SWI ROM state machine, a 1-WIRE ROM state machine, a receiving buffer, a sending buffer and a register group; wherein the register group comprises a control register storing control information and a state register storing state information, the control information being set by a microprocessor in the slave device according to a communication protocol of a host, and different transceivers being selected to be turned on based on different communication protocols of the host; The data converter is configured to determine whether the SWI transceiver or the 1-WIRE transceiver is turned on according to the control information, and to convert high and low level signals from a single bus interface into single bit data and send the single bit data to the SWI transceiver or the 1-WIRE transceiver when the state information indicates that the slave device is in a FUNCTION stage, and convert single bit data from the SWI transceiver or the 1-WIRE transceiver into high and low level signals and send the high and low level signals to the single bus interface; The SWI transceiver is configured to, when turned on, convert single bit data sent by the data converter into parallel data according to SWI timing and send the parallel data to the receiving buffer, convert parallel data from the sending buffer into single bit data according to SWI timing and send the single bit data to the data converter, and interact with the SWI ROM state machine in a ROM stage to complete a ROM process; The 1-WIRE transceiver is configured to, when turned on, convert single bit data sent by the data converter into parallel data according to 1-WIRE timing and send the parallel data to the receiving buffer, convert parallel data from the sending buffer into single bit data according to 1-WIRE timing and send the single bit data to the data converter, and interact with the 1-WIRE ROM state machine in a ROM stage to complete a ROM process; The SWI ROM state machine is configured to receive a ROM instruction from a single bus interface through the SWI transceiver to complete a ROM process; The 1-WIRE ROM state machine is configured to receive a ROM instruction from a single bus interface through the 1-WIRE transceiver to complete a ROM process; The sending buffer is configured to store parallel data from a memory in the slave device for reading by the SWI transceiver or the 1-WIRE transceiver; The receiving buffer is configured to store parallel data from the SWI transceiver or the 1-WIRE transceiver for storing the parallel data from the SWI transceiver or the 1-WIRE transceiver into a memory in the slave device by the slave device.

2. The single bus communication assembly of claim 1, wherein, The data converter comprises a first data converter and a second data converter; wherein The first data converter is configured to determine whether the SWI transceiver is turned on according to the control information, and to convert high and low level signals from the single bus interface into single bit data and send the single bit data to the SWI transceiver, and convert single bit data from the SWI transceiver into high and low level signals and send the high and low level signals to the single bus interface when the state information indicates that the slave device is in the FUNCTION stage. The second data converter is configured to determine whether the 1-WIRE transceiver is turned on according to the control information, and to convert high and low level signals from the single bus interface into single bit data and send the single bit data to the 1-WIRE transceiver, and convert single bit data from the 1-WIRE transceiver into high and low level signals and send the high and low level signals to the single bus interface when the state information indicates that the slave device is in the FUNCTION stage.

3. The single bus communication assembly of claim 1, wherein, The data converter is a serial data multiplexer.

4. The single bus communication assembly of claim 1, wherein, The receiving buffer includes a first receiving buffer and a second receiving buffer, and the sending buffer includes a first sending buffer and a second sending buffer. The SWI transceiver is configured to convert single bit data sent by the data converter into parallel data according to SWI timing and send the parallel data to the first receiving buffer when the SWI transceiver is turned on, convert parallel data from the first sending buffer into single bit data according to SWI timing and send the single bit data to the data converter, and interact with the SWI ROM state machine in the ROM stage to complete the ROM process. The 1-WIRE transceiver is configured to convert single bit data sent by the data converter into parallel data according to 1-WIRE timing and send the parallel data to the second receiving buffer when the 1-WIRE transceiver is turned on, convert parallel data from the second sending buffer into single bit data according to 1-WIRE timing and send the single bit data to the data converter, and interact with the 1-WIRE ROM state machine in the ROM stage to complete the ROM process.

5. The single bus communication assembly of claim 1, wherein, The SWI transceiver and the 1-WIRE transceiver use the same sending buffer, and the SWI transceiver and the 1-WIRE transceiver use the same receiving buffer. Further comprising a parallel data multiplexer. The parallel data multiplexer is configured to send parallel data from the sending buffer to the SWI transceiver or the 1-WIRE transceiver, and to send parallel data from the SWI transceiver or the 1-WIRE transceiver to the receiving buffer, and the parallel data multiplexer determines a data transmission direction and a data communication channel according to the control information.

6. The single bus communication assembly of claim 1, wherein, Further comprising: a DMA controller. The DMA controller is configured to determine a data transmission direction according to the control information, when in a sending direction, write parallel data from the memory in the slave device to the sending buffer, and modify the state information in the state register when the sending is completed, to provide a sending completion interrupt to the microprocessor; when in a receiving direction, write parallel data stored in the receiving buffer to the memory in the slave device, and modify the state information in the state register when the receiving is completed, to provide a receiving completion interrupt to the microprocessor.

7. The single bus communication assembly of claim 6, wherein, The DMA controller is further configured to stop writing parallel data from the memory in the slave device to the sending buffer when the remaining space of the sending buffer is less than or equal to a preset size, wherein the preset size is equal to n transmission units of the memory in the slave device, and n≥2.

8. The single bus communication assembly of claim 1, wherein, The data converter is a parallel data multiplexer, the SWI transceiver and the 1-WIRE transceiver use the same sending buffer, and the SWI transceiver and the 1-WIRE transceiver use the same receiving buffer, and the single bus communication assembly further comprises a DMA controller and a parallel data multiplexer. The DMA controller is configured to determine a data transmission direction according to the control information, when in a sending direction, write parallel data from the memory in the slave device to the sending buffer, and modify the state information in the state register when the sending is completed, to provide a sending completion interrupt to the microprocessor; when in a receiving direction, write parallel data stored in the receiving buffer to the memory in the slave device, and modify the state information in the state register when the receiving is completed, to provide a receiving completion interrupt to the microprocessor. The parallel data multiplexer is configured to send parallel data from the sending buffer to the SWI transceiver or the 1-WIRE transceiver, and send parallel data from the SWI transceiver or the 1-WIRE transceiver to the receiving buffer; wherein the parallel data multiplexer determines a data transmission direction and a data communication channel according to the control information.

9. The single-wire communication assembly of any one of claims 1 to 8, wherein, The default mode of the control information represents turning on the 1-WIRE transceiver.

10. A slave device, comprising: A single bus communication assembly comprising any one of claims 1 to 9.

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