Non-volatile in-memory computing structure of enhanced MRAM (Magnetic Random Access Memory) and computer

Abstract

The invention discloses a nonvolatile in-memory computing structure of an enhanced MRAM (Magnetic Random Access Memory) and a computer. The in-memory computing structure comprises a storage-operation integrated array and a mode selection module. The storage-operation integrated array comprises a plurality of magnetic tunnel junctions, a plurality of vanadium dioxide phase change materials and a plurality of transistors; the magnetic tunnel junction and the vanadium dioxide phase change material are connected through a transistor to form a storage unit; the plurality of storage units are arranged in a rectangular shape; in a read-write mode, the vanadium dioxide phase change material is in a metal state, and the magnetic tunnel junction is in a storage state; in a calculation mode, the parallel-state magnetic tunnel junction is combined with the metallic-state vanadium dioxide phase change material, and the anti-parallel-state magnetic tunnel junction is combined with the insulated-state vanadium dioxide phase change material. And the mode selection module is used for switching the working mode of the storage-operation integrated array according to an external enable signal. According to the method, the network operation energy efficiency is effectively improved, meanwhile, high storage density and computing power density are achieved, and the area overhead is reduced.

Description

Technical Field

[0001] The present invention relates to a computing structure in the field of integrated circuit technology, and particularly to a non-volatile in-memory computing structure of an enhanced MRAM, and also relates to a computer. Background Art

[0002] In recent years, convolutional neural networks have achieved unprecedented success in many applications related to artificial intelligence (AI) and the Internet of Things (IoT), such as image recognition, speech keyword detection, face recognition, etc. Convolutional neural networks mainly include the following hierarchical structures: data input layer, convolutional calculation layer, function excitation layer, pooling layer, and fully connected layer. Its calculation process can be summarized as that the current network layer performs a weighted sum on the activation values of the previous layer, then adds a bias term, and finally obtains the activation values of the next layer through an activation function. However, limited by computing hardware, the efficiency is low when processing AI tasks.

[0003] Existing computing hardware is based on the von Neumann architecture. Since the memory and the computing unit are two independent parts, when a computer performs a computing operation, it needs to fetch data from the memory, transfer it to the computing unit for calculation, and then write it back to the memory. Due to the movement of data between the processing unit and the memory, problems such as excessive energy consumption and latency are likely to occur, which is called the "memory wall". Therefore, the existing computing storage structure has high data migration and memory access consumption, and large area overhead. Summary of the Invention

[0004] To solve the technical problems of high data migration and memory access consumption of the existing computing storage structure and large area overhead, the present invention provides a non-volatile in-memory computing structure of an enhanced MRAM and a computer.

[0005] The present invention is implemented by the following technical solutions: A non-volatile in-memory computing structure of an enhanced MRAM, which includes:

[0006] A storage-computation integrated array, which includes a plurality of magnetic tunnel junctions, a plurality of vanadium dioxide phase change materials, and a plurality of transistors; at least one magnetic tunnel junction and at least one vanadium dioxide phase change material are connected through at least one transistor and form a storage unit; a plurality of storage units are arranged in a rectangular layout and provide read / write mode and calculation mode; in the read / write mode, the vanadium dioxide phase change material is in the metallic state, and the magnetic tunnel junction is in the storage state; in the calculation mode, the magnetic tunnel junctions in the parallel state in each storage unit are combined with the vanadium dioxide phase change material in the metallic state, and the magnetic tunnel junctions in the anti-parallel state are combined with the vanadium dioxide phase change material in the insulating state to control the on / off of the corresponding storage unit; and

[0007] A mode selection module, which is used to switch the working mode of the storage-computation integrated array according to an external enable signal; the working mode is the read-write mode or the computing mode.

[0008] In the present invention, a magnetic tunnel junction, a vanadium dioxide phase change material, and a transistor are combined to form a memory cell matrix. By using the parallel state and the antiparallel state of the magnetic tunnel junction, the switching of the conductive state of the vanadium dioxide phase change material is realized. That is, the magnetic tunnel junction in the parallel state is combined with the vanadium dioxide phase change material in the metallic state, and the magnetic tunnel junction in the antiparallel state is combined with the vanadium dioxide phase change material in the insulating state, so as to realize the conduction and disconnection of the memory cell. In the read-write mode, it can ensure that the vanadium dioxide phase change material continuously works in the metallic state without having an additional impact on the read-write function of the magnetic tunnel junction. On the contrary, in the computing mode, the vanadium dioxide phase change material can be conductive or disconnected. By controlling multiple memory cells, the function of multiply-accumulate calculation can be realized. In this way, the multiply-accumulate calculation is completed while reading data, solving the technical problems of high data migration and high memory access consumption and large area overhead in the existing computing storage structure. Compared with the neural network accelerator based on the traditional von Neumann architecture, it effectively improves the network operation energy efficiency, and at the same time has a high storage density and computing power density, reducing the area overhead.

[0009] As a further improvement of the above solution, the non-volatile in-memory computing structure further includes:

[0010] A quantization unit structure, which includes a capacitor array, a successive approximation logic control unit, and a voltage comparator; the capacitor array includes a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, and a fifth capacitor; the upper plates of the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, and the fifth capacitor are all connected to one input end of the voltage comparator and the connection node INP, and the lower plates are respectively connected to five control switches; each control switch is used to connect the corresponding capacitor to one of the computing bit lines CBL / CBLB, the reference voltage VREF, and the power supply VDD; the successive approximation logic control unit is used to control the capacitor array by generating a control signal and control the voltage comparator by an enable signal EN; the other input end of the voltage comparator is connected to the node INN, and the node INN is connected to the common mode voltage VCM; when the control signal is turned on, the node INP and the node INN are short-circuited; when the enable signal EN is turned on, the voltage comparator compares the voltages of the node INP and the node INN and outputs a comparison result.

[0011] Further, the non-volatile in-memory computing structure further includes:

[0012] A current mirror; and

[0013] A calculation result output module, which is used to output the calculation result of the storage - operation integrated array in the calculation mode;

[0014] Wherein, the current mirror is used to copy the calculation current of the bit line in the storage - operation integrated array to the quantization unit structure and the calculation result output module in the calculation mode.

[0015] Furthermore, the non - volatile in - memory computing structure further includes:

[0016] A sense amplifier; in the read - write mode, the mode selection module connects the output of the storage - operation integrated array to the sense amplifier;

[0017] A read drive circuit, which is used to compare the read current generated by the storage cell with a reference current together with the sense amplifier, and amplify and output the read weight for the corresponding conversion voltage;

[0018] A write drive circuit, which is used to drive the storage cell to perform a write operation; and

[0019] A timing control circuit, which is used to control the storage - operation integrated array by generating timing.

[0020] As a further improvement of the above - mentioned solution, the non - volatile in - memory computing structure further includes:

[0021] A row decoder; and

[0022] A column selector; the row decoder and the column selector are used to perform read - write access to the corresponding storage cells in the storage - operation integrated array according to an external address signal in the read - write mode; the column selector is used to select and cascade multiple storage cells as computing units in the calculation mode.

[0023] Further, the sense amplifier includes a current sampling unit and a voltage amplifier; the current sampling unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; the voltage amplifier includes a seventh PMOS transistor, an eighth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an inverter INV1; the gate of the first PMOS transistor is connected to the enable signal SAEN, the source is connected to the power supply VDD, and the drain is connected to the node NET1; the gate and the drain of the second PMOS transistor are connected to the node NET1, and the source is connected to the power supply VDD; the gate of the third PMOS transistor is connected to the node NET1, the source is connected to the power supply VDD, and the drain is connected to the first-stage output node SO; the gate of the fourth PMOS transistor is connected to the node NET2, the source is connected to the power supply VDD, and the drain is connected to the first-stage output node SOB; the gate and the drain of the fifth PMOS transistor are connected to the node NET2, and the source is connected to the power supply VDD; the gate of the sixth PMOS transistor is connected to the enable signal SAEN, the source is connected to the power supply VDD, and the drain is connected to the node NET2; the gate of the first NMOS transistor is connected to the clamp signal CLP, the source is connected to the bit line BL in the storage-computation integrated array, and the drain is connected to the node NET1; the gate of the second NMOS transistor is connected to the first-stage output node SOB, the source is connected to the ground GND, and the drain is connected to the first-stage output node SO; the gate and the drain of the third NMOS transistor are connected to the first-stage output node SOB, and the source is connected to the ground GND; the gate of the fourth NMOS transistor is connected to the clamp signal CLP, the source is connected to the reference bit line REF in the storage-computation integrated array, and the drain is connected to the node NET2; the gate and the drain of the seventh PMOS transistor are connected to the node NET3, and the source is connected to the power supply VDD; the gate and the drain of the eighth PMOS transistor are connected to the node NET4, and the source is connected to the power supply VDD; the gate of the fifth NMOS transistor is connected to the first-stage output node SO, the source is connected to the node NET5, and the drain is connected to the node NET3; the gate of the sixth NMOS transistor is connected to the first-stage output node SOB, the source is connected to the node NET5, and the drain is connected to the node NET5; the gate of the seventh NMOS transistor is connected to the enable signal SAEN, the source is connected to the ground GND, and the drain is connected to the node NET5; the input terminal of the inverter INV1 is connected to the node NET4 and outputs the signal DOUT.

[0024] As a further improvement of the above solution, the read / write mode is the standard read / write mode, and the calculation mode is the multiply-accumulate calculation mode; the storage-computation integrated array configures 1bit×1bit to N bit×1bit multiply-accumulate operations in the multiply-accumulate calculation mode, and there is the following calculation formula:

[0025] n = 2 N-1

[0026] Wherein, n is the number of rows of activated memory cells in the storage-computation integrated array.

[0027] As a further improvement of the above solution, one end of each magnetic tunnel junction is connected to the source line SL in the storage-computation integrated array, and the other end is connected to the source electrode of the corresponding transistor; the gate of each transistor is connected to the word line WL in the storage-computation integrated array, and the drain is connected to the corresponding vanadium dioxide phase change material; both ends of each vanadium dioxide phase change material are respectively connected to the bit line BL and the drain of the corresponding transistor.

[0028] Furthermore, the mode selection module includes a transmission tube T1 and a transmission tube T2; when the mode selection signal in the external enable signal is at a high level of 1, the transmission tube T1 is turned on and the transmission tube T2 is turned off, and the output of the storage-computation integrated array is connected to the sense amplifier; when the mode selection signal in the external enable signal is at a high level of 0, the transmission tube T1 is turned off and the transmission tube T2 is turned on, and the output of the storage-computation integrated array is connected to the current mirror and assigned to the quantization unit structure.

[0029] The present invention also provides a computer, which includes the non-volatile in-memory computing structure of any one of the above enhanced MRAMs.

[0030] Compared with the existing computing storage structure, the non-volatile in-memory computing structure of the enhanced MRAM and the computer of the present invention have the following beneficial effects:

[0031] 1. The non-volatile in-memory computing structure of the enhanced MRAM combines magnetic tunnel junctions, vanadium dioxide phase change materials, and transistors to form a memory cell matrix. By using the parallel state and anti-parallel state of the magnetic tunnel junctions, the switching of the conductive state of the vanadium dioxide phase change materials is realized, that is, the parallel-state magnetic tunnel junctions are combined with the metal-state vanadium dioxide phase change materials, and the anti-parallel-state magnetic tunnel junctions are combined with the insulating-state vanadium dioxide phase change materials to achieve the conduction and disconnection of the memory cells. In the read-write mode, it can ensure that the vanadium dioxide phase change materials continuously work in the metal state without causing additional effects on the read-write functions of the magnetic tunnel junctions. On the contrary, in the computing mode, the vanadium dioxide phase change materials can conduct or disconnect, and by controlling multiple memory cells, the function of multiply-accumulate calculation can be realized. In this way, the multiply-accumulate calculation is completed while reading the data, solving the technical problems of high data migration and high memory access consumption and large area overhead of the existing computing storage structure. Compared with the neural network accelerator of the traditional von Neumann architecture, it effectively improves the network operation energy efficiency, and at the same time has a high storage density and computing power density, reducing the area overhead.

[0032] 2. The non-volatile in-memory computing structure of the enhanced MRAM completes the multi-bit multiply-accumulate operation by discharging and accumulating the load capacitance of the computational bit lines, and finally obtains a digital result output through a quantization unit. The design of fractional-bit weights and separated global bit lines has good computational parallelism and stability, and can support the configurable multi-bit MAC operation of 1-bit×N-bit in deep neural networks, with high inference accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 FIG. is a schematic structural diagram of the non-volatile in-memory computing structure of the enhanced MRAM according to Embodiment 1 of the present invention;

[0034] Figure 2 is Figure 1 a key structural diagram of the storage-computation integrated array in the in-memory computing structure in;

[0035] Figure 3 is Figure 1 a circuit structural diagram of the quantization unit structure in the in-memory computing structure in;

[0036] Figure 4 is Figure 1 a circuit structural diagram of the sense amplifier in the in-memory computing structure in;

[0037] Figure 5 FIG. is a schematic diagram of the principle of performing 2-bit input and 1-bit weight multiply-accumulate calculation of the non-volatile in-memory computing structure of the enhanced MRAM according to Embodiment 2 of the present invention;

[0038] Figure 6 FIG. is a schematic diagram corresponding to the timing control and truth table of performing 2-bit input and 1-bit weight multiply-accumulate calculation of the non-volatile in-memory computing structure of the enhanced MRAM according to Embodiment 2 of the present invention;

[0039] Figure 7 FIG. is a Monte Carlo simulation result diagram of performing 2-bit input and 1-bit weight multiply-accumulate calculation of the non-volatile in-memory computing structure of the enhanced MRAM according to Embodiment 2 of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0040] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0041] Embodiment 1

[0042] Please refer to Figures 1 to 4, this embodiment provides a non-volatile in-memory computing structure for an enhanced MRAM. This in-memory computing structure embeds a computing circuit in a memory, integrating storage and computing. This in-memory computing structure is a non-volatile in-memory computing array structure of a phase change field-effect transistor enhanced MRAM, including a storage-computation integrated array and a mode selection module. In this embodiment and some other embodiments, this in-memory computing structure may further include a quantization unit structure, a current mirror, a calculation result output module, a sense amplifier, a read driver circuit, a write driver circuit, a timing control circuit, a row decoder, and a column selector. In some other embodiments, these may not be included or may include some of these modules or circuits, which can be specifically set according to actual needs.

[0043] Please continue to refer to Figure 2 , the storage-computation integrated array includes multiple magnetic tunnel junctions, multiple vanadium dioxide phase change materials, and multiple transistors. At least one magnetic tunnel junction and at least one vanadium dioxide phase change material are connected through at least one transistor to form a storage cell. Multiple storage cells are arranged in a rectangular pattern and provide read-write mode and calculation mode. The storage array formed by the storage cells can realize the function switching between the standard read-write mode and the multi-bit multiply-accumulate calculation mode. In the read-write mode, the vanadium dioxide phase change material is in the metallic state, and the magnetic tunnel junction is in the storage state. In the calculation mode, the magnetic tunnel junction in the parallel state in each storage cell is combined with the vanadium dioxide phase change material in the metallic state, and the magnetic tunnel junction in the antiparallel state is combined with the vanadium dioxide phase change material in the insulating state to control the on-off of the corresponding storage cell. Among them, the read-write mode is the standard read-write mode, and the calculation mode is the multiply-accumulate calculation mode. One end of each magnetic tunnel junction is connected to the source line SL in the storage-computation integrated array, and the other end is connected to the source electrode of the corresponding transistor. The gate of each transistor is connected to the word line WL in the storage-computation integrated array, and the drain is connected to the corresponding vanadium dioxide phase change material. Both ends of each vanadium dioxide phase change material are respectively connected to the bit line BL and the drain of the corresponding transistor.

[0044] In this embodiment, it is jointly composed of a phase change field effect transistor composed of a magnetic tunnel junction (MTJ) and a vanadium dioxide phase change material (VO2). The memory array includes N columns and M rows of memory cells, as well as a reference column. In the standard read / write mode, it can ensure that the phase change material continuously operates in the metallic state without having an additional impact on the read / write function of the magnetic tunnel junction. The magnetic tunnel junction device (MTJ) can exhibit two states of high resistance and low resistance according to the direction of the write operation current. The first vanadium dioxide phase change material can switch between the metallic state and the insulating state and always remains in the metallic state unchanged in the standard read / write mode. In the multiply-accumulate calculation mode, the phase change material vanadium dioxide can be controlled to switch between the metallic state and the insulating state according to the parallel state (P) and the antiparallel state (AP) of the magnetic tunnel junction (MTJ) (the parallel magnetic tunnel junction is combined with the metallic state vanadium dioxide (VO2), and the antiparallel magnetic tunnel junction (MTJ) is combined with the insulating state vanadium dioxide (VO2)), thereby turning on and off the non-volatile memory cell to obtain a proportional current calculation result. The memory-computation integrated array configures multiply-accumulate operations from 1bit×1bit to Nbit×1bit in the multiply-accumulate calculation mode, and there is the following calculation formula:

[0045] n = 2 N-1

[0046] Among them, n is the number of rows of memory cells activated in the memory-computation integrated array.

[0047] The mode selection module is used to switch the working mode of the memory-computation integrated array according to an external enable signal. The working mode is the read / write mode or the calculation mode. In this embodiment, the mode selection module includes a transmission tube T1 and a transmission tube T2. When the mode selection signal (MEN) in the external enable signal is at a high level of 1, the transmission tube T1 is turned on and the transmission tube T2 is turned off, and the output of the memory-computation integrated array is connected to a sense amplifier. When the mode selection signal (MEN) in the external enable signal is at a low level of 0, the transmission tube T1 is turned off and the transmission tube T2 is turned on, and the output of the memory-computation integrated array is connected to a current mirror and assigned to the quantization unit structure. In the read / write mode, the mode selection module connects the output of the memory-computation integrated array to a sense amplifier.

[0048] The row decoder and the column selector are used to perform read / write access to the corresponding memory cells in the memory-computation integrated array according to an external address signal in the read / write mode. The column selector is used to perform gated cascade calculations on multiple memory cells in the calculation mode.

[0049] Please continue to refer to Figure 3, the quantization unit structure includes a capacitor array, a successive approximation logic control unit, and a voltage comparator. The capacitor array includes a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, and a fifth capacitor, which are capacitor C0, C1, C2, C3, and C4 respectively. In this embodiment, the ratio of their capacitance values is C4:C3:C2:C1:C0 = 8:4:2:1:1, and the ratio will be different in other embodiments. The upper plates of the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, and the fifth capacitor are all connected to one input terminal of the voltage comparator and the connection node INP, and the lower plates are respectively connected to five control switches, which are S[0], S[1], S[2], S[3], and S[4] respectively. Each control switch is used to connect the corresponding capacitor to one of the calculation bit lines CBL / CBLB, the reference voltage VREF, and the power supply VDD. The successive approximation logic control unit is used to control the capacitor array by generating control signals and control the voltage comparator through the enable signal EN. The other input terminal of the voltage comparator is connected to the node INN, and the node INN is connected to the common mode voltage VCM. When the control signal CE is turned on, the node INP and the node INN are short-circuited. When the enable signal EN is turned on, the voltage comparator compares the voltages of the node INP and the node INN and outputs the comparison result Output.

[0050] The current mirror is used to copy the calculation current of the bit line (BL) in the storage-computation integrated array to the quantization unit structure and the calculation result output module in the calculation mode. The calculation result output module is used to output the calculation result of the storage-computation integrated array in the calculation mode. The quantization unit and the calculation output module are used to quantify the accumulated discharge amount of the global bit line in the multi-bit multiply-accumulate calculation mode, so as to obtain a digital result output, and the quantization result is the result of the convolution calculation.

[0051] The sense amplifier, the read drive circuit, the write drive circuit, and the timing control circuit are used to implement the read and write operations and the multi-bit calculation operations of the storage array. The read drive circuit and the sense amplifier are used to compare the read current generated by the storage unit with the reference current and amplify and output the read weight of the corresponding conversion voltage. The write drive circuit is used to drive the storage unit to perform a write operation. The timing control circuit is used to control the storage-computation integrated array by generating timing.

[0052] Please continue to refer to Figure 4, the sense amplifier includes a current sampling unit and a voltage amplifier. The current sampling unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The transistors correspond to PMOS transistors P1, P2, P3, P4, P5, P6 and NMOS transistors N1, N2, N3, N4. The voltage amplifier includes a seventh PMOS transistor, an eighth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an inverter INV1. The transistors correspond to PMOS transistors P7, P8 and NMOS transistors N5, N6, N7. The gate of the first PMOS transistor is connected to the enable signal SAEN, the source is connected to the power supply VDD, and the drain is connected to the node NET1. The gate and drain of the second PMOS transistor are connected to the node NET1, and the source is connected to the power supply VDD. The gate of the third PMOS transistor is connected to the node NET1, the source is connected to the power supply VDD, and the drain is connected to the first-stage output node SO. The gate of the fourth PMOS transistor is connected to the node NET2, the source is connected to the power supply VDD, and the drain is connected to the first-stage output node SOB. The gate and drain of the fifth PMOS transistor are connected to the node NET2, and the source is connected to the power supply VDD. The gate of the sixth PMOS transistor is connected to the enable signal SAEN, the source is connected to the power supply VDD, and the drain is connected to the node NET2. The gate of the first NMOS transistor is connected to the clamp signal CLP, the source is connected to the bit line BL in the storage-computation integrated array, and the drain is connected to the node NET1. The gate of the second NMOS transistor is connected to the first-stage output node SOB, the source is connected to the ground GND, and the drain is connected to the first-stage output node SO. The gate and drain of the third NMOS transistor are connected to the first-stage output node SOB, and the source is connected to the ground GND. The gate of the fourth NMOS transistor is connected to the clamp signal CLP, the source is connected to the reference bit line REF in the storage-computation integrated array, and the drain is connected to the node NET2. The gate and drain of the seventh PMOS transistor are connected to the node NET3, and the source is connected to the power supply VDD. The gate and drain of the eighth PMOS transistor are connected to the node NET4, and the source is connected to the power supply VDD. The gate of the fifth NMOS transistor is connected to the first-stage output node SO, the source is connected to the node NET5, and the drain is connected to the node NET3. The gate of the sixth NMOS transistor is connected to the first-stage output node SOB, the source is connected to the node NET5, and the drain is connected to the node NET5. The gate of the seventh NMOS transistor is connected to the enable signal SAEN, the source is connected to the ground GND, and the drain is connected to the node NET5. The input terminal of the inverter INV1 is connected to the node NET4 and outputs the signal DOUT. When the reference current is less than the bit line current, the output DOUT is at a low level of 0. When the reference current is greater than the bit line current, the output DOUT is at a high level of 1.

[0053] Compared with the existing computing storage structure, the non-volatile in-memory computing structure of the enhanced MRAM in this embodiment has the following beneficial effects:

[0054] 1. The non-volatile in-memory computing structure of the enhanced MRAM forms a storage cell matrix by combining a magnetic tunnel junction, a vanadium dioxide phase change material, and a transistor. By using the parallel state and anti-parallel state of the magnetic tunnel junction, the switching of the conductive state of the vanadium dioxide phase change material is realized. That is, the parallel-state magnetic tunnel junction is combined with the metallic-state vanadium dioxide phase change material, and the anti-parallel-state magnetic tunnel junction is combined with the insulating-state vanadium dioxide phase change material to achieve the conduction and disconnection of the storage cell. In the read-write mode, it can ensure that the vanadium dioxide phase change material continuously operates in the metallic state without causing additional influence on the read-write function of the magnetic tunnel junction. On the contrary, in the computing mode, the vanadium dioxide phase change material can be conductive or non-conductive. By controlling multiple storage cells, the function of multiply-accumulate calculation can be realized. In this way, the multiply-accumulate calculation is completed while reading the data, solving the technical problems of high data migration and high memory access consumption, and large area overhead in the existing computing storage structure. Compared with the neural network accelerator based on the traditional von Neumann architecture, it effectively improves the network operation energy efficiency, and at the same time has a high storage density and computing power density, reducing the area overhead.

[0055] 2. The non-volatile in-memory computing structure of the enhanced MRAM completes the multi-bit multiply-accumulate operation by discharging and accumulating the load capacitance of the computing bit line, and finally obtains the digital result output through the quantization unit. The design of bit-wise weight and separated global bit line has good computing parallelism and stability, and can support the configurable multi-bit MAC operation of 1-bit×N-bit in the deep neural network, with a high inference accuracy.

[0056] Embodiment 2

[0057] Please refer to Figure 5 、 Figure 6 and Figure 7 This embodiment provides a non-volatile in-memory computing structure of an enhanced MRAM. Based on the computing structure of Embodiment 1, as shown in Figure 5 , a 2bit×1bit calculation is performed. Three rows of bit units need to be activated, and a voltage source is given on the SL, and the calculation current result is obtained from the BL.

[0058] According to Ohm's law, the current on each bit unit is:

[0059]

[0060] where I cell is the current on each bit unit, V MAC is the voltage across each bit unit, and RBitcell The resistance of each bit cell.

[0061] According to the series resistance formula:

[0062]

[0063] Wherein, is the resistance of the vanadium dioxide phase change material of the bit cell, R MTJ is the resistance of the magnetic tunnel junction of the bit cell, R mos is the resistance of the transistor of the bit cell.

[0064] According to the properties of VO2, it initially operates in the insulating state. Once the current flowing through VO2 exceeds I MIT , VO2 will transform from the insulating state to the metallic state. According to the parameter settings of this example:

[0065]

[0066] Wherein, R insulation is the resistance of the vanadium dioxide phase change material in the insulating state, R MTJ,AP is the resistance of the magnetic tunnel junction in the AP state.

[0067] This enables the VO2 in the bit cells where the magnetic tunnel junction MTJ is in the AP state to always remain in the metallic state, while the VO2 in the bit cells where the magnetic tunnel junction MTJ is in the P state will flip to the metallic state. Also, since the total resistance of the bit cells with insulating VO2 is very large and can be approximated as an open circuit, according to the parallel formula, the total current:

[0068]

[0069] Wherein, I total is the total current, n is the number of rows of storage cells, R metal is the resistance of the vanadium dioxide phase change material in the metallic state. Therefore, by configuring the state of the magnetic tunnel junction MTJ of the bit cell and the activation number of the bit cell, a 2bit×1bit calculation result can be obtained, as Figure 6 shown.

[0070] The quantization unit structure quantizes 7 different multiply-accumulate results into 4-bit data (0 to 15), that is, the maximum quantization result MAC_MAX = 15, and the quantization unit performs a standard binary conversion. Its working process is as follows (taking multiply-accumulate MAC = 9 as an example): First, CE is enabled, and the node INN and the node INP are shorted to the common-mode voltage VCM, and VCM corresponds to the quantization digital output 0. When the capacitor array completes the sampling of the analog voltage obtained by multiply-accumulating on the computational bit lines CBL / CBLB, the switches S[4:0] are switched to the power supply VDD. At this time, the voltage of the node INP is:

[0071] V INP = V CM + V DD - V CBL / CBLB

[0072] Wherein, V INP is the voltage value of node INP, V CM is the common-mode voltage VCM, V DD is the voltage of power supply VDD, V CBL / CBLB is the voltage of bit line CBL / CBLB.

[0073] When the comparison stage starts, the successive approximation logic control unit connects the lower plate of the fifth capacitor C4 to the reference voltage VREF by controlling the switch S[4], and the voltage of node INP is obtained as:

[0074]

[0075] In the formula, V REF is the reference voltage VREF.

[0076] After the voltage comparator compares the magnitudes of V INP and V INN and gets an output of 0, it feeds back to the successive approximation logic control unit. The successive approximation logic control unit controls the switch S[3] to connect the lower plate of the fourth capacitor C3 to the reference voltage V REF and the voltage of node INP is obtained as:

[0077]

[0078] After the voltage comparator compares the magnitudes of V INP and V 2IN and gets an output of 1, it feeds back to the successive approximation logic control unit. The successive approximation logic control unit controls the switches S[3] and S[2] to switch the lower plate of the fourth capacitor C3 to be connected to the power supply VDD, and connect the lower plate of the third capacitor C2 to the reference voltage VREF, and the voltage of node INP is obtained as:

[0079]

[0080] At this time, V INP and V INN are equal, and the quantization unit outputs the multiply-accumulate calculation digital result MAC = 9.

[0081] Such as Figure 7The figure shows the in-memory computing structure provided by the embodiment, which is a Monte Carlo simulation result diagram of the multiplication and accumulation calculation of 2-bit input and 1-bit weight. It can be seen from the figure that the multi-bit in-memory computing array disclosed by the present invention has reliability in performing multi-bit multiplication and accumulation calculations in the current domain.

[0082] Embodiment 3

[0083] This embodiment provides a computer, which is an in-memory computing computer and includes the non-volatile in-memory computing structure of the enhanced MRAM in Embodiment 1 or Embodiment 2. The computer in this embodiment can be used as an artificial intelligence device and can be used as a non-volatile data storage and low-power battery-powered micro AI device. In addition to using the in-memory computing structure, this computer also includes some other common computer structures, such as a display, a memory, a graphics card, etc., which can be selected according to actual needs. In the computer of this embodiment, the computing array is composed of high-density variable field effect transistor enhanced non-volatile storage units. While realizing the multiplication and accumulation calculation, the read and write working modes of the MRAM are retained, and the design of the phase change field effect transistor enhanced MRAM computing array with integrated computing and storage in the array is realized. The multi-bit multiplication and accumulation operation is completed by discharging and accumulating the load capacitance of the computing bit line, and the digital result output is finally obtained through the quantization unit. The design of the sub-bit weight and the separated global bit line has good computing parallelism and stability, and can support the configurable multi-bit MAC operation of 1-bit×N-bit in the deep neural network, with high inference accuracy. Moreover, this computer has a high storage density and computing power density, reducing the area overhead. The multi-bit multiplication and accumulation operation is completed while accessing the memory, which can significantly reduce the overall power consumption of the network, has better performance than the existing computers, and can also effectively improve the network operation energy efficiency.

[0084] Embodiment 4

[0085] This embodiment provides an artificial intelligence chip, which includes the non-volatile in-memory computing structure of the enhanced MRAM in Embodiment 1 or Embodiment 2, and has a standard read and write mode and a multiplication and accumulation calculation mode. The read and write operations of the data in the storage array can be realized in the standard read and write mode. In the multiplication and accumulation calculation mode, the chip can realize the operation of multiplying and accumulating from 1bit×1bit to Nbit×1bit in the convolutional neural network calculation. In this way, the chip can efficiently process artificial intelligence tasks, is not prone to problems such as excessive energy consumption and delay, avoids the "memory wall", and greatly reduces the data migration and memory access consumption. The artificial intelligence chip of this embodiment has the multiplication and accumulation of multi-bit input (IN) and output (OUT), which is conducive to promoting the realization of artificial intelligence chips with high inference accuracy.

[0086] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A non-volatile in-memory computing structure of an enhanced MRAM, characterized in that: It includes: A storage-computing integrated array comprising a plurality of magnetic tunnel junctions, a plurality of vanadium dioxide phase change materials and a plurality of transistors; At least one magnetic tunnel junction and at least one vanadium dioxide phase change material are connected through at least one transistor to form a storage unit; a plurality of storage units are arranged in a rectangular shape and provide a read-write mode and a calculation mode; in the read-write mode, the vanadium dioxide phase change material is in a metallic state, and the magnetic tunnel junction is in a storage state; in the calculation mode, the parallel magnetic tunnel junction in each storage unit is combined with the metallic vanadium dioxide phase change material, and the antiparallel magnetic tunnel junction is combined with the insulating vanadium dioxide phase change material to control the on and off of the corresponding storage unit; as well as A mode selection module is used to switch the working mode of the storage-computation integrated array according to an external enable signal; the working mode is the read-write mode or the calculation mode.

2. The non-volatile in-memory computing structure of the enhanced MRAM as claimed in claim 1, characterized in that: The non-volatile in-memory computing structure also includes: A quantization unit structure, comprising a capacitor array, a successive approximation logic control unit and a voltage comparator; the capacitor array comprises a first capacitor, a second capacitor, a third capacitor, a fourth capacitor and a fifth capacitor; the upper plates of the first capacitor, the second capacitor, the third capacitor, the fourth capacitor and the fifth capacitor are all connected to one of the input terminals of the voltage comparator and to the node INP, and the lower plates are respectively connected to five control switches; each control switch is used to connect the corresponding capacitor to one of the calculation bit lines CBL / CBLB, the reference voltage VREF and the power supply VDD; the successive approximation logic control unit is used to control the capacitor array by generating a control signal and control the voltage comparator by an enable signal EN; another input terminal of the voltage comparator is connected to the node INN, and the node INN is connected to the common mode voltage VCM; when the control signal is turned on, the node INP and the node INN are short-circuited; when the enable signal EN is turned on, the voltage comparator compares the voltages of the node INP and the node INN, and outputs the comparison result.

3. The non-volatile in-memory computing structure of the enhanced MRAM as claimed in claim 2, characterized in that: The non-volatile in-memory computing structure also includes: current mirror; and A calculation result output module, which is used to output the calculation result of the storage-computation integrated array in the calculation mode; The current mirror is used to copy the calculation current of the bit line in the storage-computation integrated array to the quantization unit structure and the calculation result output module in the calculation mode.

4. The non-volatile in-memory computing structure of the enhanced MRAM as claimed in claim 3, characterized in that: The non-volatile in-memory computing structure also includes: Sensitive amplifier; in read-write mode, the mode selection module connects the output of the storage-computation integrated array to the sensitive amplifier; a readout drive circuit, which is used together with the sense amplifier to compare the read current generated by the storage unit with a reference current, and to amplify the corresponding conversion voltage to output a read weight; a write drive circuit, which is used to drive the storage unit to perform a write operation; and The timing control circuit is used to control the storage-computation integrated array by generating a timing sequence.

5. The non-volatile in-memory computing structure of the enhanced MRAM as claimed in claim 1, characterized in that: The non-volatile in-memory computing structure also includes: a row decoder; and Column selector; the row decoder and the column selector are used to read and write the corresponding storage cells in the storage-computation integrated array according to the external address signal in the read-write mode; the column selector is used to select the cascaded computing unit for multiple storage cells in the computing mode.

6. The non-volatile in-memory computing structure of the enhanced MRAM as claimed in claim 4, characterized in that: The sensitive amplifier includes a current sampling unit and a voltage amplifier; the current sampling unit includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube; the voltage amplifier includes a seventh PMOS tube, an eighth PMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube and an inverter INV1; the gate of the first PMOS tube is connected to an enable signal SAEN, the source is connected to a power supply VDD, and the drain is connected to a node NET 1; the gate and drain of the second PMOS tube are connected to the node NET1, and the source is connected to the power supply VDD; the gate of the third PMOS tube is connected to the node NET1, the source is connected to the power supply VDD, and the drain is connected to the first-stage output node SO; the gate of the fourth PMOS tube is connected to the node NET2, the source is connected to the power supply VDD, and the drain is connected to the first-stage output node SOB; the gate and drain of the fifth PMOS tube are connected to the node NET2, and the source is connected to the power supply VDD; the gate of the sixth PMOS tube is connected to the enable signal SAEN, the source is connected to the power supply VDD, and the drain is connected to the node NET2; the first NMOS The gate of the transistor is connected to the clamp signal CLP, the source is connected to the bit line BL in the storage-computation integrated array, and the drain is connected to the node NET1; the gate of the second NMOS transistor is connected to the first-stage output node SOB, the source is connected to the ground GND, and the drain is connected to the first-stage output node SO; the gate and drain of the third NMOS transistor are connected to the first-stage output node SOB, and the source is connected to the ground GND; the gate of the fourth NMOS transistor is connected to the clamp signal CLP, the source is connected to the reference bit line REF in the storage-computation integrated array, and the drain is connected to the node NET2; the gate and drain of the seventh PMOS transistor are connected to the node NE T3, the source is connected to the power supply VDD; the gate and drain of the eighth PMOS tube are connected to the node NET4, and the source is connected to the power supply VDD; the gate of the fifth NMOS tube is connected to the first-stage output node SO, the source is connected to the node NET5, and the drain is connected to the node NET3; the gate of the sixth NMOS tube is connected to the first-stage output node SOB, the source is connected to the node NET5, and the drain is connected to the node NET5; the gate of the seventh NMOS tube is connected to the enable signal SAEN, the source is connected to the ground GND, and the drain is connected to the node NET5; the input end of the inverter INV1 is connected to the node NET4, and the output signal DOUT.

7. The non-volatile in-memory computing structure of the enhanced MRAM as claimed in claim 1, characterized in that: The read / write mode is a standard read / write mode, and the calculation mode is a multiplication-accumulation calculation mode; the storage-calculation integrated array configures a 1-bit×1-bit to N-bit×1-bit multiplication-accumulation calculation in the multiplication-accumulation calculation mode, and the following calculation formula exists: n＝2 N-1 Wherein, n is the number of activated storage unit rows in the storage-computation integrated array.

8. The non-volatile in-memory computing structure of the enhanced MRAM as claimed in claim 1, characterized in that: One end of each magnetic tunnel junction is connected to the source line SL in the storage-computation integrated array, and the other end is connected to the source of the corresponding transistor; the gate of each transistor is connected to the word line WL in the storage-computation integrated array, and the drain is connected to the corresponding vanadium dioxide phase change material; the two ends of each vanadium dioxide phase change material are respectively connected to the bit line BL and the drain of the corresponding transistor.

9. The non-volatile in-memory computing structure of the enhanced MRAM as claimed in claim 4, characterized in that: The mode selection module includes a transmission tube T1 and a transmission tube T2; when the mode selection signal in the external enable signal is a high level 1, the transmission tube T1 is turned on and the transmission tube T2 is turned off, and the output of the storage-computation integrated array is connected to the sensitive amplifier; when the mode selection signal in the external enable signal is a high level 0, the transmission tube T1 is turned off and the transmission tube T2 is turned on, and the output of the storage-computation integrated array is connected to the current mirror and assigned to the quantization unit structure.

10. A computer, characterized in that: It includes a non-volatile in-memory computing structure of an enhanced MRAM as described in any one of claims 1-9.

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