Structural Optimization Method and System for Void Ratio of IGBT Copper Heat Dissipation Bottom Plate Contact Surface

Abstract

The present invention discloses a structural optimization method and system for the void ratio of the contact surface of an IGBT copper heat dissipation base plate, which relates to the field of chip technology. The method includes: making an online call to obtain a chip simulation model; determining the chip application scenario; performing electro-thermal coupling simulation and outputting the distribution of heat dissipation requirements on the contact surface; performing flow field simulation optimization analysis to locate the distribution of pin fin density on the heat dissipation surface; performing collaborative layout analysis and outputting the distribution of welding areas; performing matching of welding groove structure parameters and outputting the distribution of welding grooves; fusing the distribution of welding grooves and the distribution of pin fin density on the heat dissipation surface into the contact surface structure to obtain a void ratio optimization model; and performing mold opening and mass production of the copper heat dissipation base plate according to the void ratio optimization model. It solves the technical problem in the prior art that the void ratio of the contact surface of the IGBT copper heat dissipation base plate is uneven, resulting in unstable heat dissipation performance, and achieves the technical effects of optimizing the void ratio of the contact surface of the heat dissipation base plate, improving the heat dissipation efficiency and stability.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and particularly to a method and system for optimizing the void ratio structure of the contact surface of an IGBT copper heat dissipation bottom plate. Background Art

[0002] With the continuous miniaturization and high performance of electronic devices, especially the wide application of IGBT (Insulated Gate Bipolar Transistor) in the field of power electronics, increasingly strict requirements are imposed on its heat dissipation performance. During the operation of an IGBT chip, a large amount of heat is generated. If it cannot be dissipated in a timely and effective manner, the chip temperature will be too high, which will affect its normal operation and may even cause equipment damage. As a key connecting component between the IGBT chip and the external heat dissipation structure, the heat dissipation performance of the contact surface of the copper heat dissipation bottom plate becomes an important factor affecting the working temperature and reliability of the IGBT chip. However, in the prior art, there are problems such as uneven void ratio distribution and unstable heat dissipation performance in the design of the contact surface of the copper heat dissipation bottom plate, resulting in the heat dissipation effect not meeting the expectations, and further affecting the reliability and service life of the overall system. Summary of the Invention

[0003] This application provides a method and system for optimizing the void ratio structure of the contact surface of an IGBT copper heat dissipation bottom plate, which solves the technical problem of uneven void ratio of the contact surface of the IGBT copper heat dissipation bottom plate in the prior art, resulting in unstable heat dissipation performance.

[0004] In the first aspect of this application, a method for optimizing the void ratio structure of the contact surface of an IGBT copper heat dissipation bottom plate is provided. The method includes:

[0005] Performing model network call according to the packaging structure of the IGBT chip to obtain a chip simulation model; performing local order call according to the chip unique identifier to determine the chip application scenario; extracting the power distribution characteristics of the chip application scenario to perform electro-thermal coupling simulation on the chip simulation model, and outputting the contact surface heat dissipation demand distribution; performing flow field simulation optimization analysis according to the contact surface heat dissipation demand distribution to locate the pin fin density distribution of the heat dissipation surface; performing collaborative layout analysis according to the contact surface heat dissipation demand distribution and the pin fin density distribution of the heat dissipation surface, and outputting the welding area distribution; dividing the welding area distribution based on the consistency of heat dissipation requirements to obtain multiple local welding areas, performing welding groove structure parameter matching according to the multiple area heat dissipation requirements of the multiple local welding areas, and outputting the welding groove distribution; fusing the welding groove distribution and the pin fin density distribution of the heat dissipation surface into the contact surface structure to obtain a void ratio optimization model; and performing mold opening and mass production of the copper heat dissipation bottom plate according to the void ratio optimization model.

[0006] In the second aspect of this application, a system for optimizing the void ratio structure of the contact surface of an IGBT copper heat dissipation bottom plate is provided. The system includes:

[0007] The first call module is used to perform model network call according to the packaging structure of the IGBT chip to obtain a chip simulation model; the second call module is used to perform local order call according to the chip unique identifier to determine the chip application scenario; the simulation module is used to extract the power distribution characteristics of the chip application scenario to perform electro-thermal coupling simulation on the chip simulation model and output the contact surface heat dissipation demand distribution; the optimization analysis module is used to perform flow field simulation optimization analysis according to the contact surface heat dissipation demand distribution to locate the fin density distribution of the heat dissipation surface; the collaborative analysis module is used to perform collaborative layout analysis according to the contact surface heat dissipation demand distribution and the fin density distribution of the heat dissipation surface and output the welding area distribution; the parameter matching module is used to divide the welding area distribution based on the consistency of heat dissipation requirements to obtain multiple local welding areas, perform welding groove structure parameter matching according to the multiple area heat dissipation requirements of the multiple local welding areas, and output the welding groove distribution; the fusion module is used to fuse the welding groove distribution and the fin density distribution of the heat dissipation surface into the contact surface structure to obtain a void ratio optimization model; the production module is used to perform mold opening and mass production of the copper heat dissipation bottom plate according to the void ratio optimization model.

[0008] One or more technical solutions provided in this application have at least the following technical effects or advantages:

[0009] First, perform a model network call according to the packaging structure of the IGBT chip to obtain a chip simulation model. Next, perform a local order call according to the chip unique identifier to determine the chip application scenario. Further, extract the power distribution characteristics of the chip application scenario to perform electro-thermal coupling simulation on the chip simulation model and output the contact surface heat dissipation demand distribution. Then, perform flow field simulation optimization analysis according to the contact surface heat dissipation demand distribution to locate the fin density distribution of the heat dissipation surface. Next, perform collaborative layout analysis according to the contact surface heat dissipation demand distribution and the fin density distribution of the heat dissipation surface and output the welding area distribution. Further, divide the welding area distribution based on the consistency of heat dissipation requirements to obtain multiple local welding areas, perform welding groove structure parameter matching according to the multiple area heat dissipation requirements of the multiple local welding areas, and output the welding groove distribution. Finally, fuse the welding groove distribution and the fin density distribution of the heat dissipation surface into the contact surface structure to obtain a void ratio optimization model; perform mold opening and mass production of the copper heat dissipation bottom plate according to the void ratio optimization model. It solves the technical problem in the prior art that the void ratio of the contact surface of the IGBT copper heat dissipation bottom plate is uneven, resulting in unstable heat dissipation performance, and achieves the technical effect of optimizing the void ratio of the contact surface of the heat dissipation bottom plate and improving the heat dissipation efficiency and stability. Description of the Drawings

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0011] Figure 1 Schematic flow diagram of the structural optimization method for the void ratio of the IGBT copper heat dissipation bottom plate contact surface provided by the embodiments of the present application;

[0012] Figure 2 Schematic structural diagram of the structural optimization system for the void ratio of the IGBT copper heat dissipation bottom plate contact surface provided by the embodiments of the present application.

[0013] Explanation of reference numerals: First call module 11, second call module 12, simulation module 13, optimization analysis module 14, collaborative analysis module 15, parameter matching module 16, fusion module 17, production module 18. Specific embodiments

[0014] By providing a structural optimization method and system for the void ratio of the IGBT copper heat dissipation bottom plate contact surface, the present application solves the technical problem in the prior art that the void ratio of the IGBT copper heat dissipation bottom plate contact surface is uneven, resulting in unstable heat dissipation performance.

[0015] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0016] It should be noted that the terms "including" and "having" are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or server that includes a series of steps or units does not necessarily have to be limited to those clearly listed steps or units, but may include other steps or modules that are not clearly listed or are inherent to these processes, methods, products, or devices.

[0017] Embodiment 1, as Figure 1 shown, the present application provides a structural optimization method for the void ratio of the IGBT copper heat dissipation bottom plate contact surface, wherein the method includes:

[0018] Perform model network call according to the packaging structure of the IGBT chip to obtain a chip simulation model.

[0019] By extracting the characteristic parameters of the IGBT chip packaging structure, information such as the geometric features, material properties, and process features of the chip packaging is obtained. Specifically, the geometric features include the size, shape, packaging method, etc. of the chip; the material properties include the thermal conductivity, electrical conductivity, expansion coefficient, etc. of the chip packaging material; the process features include the welding process, bonding process, and material distribution used during the packaging process. Based on the extracted characteristic parameters, a network call is made in the cloud model library to search for the chip simulation model that best matches the current packaging structure.

[0020] Furthermore, according to the packaging structure of the IGBT chip, a network call is made to obtain the chip simulation model. The method includes:

[0021] By extracting the characteristic parameters of the packaging structure, the packaging structure parameters are obtained, where the packaging structure parameters include a geometric feature set, a material property set, and a process feature set; the packaging structure parameters are converted into a structured feature vector using hierarchical JSON; there is a parameterized model library pre-stored in the cloud, where the parameterized model library stores multiple sample feature vectors of multiple sample candidate models; after loading the structured feature vector into the parameterized model library, model retrieval is performed in the parameterized model library using the feature vector similarity algorithm to determine the chip simulation model.

[0022] Specifically, the characteristic parameters of the IGBT chip packaging structure are extracted. The packaging structure parameters include a geometric feature set, a material property set, and a process feature set. Among them, the geometric feature set includes the external dimensions, packaging method, and contact surface distribution of the chip; the material property set includes properties such as the thermal conductivity, electrical conductivity, and expansion coefficient of the packaging material; the process feature set includes technical parameters such as the welding process, bonding method, and temperature control during the packaging process; the packaging structure parameters are converted into a structured feature vector using the hierarchical JSON format. This feature vector contains all the information of the packaging structure, facilitating computer processing and subsequent model retrieval.

[0023] There is a parameterized model library pre-stored in the cloud. The parameterized model library stores multiple sample candidate models and their corresponding feature vectors. Among them, each sample candidate model represents a typical packaging structure, and the feature vector of each model is generated based on the geometric features, material properties, and process features of the packaging structure.

[0024] By loading the structured feature vector into the parameterized model library, model retrieval is performed based on the feature vector similarity algorithm (such as Euclidean distance), that is, the similarity between the structured feature vector and the feature vectors of each candidate model in the library is calculated, and the chip simulation model that is most similar to the packaging structure is selected. Based on the selected chip simulation model, local calibration is performed in combination with the extracted packaging structure parameters to obtain an accurate chip simulation model.

[0025] Furthermore, by using the feature vector similarity algorithm in the parametric model library to perform model retrieval, the chip simulation model is determined. The method includes:

[0026] Using the feature vector similarity algorithm in the parametric model library to perform model retrieval to determine N candidate models; evaluating the scene type matching degree between the chip application scenario and the N historical application scenarios of the N candidate models to screen and output an initial simulation model from the N candidate models; performing local parameter calibration on the initial simulation model based on the package structure parameters to obtain the chip simulation model.

[0027] In the parametric model library, the feature vector similarity algorithm is used to compare the input package structure feature vector with the feature vectors of multiple candidate models in the model library, and N candidate models are screened out. Each candidate model represents a potential simulation model of a package structure, and the similarity between its feature vector and the input package structure feature vector is the highest.

[0028] For the selected N candidate models, the type matching degree of the historical application scenario of each candidate model is evaluated based on the actual application scenario of the chip. Specifically, by comparing factors such as the working environment, electrical load, and thermal management of the chip with the historical application scenarios of the candidate models, the applicability of each candidate model in the current application scenario is evaluated. According to the matching degree evaluation results, the initial simulation model that best matches the actual application scenario is screened out from the N candidate models.

[0029] Based on the parameters of the package structure, local parameter calibration is performed on the selected initial simulation model. Specifically, relevant physical parameters in the initial simulation model can be adjusted according to the geometric features, material properties, and process features of the input package structure to ensure that the simulation model can accurately reflect the thermoelectric characteristics of the IGBT chip under actual working conditions. After calibration, the final chip simulation model is obtained.

[0030] The chip application scenario is determined by making a local order call according to the chip unique identifier.

[0031] In the embodiment of the present application, the unique identifier of each IGBT chip (such as chip serial number, model number, etc.) is obtained. The unique identifier can uniquely identify each chip and is associated with its relevant application information.

[0032] It is called through the local order system. Specifically, the local order system stores all order data related to the chip, including information such as chip manufacturing, delivery, installation, and application scenarios. By inputting the unique identifier of the chip, the system can retrieve the detailed information of the chip in a specific order and determine the specific application scenario of the chip. According to the background information of the order where the chip is located, identify its working conditions and environment in actual use. For example, the chip may be applied to different power electronic devices, such as inverters, frequency converters, motor controllers, etc., and the thermal and electrical characteristic requirements of each application scenario may be different. Through local order calling, the system can clarify the working load, cooling requirements, and other environmental factors of the chip, so as to provide accurate application background information for the subsequent establishment of the chip simulation model.

[0033] Extract the power distribution characteristics of the chip application scenario, perform electro-thermal coupling simulation on the chip simulation model, and output the heat dissipation demand distribution of the contact surface.

[0034] In the embodiment of the present application, based on the determined chip application scenario, extract the power distribution characteristics under this scenario. The power distribution characteristics include information such as power density, power loss spectrum, and electrical load of the chip under different working conditions. These characteristic data reflect the thermal load distribution of the chip in actual application, such as the heat generation situation in different regions, the spatio-temporal variation of power density, etc. Use the extracted power distribution characteristics as boundary conditions and apply them to the chip simulation model. The chip simulation model simulates the heat conduction and current distribution of the chip through electro-thermal coupling simulation, so as to obtain the heat dissipation demand distribution of the contact surface. The heat dissipation demand distribution describes the heat that needs to be dissipated in different regions and the heat flux density required to achieve heat dissipation in this region.

[0035] Furthermore, extracting the power distribution characteristics of the chip application scenario, performing electro-thermal coupling simulation on the chip simulation model, and outputting the heat dissipation demand distribution of the contact surface, the method includes:

[0036] According to the chip application scenario, extract the electrical parameters and cooling condition parameters of typical working conditions; based on the electrical parameters of typical working conditions, perform spatio-temporal distribution modeling to obtain the power density distribution matrix, and use the power density distribution matrix as the power distribution characteristics; after hierarchically loading the material property parameters of the chip simulation model, apply thermal boundary conditions to the chip simulation model based on the cooling condition parameters, and apply electro-thermal coupling boundary conditions to the chip simulation model based on the power density distribution matrix to solve and output the heat flux density distribution of the contact surface and the temperature field of the contact surface; calculate the local thermal resistance distribution according to the heat flux density distribution of the contact surface and the temperature field of the contact surface; based on the local thermal resistance distribution and multiple heat flux density thresholds, divide the heat dissipation demand levels and output the heat dissipation demand distribution of the contact surface.

[0037] Preferably, based on the chip application scenario, typical operating condition electrical parameters and cooling condition parameters in this application scenario are extracted from big data. The electrical parameters include switching frequency, duty cycle, conduction current, etc. during the chip operation, and the cooling condition parameters include coolant flow rate, ambient temperature, etc. in the environment where the chip is located.

[0038] Using the extracted typical operating condition electrical parameters, the power density distribution of the chip at different time and space positions is obtained through modeling and calculation. Specifically, based on the electrical parameters, the power losses at each time point and each position are calculated, including conduction losses, switching losses, reverse recovery losses, etc. Through these data, a power density distribution matrix is formed, which represents the power distribution characteristics of the chip during operation. The power density distribution matrix will be used as the power distribution characteristic input to the chip simulation model.

[0039] In the chip simulation model, hierarchical loading of material property parameters is carried out, including physical properties such as thermal conductivity, electrical conductivity, and expansion coefficient; then, based on the cooling condition parameters, thermal boundary conditions are applied to the chip simulation model, and these boundary conditions reflect the heat exchange between the chip and the cooling environment; then, according to the power density distribution matrix, electro-thermal coupling boundary conditions are applied. Through this series of conditions, the simulation model can truly reflect the electro-thermal behavior of the chip in actual applications.

[0040] Through electro-thermal coupling simulation, the heat flux density distribution and temperature field distribution on the chip contact surface are solved. Among them, the heat flux density distribution describes the heat transfer situation on the chip contact surface, and the temperature field distribution describes the temperature changes at each position. According to the obtained heat flux density distribution on the contact surface and the contact surface temperature field data, the local thermal resistance distribution is calculated. The local thermal resistance represents the thermal conduction resistance of each area on the chip contact surface, reflecting the hindering effect of different positions on heat conduction. The thermal resistance calculation formula: R = ΔT / Q, where R represents the thermal resistance, ΔT represents the temperature difference between any position and its adjacent area, and Q is the heat flux density at any position.

[0041] Combined with the local thermal resistance distribution and the set multi-level heat flux density thresholds, the heat dissipation requirement levels of each area on the contact surface are divided; according to the heat dissipation requirement levels of different areas, the required heat dissipation amount and heat dissipation capacity of this area are determined. Finally, the output heat dissipation requirement distribution on the contact surface can provide detailed heat dissipation requirement information for subsequent heat dissipation optimization design to ensure that the heat dissipation system can meet the thermal management requirements of the chip.

[0042] Furthermore, based on the typical operating condition electrical parameters, a spatio-temporal distribution model is established to obtain the power density distribution matrix. The method includes:

[0043] Calculate the dynamic power loss spectrum based on the electrical parameters of the typical working conditions, where the dynamic power loss spectrum includes the spatio-temporal distributions of conduction loss, switching loss, and reverse recovery loss; discretize the dynamic power loss spectrum into the power density distribution matrix.

[0044] The dynamic power loss spectrum describes the characteristics of the power loss of the chip changing with time and space under different working conditions. According to the electrical parameters of the typical working conditions (such as working voltage, current, switching frequency, etc.), the dynamic power loss spectrum of the chip can be obtained by calculating the spatio-temporal distribution of the power loss.

[0045] When the IGBT chip is in the conduction state, the chip will generate heat due to the flowing current. The conduction loss is caused by the resistance of the conductive material in the chip. The conduction loss calculation formula: is the on-resistance of the chip.

[0046] The switching loss refers to the energy loss generated by the multiplication of the instantaneous current and voltage during the switching process. The switching loss calculation formula: is the switching loss, is the switching frequency.

[0047] The reverse recovery loss refers to the loss generated by the recombination or migration of carriers when the IGBT chip switches from the conduction state to the off state. The reverse recovery loss usually depends on the reverse recovery time and the reverse current characteristics, and can be calculated from experimental data.

[0048] The dynamic power loss spectrum contains the power loss conditions of each position and time point during the operation of the chip. By discretizing the dynamic power loss spectrum into a grid power density matrix, it is used to provide load input for subsequent simulations. Among them, each grid cell corresponds to the local power density value on the chip surface.

[0049] Conduct a flow field simulation optimization analysis according to the heat dissipation demand distribution of the contact surface, and locate the pin fin density distribution on the heat dissipation surface.

[0050] By analyzing the matching of the coolant flow field distribution and the heat flux density, locate the pin fin layout to maximize the heat dissipation surface area and reduce the flow resistance, so as to achieve enhanced heat dissipation.

[0051] Furthermore, conduct a flow field simulation optimization analysis according to the heat dissipation demand distribution of the contact surface, and locate the pin fin density distribution on the heat dissipation surface. The method includes:

[0052] Decompose the heat dissipation demand distribution of the contact surface based on the demand level to obtain the first heat dissipation demand area distribution, the second heat dissipation demand area distribution up to the Kth heat dissipation demand area distribution; locally call the H sample pin fin densities of the H-level heat dissipation demand, where H is a positive integer greater than K; traverse the H-level heat dissipation demand by using the first heat dissipation demand area distribution, the second heat dissipation demand area distribution up to the Kth heat dissipation demand area distribution, and extract the initial pin fin density demand from the H sample pin fin densities, where the initial pin fin density demand includes the first pin fin density demand, the second pin fin density demand up to the Kth pin fin density demand; after loading the pin fin model in the contact surface simulation layer of the chip simulation model according to the initial pin fin density demand and the heat dissipation demand distribution of the contact surface, run the flow field simulation in combination with the cooling condition parameters and the power density distribution matrix, and output the heat dissipation efficiency distribution and the fluid resistance distribution; perform iterative optimization of the pin fin layout based on the heat dissipation efficiency distribution and the fluid resistance distribution, and output the pin fin density distribution of the heat dissipation surface.

[0053] Based on the heat dissipation demand distribution of the contact surface, divide this distribution into demand levels to obtain multiple heat dissipation demand areas. Specifically, according to the high and low heat flux density, the contact surface can be divided into the first heat dissipation demand area, the second heat dissipation demand area, up to the Kth heat dissipation demand area, and the heat dissipation demand level of each area will reflect the different requirements of this area for heat dissipation capacity. For each heat dissipation demand area, the system calls the H sample pin fin densities of the H-level heat dissipation demand, where H is a positive integer greater than K. Each sample pin fin density represents the actual pin fin distribution of different heat dissipation demand levels.

[0054] By traversing the first to the Kth heat dissipation demand areas and combining the H-level heat dissipation demand, extract the initial pin fin density demand for each area. The initial pin fin density demand includes the first pin fin density demand, the second pin fin density demand, up to the Kth pin fin density demand. According to the obtained initial pin fin density demand and the heat dissipation demand distribution of the contact surface, load the pin fin model in the contact surface simulation layer of the chip simulation model. After the loading is completed, combine the cooling condition parameters and the power density distribution matrix, and run the flow field simulation to simulate the heat dissipation efficiency and the fluid resistance of the pin fin layout on the heat dissipation surface. Based on the heat dissipation efficiency distribution and the fluid resistance distribution obtained from the flow field simulation, the system performs iterative optimization of the pin fin layout. Through the optimization process, gradually adjust the density distribution of the pin fins to achieve the optimal heat dissipation effect and fluid flow characteristics. The finally output pin fin density distribution of the heat dissipation surface can ensure that while meeting the heat dissipation demands of each area, improve the heat dissipation efficiency and stability of the entire system.

[0055] Furthermore, perform iterative optimization of the pin fin layout based on the heat dissipation efficiency distribution and the fluid resistance distribution, and output the pin fin density distribution of the heat dissipation surface. The method includes:

[0056] Locally call the heat dissipation efficiency threshold and the fluid resistance threshold; use the heat dissipation efficiency threshold and the fluid resistance threshold to traverse the heat dissipation efficiency distribution and the fluid resistance distribution in the superposition state, and locate the initial efficiency-resistance deviation distribution; perform pin fin density matching update according to the deviation scale identification of the initial efficiency-resistance deviation distribution, and output the first optimized density requirement; according to the initial pin fin density requirement, the first optimized density requirement and the contact surface heat dissipation requirement distribution, after loading the pin fin model in the contact surface simulation layer of the chip simulation model, run the flow field simulation in combination with the cooling condition parameters and the power density distribution matrix, and output the first optimized efficiency distribution and the first optimized resistance distribution; use the heat dissipation efficiency threshold and the fluid resistance threshold to traverse the superposition state of the first optimized efficiency distribution and the first optimized resistance distribution, and locate the first optimized deviation distribution; perform pin fin density matching update according to the deviation scale identification of the first optimized deviation distribution, and output the second optimized density requirement; and so on, perform iterative optimization of the pin fin layout until the pin fin density distribution of the heat dissipation surface is output.

[0057] Locally call the heat dissipation efficiency threshold and the fluid resistance threshold. The heat dissipation efficiency threshold sets the minimum heat dissipation efficiency required for each region, and the fluid resistance threshold sets the maximum acceptable resistance in fluid flow. Through these two thresholds, the effectiveness of the optimization process is ensured, and invalid adjustments within unreasonable ranges are avoided. Use the heat dissipation efficiency threshold and the fluid resistance threshold to traverse the heat dissipation efficiency distribution and the fluid resistance distribution in the superposition state, so as to determine the initial efficiency-resistance deviation distribution of each region. In the initial efficiency-resistance deviation distribution, each deviation region has an efficiency deviation scale and a resistance deviation scale identification.

[0058] Perform pin fin density matching update according to the deviation scale identification of the initial efficiency-resistance deviation distribution. Specifically, if the heat dissipation efficiency in some regions is insufficient, it may be necessary to increase the density of the pin fins to improve the heat dissipation capacity; on the contrary, if the fluid resistance in some regions is too large, it may be necessary to reduce the density of the pin fins to reduce the fluid resistance. Through this adjustment of the pin fin density, output the first optimized density requirement as the guiding basis for optimizing the pin fin layout.

[0059] Based on the initial pin fin density requirement, the first optimized density requirement, and the contact surface heat dissipation requirement distribution, the pin fin model is loaded on the contact surface simulation layer of the chip simulation model. After the loading is completed, combined with the extracted cooling condition parameters and the power density distribution matrix, the flow field simulation is run to output the first optimized heat dissipation efficiency distribution and the first optimized fluid resistance distribution. Using the heat dissipation efficiency threshold and the fluid resistance threshold, traverse the first optimized heat dissipation efficiency distribution and the first optimized fluid resistance distribution to locate the first optimized deviation distribution. According to the deviation scale identification of the first optimized deviation distribution, perform the second matching update of the pin fin density. By adjusting the second pin fin density, further optimize the balance between the heat dissipation efficiency and the fluid resistance. Finally, after multiple rounds of iterative optimization, until the final heat dissipation surface pin fin density distribution is output.

[0060] Perform collaborative layout analysis according to the contact surface heat dissipation requirement distribution and the heat dissipation surface pin fin density distribution, and output the welding area distribution.

[0061] Perform collaborative layout analysis according to the contact surface heat dissipation requirement distribution and the heat dissipation surface pin fin density distribution, identify the areas where welding can be performed, and generate the welding area distribution.

[0062] Furthermore, perform collaborative layout analysis according to the contact surface heat dissipation requirement distribution and the heat dissipation surface pin fin density distribution, and output the welding area distribution. The method includes:

[0063] Preset the welding heat flux density threshold, and use the welding heat flux density threshold to traverse the contact surface heat dissipation requirement distribution to locate the first non-weldable area distribution; preset the pin fin spacing threshold, and use the pin fin spacing threshold to traverse the heat dissipation surface pin fin density distribution to locate the second non-weldable area distribution; reverse locate the welding area distribution according to the first non-weldable area distribution and the first non-weldable area distribution.

[0064] Preset the welding heat flux density threshold, which is used to identify which areas have too high heat flux density and are thus not suitable for welding. By using the welding heat flux density threshold to traverse the contact surface heat dissipation requirement distribution, locate the first non-weldable area distribution. The first non-weldable areas are those areas where the heat dissipation capacity cannot meet the temperature requirements during the welding process. These areas usually cannot withstand the high temperature generated during the welding process due to excessive heat or insufficient heat dissipation.

[0065] Preset the pin fin spacing threshold, and traverse the heat dissipation surface pin fin density distribution through this threshold to locate the second non-weldable area distribution. The second non-weldable areas are those areas where the layout of the pin fins is inappropriate (such as too small or too large pin fin spacing), resulting in uneven heat conduction during the welding process or the welding quality cannot be guaranteed.

[0066] Locate the welding area distribution in reverse according to the first non-weldable area distribution and the second non-weldable area distribution. By analyzing the non-weldable areas, the weldable areas are deduced in reverse. These welding areas should meet the requirements of welding heat flux density and avoid interference with the welding process caused by over-dense pin fin layouts. Finally, the output welding area distribution can ensure that the welding process does not affect the heat dissipation performance and guarantee the welding quality.

[0067] Divide the welding area distribution based on the consistency of heat dissipation requirements to obtain multiple local welding areas. Match the welding groove structure parameters according to the heat dissipation requirements of the multiple local welding areas, and output the welding groove distribution.

[0068] The consistency of heat dissipation requirements means that within the welding area, the heat dissipation requirements at each position are consistent within a certain range. Based on the consistency of heat dissipation requirements on the contact surface, the welding area is divided, that is, to determine which areas have similar heat dissipation requirements and divide them into multiple local welding areas.

[0069] According to the heat dissipation requirements of each local welding area, match the welding groove structure parameters, and select suitable groove depths, widths, shapes, groove wall inclination angles, bottom surface curvatures, etc. to ensure that the heat dissipation requirements can be met after welding. Finally, output the optimized welding groove distribution to ensure the best heat dissipation effect for each welding area.

[0070] Furthermore, the method of dividing the welding area distribution based on the consistency of heat dissipation requirements to obtain multiple local welding areas, matching the welding groove structure parameters according to the heat dissipation requirements of the multiple local welding areas, and outputting the welding groove distribution includes:

[0071] Extract the geometric contours of the multiple local welding areas to obtain multiple welding geometries; match the welding grooves in the welding groove structure parameter library according to the multiple welding geometries and the heat dissipation requirements of the multiple areas to obtain multiple initial welding grooves; perform smoothing processing on the connection nodes of the multiple initial welding grooves to obtain the welding groove distribution.

[0072] By analyzing the shape and size of each local welding area, its geometric contour is extracted to obtain multiple welding geometries, which will provide basic data for the subsequent design of welding grooves to ensure that the grooves can match the physical properties and heat dissipation requirements of each local area. According to the obtained multiple welding geometries and the heat dissipation requirements of multiple areas, welding groove matching is carried out in the welding groove structure parameter library. The welding groove structure parameter library contains a variety of different welding groove designs, and each design has different parameters such as groove depth, width, shape, etc. By comparing the multiple welding geometries with the heat dissipation requirements of the area, the most suitable welding groove parameters are selected to ensure that the heat dissipation capacity of the welding area matches the actual requirements, thereby effectively improving the heat dissipation efficiency.

[0073] During the matching process, the system automatically selects a suitable initial welding groove according to the specific requirements of each local welding area and outputs design schemes for multiple initial welding grooves. The connection nodes of the obtained multiple initial welding grooves are smoothed, that is, the seams or abrupt transition parts between the welding grooves are eliminated to ensure a smooth transition at the connection of the welding area, so as to optimize the heat conduction effect and avoid stress concentration. After the smoothing process, the final welding groove distribution is obtained.

[0074] The welding groove distribution and the heat dissipation surface pin fin density distribution are integrated into the contact surface structure to obtain a void ratio optimization model.

[0075] The welding groove distribution is designed based on the heat dissipation requirements and geometric shapes of each local welding area, while the heat dissipation surface pin fin density distribution reflects the heat dissipation capacity of different areas on the heat dissipation surface. By integrating the welding groove distribution with the heat dissipation surface pin fin density distribution, a void ratio optimization model can be obtained, which describes the distribution of the void areas formed by the welding grooves and pin fin layouts in the contact surface structure.

[0076] Based on the void ratio optimization model, the copper heat dissipation bottom plate is molded and mass-produced.

[0077] The void ratio optimization model has integrated the optimization results of the welding groove distribution and the heat dissipation surface pin fin density distribution, which can ensure the best heat dissipation effect in each area of the heat dissipation bottom plate and minimize the negative impact of the welding grooves and void areas on the overall heat dissipation performance. Using the design data in the void ratio optimization model, the copper heat dissipation bottom plate is molded, and after the mold is made, the copper heat dissipation bottom plate is mass-produced.

[0078] In summary, the embodiments of the present application have at least the following technical effects:

[0079] First, perform a model network call according to the packaging structure of the IGBT chip to obtain a chip simulation model. Next, perform a local order call according to the unique chip identifier to determine the chip application scenario. Further, extract the power distribution characteristics of the chip application scenario to perform electro-thermal coupling simulation on the chip simulation model, and output the contact surface heat dissipation demand distribution. Next, perform a flow field simulation optimization analysis according to the contact surface heat dissipation demand distribution to locate the fin density distribution of the heat dissipation surface. Then, perform a collaborative layout analysis according to the contact surface heat dissipation demand distribution and the fin density distribution of the heat dissipation surface, and output the welding area distribution. Further, divide the welding area distribution based on the consistency of heat dissipation requirements to obtain multiple local welding areas, and perform welding groove structure parameter matching according to the heat dissipation requirements of multiple local welding areas to output the welding groove distribution. Finally, fuse the welding groove distribution and the fin density distribution of the heat dissipation surface into the contact surface structure to obtain a void ratio optimization model; perform die opening and mass production of the copper heat dissipation bottom plate according to the void ratio optimization model. This solves the technical problem in the prior art that the void ratio of the contact surface of the IGBT copper heat dissipation bottom plate is uneven, resulting in unstable heat dissipation performance, and achieves the technical effect of optimizing the void ratio of the contact surface of the heat dissipation bottom plate and improving the heat dissipation efficiency and stability.

[0080] Embodiment 2, based on the same inventive concept as the method for optimizing the structure of the void ratio of the contact surface of the IGBT copper heat dissipation bottom plate in the foregoing embodiment, as Figure 2 shown, the present application provides a system for optimizing the structure of the void ratio of the contact surface of the IGBT copper heat dissipation bottom plate, wherein the system includes:

[0081] A first calling module 11, configured to perform a model network call according to the packaging structure of the IGBT chip to obtain a chip simulation model; a second calling module 12, configured to perform a local order call according to the unique chip identifier to determine the chip application scenario; a simulation module 13, configured to extract the power distribution characteristics of the chip application scenario to perform electro-thermal coupling simulation on the chip simulation model, and output the contact surface heat dissipation demand distribution; an optimization analysis module 14, configured to perform a flow field simulation optimization analysis according to the contact surface heat dissipation demand distribution to locate the fin density distribution of the heat dissipation surface; a collaborative analysis module 15, configured to perform a collaborative layout analysis according to the contact surface heat dissipation demand distribution and the fin density distribution of the heat dissipation surface, and output the welding area distribution; a parameter matching module 16, configured to divide the welding area distribution based on the consistency of heat dissipation requirements to obtain multiple local welding areas, and perform welding groove structure parameter matching according to the heat dissipation requirements of multiple local welding areas to output the welding groove distribution; a fusion module 17, configured to fuse the welding groove distribution and the fin density distribution of the heat dissipation surface into the contact surface structure to obtain a void ratio optimization model; a production module 18, configured to perform die opening and mass production of the copper heat dissipation bottom plate according to the void ratio optimization model.

[0082] Further, the simulation module 13 is used to execute the following method:

[0083] Extract the electrical parameters and cooling condition parameters of typical working conditions according to the chip application scenario; perform a spatio-temporal distribution modeling based on the electrical parameters of the typical working conditions to obtain a power density distribution matrix, and use the power density distribution matrix as the power distribution feature; after hierarchically loading the material property parameters of the chip simulation model, apply a thermal boundary condition to the chip simulation model based on the cooling condition parameters, and apply an electro-thermal coupling boundary condition to the chip simulation model based on the power density distribution matrix to solve and output the contact surface heat flux density distribution and the contact surface temperature field; calculate the local thermal resistance distribution according to the contact surface heat flux density distribution and the contact surface temperature field; divide the heat dissipation demand level based on the local thermal resistance distribution and multiple heat flux density thresholds, and output the contact surface heat dissipation demand distribution.

[0084] Further, the simulation module 13 is used to execute the following method:

[0085] Calculate the dynamic power loss spectrum based on the electrical parameters of the typical working conditions, where the dynamic power loss spectrum includes the spatio-temporal distributions of conduction loss, switching loss, and reverse recovery loss;

[0086] Discretize the dynamic power loss spectrum into the power density distribution matrix.

[0087] Further, the optimization analysis module 14 is used to execute the following method:

[0088] Decompose the contact surface heat dissipation demand distribution based on the demand level to obtain the first heat dissipation demand area distribution, the second heat dissipation demand area distribution to the Kth heat dissipation demand area distribution; locally call the H sample pin fin densities of the H-level heat dissipation demand, where H is a positive integer greater than K; by using the first heat dissipation demand area distribution, the second heat dissipation demand area distribution to the Kth heat dissipation demand area distribution to traverse the H-level heat dissipation demand, extract the initial pin fin density demand from the H sample pin fin densities, where the initial pin fin density demand includes the first pin fin density demand, the second pin fin density demand to the Kth pin fin density demand; according to the initial pin fin density demand and the contact surface heat dissipation demand distribution, after loading the pin fin model in the contact surface simulation layer of the chip simulation model, combine the cooling condition parameters and the power density distribution matrix to run the flow field simulation, and output the heat dissipation efficiency distribution and the fluid resistance distribution; perform iterative optimization of the pin fin layout based on the heat dissipation efficiency distribution and the fluid resistance distribution, and output the pin fin density distribution of the heat dissipation surface.

[0089] Further, the optimization analysis module 14 is used to execute the following method:

[0090] Local call of the heat dissipation efficiency threshold and the fluid resistance threshold; traversing and superimposing the heat dissipation efficiency distribution and the fluid resistance distribution in the superimposed state using the heat dissipation efficiency threshold and the fluid resistance threshold to locate the initial efficiency-resistance deviation distribution; performing pin fin density matching update according to the deviation scale identification of the initial efficiency-resistance deviation distribution to output the first optimized density requirement; according to the initial pin fin density requirement, the first optimized density requirement and the contact surface heat dissipation requirement distribution, after loading the pin fin model in the contact surface simulation layer of the chip simulation model, running the flow field simulation in combination with the cooling condition parameters and the power density distribution matrix to output the first optimized efficiency distribution and the first optimized resistance distribution; traversing and superimposing the first optimized efficiency distribution and the first optimized resistance distribution in the superimposed state using the heat dissipation efficiency threshold and the fluid resistance threshold to locate the first optimized deviation distribution; performing pin fin density matching update according to the deviation scale identification of the first optimized deviation distribution to output the second optimized density requirement; and so on, performing iterative optimization of the pin fin layout until the pin fin density distribution of the heat dissipation surface is output.

[0091] Further, the collaborative analysis module 15 is used to execute the following method:

[0092] Preset the welding heat flux density threshold, and traverse the contact surface heat dissipation requirement distribution using the welding heat flux density threshold to locate the first non-weldable area distribution; preset the pin fin spacing threshold, and traverse the pin fin density distribution of the heat dissipation surface using the pin fin spacing threshold to locate the second non-weldable area distribution; and reverse-locate the welding area distribution according to the first non-weldable area distribution and the first non-weldable area distribution.

[0093] Further, the parameter matching module 16 is used to execute the following method:

[0094] Extract the geometric contours of the multiple local welding areas to obtain multiple welding geometries; perform welding groove matching in the welding groove structure parameter library according to the multiple welding geometries and the heat dissipation requirements of the multiple areas to obtain multiple initial welding grooves; and perform smoothing processing on the connection nodes of the multiple initial welding grooves to obtain the welding groove distribution.

[0095] Further, the first call module 11 is used to execute the following method:

[0096] By extracting the characteristic parameters of the encapsulation structure, encapsulation structure parameters are obtained, where the encapsulation structure parameters include a geometric feature set, a material property set, and a process feature set; the encapsulation structure parameters are converted into a structured feature vector using hierarchical JSON; a parameterized model library is pre-stored in the cloud, where the parameterized model library stores multiple sample feature vectors of multiple sample candidate models; after loading the structured feature vector into the parameterized model library, a model retrieval is performed in the parameterized model library using a feature vector similarity algorithm to determine the chip simulation model.

[0097] Further, the first call module 11 is used to execute the following method:

[0098] A model retrieval is performed in the parameterized model library using a feature vector similarity algorithm to determine N candidate models; a scenario type matching degree evaluation is performed on the chip application scenario and the N historical application scenarios of the N candidate models to screen and output an initial simulation model from the N candidate models; local parameter calibration is performed on the initial simulation model based on the encapsulation structure parameters to obtain the chip simulation model.

[0099] It should be noted that the above order of the embodiments of the present application is only for description and does not represent the advantages and disadvantages of the embodiments. And the above specific embodiments of the present specification have been described. The processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0100] The above are only the preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

[0101] This specification and the drawings are only exemplary descriptions of the present application and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the present application. Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the present application and its equivalent technologies, the present application is intended to include these changes and modifications.

Claims

1. A structural optimization method for the void ratio of the contact surface of an IGBT copper heat dissipation base plate, characterized in that, The method includes: Performing model network calls according to the packaging structure of the IGBT chip to obtain a chip simulation model; Performing local order calls according to the chip unique identifier to determine the chip application scenario; Extracting the power distribution characteristics of the chip application scenario to perform electrothermal coupling simulation on the chip simulation model, and outputting the contact surface heat dissipation demand distribution; Performing flow field simulation optimization analysis according to the contact surface heat dissipation demand distribution to locate the fin density distribution of the heat dissipation surface; Performing collaborative layout analysis according to the contact surface heat dissipation demand distribution and the fin density distribution of the heat dissipation surface, and outputting the welding area distribution; Dividing the welding area distribution based on the consistency of heat dissipation requirements to obtain multiple local welding areas, and performing welding groove structure parameter matching according to the heat dissipation requirements of the multiple local welding areas to output the welding groove distribution; Fusing the welding groove distribution and the fin density distribution of the heat dissipation surface into the contact surface structure to obtain a void ratio optimization model; Performing mold opening and mass production of the copper heat dissipation bottom plate according to the void ratio optimization model.

2. The structural optimization method for the void ratio of the IGBT copper heat dissipation bottom plate contact surface according to claim 1, characterized in that, Extracting the power distribution characteristics of the chip application scenario to perform electrothermal coupling simulation on the chip simulation model, and outputting the contact surface heat dissipation demand distribution, the method includes: Extracting typical operating condition electrical parameters and cooling condition parameters according to the chip application scenario; Performing spatio-temporal distribution modeling based on the typical operating condition electrical parameters to obtain a power density distribution matrix, and using the power density distribution matrix as the power distribution characteristic; After performing hierarchical loading of material property parameters on the chip simulation model, applying thermal boundary conditions to the chip simulation model based on the cooling condition parameters, and applying electrothermal coupling boundary conditions to the chip simulation model based on the power density distribution matrix to solve and output the contact surface heat flux density distribution and the contact surface temperature field; Calculating the local thermal resistance distribution according to the contact surface heat flux density distribution and the contact surface temperature field; Dividing the heat dissipation demand levels based on the local thermal resistance distribution and multiple heat flux density thresholds, and outputting the contact surface heat dissipation demand distribution.

3. The structural optimization method for the void ratio of the IGBT copper heat dissipation bottom plate contact surface according to claim 2, characterized in that, Performing spatio-temporal distribution modeling based on the typical operating condition electrical parameters to obtain a power density distribution matrix, the method includes: Calculating a dynamic power loss spectrum based on the typical operating condition electrical parameters, where the dynamic power loss spectrum includes the spatio-temporal distribution of conduction loss, switching loss, and reverse recovery loss; Discretizing the dynamic power loss spectrum into the power density distribution matrix.

4. The structural optimization method for the void ratio of the IGBT copper heat dissipation bottom plate contact surface according to claim 2, characterized in that Performing flow field simulation optimization analysis according to the contact surface heat dissipation demand distribution to locate the fin density distribution of the heat dissipation surface, the method includes: Decomposing the contact surface heat dissipation demand distribution based on the demand level to obtain a first heat dissipation demand area distribution, a second heat dissipation demand area distribution to a Kth heat dissipation demand area distribution; Locally calling the fin densities of H samples with H-level heat dissipation requirements, where H is a positive integer greater than K; By adopting the first heat dissipation demand area distribution, the second heat dissipation demand area distribution to the Kth heat dissipation demand area distribution to traverse the H-level heat dissipation demand, the initial pin fin density demand is extracted from the H sample pin fin densities, where the initial pin fin density demand includes the first pin fin density demand, the second pin fin density demand to the Kth pin fin density demand; According to the initial pin fin density demand and the contact surface heat dissipation demand distribution, after loading the pin fin model in the contact surface simulation layer of the chip simulation model, the flow field simulation is run in combination with the cooling condition parameters and the power density distribution matrix, and the heat dissipation efficiency distribution and the fluid resistance distribution are output; Based on the heat dissipation efficiency distribution and the fluid resistance distribution, iterative optimization of the pin fin layout is carried out, and the pin fin density distribution of the heat dissipation surface is output.

5. The structural optimization method for the void ratio of the IGBT copper heat dissipation bottom plate contact surface according to claim 4, characterized in that, Based on the heat dissipation efficiency distribution and the fluid resistance distribution, iterative optimization of the pin fin layout is carried out, and the pin fin density distribution of the heat dissipation surface is output. The method includes: Locally call the heat dissipation efficiency threshold and the fluid resistance threshold; Use the heat dissipation efficiency threshold and the fluid resistance threshold to traverse the superimposed heat dissipation efficiency distribution and fluid resistance distribution, and locate the initial efficiency-resistance deviation distribution; According to the deviation scale identification of the initial efficiency-resistance deviation distribution, perform pin fin density matching update, and output the first optimized density demand; According to the initial pin fin density demand, the first optimized density demand and the contact surface heat dissipation demand distribution, after loading the pin fin model in the contact surface simulation layer of the chip simulation model, the flow field simulation is run in combination with the cooling condition parameters and the power density distribution matrix, and the first optimized efficiency distribution and the first optimized resistance distribution are output; Use the heat dissipation efficiency threshold and the fluid resistance threshold to traverse the superimposed first optimized efficiency distribution and first optimized resistance distribution, and locate the first optimized deviation distribution; According to the deviation scale identification of the first optimized deviation distribution, perform pin fin density matching update, and output the second optimized density demand; And so on, perform iterative optimization of the pin fin layout until the pin fin density distribution of the heat dissipation surface is output.

6. The structural optimization method for the void ratio of the IGBT copper heat dissipation bottom plate contact surface according to claim 1, characterized in that According to the contact surface heat dissipation demand distribution and the pin fin density distribution of the heat dissipation surface, a collaborative layout analysis is carried out, and the welding area distribution is output. The method includes: Preset the welding heat flux density threshold, and use the welding heat flux density threshold to traverse the contact surface heat dissipation demand distribution to locate the first non-weldable area distribution; Preset the pin fin spacing threshold, and use the pin fin spacing threshold to traverse the pin fin density distribution of the heat dissipation surface to locate the second non-weldable area distribution; According to the first non-weldable area distribution and the first non-weldable area distribution, reverse-locate the welding area distribution.

7. The structural optimization method for the void ratio of the IGBT copper heat dissipation bottom plate contact surface according to claim 1, wherein Based on the heat dissipation demand consistency, divide the welding area distribution to obtain multiple local welding areas. According to the multiple area heat dissipation demands of the multiple local welding areas, perform welding groove structure parameter matching, and output the welding groove distribution. The method includes: Extract the geometric contours of the multiple local welding areas to obtain multiple welding geometries; According to the multiple welding geometries and the multiple area heat dissipation demands, perform welding groove matching in the welding groove structure parameter library to obtain multiple initial welding grooves; Perform smoothing processing on the connection nodes of the multiple initial welding grooves to obtain the distribution of the welding grooves.

8. The structural optimization method for the void ratio of the IGBT copper heat dissipation bottom plate contact surface according to claim 1, wherein, According to the packaging structure of the IGBT chip, perform model network calls to obtain a chip simulation model. The method includes: Extract characteristic parameters from the packaging structure to obtain packaging structure parameters. Among them, the packaging structure parameters include a geometric feature set, a material property set, and a process feature set. Convert the packaging structure parameters into a structured feature vector using hierarchical JSON. Pre-store a parameterized model library in the cloud, where the parameterized model library stores multiple sample feature vectors of multiple sample candidate models. After loading the structured feature vector into the parameterized model library, perform model retrieval in the parameterized model library using a feature vector similarity algorithm to determine the chip simulation model.

9. The structural optimization method for the void ratio of the IGBT copper heat dissipation bottom plate contact surface according to claim 8, characterized in that Perform model retrieval in the parameterized model library using a feature vector similarity algorithm to determine the chip simulation model. The method includes: Perform model retrieval in the parameterized model library using a feature vector similarity algorithm to determine N candidate models. Evaluate the scene type matching degree between the chip application scenario and the N historical application scenarios of the N candidate models to screen and output an initial simulation model from the N candidate models. Perform local parameter calibration on the initial simulation model based on the packaging structure parameters to obtain the chip simulation model.

10. The structural optimization system for the void ratio of the IGBT copper heat dissipation bottom plate contact surface, characterized in that, For implementing the structural optimization method for the void ratio of the IGBT copper heat dissipation bottom plate contact surface described in any one of claims 1-9, the system includes: A first call module for performing model network calls according to the packaging structure of the IGBT chip to obtain a chip simulation model. A second call module for performing local order calls according to the chip unique identifier to determine the chip application scenario. A simulation module for extracting the power distribution characteristics of the chip application scenario to perform electrothermal coupling simulation on the chip simulation model and output the contact surface heat dissipation demand distribution. An optimization analysis module for performing flow field simulation optimization analysis according to the contact surface heat dissipation demand distribution to locate the pin fin density distribution of the heat dissipation surface. A collaborative analysis module for performing collaborative layout analysis according to the contact surface heat dissipation demand distribution and the pin fin density distribution of the heat dissipation surface and outputting the welding area distribution. A parameter matching module for dividing the welding area distribution based on the consistency of heat dissipation requirements to obtain multiple local welding areas, performing welding groove structure parameter matching according to the multiple area heat dissipation requirements of the multiple local welding areas, and outputting the welding groove distribution. A fusion module for fusing the welding groove distribution and the pin fin density distribution of the heat dissipation surface into the contact surface structure to obtain a void ratio optimization model. A production module for performing mold opening and batch production of the copper heat dissipation bottom plate according to the void ratio optimization model.

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