A Routing Optimization Placement Method for FPGAs Based on Maximum Independent Sets

Abstract

This invention discloses a layout optimization method for FPGA routing based on the maximum independent set, comprising the following steps: S1, defining the detailed layout optimization object in FPGA architecture definition; S2, efficiently parsing the occupancy of valid layout logic units; S3, solving for the maximum independent set in the FPGA netlist; S4, selecting the optimization object to be moved and candidate positions; S5, determining the line length evaluation algorithm; S6, designing the movement cost for routing optimization; S7, globally optimizing the layout using the maximum independent set; S8, directional optimization of the layout; S9, outputting the detailed layout results. The advantages of this invention compared to existing technologies are: the algorithm finds the global maximum independent set to construct the optimization object, finds a suitable target position for the optimization object to move, and avoids getting trapped in local optima for line length optimization. The algorithm proposed in this invention can significantly optimize the overall line length required in the routing stage without disturbing the global validity and timing of the FPGA circuit netlist, and also reduces the congestion density of the global circuit netlist.

Description

Technical Field

[0001] This invention relates to the field of electronic design automation technology, specifically to a routing optimization layout method for FPGAs based on the maximum independent set. Background Technology

[0002] With the rapid growth in the overall scale and integration of FPGA devices, the number of internal interconnects has exploded. Routing has gradually become the most time-consuming step in the entire FPGA EDA process, occupying a large part of the design cycle. The traditional placement and routing process usually includes three stages: global placement, detailed placement, and routing. The main goal of the global placement stage is to determine the approximate location of each logic cell and optimize timing and congestion metrics as much as possible. Global placement algorithms typically use methods such as simulated annealing and quadratic programming to find a better cell placement scheme globally. Currently, research on global placement has achieved certain results. For example, machine learning-based global placement methods can effectively improve placement quality and efficiency. The detailed placement stage further adjusts and optimizes the cell positions based on the global placement to meet various constraints, such as timing constraints and congestion constraints. Detailed placement algorithms typically use greedy algorithms and force-directed algorithms to find an optimal cell placement scheme locally. Currently, research on detailed placement mainly focuses on how to better handle various constraints and how to improve the robustness of the placement.

[0003] Based on observational experience, even when the optimization goal has been achieved in the global placement stage, and cell placement and legalization processing (i.e., eliminating cell overlap and satisfying various placement constraints) have been completed, there may still be room for further optimization of routing resources. Without significantly disturbing the timing performance and cell density distribution of the global placement, the routing topology can be further optimized by fine-tuning and moving the cell positions within a small range, reducing routing length and congestion, thereby improving routing success rate and timing performance. This local optimization method can further explore routing potential while maintaining the advantages of global placement, shortening the FPGA design cycle and improving design efficiency. This invention proposes a novel detailed placement method for routing optimization based on the maximum independent set search algorithm. Without disturbing the existing global placement and signal timing, it searches for the global maximum independent set and modules with low congestion density using the FPGA netlist and timing file after legalization placement, and moves the cells accordingly, ultimately optimizing the routing and congestion resources of the FPGA during the routing stage. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a routing optimization layout method for FPGA based on the maximum independent set, addressing the shortcomings mentioned in the background art.

[0005] To solve the above-mentioned technical problems, the technical solution provided by the present invention is: a layout optimization method for FPGA routing based on the maximum independent set, which includes the following steps:

[0006] S1, FPGA architecture definition, detailed layout optimization objects;

[0007] S2. Efficiently analyze the occupancy of legalized layout logic units;

[0008] S3. Find the maximum independent set of the FPGA netlist;

[0009] S4. Select the object to be moved and the candidate positions;

[0010] S5. Determine the line length evaluation algorithm;

[0011] S6. Design the movement cost for cabling optimization;

[0012] S7. Optimize the global layout using the largest independent set;

[0013] S8, Targeted Optimized Layout;

[0014] S9. Output detailed layout results.

[0015] Furthermore, in step S1, the FPGA architecture model includes: programmable logic units (CLBs), programmable interconnect resources (such as global interconnect resource switch boxes SB and regional interconnect resource switch boxes CB), input / output units (IO), and built-in IP resources (such as DSP modules and memory blocks).

[0016] The core unit of an FPGA is the programmable logic unit (CLB), which consists of lookup tables (LUTs), flip-flops (DFFs), and multiplexers.

[0017] A CLB contains 8 LUTs and 16 DFFs. Connected LUTs and DFFs within the same CLB constitute a BLE unit. If the location of a CLB in the FPGA architecture is defined as (x0, y0), then the coordinates of the LUTs within it are (x0, y0, z). i The position coordinates of DFF are (x0, y0, z). j ).

[0018] Furthermore, in step S2, the occupancy status of the same CLB needs to be initialized, and the position coordinates z of each movable unit LUT (DFF) are defined during the initialization. i (z jMapping to state 00 (state 0). In addition, in order to parse another part of the fixed LUT and DFF units in the netlist and efficiently perform subsequent algorithm steps, this step divides the 01 and 11 states into fixed and non-fixed types. The same applies to DFF.

[0019] Update the overall CLB occupancy status by iterating through all cells in the netlist. At this point, the position z of each LUT(DFF) is... i (z j The state transitions from state 00 (state 0). When the traversed cell is a fixed cell, it will transition to the fixed state 01 (state 1). The netlist LUT6X construction will directly transition to the fixed state 11. The fixed LUT6 will transition to the fixed state 01, and so on. For non-fixed LUTs, it will first transition to state 01. If the same coordinates are encountered in subsequent traversals, it will transition to state 11. The same applies to DFF.

[0020] Furthermore, in step S3, the netlist is mapped to a hypergraph, and a greedy algorithm is used based on the netlist size to find the largest independent set in the circuit netlist. In the detailed layout, the clock line net is not included in the scope of optimization.

[0021] First, iterate through all movable cells v in the circuit netlist G and assign a state value State[v] to each cell v.

[0022] Initially, all superpoints are in false state. Then, all v in the circuit netlist G are traversed. If the state of the currently visited superpoint v is false, the state of the currently visited cell v is set to true and it is added to the maximum independent set S.

[0023] Next, iterate through all the superpoints u contained in all the adjacent superedges of superpoint v, and set the state of these points to true if they are false.

[0024] Repeat this operation until all hypervertices in the hypergraph G are no longer false. At this point, output the maximum independent set S, which is an approximate maximum independent set of the hypergraph found by the algorithm.

[0025] Furthermore, in step S4, after finding the largest independent set of the global netlist, the LUT or DFF in the independent set is taken as one of the optimization objects, and the BEL cell composed of them under the same CLB coordinate position is taken as the complete optimization object. For the moving position, according to the properties of the largest independent set, the CLB position that has a connection relationship with the LUT or DFF in the current independent set and is different from the CLB position is selected as the candidate position.

[0026] The selection of candidate locations for movement can also be achieved by choosing CLB locations that are not connected to the optimization object in a certain way, thereby increasing the solution space for optimization.

[0027] Furthermore, in step S5, the line length evaluation model includes the Manhattan distance model and the Steiner tree model. The Steiner tree model can be solved using the open-source FLUTE library. The basic idea of ​​line length evaluation is to compare the optimization effect of the weighted average of critical and non-critical line lengths before and after the move. If the difference before and after is greater than 0, it is considered a positive optimization.

[0028] For critical line length evaluation in the netlist, the Manhattan distance model is used. The optimization object is the movable unit in CLB. Therefore, for the optimization object, the overall fan-in and fan-out line length evaluation needs to be considered. Since the fan-out of unit A, for example, port O0, to the fan-in of unit B, for example, port I0, can be equivalent to the fan-in of unit B, port I0, to the fan-out of unit AO0, the critical line length evaluation of the optimization object to be moved can be equivalent to the Manhattan distance from the object to be moved to the unit with the critical line length connection relationship. Taking BEL as the object to be moved, the Manhattan distance between the units with the connection relationship with BEL before and after the move is calculated in turn. The difference in distance before and after the move reflects the critical line length optimization effect.

[0029] For non-critical line lengths in a netlist, the Steiner tree model is generally used for evaluation. The FLUTE library provides an interface for calculating the Steiner tree model of a net. For the optimization object BEL to be moved in the CLB, in addition to calculating the Steiner tree lengths of the non-critical lines of the fan-out nets of the entire BEL object, it is also necessary to calculate the Steiner tree lengths of the non-critical lines of the driving units of the fan-in nets. The two parts are weighted, and the difference before and after the move is calculated to obtain the degree of line length optimization effect before and after the move.

[0030] This algorithm sets a threshold for the number of nets based on the netlist situation. If the number of units connected to a net exceeds this threshold, the Manhattan line length model is used to approximate the Steiner tree model.

[0031] Furthermore, in step S6, the cost of moving to the candidate position needs to consider the legality of moving to the CLB position and the change in congestion density. First, it is considered whether the LUT or DFF after the move meets the net number constraint in the CLB of the candidate position, as well as the constraint on the clock and control signal nets. In addition, the clock number in the clock region is updated at the same time. If it exceeds the clock number, it is also invalid. If the legality check is not met, the cost of positive infinity is returned directly.

[0032] Next, after satisfying the legality checks related to the net, it checks whether the pin density in the candidate positions exceeds the set threshold. This threshold can be selected as the lower limit of the pin density of a certain proportion of CLBs. According to mathematical relationships, if the pin density of the CLBs in each moved candidate position does not exceed the threshold density, the average pin density of the optimized selection proportion of CLBs will be lower than or equal to the threshold. Similarly, if the pin density of the CLBs in the moved candidate positions exceeds the threshold density, positive infinity cost is returned.

[0033] If the length is less than or equal to the pin density threshold, the critical line length and non-critical line length after the move can be calculated. The two line lengths are weighted to form the overall line length, and then the difference between the two is calculated and the length before the move. The difference is returned as the final optimization cost. If the difference is less than 0 and smaller, the cost is smaller, indicating that more line lengths are optimized, and vice versa.

[0034] Finally, when selecting a move location, priority is given to the candidate locations with a difference of less than 0 and the lowest cost, and then the corresponding resource changes are updated.

[0035] Furthermore, in step S7, the movable cells of the largest independent set found in the netlist in each iteration are traversed, and the optimization object BEL is constructed using it, that is, the combination of LUT and DFF that have a connection relationship at the location of the independent point in the CLB.

[0036] Using CLBs (Cellular Blocks) connected by independent points at different locations as candidate locations for movement, in order to optimize the movement of most movable units in each net, an iteration number is set according to the actual size of each netlist. When all movable units in the current largest independent set have been traversed, we mark each unit of the largest independent set as visited. According to step S3, we search for the unvisited largest independent set in the netlist from the unmarked movable units, and repeat steps S4, S5, and S6 until the iteration number is reached.

[0037] Furthermore, in step S8, after the maximum independent set optimization reaches a certain number of iterations, the CLB object with a low pin density in the netlist is found. Since there are relatively few interconnecting nets between the moving units in this part of the CLB, the position of the moving units in this part of the CLB can be optimized by moving or merging, thereby further reducing the wiring length.

[0038] Similar to S7, find the movable units in the CLB with pin density below a certain threshold, construct optimization objects and find corresponding candidate positions. Find the candidate position with the smallest cost less than 0 and perform the move operation, update the resource status, and repeat the above steps until the set number of iterations is reached.

[0039] Furthermore, in step S9, the optimized circuit netlist is output, completing the final detailed layout.

[0040] By employing the above method, this invention has the following advantages: The algorithm constructs the optimization object by equivalently representing the circuit netlist as a hypergraph, finding the global maximum independent set, and then finding a suitable target position for the optimization object, thus avoiding getting trapped in local optima for line length optimization. The algorithm proposed in this invention can significantly optimize the overall line length required during the routing stage without disturbing the global validity and timing of the FPGA circuit netlist. Specifically, it can significantly optimize the critical line lengths and reduce the congestion density of the global circuit netlist. Attached Figure Description

[0041] Figure 1 This is an invention flowchart of an FPGA routing optimization placement method based on the maximum independent set applied to FPGA detailed placement;

[0042] Figure 2 This diagram illustrates an FPGA routing optimization layout method based on the maximum independent set applied to efficiently analyze the occupancy of FPGA logic cells.

[0043] Figure 3 This is a schematic diagram illustrating the application of a maximum independent set-based FPGA routing optimization placement method to the selection of optimization objects and candidate locations in FPGA detailed placement.

[0044] Figure 4 This is a schematic diagram illustrating the application of a FPGA-based routing optimization placement method based on the maximum independent set to the detailed placement movement cost design of an FPGA.

[0045] Figure 5 This is a flowchart illustrating the application of a maximum independent set-based FPGA routing optimization layout method to the global and directional optimization layout of FPGA netlists. Detailed Implementation

[0046] This invention proposes a detailed placement method driven by routing optimization in the FPGA placement stage. It aims to optimize the overall routing length of logic cells and the entire system, without disrupting the legalized placement, while considering metrics such as critical line length and congestion density. Specifically, the method first efficiently parses existing FPGA constraints and netlist files, constructs a maximum independent set based on the legalized netlist, and defines the objects to be moved and their candidate regions, thus establishing a placement optimization problem oriented towards routing optimization. Then, a targeted search is performed on the optimization problem, and finally, further optimization is performed on logic cell regions with low congestion density to complete the detailed placement optimization.

[0047] The present invention will now be described in further detail with reference to the accompanying drawings.

[0048] Combined with appendix Figure 1-5 Specifically, the steps are as follows:

[0049] S1. Define detailed layout optimization objects

[0050] Before developing an optimization model, some necessary definitions and explanations are required. An FPGA architecture typically consists of the following main components: programmable logic units (CLBs), programmable interconnect resources (such as global interconnect resource boxes (SBs) and regional interconnect resource boxes (CBs), input / output units (IOs), and built-in IP resources (such as DSP modules and memory blocks). The core unit of an FPGA is the programmable logic unit (CLB), which typically consists of lookup tables (LUTs), flip-flops (DFFs), and multiplexers.

[0051] A CLB contains 8 LUT6s (capable of accommodating complex lookup table permutations with a total input of no more than 6 and an output of no more than 2) and 16 DFFs. Connected LUTs and DFFs within the same CLB constitute a BLE unit. If the location of a CLB in the FPGA architecture is defined as (x0, y0), then the coordinates of the LUTs within it are (x0, y0, z). i The position coordinates of DFF are (x0, y0, z). j Where i = 0, 1, ..., 7, j = 0, 1, ..., 15.

[0052] After the FPGA completes the legal placement, it outputs a circuit netlist containing the location of each cell and their interconnections, including a label indicating whether each cell is movable. Most movable LUTs and DFF cells are used for model optimization.

[0053] S2. Efficiently analyze the occupancy of legalized layout logic units.

[0054] The occupancy status of the same CLB needs to be initialized, and the initialization defines the position coordinates z of each movable unit LUT (DFF). i (z j The mapping is done to the 00 state (0 state). For a LUT, 00 represents an empty position, 01 represents that there is only one LUT at that position, and 11 represents that there are two LUTs with the same coordinates at that position, forming LUT6. Furthermore, to efficiently resolve the other fixed LUTs and DFFs in the netlist and perform subsequent algorithm steps, this step categorizes the 01 and 11 states as fixed and non-fixed types. The same applies to DFFs.

[0055] To update the overall CLB occupancy, it is necessary to traverse all cells in the netlist. At this point, the position z of each LUT(DFF) is... i (z j The state transitions from state 00 (state 0). If the traversed cell is a fixed cell, it will transition to the fixed state 01 (state 1). Since there are many LUT6X elements in the netlist, considering their construction, this invention directly transitions them to the fixed state 11. For some fixed LUT6 elements, they transition to the fixed state 01, and so on. For non-fixed LUTs, they first transition to state 01, and if the same coordinates are encountered subsequently, they transition to state 11. The same applies to DFFs.

[0056] S3. Solving for the maximum independent set of the FPGA netlist

[0057] In FPGAs, logic resources such as DFFs, CARRYs, and LUTs can be considered as superpoints in the graph, while connections between devices, such as signal lines, can be considered as hyperedges. The netlist file details the connections between various components in the circuit. When performing operations such as moving points, the complexity of these connections can lead to negative optimization. To find devices with simpler connections, i.e., those with relatively low movement costs, we map the netlist to a hypergraph and use a greedy algorithm based on the netlist size to find the largest independent set in the circuit netlist. In detailed placement, clock line nets are not included in the optimization scope.

[0058] First, iterate through all movable cells v in the circuit netlist G, assigning each cell v a state value State[v]. Initially, all hypervertices are false. Then, iterate through all v in the circuit netlist G. If the state of the currently visited hypervertices v is false, set the state of the currently visited cell v to true and add it to the maximum independent set S. Next, iterate through all hypervertices u contained in all adjacent hyperedges of hypervertices v. If the state of these u is false, set it to true. Repeat this operation until the state of all hypervertices in the hypergraph G is no longer false. At this point, output the maximum independent set S, which is an approximate maximum independent set of the hypergraph found by the algorithm. The specific algorithm implementation based on the greedy strategy for the circuit netlist is as follows:

[0059]

[0060]

[0061] S4. Select the target to be moved and candidate locations.

[0062] After finding the largest independent set in the global netlist, the LUTs or DFFs within the independent set are selected as optimization targets. The BEL cells formed by these independent sets at the same CLB coordinate position are then identified as the complete optimization targets. For the move location, based on the properties of the largest independent set, we select CLB positions that are connected to the LUTs or DFFs in the current independent set but have different CLB positions as candidate locations. Since this part is independent, it is suitable to use multi-threading to calculate the move cost later.

[0063] Furthermore, the selection of candidate locations for movement can be achieved by choosing CLB locations that are not connected to the target object in the vicinity, thereby increasing the solution space. Considering computational cost, the algorithm selects a subset of CLB locations within the coordinate range of the BEL and multiple candidate locations that are not connected to the target object as new candidate locations, increasing the likelihood of finding the shortest path from the moved object to each connected unit.

[0064] S5. Determine the line length evaluation algorithm

[0065] The line length evaluation model includes the Manhattan distance model and the Steiner tree model, where the Steiner tree model can be solved using the open-source FLUTE library. The basic idea of ​​line length evaluation is to compare the weighted optimization effect of critical and non-critical line lengths before and after the move; if the difference is greater than 0, it is considered positive optimization. For critical line length evaluation in the netlist, the Manhattan distance model is used, and the optimization object is the movable unit in the CLB. Therefore, for the optimization object, the overall fan-in and fan-out line length evaluation needs to be considered. Since the fan-out of unit A (e.g., port O0) to the fan-in of unit B (e.g., port I0) can be equivalent to the fan-in of unit B (I0 port I0) to unit AO0 port, the critical line length evaluation of the optimization object to be moved can be equivalent to the Manhattan distance from the object to be moved to the unit with a critical line length connection. Taking BEL as the object to be moved, the Manhattan distance between the units connected to BEL before and after the move is calculated sequentially. The difference in distance before and after the move reflects the critical line length optimization effect.

[0066] RSMT is a routing method similar to minimum spanning tree (MST). Compared to MST, RSMT allows adding extra points outside a given point to minimize the sum of edge weights in the tree. For non-critical wire lengths in a netlist, a Steiner tree model is generally used for evaluation. The FLUTE library provides an interface for calculating the Steiner tree model of a net. For the optimization object BEL to be moved in a CLB, in addition to calculating the Steiner tree lengths of the non-critical wires of the fan-out nets of the entire BEL object, it is also necessary to calculate the Steiner tree lengths of the non-critical wires of the driving units of the fan-in nets. The two parts are weighted, and the difference before and after the move is calculated to obtain the degree of optimization effect on the wire lengths.

[0067] While RSMT most closely approximates actual routing performance and evaluates non-critical wire lengths, it is not efficient for FLUTE libraries with very large fanouts, requiring more time. In the actual algorithm design, this algorithm sets a threshold for the number of nets based on the netlist. If the number of cells connected to a net exceeds this threshold, the Manhattan wire length model is used to approximate the Steiner tree model.

[0068] S6. Designing the movement cost for routing optimization

[0069] The cost of moving to a candidate location needs to consider the legitimacy of the move to that CLB location, as well as changes in congestion density. We first consider whether the moved LUT or DFF satisfies the net count constraint in the corresponding CLB of the candidate location, and the constraints regarding clock and control signal nets, such as only one CLOCK signal net per bank. Additionally, we update the clock count in the clock region simultaneously; exceeding this limit is also invalid. If this legitimacy check is not met, we directly return a cost of positive infinity.

[0070] Next, after satisfying the legality checks related to the wireframe, we need to check whether the pin density in the candidate positions exceeds a set threshold. This threshold can be selected as the lower limit of the pin density of a certain proportion of CLBs. Mathematically, if the pin density of the CLBs at each moved candidate position does not exceed this threshold, the average pin density of the optimized selection proportion of CLBs will be lower than or equal to this threshold. Similarly, if the pin density of the CLBs at the moved candidate position exceeds the threshold, positive infinity is returned. If it is lower than or equal to the pin density threshold, the critical and non-critical wire lengths after the move can be calculated. These two lengths are weighted to obtain the overall wire length, and the difference between this and the length before the move is calculated. This difference is returned as the final optimized cost. If the difference is less than 0 and smaller, the cost is smaller, indicating more optimized wire lengths, and vice versa. Finally, in selecting the move positions, we prioritize moving the candidate positions with a difference less than 0 and the lowest cost, and then update the corresponding resource changes.

[0071] S7. Global layout optimization using the maximum independent set.

[0072] In each iteration, we iterate through the movable cells of the largest independent set found in the netlist and construct optimization objects (BELs) using them. These BELs are combinations of LUTs and DFFs that are connected to the independent point at its CLB position. We use the CLBs connected to the independent point at different positions as candidate locations for movement. To optimize the movement of most movable cells in each netlist, we set a number of iterations based on the actual size of each netlist. When all movable cells in the current largest independent set have been traversed, we mark each cell in that largest independent set as visited. Following step S3, we search for unvisited largest independent sets in the netlist from the unmarked movable cells, repeating steps S4, S5, and S6 until the number of iterations is reached.

[0073] S8. Targeted Optimization Layout

[0074] After the maximum independent set optimization reaches a certain number of iterations, we look for CLB objects with low pin density in the netlist. Since these CLBs have relatively few interconnecting nets for movable units, we can optimize the positions of movable units in these CLBs by moving or merging them, further reducing wiring length. Consistent with S7, we construct optimization objects and find corresponding candidate positions for these movable units in CLBs with pin density below a certain threshold. We then find the candidate position with the lowest cost (less than 0) and perform a move operation, updating the resource situation. We repeat the above steps until the set number of iterations is reached.

[0075] S9. Output detailed layout results

[0076] Output the optimized circuit netlist to complete the final detailed layout.

[0077] In specific implementation, the present invention is further illustrated below with reference to implementation examples. In this implementation example, we select 11 publicly available real netlists and implement the detailed layout algorithm involved in the present invention.

[0078] S1. Define detailed layout optimization objects

[0079] The FPGA architecture model involved in this example consists of diverse logic resources, including programmable logic blocks (CLBs), block random access memory (BRAM), digital signal processors (DSPs), input / output (I / O) interfaces, and complex IP modules. These resources are arranged in columns within the FPGA chip, forming an array structure. The CLB, as the basic logic unit, can implement basic combinational logic, lookup tables, and sequential logic functions, and provides a dedicated fast carry logic chain for performing efficient arithmetic addition and subtraction operations. RAM and DSP resources have the same width as CLBs, but occupy multiple CLB units in height. Multiple CLBs and dedicated logic units share a clock region. Each clock region can hold a certain number of clock signals, typically limited to 28 clock signals.

[0080] Each CLB contains two independent banks, and each bank contains four 6-input 2-output lookup tables (LUTs), eight flip-flops (DFFs), and a fast carry chain. The LUTs in the CLB are numbered 0-7 from bottom to top, and the DFFs are numbered 0-15 from bottom to top. Because the lookup tables are designed with two outputs, they can accommodate various complex lookup table permutations with a total input of no more than 6 and a total output of no more than 2. If the position of a CLB in the FPGA architecture is defined as (x0, y0), then the position coordinates of the LUTs within it are (x0, y0, z). i The position coordinates of DFF are (x0, y0, z). j Where i = 0, 1, ..., 7, j = 0, 1, ..., 15.

[0081] The 11 publicly available netlists contain information on various logical resource units, their locations, and interconnections, including whether each unit is movable. The number of LUTs and DFFs in the 11 publicly available real-world netlists ranges from 50,000 to 200,000 and from 50,000 to 300,000, respectively. The majority of movable LUTs and DFFs will be the focus of the model's optimization.

[0082] S2. Efficiently analyze the occupancy of legalized layout logic units.

[0083] First, initialize the position coordinates z of each movable unit LUT (DFF) in the CLB. i (z j Map to 00 state (0 state). Traverse all cells in the netlist, and assign the position z of each LUT (DFF) to... i (z jThe state transitions from state 00 (state 0). If the traversed cell is a fixed cell, it will transition to the fixed state 01 (state 1). Since there are a large number of LUT6X in the 11 public netlists, considering their structure, this invention directly transitions them to the fixed state 11. For the DRAM in this embodiment, considering its structure consists of 4 LUTs, the 4 LUTs of the corresponding BANK are converted from the initial state 00 to the fixed state 01. For some fixed LUT6, they are transitioned to the fixed state 01, and so on. For non-fixed LUTs, they are first transitioned to the non-fixed state 01, and if the same coordinates are encountered subsequently, they will transition to state 11. The same applies to DFF.

[0084] S3. Solving for the maximum independent set of the FPGA netlist

[0085] In this implementation example, logic resources such as DFFs and LUTs can be considered as hypervertices in the graph, while the connections between logic resources are considered as hyperedges, thus constructing a hypergraph model. A greedy algorithm is used based on the netlist size to find the largest independent set in the circuit netlist. Clock lines and fixed logic resources are not included in the optimization scope.

[0086] First, iterate through all movable cells v in the circuit netlist G, assigning each cell v a state value, initially false. Next, iterate through all v in the circuit netlist G; if the state of the currently visited superpoint v is false, set the state of the currently visited cell v to true and add it to the maximum independent set S. Finally, sequentially check the states of other superpoints u in all adjacent superedges of superpoint v; if the states of these points are false, set them to true. Repeat this operation until the states of all superpoints in the hypergraph G are no longer false, at which point the maximum independent set S is output.

[0087] S4. Select the target to be moved and candidate locations.

[0088] Find the BEL element composed of independent LUTs or DFFs at the same CLB coordinate position as the optimization object.

[0089] For candidate positions, first select CLB positions that are connected to the LUT or DFF in the current independent set but have different CLB positions. Assume the smallest x and y coordinates of the candidate positions are xmin and ymin, and the largest are xmax and ymax. Next, select CLB positions that are adjacent to the optimization object but have no connection to it. Finally, select CLB positions with coordinates (xmin+d, ymin+d) that are not connected to the optimization object as supplementary candidate positions, where xmin... <xmax,ymin<ymax,d<min{(xmax-xmin),(ymax-ymin)}。

[0090] S5. Determine the line length evaluation algorithm

[0091] For critical line length evaluation in the netlist, the Manhattan distance model is used. The optimization object is the movable unit in the CLB. The BEL constructed by the movable unit is taken as the object to be moved. The Manhattan distance between the units connected to the BEL before and after the move is calculated in turn. The difference between the distances before and after the move reflects the optimization effect of the critical line length.

[0092] For the non-critical line lengths of nets in the netlist, the Steiner tree model is used for evaluation, and the Steiner tree model line lengths of the nets are calculated using the FLUTE library. For the optimization object BEL to be moved in the CLB, the Steiner tree line lengths of the non-critical lines of the fan-out nets and the Steiner tree line lengths of the non-critical lines of the driving units of the fan-in nets of the entire BEL object are calculated, and the two parts are weighted.

[0093] This implementation example sets a threshold for the number of nets based on the netlist situation. That is, if the number of cells connected to a net exceeds 50, the Manhattan line length model is used to approximate the Steiner tree model to calculate the non-critical line length.

[0094] Compare the optimization effect of the weighted average of critical and non-critical line lengths before and after the move. If the difference before and after is greater than 0, it is considered a positive optimization.

[0095] S6. Designing the movement cost for routing optimization

[0096] First, consider whether the moved LUT or DFF satisfies the net count constraint in the CLB of the candidate location, as well as the constraints regarding clock and control signal nets. In this implementation example, for the 8 DFFs within the same bank, the clock nets and reset signals must be identical, and the number of ce signals must not exceed 2. Additionally, updating the number of clocks in the clock region simultaneously is also invalid if it exceeds the 28 clock channels of the Clock Region in this implementation example. If invalid, the cost of positive infinity is directly returned.

[0097] After satisfying the CLB-related legitimacy checks, we need to check whether the pin density in the candidate positions exceeds a set threshold. In this implementation example, this threshold is selected as the lowest pin density *s* among the top 5% of pin densities in the overall CLB. If the pin density of the CLB at the candidate position after the move exceeds the threshold density *s*, then positive infinity cost is returned. If it is lower than or equal to the pin density threshold *s*, then the critical and non-critical line lengths after the move are calculated. These two line lengths are weighted in a 4:1 ratio to represent the overall line length, and the difference between this and the original length is calculated as the final optimized cost. Finally, this implementation example selects the candidate position with the smallest cost and a difference less than 0 for the move, and then updates the corresponding resource changes.

[0098] S7. Global layout optimization using the maximum independent set.

[0099] In this implementation example, based on the actual size of 11 netlists, the number of iterations is set. After all the movable cells in the current largest independent set have been traversed, the algorithm marks each cell in the current largest independent set as having been visited. According to step S3, the algorithm continues to search for the unvisited largest independent set in the netlist from the unmarked movable cells, and repeats steps S4, S5, and S6 until the number of iterations is reached.

[0100] S8. Targeted Optimization Layout

[0101] After the maximum independent set optimization reaches a certain number of iterations, this implementation example finds movable cells in the CLB with a pin density lower than 0.9*s in the netlist to construct the optimization object BEL. Consistent with S7, steps S4, S5, and S6 are repeated until the number of iterations is reached.

[0102] S9. Output detailed layout results

[0103] This example test environment was conducted on a server running Ubuntu 20.04.4LTS, with an Intel(R) Xeon(R) Platinum 8368 CPU@2.40GHz and 70GB of memory. The optimized netlist after detailed layout was output, and compared with the netlist before detailed layout. The algorithm test results are shown in the table below:

[0104] Table: Experimental Results on the Public Test Set

[0105]

[0106]

[0107] Under the conditions of legality and no deterioration in pin density, all test results showed high operational efficiency, with an average bus length optimization of 12.61%, of which critical line length was optimized by an average of 19.58% and non-critical line length by 10.40%. Overall, all cases, regardless of critical or non-critical line length, achieved some degree of optimization with high operational efficiency. Specifically, critical line lengths in cases 1, 2, 6, and 10 were optimized by over 20%, but the optimization effect on non-critical line lengths in case 8 was only moderate. Furthermore, pin density was reduced by an average of 1.58% while meeting requirements.

[0108] In summary, based on publicly available test benchmarks, the algorithm proposed in this invention demonstrates certain effectiveness and efficiency in FPGA applications.

[0109] The detailed layout can effectively reduce the cabling resources required in future cabling phases and reduce congestion density to a certain extent.

[0110] The present invention and its embodiments have been described above. This description is not restrictive, and the actual structure is not limited thereto. In conclusion, if those skilled in the art, inspired by this description, design similar structures and embodiments without departing from the spirit of the invention, such designs should fall within the scope of protection of this invention.

Claims

1. A routing optimization placement method for FPGAs based on maximum independent sets, characterized in that: It includes the following steps: S1. FPGA architecture definition, detailed layout optimization objects; S2. Efficiently analyzes the occupancy of legalized layout logic units; S3. Find the maximum independent set of the FPGA netlist; S4. Select the object to be moved and the candidate positions; S5. Determine the line length evaluation algorithm; S6. Design the movement cost for cabling optimization; S7. Optimize the global layout using the largest independent set; S8. Targeted Optimized Layout; S9. Output detailed layout results; In step S1, the FPGA architecture model includes: programmable logic units (CLBs), programmable interconnect resources, input / output units (IOs), and built-in IP resources; The core unit of an FPGA is the programmable logic unit (CLB), which consists of lookup tables (LUTs), flip-flops (DFFs), and multiplexers. A CLB contains 8 LUTs and 16 DFFs. Connected LUTs and DFFs within the same CLB constitute a Basic Logic Unit (BEL). If the location of a CLB in the FPGA architecture is defined as (x0, y0), then the coordinates of the LUTs within it are (x0, y0, z). i The position coordinates of DFF are (x0, y0, z). j ); In step S2, the occupancy status of the same CLB needs to be initialized. The initialization defines the position coordinates z of each LUT as a movable unit. i Mapped to a 00 state, each DFF is initialized and defined as the position coordinate z of a movable unit. j The mapping is to state 0. In addition, in order to parse another part of the fixed LUT and DFF cells in the netlist LUT6X and efficiently perform subsequent algorithm steps, this step divides the 01 and 11 states into fixed and non-fixed types. The same applies to DFF. Update the overall CLB occupancy status by traversing all cells in the LUT6X netlist. At this point, the position z of each LUT is... i The state transitions from state 00, and the position z of each DFF... j The state transitions from state 0. When the traversed cell is a fixed cell, the LUT position will transition to a fixed 0 or 1 state, and the DFF position z... j Then it will be transferred to the fixed state 1. The netlist LUT6X construction will be directly transferred to the fixed state 11. The fixed LUT6 will be transferred to the fixed state 01. The others are similar. For non-fixed LUTs, they will first be transferred to the state 01. If the same coordinates are encountered in subsequent traversals, they will be transferred to the state 11. The same applies to DFF. The fixed type of cell is a fixed cell, and the non-fixed type of cell is a movable cell. In step S3, the netlist is mapped to a hypergraph. A greedy algorithm is used based on the netlist size to find the largest independent set in the circuit netlist. In the detailed layout, the clock line net is not included in the optimization scope. First, iterate through all movable cells v in the circuit netlist and assign a state value State[v] to each cell v. Initially, all movable units v are in the false state. Then, all movable units v in the circuit netlist are traversed. If the state of the currently visited movable unit v is false, the state of the currently visited movable unit v is set to true, and it is added to the maximum independent set S. Next, iterate through all movable units u contained in all adjacent hyperedges of movable unit v, and set the state of these points to true if they are false. Repeat this operation until the state of all movable units in the hypergraph is no longer false. At this point, output the maximum independent set S, which is an approximate maximum independent set of the hypergraph found by the algorithm. In step S4, after finding the largest independent set in the global netlist, the LUT or DFF in the independent set is taken as one of the optimization objects, and the BEL composed of them at the same CLB coordinate position is taken as the complete optimization object. For the moving position, according to the properties of the largest independent set, the CLB position that has a connection relationship with the LUT or DFF in the current independent set and is different from the CLB position is selected as the candidate position. The selection of candidate locations for movement is also carried out in a certain way, choosing CLB locations that have no connection relationship with the optimization object, thereby increasing the solution space of the optimization.

2. The FPGA routing optimization placement method based on maximum independent sets according to claim 1, characterized in that: The programmable interconnect resources include a global interconnect resource switch box SB and a regional interconnect resource switch box CB, and the built-in IP resources include DSP modules and memory blocks.

3. The FPGA routing optimization placement method based on maximum independent sets according to claim 1, characterized in that: In step S5, the line length evaluation model includes the Manhattan distance model and the Steiner tree model. The Steiner tree model is solved using the open-source FLUTE library. The basic idea of ​​line length evaluation is to compare the optimization effect of the weighted average of critical line lengths and non-critical line lengths before and after the move. If the difference before and after is greater than 0, it is considered a positive optimization. For critical line length evaluation in the netlist, the Manhattan distance model is used. The optimization object is the movable unit in CLB. Therefore, for the optimization object, the overall fan-in and fan-out line length evaluation needs to be considered. Since the fan-out O0 port of unit A to the fan-in I0 port of unit B in the critical line length is equivalent to the fan-in I0 port of unit B to the fan-out O0 port of unit A, the critical line length evaluation of the optimization object to be moved is equivalent to the Manhattan distance between the object to be moved and the unit with the critical line length connection relationship. Taking BEL as the object to be moved, the Manhattan distance between the unit with the connection relationship with BEL before and after the move is calculated in turn. The difference in distance before and after the move reflects the critical line length optimization effect. For non-critical line lengths in a netlist, the Steiner tree model is generally used for evaluation. The FLUTE library provides an interface for calculating the Steiner tree model of a net. For the optimization object BEL to be moved in the CLB, in addition to calculating the Steiner tree lengths of the non-critical lines of the fan-out nets of the entire BEL object, it is also necessary to calculate the Steiner tree lengths of the non-critical lines of the driving units of the fan-in nets. The two parts are weighted, and the difference before and after the move is calculated to obtain the degree of line length optimization effect before and after the move. This algorithm sets a threshold for the number of nets based on the netlist situation. If the number of units connected to a net exceeds this threshold, the Manhattan line length model is used to approximate the Steiner tree model.

4. The FPGA routing optimization placement method based on the maximum independent set according to claim 3, characterized in that: In step S6, the cost of moving to the candidate position needs to consider the legality of moving to the CLB position and the change in congestion density. First, it is considered whether the LUT or DFF after the move meets the net number constraint in the CLB of the candidate position, as well as the constraints on clock and control signal nets. In addition, the clock number in the clock region is updated at the same time. If it exceeds the clock number, it is also invalid. If the legality check is not met, the cost of positive infinity is returned directly. Next, after satisfying the legality checks related to the net, it checks whether the pin density in the candidate positions exceeds a set threshold. This threshold is selected as the lower limit of the pin density of a certain proportion of CLBs. According to mathematical relationships, if the pin density of the CLBs in each moved candidate position does not exceed the threshold, the average pin density of the optimized selection proportion of CLBs will be lower than or equal to the threshold. Similarly, if the pin density of the CLBs in the moved candidate positions exceeds the threshold, positive infinity cost is returned. If the value is lower than or equal to the pin density threshold, calculate the critical line length and non-critical line length after the move, weight the two line lengths as the overall line length, and then calculate the difference with the value before the move. The difference is returned as the final optimization cost. If the difference is less than 0 and smaller, the cost is smaller, indicating that more line lengths are optimized, and vice versa. Finally, when selecting a move location, priority is given to the candidate locations with a difference of less than 0 and the lowest cost, and then the corresponding resource changes are updated.

5. The FPGA routing optimization placement method based on maximum independent sets according to claim 4, characterized in that: In step S7, the movable unit of the largest independent set found in the netlist in each iteration is traversed, and the optimization object BEL is constructed using it, that is, the combination of LUT and DFF that have a connection relationship at the position of the CLB of the BEL. Using CLBs (Cellular Blocks) connected by independent points at different locations as candidate locations for movement, in order to optimize the movement of most movable units in each net, an iteration number is set according to the actual size of each netlist. When all movable units in the current largest independent set have been traversed, we mark each unit of the largest independent set as visited. According to step S3, we search for the unvisited largest independent set in the netlist from the unmarked movable units, and repeat steps S4, S5, and S6 until the iteration number is reached.

6. The FPGA routing optimization placement method based on maximum independent sets according to claim 5, characterized in that: In step S8, after the maximum independent set optimization reaches a certain number of iterations, the CLB objects with low pin density in the netlist are found. Since there are relatively few interconnecting nets between the moving units in this part of the CLB, the positions of the moving units in this part of the CLB are optimized by moving or merging, thereby further reducing the wiring length. Similar to S7, find the movable units in the CLB with pin density below a certain threshold, construct optimization objects and find corresponding candidate positions. Find the candidate position with the smallest cost less than 0 and perform the move operation, update the resource status, and repeat the above steps until the set number of iterations is reached.

7. The FPGA routing optimization placement method based on maximum independent sets according to claim 6, characterized in that: In step S9, the optimized circuit netlist is output, completing the final detailed layout.

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