Carrier synchronization control method of motor controller of distributed FPGA architecture

Abstract

The application provides a carrier wave synchronization control method of a motor controller with a distributed FPGA architecture. The motor controller comprises a master control unit and three sub-control units. The FPGA of each sub-control unit cyclically performs the following operations: receiving communication data sent by the master control unit and extracting to-be-verified control information and to-be-verified synchronization information therefrom; judging whether the to-be-verified synchronization information is valid, and determining the update mode of the carrier generation time, the current synchronization information and the current control information according to the judgment result; and generating the carrier and the PWM control signal of the phase corresponding to the sub-control unit based on the current control information and the carrier clock period of the FPGA of the sub-control unit from the updated carrier generation time. The control method provided by the application can effectively solve the phase carrier synchronization problem of the distributed motor controller under high-frequency switching control.

Description

Technical Field

[0001] This application belongs to the field of motor controller technology, and relates to motor controller carrier synchronization technology. Specifically, it provides a carrier synchronization control method for a motor controller with a distributed FPGA architecture. Background Technology

[0002] Power devices (such as IGBTs and SiC MOSFETs) are core components of motor controllers, and their performance directly affects the system's efficiency, power density, and reliability. In fields such as new energy vehicles and industrial drives, motor controllers require power devices to operate stably under high switching frequencies, high currents, and high temperatures. Therefore, parameters such as the dynamic characteristics, conduction losses, and thermal resistance of these devices are particularly critical. However, there is a significant difference between the current testing standards of power device manufacturers and the actual application needs of motor controller manufacturers: device manufacturers mainly focus on the static parameters of single transistors or modules (such as Vce(sat), Eon / Eoff losses) and reliability verification under standardized operating conditions (such as HTRB and H3TRB); controller manufacturers, on the other hand, pay more attention to the performance of devices in complex application scenarios, such as transient overcurrent capability, the impact of parasitic parameters on EMI, and lifespan degradation under high-temperature cycling. This difference leads to long device selection and system verification cycles, and even the contradiction of "excellent laboratory data, frequent failures in real-world vehicle applications."

[0003] To resolve this contradiction, application-oriented testing (AOT) of power devices has become a key breakthrough. By simulating active loads in automotive scenarios (such as dynamic motor torque changes and stall conditions) using a motor simulator and driving the device under test against a motor controller, the performance of the device in a real controller can be directly verified. This method can shorten the verification path from device design to system integration, accelerate iteration efficiency, and provide data support for device manufacturers to optimize product definitions and for controller manufacturers to improve selection accuracy, ultimately promoting the collaborative optimization of power devices and motor control systems.

[0004] To simultaneously achieve adjustable control frequency, adjustable three-phase drive resistance, adjustable three-phase drive voltage, and real-time acquisition of power module temperature, and to facilitate testing of the performance of power devices under different control and drive conditions, the motor controller used for application testing can adopt a distributed FPGA architecture. One main control unit generates adjustable frequency control signals, and three sub-control units are responsible for the adjustable drive resistance and voltage of each phase and the module temperature acquisition function. This allows for reasonable allocation of resource requirements, reduces the FPGA resource load on the main control board, and improves the testable range of the control frequency.

[0005] However, this distributed FPGA architecture also brings new problems. For example, as the testing time increases, the carrier synchronization problem occurs among the sub-control units, resulting in additional harmonics, increasing the torque fluctuation and heat generation of the equipment, and in severe cases, causing the system to lose control. In addition, during the high-speed communication between the main control unit and each sub-control unit, there is a problem that data transmission is distorted due to various interferences, causing each sub-control unit to control based on incorrect control signals. Summary of the Invention

[0006] This application provides a carrier synchronization control method for a motor controller with a distributed FPGA architecture through embodiments, which is used to solve the problem of three-phase drive carrier asynchrony in the distributed FPGA motor controller. The motor controller includes a main control unit and three sub-control units communicatively connected to the main control unit. Each main control unit and sub-control units are equipped with an FPGA, and the actual crystal oscillator period of each FPGA is independent. Each sub-control unit's FPGA cyclically executes the following steps:

[0007] Receive communication data sent by the main control unit and extract the control information and synchronization information to be verified from it;

[0008] Determine whether the synchronization information to be verified is valid. If it is, update the carrier generation time and the current synchronization information based on the synchronization information to be verified, and update the current control information based on the control information to be verified. If it is not valid, update the carrier generation time based on the carrier clock period of the FPGA of the sub-control unit and the current control information, and update the current synchronization information based on the synchronization information to be verified.

[0009] Based on the updated carrier generation time, the carrier and PWM control signals for the corresponding phase of the sub-control unit are generated according to the current control information and the carrier clock period of the FPGA of the sub-control unit.

[0010] The control method provided in the embodiments of this application first verifies the validity of the information by comparing the synchronization information to be verified in two consecutively received communication data. If the verification result is invalid, each sub-control unit still sets the carrier generation time according to the FPGA's own carrier clock period and the current control information. If the verification result is valid, the time when new communication data is received is used as the carrier generation time, thereby realizing carrier synchronization operation only when the communication data is valid. Second, regardless of whether the verification result is valid or not, the current synchronization information is updated with the latest synchronization information to be verified, so that the verification operation can be performed continuously based on the synchronization information to be verified received in two consecutive times. Finally, if the verification result is valid, the current control information is updated with the newly received control information, so that when valid communication data is received and includes adjustments to parameters such as switching frequency, a PWM modulation signal can be generated in a timely manner based on the updated parameters.

[0011] The synchronization and information validity verification mechanism disclosed in the above embodiments enables carrier synchronization processing of each sub-control unit during high-frequency switching control of the motor controller (such as switching frequency reaching 10kHz or even higher) in each switching cycle. At the same time, the data validity is judged by comparing two consecutive synchronization information, avoiding the problem of large computational load and unreliable speed when using complex validity judgment logic to process high-frequency received synchronization data. Attached Figure Description

[0012] Figure 1 A schematic diagram of the system framework for a motor controller based on a distributed FPGA architecture;

[0013] Figure 2 This is a schematic diagram illustrating the process of determining the carrier wave and modulation wave of each phase in a motor controller based on a distributed FPGA architecture.

[0014] Figure 3 This is a schematic diagram illustrating the principle of carrier generation by the FPGA of the sub-control unit in one embodiment;

[0015] Figure 4 This is a schematic diagram of the FPGA generating a carrier in one embodiment;

[0016] Figure 5 This is a schematic diagram illustrating the principle of the FPGA of the sub-control unit generating PWM signals based on carrier waves and modulation waves in one embodiment;

[0017] Figure 6 In one specific embodiment, the waveform diagram of the current output of each phase of the motor controller of the distributed FPGA architecture is shown.

[0018] Figure 7This is a schematic diagram of the carrier error of each phase when the FPGA of each phase control unit is not synchronized with the carrier.

[0019] Figure 8 A schematic diagram illustrating the principle of high-frequency circulating current caused by carrier asynchrony;

[0020] Figure 9 This is a schematic diagram showing the current situation of each phase control unit's FPGA when carrier synchronization is not performed.

[0021] Figure 10 This is a flowchart of a carrier synchronization control method for a motor controller with a distributed FPGA architecture provided in an embodiment of this application;

[0022] Figure 11 This is a schematic diagram illustrating the transmission of communication data between the main control unit and the sub-control unit in an embodiment of this application.

[0023] Figure 12 This is a timing diagram of the FPGA of the sub-control unit receiving communication data in one embodiment of this application;

[0024] Figure 13 This is a timing diagram of the FPGA of the sub-control unit receiving communication data in another embodiment of this application;

[0025] Figure 14 This is a schematic diagram illustrating how the FPGA of the control unit stores communication data in an embodiment of this application;

[0026] Figure 15 This is a flowchart for determining whether the synchronization information to be verified is valid in one embodiment of this application;

[0027] Figure 16 This is a schematic diagram illustrating how the FPGA of the sub-control unit updates stored data when the synchronization information to be verified is valid.

[0028] Figure 17 This is a schematic diagram illustrating the FPGA updating stored data in the sub-control unit when the synchronization information to be verified is invalid.

[0029] Figure 18 This is a schematic diagram of the waveforms of each phase carrier when the synchronization information to be verified is valid, according to one embodiment of this application.

[0030] Figure 19 This is a schematic diagram of the waveforms of each phase carrier when the synchronization information to be verified is invalid, according to one embodiment of this application.

[0031] Figure 20 This is a schematic diagram of the current output by a motor controller of a distributed FPGA architecture after carrier synchronization using the method provided in this application, in one specific embodiment. Detailed Implementation

[0032] Figure 1 This paper presents a framework for a motor controller employing a distributed FPGA architecture, which can be applied to scenarios such as towing tests of automotive motor controllers. Figure 2 Taking phase U as an example, a schematic diagram of the process for determining the carrier wave and modulation wave of each phase in the motor controller is shown.

[0033] See Figure 1 , Figure 2 The motor controller includes four control units: a main control unit and sub-control units for controlling the U, V, and W phases. Each control unit includes a core control module composed of FPGA (Field Programmable Gate Array) and ARM (Advanced RISC Machine) chips.

[0034] The main control unit is primarily responsible for covering the functions of the automotive controller that need to be tested, generating control parameters such as control frequency, torque, and speed for various operating conditions including low-speed light load, low-speed heavy load, high-speed light load, and high-speed heavy load. The control frequency can cover the performance indicators of current automotive controllers and next-generation automotive controllers (adjustable from 2-20kHz). The ARM of the main control unit is responsible for connecting with the host computer, transmitting the motor speed, torque, switching frequency, and on / off voltage and resistance of each phase power device set by the host computer to the FPGA chip. After receiving these signals, the FPGA chip of the main control unit combines the resolver speed signal, motor NTC temperature signal, bus voltage signal, and three-phase current signal (which requires signal conversion processing to convert the original values ​​into true values) collected by the various peripheral circuits of the main control unit to perform closed-loop calculations, generate the three-phase target duty cycle signal corresponding to the control frequency, and communicate with each sub-control unit at high speed through the SPI transceiver circuit to transmit various control signals to each phase sub-control unit. At the same time, it also reads various status signals returned by each phase sub-control unit through high-speed SPI communication.

[0035] Each phase control unit's FPGA communicates with the main control unit via its own SPI transceiver circuit at high speed. It reads the carrier amplitude (or switching frequency) and target duty cycle sent by the main control unit, adjusts the carrier period length based on the carrier amplitude or switching frequency information, and generates a PWM wave with the corresponding switching frequency based on the target duty cycle information. This PWM wave is then controlled by the driver board to turn the power module on and off, thus completing the switching control. Furthermore, to simulate the performance of power devices under different operating conditions, the main control unit can send control signals such as target drive voltage and target drive resistance to the phase control units. The phase control units then control the variable drive voltage circuit and variable drive resistance circuit respectively to adjust the on / off voltage and resistance. Simultaneously, the phase control units can also transmit the acquired real-time drive voltage and communication interference count back to the main control board via SPI high-speed communication, and transmit the acquired power module NTC temperature back to the main control unit via Ethernet.

[0036] In some specific embodiments, the main control unit and each sub-control unit can be integrated on the main control board and the sub-control board of each phase, respectively. As analyzed in the background art, the motor controller is built using a distributed architecture, which can adapt to the functions required for power device testing of the electric controller, such as adjustable control frequency, adjustable three-phase drive resistance, adjustable three-phase drive voltage, and real-time acquisition of power module temperature. It can reasonably allocate board resource requirements, reduce the resource pressure of FPGA chip under a single control architecture, increase the adjustable control frequency space, and reduce equipment cost.

[0037] You should know, Figure 1 In the motor controller disclosed in the embodiments, each peripheral circuit and ARM chip are illustrative. Those skilled in the art can adjust or replace the above peripheral circuits, ARM chips, etc., according to the specific test specifications and test project requirements without departing from the technical concept of the above distributed FPGA architecture. For example, other high-speed information transmission methods can be used to replace the SPI communication method, or other types of microprocessors (MCUs) can be used to replace the ARM chip and work in collaboration with the FPGA.

[0038] However, during actual operation, the applicant discovered that for this distributed FPGA architecture, each sub-control unit's FPGA determines the carrier clock period and generates the carrier based on its own crystal oscillator (which generates the basic clock cycle, from which all clocks are derived) and the carrier. Since the crystal oscillator cycles of each sub-control unit and the main control unit are independent, slight time differences inevitably exist between them. Therefore, this control method, where each sub-control unit's FPGA generates its own carrier and PWM wave, will inevitably lead to carrier asynchrony between phases over time, generating high-frequency circulating currents in the phase circuits. The following is a combination of... Figures 3 to 8 Please provide a detailed explanation.

[0039] Figure 3 , Figure 4 The principle and specific process of FPGA generating carrier waves based on information received from the main control unit are shown for each phase control unit. Figure 5 This demonstrates the principle of how the FPGA of each phase control unit in the motor controller generates PWM signals based on carrier waves and modulation waves.

[0040] like Figure 3 As shown, each phase control unit can determine its own "ideal" carrier clock period based on its own FPGA crystal oscillator. After obtaining the carrier peak value (or switching frequency, or switching period information) sent by the main control unit, it uses the absolute value of the carrier peak value and the carrier amplitude change in each carrier clock period. The ratio (or the ratio of the switching period to the carrier clock period) determines the number of carrier clock periods contained in one switching period. Then, starting with a carrier amplitude of 0, in the first 0.5... In each carrier clock cycle To determine the amplitude increase, the carrier amplitude is gradually increased until the carrier peak value is reached, and then increased by 0.5%. In each carrier clock cycle To decrease the amplitude, the carrier amplitude is gradually reduced. After the carrier amplitude reaches 0, the rising process is restarted. By repeating the above steps, the carrier corresponding to the phase of the sub-control unit can be generated.

[0041] Taking an FPGA with a crystal oscillator frequency of 100MHz as an example, the crystal oscillator period is 10ns. Each phase of the FPGA can use this period as the carrier clock period. When it is necessary to test the performance of power devices at a switching frequency of 10kHz (switching period of 100us), it is easy to determine that each switching period contains 10,000 carrier clock periods, i.e. For ease of calculation, the absolute value of the carrier amplitude change in each carrier clock cycle is used. If set to 1, the main control unit can set the carrier peak value to 5000. This carrier peak value information is sent as a frequency-related setting value to the FPGA of each sub-control unit as part of the PWM signal. The FPGA of each phase sub-control unit receives the first 0.5 seconds of the signal. In each carrier clock cycle, starting from 0, the carrier amplitude is incremented by 1 in each carrier clock cycle until the carrier value reaches 5000, and then incremented by 0.5. In each carrier clock cycle, starting from 5000, the amplitude is decreased by 1 in each clock cycle until the carrier amplitude is reduced to 0. Then the carrier amplitude is accumulated again in this way to form a cyclic triangular carrier.

[0042] Figure 4This illustrates, in a specific embodiment, the FPGA of each sub-control unit generates a periodically adjustable carrier wave, which can be executed by a program placed within a 100MHz fixed clock cycle, such as... Figure 4 As shown, J is the flag variable, ADD represents the carrier amplitude rising period, and SUB represents the falling period.

[0043] Before generating the carrier in a loop, the carrier amplitude A and J=ADD are first input. Then, after a delay of 1 / z (1 / z can be set as the carrier clock period), the initial C0 of the carrier is read in. After passing through the J=ADD judgment module, the incremental loop is entered. It should be noted that the phase of the carrier can be changed by changing the initial value C0 of the carrier, but its value cannot exceed the carrier amplitude and cannot be negative.

[0044] After entering the incrementing cycle, each time the carrier is incremented by 1 and output, it is simultaneously checked whether the carrier C after incrementing by 1 is less than the carrier amplitude A. If C is less than A, it can continue to accumulate, and the output J=ADD, so that the carrier continues to operate in the incrementing cycle; if C is greater than or equal to A, it means that the carrier has accumulated to the peak value and needs to start to decrease, and the output J=SUB, so that the carrier enters the decrementing cycle.

[0045] Once the carrier enters the decrementing cycle, a carrier--1 operation is performed each time. At the same time, it is determined whether the carrier C before decrementing is equal to 1. If C is not equal to 1, the decrementing can continue, and the output J=SUB makes the carrier continue to operate in the decrementing cycle. If C is equal to 1, it means that the current cyclic carrier C has become 0 after decrementing, and it needs to start increasing. The output J=ADD makes the carrier enter the incrementing cycle.

[0046] It is worth noting that, due to the existence of the delay 1 / z, the carrier C output in the current cycle can become the input of the next cycle, so it can run continuously in a 100MHz timing cycle.

[0047] Figure 5 Taking phase U as an example, it shows the process in two switching cycles. Ts 1. Ts The schematic diagram of U-phase PWM signal generation in section 2 is as follows: Figure 2 and Figure 5 As shown, after the main control unit determines the target duty cycle of the U phase based on the closed-loop control strategy, it transmits it to the FPGA of the U phase sub-control unit. After receiving the target duty cycle, the FPGA converts it into a U phase modulation wave (for the case where the carrier is a triangular wave, the target duty cycle multiplied by the carrier peak value can be easily obtained, which is the modulation wave amplitude). Then, it continuously compares the U phase carrier with the U phase modulation wave and generates a high-level or low-level signal according to the comparison result, thereby obtaining the U phase PWM signal.

[0048] Figure 6The waveforms of the phase currents generated through the above steps are shown, where the frequency of each phase current is 125Hz and the amplitude is approximately 50A. Figure 6 It can be clearly seen that there is a large-amplitude 10kHz high-frequency circulating current between each phase. This large-amplitude high-frequency circulating current will not only increase the torque fluctuation and heat generation of the equipment, but may even cause the system to run out of control in severe cases.

[0049] By analyzing the PWM signal generation mechanism of the distributed FPGA architecture, the applicant found that the asynchronous phenomenon between the carriers output by each phase control unit is an important factor leading to the high-frequency circulating current between the phases. The reason is that each FPGA of the control unit determines the carrier clock period with its own crystal oscillator period. Since the actual crystal oscillator period of each FPGA is independent and inevitably has a slight time difference from the ideal crystal oscillator period, the phase difference between the three phase carriers will gradually accumulate over time.

[0050] For example, like Figure 7 As shown, due to the slight difference in the FPGA crystal oscillator period between the U-phase control unit and the V-phase control unit, the carrier clock periods of the two also differ. This difference causes a synchronization error in the phase of the U-phase carrier and the V-phase carrier, and the synchronization error gradually increases over time. If the U-phase and V-phase carrier clock periods differ by 0.1ns in each switching cycle, the two carrier phases will differ by 1us after one switching cycle, and by 50us after fifty switching cycles (5ms), which is equivalent to shifting the two carriers by half a cycle.

[0051] Figure 8 The generation mechanism of high-frequency circulating current is shown in the figure, where the U-phase and V-phase carriers are fully synchronized and out of phase by half a cycle. The amplitude of the U-phase modulation wave is 2 / 3 of the carrier peak value, and the amplitude of the V-phase modulation wave is 1 / 3 of the carrier peak value.

[0052] As can be seen from the figure, when there is no phase difference between phases U and V, the PWM waves of the two phases are only between 1 / 6 and 1 / 3. T s and 2 / 3~5 / 6 T s There are interphase circulating current loops with opposite directions; when the phase difference between the phases is 180°, there are interphase circulating current loops in both phases throughout the entire switching cycle, with the current direction from phase U to phase V as the positive direction, and its value is between 0 and 1 / 3. T s 2 / 3~1 T s A total of 2 / 3 switching cycles T s Within a certain time period, the circulation increases, specifically between 1 / 3 and 2 / 3 of the time.T s A total of 1 / 3 of a switching cycle T s Within a certain time, the circulation decreases, and the overall high-frequency circulation amplitude is twice the amplitude without phase difference.

[0053] Figure 9 The simulation example shown is a comparison of the simulation results of the three-phase motor phase current under the conditions of bus voltage 100V, electrical frequency 33.33Hz, and switching frequency 10kHz, with synchronous and asynchronous phase carriers for each phase, and with phases A and C carriers remaining unchanged while phase B carrier is shifted by 180°. As shown in the figure, the high-frequency harmonic amplitude of the motor phase current is significantly larger under the asynchronous carrier condition than under the synchronous carrier condition.

[0054] In addition to the aforementioned carrier asynchrony issues, during data communication in a distributed architecture, information such as carrier peak value and target duty cycle received by each sub-control unit may be erroneous due to electromagnetic interference and other reasons. This is especially true when the switching frequency reaches the 10kHz level. To resolve the carrier asynchrony problem, each sub-control unit may need to receive information from the main control unit at a 1µs interval. This high-frequency data interaction process will greatly increase the probability of data transmission errors. At the same time, the limitations of FPGA processing resources mean that some conventional data verification methods cannot be applied to this high-frequency data interaction scenario.

[0055] To address the aforementioned problems, this application provides a carrier synchronization control method for a motor controller based on the aforementioned distributed FPGA architecture through an embodiment, such as... Figure 10 As shown, in this method, the FPGA of each sub-control unit cyclically executes the following steps:

[0056] Step 100: Receive communication data sent by the main control unit and extract the control information and synchronization information to be verified from it;

[0057] Step 200: Determine whether the synchronization information to be verified is valid. If so, update the carrier generation time and current synchronization information based on the synchronization information to be verified, and update the current control information based on the control information to be verified. If not, update the carrier generation time based on the carrier clock period of the FPGA of the sub-control unit and the current control information, and update the current synchronization information based on the synchronization information to be verified.

[0058] Step 300: Based on the updated carrier generation time, the carrier and PWM control signals for the corresponding phase of the sub-control unit are generated according to the current control information and the carrier clock period of the FPGA of the sub-control unit.

[0059] The implementation process of steps 100 to 300 will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0060] <Communication Data>

[0061] In step 100, after receiving the communication data sent by the main control unit, the FPGA of each sub-control unit extracts the control information to be verified and the synchronization information to be verified from it.

[0062] Figure 11 The diagram illustrates the format of the communication data generated by the main control unit and the transmission method in some embodiments of this application. Figure 11 In the illustrated embodiment, the communication data sent to each sub-control unit includes two parts: control information to be verified and synchronization information to be verified. The control information to be verified contains the control information required by each sub-control unit to generate the PWM signal of the corresponding phase. After verification, this control information will replace the original control information, thereby realizing the dynamic adjustment of the switching frequency of the power device during operation. One of the functions of the synchronization information to be verified is to trigger the FPGA of each sub-control unit to enter the synchronization processing process described later.

[0063] The specific values ​​of the control information to be verified are generated based on the control objectives of each phase of the sub-control unit. These include setting values ​​related to the frequency of the PWM signal and setting values ​​related to the duty cycle of the PWM signal. For example, the control information sent to the FPGA of the U-phase sub-control unit includes setting values ​​related to the frequency of the U-phase PWM signal, which can be the carrier peak value mentioned earlier, or the switching frequency / switching period. Additionally, it includes setting values ​​related to the duty cycle of the U-phase PWM signal, such as the target duty cycle of the U-phase. Generally, the setting values ​​related to the frequency of the PWM signal are the same for all three phases (U, V, and W), while the setting values ​​related to the duty cycle of the PWM signal are set to the same or different values ​​depending on the control objectives for each phase.

[0064] In addition, in some optional embodiments, in order to achieve the adjustment of voltage and resistance, the control information to be verified may also include the corresponding target driving resistor, target driving voltage, etc.

[0065] Based on the analysis above, especially referring to... Figure 7 It can be observed that the synchronization error caused by the slight difference in crystal oscillator period in the FGPA of each sub-control unit is not randomly generated, but gradually accumulates in each switching cycle. When operating at high frequencies, with switching cycles reaching 10kHz or even higher, the rate of error accumulation becomes extremely rapid. Therefore, to suppress this error, the frequency of synchronization processing must be increased accordingly. For this reason, such as... Figure 11As shown, the FPGA of the main control unit determines the switching cycle of the motor controller based on its own crystal oscillator cycle. Ts (That is, the ideal value of the crystal oscillator of the FPGA in the main control unit is used to determine each switching cycle) Ts After the number of crystal oscillator cycles that should be included, every [number of cycles] Ts The system sends communication data to the FPGA of each sub-control unit once, so that each sub-control unit performs a synchronization process once after a switching cycle determined by the FPGA of the main control unit.

[0066] However, this high-frequency data communication brings new problems: due to various interference factors during the communication process, the probability of inconsistencies between the communication data sent by the main control unit and the communication data received by each sub-control board increases significantly. Taking a switching cycle of 10kHz as an example, the sub-control unit will receive approximately 10,000 communication data per second. Since the communication data contains setting values ​​for controlling the motor, if the operation is performed according to the incorrect setting values, it will inevitably lead to the risk of motor loss of control. Therefore, it is necessary to perform about 10,000 verification operations on the communication data per second. Obviously, a reasonable verification mechanism needs to be set to ensure that the FPGA of each sub-control board can perform verification operations at such a high frequency.

[0067] Therefore, in the embodiments of this application, the synchronization information contained in each communication data is used not only to trigger the FGPA of each sub-control unit to enter the synchronization processing flow, but also to contain information for verifying the authenticity of the data.

[0068] Specifically, in the embodiments of this application, the synchronization information to be verified sent by the main control unit to the FPGA of the three sub-control units each time remains consistent. Preferably, the synchronization information to be verified is a non-negative integer and has a preset upper limit.

[0069] Furthermore, the value of the synchronization information to be verified is incremented by 1 in each transmission until an overflow is triggered (i.e., the value reaches the upper limit). In the next transmission of communication data, the value of the synchronization information to be verified is reset to 0, and then the cycle of incrementing by 1 in each transmission of communication data begins again.

[0070] For example, like Figure 11 As shown, the synchronization information to be verified is an integer between 0 and M, where M is the preset upper limit of the value of the synchronization information to be verified. In some specific embodiments, the synchronization information to be verified can be set in binary format. For example, it can be a 7-bit binary number, in which case its minimum value is 0 and its maximum value is 127.

[0071] The advantage of using binary is that it can be well matched with the data storage and processing format of FPGA. However, those skilled in the art can also set the synchronization information to be verified according to various integer data formats such as octal and decimal based on specific application needs.

[0072] Figure 12 and Figure 13 The following diagram illustrates the timing of the FPGA receiving communication data in some specific embodiments, such as... Figure 12 , Figure 13 As shown, due to the FPGA of the main control unit every Ts Each unit sends communication data once, and the synchronization information value will change successively. Therefore, the FGPA of each sub-control unit can detect the value of the synchronization information part in register A through the edge detection circuit. If a change is detected in the position of register A before and after a clock cycle, an "event pulse" can be generated, and then this "event pulse" can be used to drive the subsequent verification process.

[0073] In some alternative embodiments, such as Figure 14 As shown, the FPGA of the U-phase sub-control unit stores new communication data in register A after each reception. Additionally, register B stores a set of data with the same format as the communication data. The portion with the same format as the control information to be verified is called the current control information, and the portion with the same format as the synchronization information to be verified is called the current synchronization information. For the FPGA of the V-phase and W-phase sub-control units, the data storage method can be found in [reference needed]. Figure 14 This will not be elaborated upon here.

[0074] In the next step 200, the FGPA of the sub-control unit will verify the validity of the received communication data through these two sets of data, and decide whether to change the carrier start position to achieve synchronization and whether to update the motor control parameters based on the verification results.

[0075] <Step 200>

[0076] Figure 15 This illustrates the flow of verification and synchronization processing performed by the sub-control unit in some embodiments, with reference to... Figure 14 , 15 The sub-control unit determines the validity of the synchronization information to be verified in the later received communication data by measuring the difference between the synchronization information to be verified contained in two consecutive received communication data. Figure 14 As shown, the synchronization information to be verified contained in the last received communication data is the synchronization information to be verified stored in register A, while the synchronization information to be verified contained in the previous communication data used for comparison is the current synchronization information stored in register B.

[0077] Specifically, if the value of the synchronization information to be verified stored in register A is 1 greater than the value of the current synchronization information stored in register B (i.e., in two consecutive received communication data, the synchronization information to be verified contained in the later received communication data is 1 greater than the synchronization information to be verified contained in the earlier received communication data), or the value of the current synchronization information stored in register B is its upper limit, while the value of the synchronization information to be verified stored in register A is 0 (i.e., in two consecutive received communication data, the synchronization information to be verified contained in the earlier received communication data is the upper limit of the value of the synchronization information to be verified, and the synchronization information to be verified contained in the later received communication data is 0), then the synchronization information to be verified stored in register A is determined to be valid, indicating that the latest received communication data stored in register A is not distorted. In this case, the carrier's initial value is modified and the control parameters are updated through the following operations:

[0078] (1-1) Determine the updated carrier generation time based on the time when the synchronization information to be verified in register A changes.

[0079] Since the timing of changes in the synchronization information to be verified received by different sub-control units' FGPA often corresponds to different carrier clock cycles, in some preferred embodiments, the rising edge of the first carrier clock cycle after the timing of the change in the synchronization information to be verified in register A can be used as the updated carrier generation timing.

[0080] by Figure 18 The embodiment shown is an example, in the figure t 1 At a certain moment, the synchronization information to be verified in the registers of the U-phase FPGA and V-phase FPGA changes and is captured by both FPGAs. Then, the U-phase FPGA... t 1 The rising edge of the first carrier clock cycle after time 1 t U As the carrier generation time after the U-phase update, the V-phase FPGA uses t 1 The rising edge of the first carrier clock cycle after time 1 t V This serves as the carrier generation time after the V-phase update.

[0081] (1-2) Store the synchronization information to be verified in register A into register B, thereby updating the current synchronization information.

[0082] (1-3) Store the control information to be verified in register A into register B, thereby updating the current control information.

[0083] If the comparison between the value of the synchronization information to be verified stored in register A and the value of the current synchronization information stored in register B does not meet the above conditions, then the synchronization information to be verified stored in register A is determined to be invalid, indicating that the latest received communication data stored in register A has a distortion problem. In this case, the following operations are performed:

[0084] (2-1) Set the carrier generation time according to the FPGA’s own carrier clock period and the current control information in register B.

[0085] (2-2) Store the synchronization information to be verified in register A into register B, thereby updating the current synchronization information.

[0086] Figure 16 , Figure 17 The operations on the data in registers A and B are shown under two different judgment results. Comparing the operations under the two judgment results, it can be seen that, firstly, when the verification result is invalid, each sub-control unit still sets the carrier generation time according to the FPGA's own carrier clock period and the current control information, that is, it maintains... Figure 3 The original carrier generation operation, as shown, uses the moment when new communication data is received as the carrier generation moment if the verification result is valid, thus enabling carrier synchronization operation to be performed only when the communication data is valid. Secondly, regardless of whether the verification result is valid or not, the current synchronization information is updated with the latest synchronization information to be verified, so that the verification operation can be performed continuously based on the synchronization information to be verified received before and after. Finally, if the verification result is valid, the current control information also needs to be updated with the newly received control information, so that when valid communication data is received that includes adjustments to parameters such as switching frequency, a PWM modulation signal can be generated in a timely manner based on the updated parameters.

[0087] The synchronization and information validity verification mechanism disclosed in the above embodiments enables carrier synchronization of each sub-control unit in each switching cycle during the high-frequency switching control of the motor controller at 10kHz and above. At the same time, the data validity is judged by comparing two consecutive synchronization information, avoiding the problem of large computational load and unreliable speed when using complex validity judgment logic to process high-frequency received synchronization data.

[0088] <Step 300>

[0089] After completing step 200, each sub-control unit can generate a carrier in step 300 according to the newly determined carrier generation time, carrier amplitude, and duty cycle information.

[0090] In some specific embodiments, step 300 includes the following steps:

[0091] The first step is to determine the number of carrier clock cycles contained in one switching cycle of the corresponding phase of the sub-control unit, based on the frequency-related settings of the PWM signal in the current control information and the theoretical value of the carrier clock period of the FPGA of the sub-control unit. ;

[0092] The second step is to determine the modulation wave amplitude of the corresponding phase of the sub-control unit based on the setting values ​​related to the frequency and duty cycle of the PWM signal in the current control information.

[0093] The third step involves iteratively executing the following steps, starting from the updated carrier generation time, to construct the carrier for the corresponding phase of the sub-control unit: using 0 as the initial carrier amplitude, in the first 0.5... The carrier amplitude is gradually increased during each carrier clock cycle, and then increased again in the last 0.5 seconds. The carrier amplitude is gradually reduced during each carrier clock cycle until the carrier amplitude becomes 0, or the carrier generation time is updated again.

[0094] The fourth step is to generate the PWM signal for the corresponding phase of the sub-control unit based on the carrier wave and modulation amplitude of the corresponding phase of the sub-control unit.

[0095] For the specific implementation process of the above steps, please refer to [reference needed]. Figure 4 The difference is that when the verification result is valid, the carrier generation time will be updated, so that the carrier is generated with 0 as the starting amplitude at that time.

[0096] In some specific embodiments, reference is made to Figure 4 The delay mechanism in the code allows each sub-control unit to directly set the carrier amplitude to 1 (i.e., after determining that the carrier generation time needs to be changed, regardless of whether the current time is in the increment or decrement phase) after the carrier generation time is determined to be changed. =1), and then set the J value to SUB. The current time is the previous carrier clock cycle as the updated carrier generation time. After a delay of one carrier clock cycle, the carrier starting amplitude corresponding to the updated carrier generation time will become 0. At the same time, since its value was 1 at the previous time, J will become ADD, thus entering the accumulation period.

[0097] Figure 18 This illustrates the generation of the U-phase and V-phase carriers when the communication data received by both the U-phase sub-control unit and the V-phase sub-control unit are valid. Figure 18 It can be seen that by using the above synchronization mechanism, the synchronization error of each phase carrier can always be controlled within one carrier clock cycle when the data is valid, thereby effectively suppressing the high-frequency circulating current caused by carrier asynchrony.

[0098] Figure 19This illustrates the carrier generation process when invalid data exists in the U phase. Figure 19 It can be seen that the sub-control unit can effectively judge after receiving invalid data, and promptly use the valid data to resynchronize the carrier after receiving valid data again.

[0099] Figure 20 In a specific embodiment, the method provided in this application is used to control the output current of a motor controller for one phase of the three-phase current. The current frequency in the figure is 25Hz, and the amplitude is approximately 95A. Figure 20 It can be seen that the high-frequency circulating current in each phase current output after using the above-mentioned carrier synchronization control has been significantly suppressed, indicating that the carrier synchronization control method provided in this application can achieve a significant high-frequency circulating current suppression effect.

[0100] The specific embodiments of this application have been described in detail above. For those skilled in the art, several improvements and modifications can be made to this application without departing from the principle of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A carrier synchronization control method for a motor controller with a distributed FPGA architecture, the motor controller comprising a main control unit and three sub-control units communicatively connected to the main control unit, wherein each of the main control unit and the sub-control units is equipped with an FPGA, characterized in that, The FPGA of each sub-control unit executes the following steps in a loop: Receive communication data sent by the main control unit and extract the control information and synchronization information to be verified from it; Determine whether the synchronization information to be verified is valid. If it is, update the carrier generation time and the current synchronization information based on the synchronization information to be verified, and update the current control information based on the control information to be verified. If it is not valid, update the carrier generation time based on the carrier clock period of the FPGA of the sub-control unit and the current control information, and update the current synchronization information based on the synchronization information to be verified. Based on the updated carrier generation time, the carrier and PWM control signals for the corresponding phase of the sub-control unit are generated according to the current control information and the carrier clock period of the FPGA of the sub-control unit.

2. The carrier synchronization control method for a motor controller with a distributed FPGA architecture according to claim 1, characterized in that, The FPGA of the main control unit determines the switching cycle of the motor controller based on its own crystal oscillator cycle, and sends communication data to each sub-control unit in each switching cycle. The communication data sent to each sub-control unit includes the control information to be verified corresponding to each sub-control unit, as well as the same synchronization information to be verified. Each of the sub-control units' FPGAs determines its own carrier clock period based on its own crystal oscillator period; The crystal oscillator cycles of the FPGA in the main control unit and the FPGA in each of the sub-control units are independent.

3. The carrier synchronization control method for a motor controller with a distributed FPGA architecture according to claim 1, characterized in that, Both the synchronization information to be verified and the current synchronization information are non-negative integers and have the same upper limit of value. In the absence of overflow, the value of the synchronization information to be verified contained in the communication data sent by the main control unit each time is the value of the synchronization information to be verified contained in the previous communication data + 1. In the event of an overflow, the value of the synchronization information to be verified contained in the communication data sent by the master control unit is 0.

4. The carrier synchronization control method of the motor controller of the distributed FPGA architecture according to claim 3, characterized by, Based on the difference between the synchronization information to be verified contained in two consecutive received communication data, it is determined whether the synchronization information to be verified contained in the later received communication data is valid, wherein the synchronization information to be verified contained in the previous received communication data is the current synchronization information.

5. The carrier synchronization control method of the motor controller of the distributed FPGA architecture according to claim 4, characterized by, The synchronization information to be verified contained in the later received communication data is considered valid if and only if: In two consecutive received communication data sets, the synchronization information to be verified in the later received communication data set is one greater than the synchronization information to be verified in the earlier received communication data set; or, In two consecutive received communication data, the synchronization information to be verified contained in the first received communication data is the upper limit of the value of the synchronization information to be verified, and the synchronization information to be verified contained in the second received communication data is 0.

6. The carrier synchronization control method of the motor controller of the distributed FPGA architecture according to claim 1, wherein, Both the control information to be verified and the current control information include the following information: Settings related to the frequency of the PWM signal and settings related to the duty cycle of the PWM signal.

7. The carrier synchronization control method of the motor controller of the distributed FPGA architecture according to claim 6, wherein Each sub-control unit's FPGA generates its corresponding phase's carrier and PWM control signals through the following steps: Based on the frequency-related settings of the PWM signal in the current control information, and the theoretical value of the carrier clock period of the FPGA of the sub-control unit, determine the number of cycles of the carrier clock period contained in one switching cycle of the corresponding phase of the sub-control unit. ; Based on the settings related to the frequency and duty cycle of the PWM signal in the current control information, the modulation wave amplitude of the corresponding phase of the sub-control unit is determined. Starting from the updated carrier generation time, the following steps are executed cyclically to construct the carrier for the corresponding phase of the sub-control unit: with 0 as the carrier starting amplitude, in the first 0.5... The carrier amplitude is gradually increased during each carrier clock cycle, and then increased again in the last 0.5 seconds. The carrier amplitude is gradually reduced during each carrier clock cycle until the carrier amplitude becomes 0, or the carrier generation time is updated again. Based on the carrier wave and modulation amplitude of the corresponding phase of the sub-control unit, the PWM signal of the corresponding phase of the sub-control unit is generated.

8. The carrier synchronization control method of the motor controller of the distributed FPGA architecture according to claim 7, characterized by, For each sub-control unit's FPGA, the carrier amplitude value of the previous carrier clock cycle at the updated carrier generation time is set to... Furthermore, the carrier amplitude change method is set to gradually decrease the carrier amplitude, so that the initial carrier amplitude corresponding to the updated carrier generation time is 0. It is the absolute value of the change in carrier amplitude during each carrier clock cycle.

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