A Parameter Extraction Method for the Equivalent Circuit Model of GaN HEMT Devices

Abstract

This invention discloses a parameter extraction method for the equivalent circuit model of a GaN HEMT device, comprising at least the following steps: Step S1: Modeling the GaN HEMT device as a small-signal equivalent circuit model; Step S2: Extracting external parasitic parameters based on the model in Step S1; Step S3: Extracting internal intrinsic parameters; In Step S1, the equivalent circuit model includes external parasitic parameters and internal intrinsic parameters, wherein the external parasitic parameters are not affected by the applied bias voltage, including the parasitic capacitance C between metal electrodes. pg C pd and C pg External parasitic inductance L g L d and L s and external parasitic resistance R g R d and R s The intrinsic parameters are affected by the channel structure and bias conditions during device operation, including the channel resistance R. gs Gate-drain resistance R gd Drain-source output conductance G ds Capacitance C between each port gs C gd C ds ; transconductance g m Delay parameter τ.

Description

Technical Field

[0001] This invention belongs to the field of GaN HEMT technology, and specifically relates to a method for extracting parameters from the equivalent circuit model of GaN HEMT devices. Technical Background

[0002] Gallium nitride high electron mobility transistors (GaN HEMTs) are ideal devices for high-power applications due to the unique properties of GaN-based materials, including high-frequency response, high breakdown voltage, and high reliability. Any system-level design, such as GaN amplifiers, oscillators, and mixers, requires an accurate device model that can simulate phenomena including breakdown characteristics, forward conduction, and dispersion effects. Accurate extraction of the small-signal circuit model is crucial for understanding the device's circuit behavior. Furthermore, it plays a key role in analyzing how microwave performance changes with device geometry. Therefore, the effectiveness of device modeling is highly dependent on the accuracy of the small-signal model.

[0003] One of the main goals of device modeling is to accurately describe the RF input / output characteristics of the device, ensuring that the device's electrical characteristics can be described by mathematical expressions under any operating conditions and external environment. Compact models (equivalent circuit models) are typically built based on limited measurement data obtained through specific measurement techniques to ensure that the model covers all operating states of the device.

[0004] In existing research, scholars have conducted detailed studies on the equivalent circuit topology of small-signal models. However, there is no precise and comprehensive optimization method for extracting the intrinsic parameters within the model. Most scholars choose to take the average value of the intrinsic parameters across the entire frequency band as the model parameters, without considering the actual application scenarios of the devices (such as high-frequency devices) or the degree of influence of the intrinsic parameters on the entire circuit model.

[0005] However, in practical applications, the appropriate values ​​of intrinsic parameters greatly affect the simulation results of the model, limiting the accuracy and stability of the model.

[0006] Therefore, given the technical deficiencies of existing technologies, it is necessary to propose a solution to address the technical problems existing in the current technologies. Summary of the Invention

[0007] Based on the above objectives, this invention proposes a parameter extraction method for the small-signal equivalent circuit model of GaN HEMT devices. This method can optimize the extracted intrinsic parameters according to the application frequency band of the device. It can quantify the error of the circuit model, thereby further improving the accuracy and stability of the small-signal equivalent circuit model. This improves the R&D efficiency of GaN HEMT RF devices, shortens the R&D cycle, and provides strong support for the technological progress and product performance of related industries.

[0008] In order to solve the technical problems existing in the prior art, the technical solution of the present invention is as follows:

[0009] A method for extracting parameters from an equivalent circuit model of a GaN HEMT device includes at least the following steps:

[0010] Step S1: Model the GaN HEMT device as a small-signal equivalent circuit model;

[0011] Step S2: Based on the model in Step S1, extract the external parasitic parameters;

[0012] Step S3: Extract intrinsic parameters;

[0013] In step S1, the equivalent circuit model includes external parasitic parameters and internal intrinsic parameters. The external parasitic parameters are unaffected by the applied bias voltage and include the parasitic capacitance C between the metal electrodes. pg C pd and C pg External parasitic inductance L g L d and L s and external parasitic resistance R g R d and R s The intrinsic parameters are affected by the channel structure and bias conditions during device operation, including the channel resistance R. gs Gate-drain resistance R gd Drain-source output conductance G ds Capacitance C between each port gs C gd C ds ; transconductance g m Delay parameter τ;

[0014] Step S3 further includes the following steps:

[0015] After extracting the external parasitic parameters, the S-parameters of the device are measured at the bias operating point, and the external parasitic parameters are embedded using the matrix network transformation formula to obtain the intrinsic Y-parameters of the device. The expressions for extracting the intrinsic parameters are shown below:

[0016]

[0017] G ds =Re(Y 22 +Y 12 )

[0018] g m =mag(Y 21 -Y 12 )

[0019]

[0020] The maximum transconductance point of the device is obtained as the selected operating point of the device, and the extracted intrinsic parameter curves under this bias within the range of 0-40 GHz are obtained by the above formula.

[0021] The average value of each intrinsic parameter across the entire frequency band is calculated; the model error is defined as:

[0022]

[0023] Where S Sim，ij These are simulation S-parameter data, S Mea，ij It is the test S-parameter data;

[0024] Let the difference between the upper and lower limits of the model error be γ, and let the extracted value of a certain intrinsic parameter at a certain frequency be A. Let:

[0025]

[0026] in, The value is the average value of the intrinsic parameter across the entire frequency band, and α is the ratio of the extracted value at this frequency point to the average value across the entire frequency band.

[0027] Substitute the extracted value A of a certain intrinsic parameter into the circuit model for simulation. Take the average value of other intrinsic parameters across the entire frequency band. Calculate the upper and lower limits γ of the model accuracy error for different α values, and take the value of the lowest point of γ as the extracted value of the intrinsic parameter. In this way, all internal intrinsic parameters are extracted.

[0028] As a further improvement, the GaN HEMT device has a gate length of 100nm and a total gate width of 75um, of which the single-finger gate width is 37.5um and the gate index is 2.

[0029] As a further improvement, step S2, when extracting the external parasitic capacitance, includes the following steps:

[0030] Under low-frequency conditions and channel-off state, the small-signal equivalent circuit of GaN HEMT device is simplified to a circuit model containing only capacitors.

[0031] The S-parameters of the test device after de-embedding are given. The imaginary part of the Y-parameters of the de-embedding device has a linear relationship with the angular frequency as shown in the following formula:

[0032] Im(Y 11 )=ω(C pg +C gs +C pgd +C gd )

[0033] Im(Y 22 )=ω(C pd +Cds +C pgd +C gd )

[0034] Im(Y 12 ) = Im(Y 21 )=-ω(C pgd +C gd )

[0035] The extraction of parasitic capacitance is optimized using an annealing algorithm;

[0036] First, initialize capacitor C. pg C pd C b The value is set to a minimum, and the value is gradually adjusted by comparing the error between simulation calculations and measured data to finally obtain the optimal capacitance value.

[0037] Next, optimize C. pgd The initial value was set to 0, and C was obtained by adjusting it to the minimum error through simulation. pgd Finally, optimize C. gs and C gd C is obtained through annealing algorithm gs C gd Finally, the optimized external parasitic capacitance value is obtained.

[0038] As a further improvement, step S2, when extracting the external parasitic inductance, includes the following steps:

[0039] Under cold-cutoff conditions, the equivalent circuit model at high frequencies neglects capacitive reactance and considers the channel distributed resistance R. c The influence of ω is explained by deriving the expression for the imaginary part of the Z-parameters in the equivalent circuit, and then using ω as the basis for the expression. 2 Plot a graph with Z as the x-axis and the imaginary part ω·Im(Z) as the y-axis; from this, the values ​​of the three parasitic inductances are extracted from the slope of the curve. The specific extraction formula is as follows:

[0040]

[0041] Among them, R g R s R d L is the parasitic resistance value. g L s L d C is the parasitic inductance value. g C s C d The parasitic capacitance value; multiplying both sides of the above three equations by the angular frequency ω, we can obtain the imaginary part of the Z-parameter as:

[0042]

[0043]

[0044] With ω 2 Draw a straight line with ωZ as the x-axis and the imaginary part of ωZ as the y-axis. The slope of the line is the extracted value of the three parasitic inductances.

[0045] Compared with existing technologies, this invention models GaN HEMT devices as small-signal equivalent circuit models, which can optimize the intrinsic parameter extraction values ​​according to the device's application frequency band. This method can quantify the error of the circuit model, thereby further improving the accuracy and stability of the small-signal equivalent circuit model. This improves the R&D efficiency of GaN HEMT RF devices, shortens the R&D cycle, and provides strong support for the technological progress and product performance of related industries. Attached Figure Description

[0046] Figure 1 This is a cubic diagram of the small-signal equivalent circuit model of the GaN HEMT device of this invention;

[0047] Figure 2 This is a plan view of the small-signal equivalent circuit model of the GaN HEMT device of this invention;

[0048] Figure 3 This is a schematic diagram of the small-signal equivalent circuit under low-frequency cold field-cutoff conditions in this invention.

[0049] Figure 4 This is a schematic diagram of the small-signal equivalent circuit under high-frequency cold field-cutoff conditions in this invention.

[0050] Figure 5 For the high-frequency cold field-cutoff condition Im(ωZ) in this invention ij ) with ω 2 Schematic diagram of the change curve;

[0051] Figure 6 For Re(Z) ij ) with 1 / (V gs -V th A schematic diagram of the change curve;

[0052] Figure 7 This is a schematic diagram of the small-signal equivalent circuit of the cold field-cutoff condition in this invention;

[0053] Figure 8 A schematic diagram comparing the measured and simulated values ​​of the small-signal equivalent circuit under the cold field-cutoff state within 0–40 GHz;

[0054] Figure 9 A schematic diagram of the extracted intrinsic parameters under this bias within the range of 0–40 GHz;

[0055] Figure 10 This is a schematic diagram comparing the test results of the small-signal equivalent circuit model and the actual device when the average value of the entire frequency band is used as the model parameter.

[0056] Figure 11 A schematic diagram illustrating the effect of adjusting a single intrinsic parameter value on the simulation S-parameters;

[0057] Figure 12 This diagram illustrates the impact of intrinsic parameter values ​​at different frequency points on model error stability.

[0058] Figure 13 This is a schematic diagram comparing the errors of the circuit model after optimization based on the extracted intrinsic parameters. Detailed Implementation

[0059] This invention provides a method for extracting parameters from the equivalent circuit model of a GaN HEMT device, comprising at least the following steps:

[0060] Step S1: Model the GaN HEMT device as a small-signal equivalent circuit model;

[0061] Step S2: Based on the model in Step S1, extract the external parasitic parameters;

[0062] Step S3: Extract intrinsic parameters;

[0063] In step S1, the equivalent circuit model includes external parasitic parameters and internal intrinsic parameters. The external parasitic parameters, including the parasitic capacitance C between metal electrodes, are affected by factors such as the physical dimensions of the device and are not influenced by the applied bias voltage. pg C pd and C pg External parasitic inductance L g L d and L s and external parasitic resistance R g R d and R s The intrinsic parameters are affected by the channel structure and bias conditions during device operation, including the channel resistance R. gs Gate-drain resistance R gd Drain-source output conductance G ds Capacitance C between each port gs C gd C ds ; transconductance g m Delay parameters, such as τ, etc. See also... Figure 1 and Figure 2The diagram shows the cubic and planar plots of the small-signal equivalent circuit model of the GaN HEMT device used in this invention, comprising 17 components. The intrinsic parameters of the model are enclosed in dashed boxes and are related to the applied bias. The GaN HEMT device used in this example has a gate length of 100 nm, a total gate width of 75 μm, a single-finger gate width of 37.5 μm, a gate index of 2, and an RF test data frequency range of 0–40 GHz.

[0064] In step S2, the specific extraction process includes:

[0065] (1) Extraction of external parasitic capacitance

[0066] Under low-frequency conditions (typically less than 3 GHz) and in the channel-off state, neglecting the effect of inductance, the small-signal equivalent circuit of the GaN HEMT device is simplified to a circuit model containing only capacitors. See [link to relevant documentation]. Figure 3 The extraction of parasitic capacitance is optimized using an annealing algorithm. First, the capacitance C is initialized. pg C pd C b The value was initially set to a minimum, and its value was gradually adjusted based on the error between simulation calculations and measured data to ultimately obtain the optimal capacitance value (C). pg =2.50fF, C pd =2.46fF, C b =23.48fF). Next, optimize C. pgd The initial value was set to 0, and C was obtained by adjusting it to the minimum error through simulation. pgd =1.05fF. Finally, considering the influence of the gate-drain spacing, C is further optimized. gs and C gd Finally, C is obtained through the annealing algorithm. gs =22.99fF, C gd =24.05fF. After these steps, the optimized external parasitic capacitance value is finally obtained.

[0067] The key to extracting extrinsic parameters from small-signal models is simplification. Figure 2 The equivalent circuit at a specific bias point. At low frequencies (typically below 3GHz), the inductive reactance jωL is very small and negligible, and under the channel turn-off condition (i.e., cold-field cutoff condition), the transistor current is almost non-existent. In this case, it is equivalent to a passive device. Therefore, the small-signal circuit model can be equivalent to a circuit with only capacitive reactance, such as... Figure 3 As shown. Taking all factors into consideration, this invention selects test data at 1 GHz to extract parasitic parameters.

[0068] In the cold field-cutoff condition (V) gs <V th V ds =0V), where V thThe threshold voltage of the device was measured to be -2V, and the S-parameters of the device after de-embedding were tested. Figure 3 From the circuit structure relationship, it can be seen that the imaginary part of the Y parameter of the de-embedded device has a linear relationship with the angular frequency as shown in the following formula:

[0069] Im(Y 11 )=ω(C pg +C gs +C pgd +C gd )

[0070] Im(Y 22 )=ω(C pd +C ds +Ck pgd +C gd )

[0071] Im(Y 12 ) = Im(Y 21 )=-ω(C pgd +C gd )

[0072] Where C pg C pd C pgd For external parasitic capacitance, C gs C ds C gd This represents the channel capacitance value under cutoff conditions.

[0073] From the above analysis, it can be seen that the general approach to extracting external parasitic capacitance is to solve for six unknowns. Using three equations to solve for three of these unknowns, the physical dimensions of the device are used to determine the equality relationship between the three unknowns. The remaining three unknowns are then solved using equations. Although the equivalent relationships obtained from the physical dimensions are not entirely equivalent, the first step has already yielded the values ​​of three unknowns. The remaining parameters are then scanned from 0, and the equations are solved to obtain the most suitable values. The extraction of external parasitic capacitance can be divided into three steps:

[0074] First, when the device is in the off state, the depletion region widths of the gate-source and gate-drain can be considered to be the same, i.e., C. gs =C gd =C b And C ds =0. Due to the parasitic capacitance C pgd This is the parasitic capacitance between the gate and drain metal electrodes, and its value is much smaller than C. pg and C pd Therefore, this value is ignored in the first step.

[0075] Using the annealing algorithm, the capacitor is initialized from C. pg C pdC b Starting with a small value, the values ​​are gradually and randomly adjusted. The adjusted capacitor combination is then substituted into the circuit model for simulation, and the error between the simulated and measured values ​​is calculated. The algorithm determines whether the new capacitor values ​​are better by calculating the change in error between the simulated and measured values. Simultaneously, the parameter search range is gradually adjusted during the optimization process to ensure that the error gradually decreases, ultimately obtaining the capacitor values ​​that best match the measured data. When the error between the simulated and measured values ​​is minimized, the values ​​of the three capacitors are obtained as C0. pg =2.50fF, C pd =2.46fF, C b =23.48fF.

[0076] Secondly, keeping the other parameters unchanged, the annealing algorithm is used to process C. pgd Optimize. First, optimize C. pgd Initialize the value to 0, gradually adjust it from a small range, and perform circuit simulation after each adjustment to calculate the error between the simulated value and the measured data. The capacitance value C is obtained when the error between the simulated value and the measured data is minimized. pgd =1.05fF.

[0077] Finally, due to the very small spacing between the gate and drain electrodes, the extracted C can be considered... pgd It is a constant value, and due to the electrode size, C gs It will not be exactly equal to C gd Using the annealing algorithm to convert C gs With C gd The circuit simulation begins at 23.48 fF. The capacitance value C is obtained when the error between the simulated and measured values ​​is minimized. gs =22.99fF, C gd =24.05fF.

[0078] In summary, the final C obtained using the annealing algorithm pg C pd C pgd The value is the external parasitic capacitance parameter value.

[0079] (2) Extraction of external parasitic inductance

[0080] Under cold-cut conditions, when the frequency exceeds 25 GHz, the capacitive reactance of the parasitic capacitance... This can be disregarded; the equivalent circuit diagram of the device under this condition can be found in [reference needed]. Figure 4 The equivalent circuit model at high frequencies neglects capacitive reactance and considers the channel distributed resistance R. c The influence of ω. By deriving the Z parameters in the equivalent circuit, the expression for its imaginary part is obtained, and ω is used as the basis for the expression. 2Plot the graph with ω·Im(Z) as the x-axis and the imaginary part as the y-axis. From this, the values ​​of the three parasitic inductances can be extracted from the slope of the curve.

[0081] Depend on Figure 4 The Z-parameter relationship of the equivalent circuit can be derived:

[0082]

[0083] Where R g R s R d L is the parasitic resistance value. g L s L d C is the parasitic inductance value. g C s C d Let be the parasitic capacitance value. Multiplying both sides of the above three equations by the angular frequency ω yields the imaginary part of the Z-parameter:

[0084]

[0085] With ω 2 Draw a straight line with ωZ as the x-coordinate and the imaginary part of ωZ as the y-coordinate. Therefore, the Z-parameters... Converting to the intercept, the slope of the straight line is the extracted value of the three parasitic inductances. See [link to relevant documentation]. Figure 5 The figure shows Im(ωZ) under the high-frequency cold field-cutoff condition in this invention. ij ) with ω 2 The change curve diagram represents the extraction result.

[0086] (3) Extraction of external parasitic resistance

[0087] The extraction of parasitic resistance needs to be performed under high-frequency conditions and the channel distributed resistance R needs to be considered. c The influence of [variable name]. Under small-signal conditions, neglecting the heating effect, the channel distributed resistance is related to 1 / (V [variable name]. gs -V th It is directly proportional to 1 / (V) gs -V th When R approaches zero c The value can be ignored. The parasitic resistance is extracted by calculating the intercept of the real part of the Z-parameter. This is done by applying different bias voltages (e.g., V). gs The Z-parameters were measured at voltages of -0.5V, 0V, 0.5V, 1V, and 1.5V, and a straight line was fitted. The Y-intercept of the fitted line was then calculated to obtain the parasitic resistance value. The formulas for the channel distributed resistance Rc and the real part of the Z-parameters are shown below:

[0088] Extracting external parasitic resistance needs to be performed at high frequencies, because the device channel behaves as a transmission line with distributed effects when it is conducting. Therefore, the channel distributed resistance R must be considered when extracting parasitic resistance parameters. c The influence of this is because the heating effect of the device is negligible in the small-signal state, therefore the channel distributed resistance R is negligible here. c Ignoring temperature dependence, its expression is as follows:

[0089]

[0090] Where L channel W channel These represent the channel length and width, μ n，channel For channel electron mobility, C ox This is the gate oxide capacitance. The above equation shows that R c Proportional to 1 / (V) gs -V th When 1 / (V) gs -V th When R approaches zero c The value of is negligible, and the real intercept of the Z-parameter relationship is the parasitic resistance value. Therefore, the real part of the Z-parameter can be rewritten as:

[0091]

[0092] Based on the above formula, choose the bias point V. gs =-0.5V, 0V, 0.5V, 1V, 1.5V, V ds The Z-parameter values ​​were measured at 0V, and a straight line was fitted to the parameter values ​​under different biases. See [reference needed]. Figure 6 The figure shows Re(Z) ij ) with 1 / (V gs -V th The parasitic resistance can be extracted by calculating the Y-intercept of the fitted straight line from the schematic diagram of the change curve.

[0093] (4) Verification of external parasitic parameters

[0094] The accuracy of the extracted parasitic parameters can be verified by comparing the measured values ​​with the simulated values ​​under cold-field-cutoff conditions. See [link to relevant documentation]. Figure 7 The figure shown is the small-signal equivalent circuit diagram of the cold field-cutoff condition in this invention.

[0095] The results of constructing a circuit using the extracted parasitic parameters in ADS (Advanced Design System) software and simulating it within the 0–40 GHz range are shown in [reference]. Figure 8 The figure shows a comparison of the measured and simulated values ​​of the small-signal equivalent circuit under the cold field-cutoff state within 0–40 GHz. Figure 8 This indicates that the measured values ​​and circuit simulation values ​​match well, and the parasitic parameter values ​​are accurately extracted. However, due to external factors such as testing equipment causing oscillations in the test RF data at high frequencies, errors in the simulation values ​​at high frequencies are unavoidable.

[0096] Step S3 also includes the following steps:

[0097] (1) Extraction of intrinsic parameters

[0098] After extracting the parasitic parameters, the intrinsic Y parameters of the device can be obtained by measuring the S-parameters of the device at the bias operating point and then embedding the external parasitic parameters using a matrix network transformation formula. The expressions for extracting the intrinsic parameters are shown below:

[0099]

[0100] G ds =Re(Y 22 +Y 12 )

[0101] g m =mag(Y 21 -Y 12 )

[0102]

[0103] DC testing revealed that the device operates at a bias gate voltage of V. gs =-1V, V ds At 10V, there is a maximum transconductance point, which is the operating point selected for the example device of this invention. The above formula yields the extracted intrinsic parameter curves for this bias within the 0–40GHz range, as shown below. Figure 9 As shown. Among them, Figure 9 (a) is C ds C gs C gd ; Figure 9 (b) is G ds g m ; Figure 9 (c) is R gs R gd , Figure 9 (d) is τ, with bias V within 0–40 GHz. gs =-1V, V ds Extracted intrinsic parameters at 10V.

[0104] In existing technologies, the average value extracted across the entire frequency band is used as a model parameter; however, inaccurate intrinsic parameter values ​​can increase model errors. To further improve the accuracy and stability of the circuit model, this invention proposes a quantitative error analysis method that can extract the values ​​of each internal intrinsic parameter more precisely.

[0105] from Figure 9 Each intrinsic parameter was obtained, and its average value across the entire frequency band was calculated, as shown in Table 1 below.

[0106] Table 1. Average values ​​of each intrinsic parameter across the entire frequency band.

[0107] <![CDATA[C gs ]]> 92.92fF <![CDATA[C gd ]]> 6.25fF <![CDATA[C ds ]]> 15.14fF <![CDATA[R gs ]]> 3.90Ω <![CDATA[R gd ]]> 169.14Ω <![CDATA[G ds ]]> 1.35mS <![CDATA[g m ]]> 50.84mS τ 1.23ps

[0108] The obtained external parasitic parameters and extracted internal intrinsic parameters are substituted into the circuit model for simulation. Furthermore, to further evaluate the accuracy of the small-signal equivalent circuit model, the model error is defined as:

[0109]

[0110] Where S Sim，ij These are simulation S-parameter data, S Mea，ij This is the test S-parameter data.

[0111] The simulation data and measured data results are as follows: Figure 10 As shown, where, Figure 10 (a) Comparison of the simulated S-parameters and the actual tested S-parameters of the device. Figure 10 (b) is the curve showing the error between the model simulation results and the actual measurement results as a function of frequency.

[0112] Depend on Figure 10 The results show that the model accuracy gradually decreases with increasing frequency, which does not meet the requirements of high-frequency device models. Let the difference between the upper and lower limits of the model error be γ, which reflects the stability of the model accuracy across the entire frequency band. In the figure above, γ is 7.465%, indicating that the model's performance across the entire frequency band is not accurate.

[0113] (2) Optimize the extracted intrinsic parameters

[0114] Therefore, the objective of this invention is to further reduce model error by optimizing the values ​​of intrinsic parameters. This requires optimizing the initial values ​​of the extracted intrinsic parameters. During the adjustment process, comparison revealed that adjusting parameter R alone... gs The value only significantly affects S 11 The parameter g has almost no effect on the other S-parameters. Similarly, the parameter g... m C gd and C ds It also shows the effect on specific S-parameters. See also Figure 11The figure shows the effect of adjusting a single intrinsic parameter value on the simulated S-parameters, where, Figure 11 (a) Display R gs -S 11 relation; Figure 11 (b) Display C gd -S 12 relation; Figure 11 (c) Display g m -S 21 relation; Figure 11 (d) Display C ds -S 22 relation. Figure 11 The specific effects of adjusting each parameter on the S-parameter are shown.

[0115] Depend on Figure 11 It is known that the simulation results of the small-signal model are largely affected by the values ​​of the four intrinsic parameters mentioned above. Therefore, this invention proposes a quantitative error analysis method. From Figure 9 It can be observed that the extracted values ​​of these four intrinsic parameters increase with increasing frequency, with R... gs For example, the average value across the entire frequency band is 3.90Ω, and at low frequencies R gs It has a minimum value of 2.78Ω and a maximum value of 4.63Ω at high frequencies. Now, let's define any eigenvalue (e.g., R) at a certain frequency. gs Let the extracted value be A, and let:

[0116]

[0117] The average value is the value across the entire frequency band, and α is the ratio of the extracted value at that frequency point to the average value across the entire frequency band. For example, the calculated range of α is 0.71 to 1.19. The extracted value A is substituted into the circuit model for simulation. Other parameters are taken as the average value across the entire frequency band. The upper and lower limits of the model accuracy error γ are adjusted to match α. (See [reference needed]). Figure 12 The diagram shows the effect of different intrinsic parameter values ​​on the stability of model error. It can be seen that when adjusting the values ​​of these four intrinsic parameters (which have the greatest impact on model accuracy), γ will have a minimum point when α > 1. This indicates that the small signal circuit model error is most stable at this time. Furthermore, since γ gradually increases with frequency, taking values ​​in the high-frequency range (α > 1) also meets the operating conditions of the device at high frequencies.

[0118] The values ​​of these four intrinsic parameters are defined as follows: Figure 12 The value of the minimum point of γ was determined, and combined with other previously extracted model parameters, the small-signal equivalent circuit model was substituted into ADS software for simulation. The optimized model and actual measurement results were obtained. (See [link to relevant documentation]). Figure 13 The figure shown is a schematic diagram comparing the errors of the circuit model after optimization based on the extracted intrinsic parameters.

[0119] from Figure 13 The study found that the stability of the small-signal circuit model after optimization of intrinsic parameters (i.e., γ = 3.46%) was significantly improved compared to the unoptimized model (γ = 7.465%), and the error accuracy of the model in the high-frequency range was as low as 2.01%, meeting the operating conditions of the device at high frequencies. This demonstrates that the present invention is effective in reducing the error rate and improving the stability of small-signal circuit models, and has certain practical value for further improving the accuracy of small-signal models.

[0120] The present invention proposes a method for extracting and optimizing intrinsic parameters of small-signal circuit models. Compared to existing methods that extract intrinsic parameters by taking the average value across the entire frequency band, this invention employs a quantitative error analysis method. It extracts intrinsic parameter values ​​at specific frequency points by quantitatively analyzing the error stability of the model. Furthermore, this invention identifies four component parameters that have the greatest impact on the simulation results among the intrinsic parameters within the model. Optimizing these parameters not only significantly improves the accuracy of the circuit model but also greatly enhances its error stability across the entire frequency band.

[0121] The above description of the embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

[0122] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined in this invention may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for extracting parameters from the equivalent circuit model of a GaN HEMT device, characterized in that, At least the following steps are included: Step S1: Model the GaN HEMT device as a small-signal equivalent circuit model; Step S2: Based on the model in Step S1, extract the external parasitic parameters; Step S3: Extract intrinsic parameters; In step S1, the equivalent circuit model includes external parasitic parameters and internal intrinsic parameters. The external parasitic parameters are unaffected by the applied bias voltage and include the parasitic capacitance C between the metal electrodes. pg C pd and C pgd External parasitic inductance L g L d and L s and external parasitic resistance R g R d and R s The intrinsic parameters are affected by the channel structure and bias conditions during device operation, including the channel resistance R. gs Gate-drain resistance R gd Drain-source output conductance G ds Capacitance C between each port gs C gd C ds ; transconductance g m Delay parameters ; Step S3 further includes the following steps: After extracting the external parasitic parameters, the S-parameters of the device are measured at the bias operating point, and the external parasitic parameters are embedded using the matrix network transformation formula to obtain the intrinsic Y-parameters of the device. The expressions for extracting the intrinsic parameters are shown below: ； ； The maximum transconductance point of the device is obtained as the selected operating point of the device, and the extracted intrinsic parameters under this bias within the range of 0~40 GHz are obtained by the above formula; The average value of each intrinsic parameter across the entire frequency band is calculated; the model error is defined as: ； in S Sim,ij These are simulation S-parameter data. S Mea,ij It is the test S-parameter data; Let the difference between the upper and lower limits of the model error be γ, and let the extracted value of a certain intrinsic parameter at a certain frequency be γ. A ,make: ； in, This is the average value of the intrinsic parameter across the entire frequency band. This is the ratio of the extracted value at this frequency point to the average value across the entire frequency band. Extracting a value from a certain intrinsic parameter A Substitute the circuit model into the simulation, take the average value of other intrinsic parameters across the entire frequency band, and calculate different... The corresponding upper and lower limits of model accuracy error ,Pick The value of the lowest point is used as the extracted value of the intrinsic parameter; all intrinsic parameters are extracted in this way.

2. The parameter extraction method for the equivalent circuit model of GaN HEMT devices according to claim 1, characterized in that, The GaN HEMT device has a gate length of 100 nm and a total gate width of 75 μm, of which the single-finger gate width is 37.5 μm and the gate index is 2.

3. The parameter extraction method for the equivalent circuit model of GaN HEMT devices according to claim 2, characterized in that, In step S2, the extraction of external parasitic capacitance includes the following steps: Under low-frequency conditions and channel-off state, the small-signal equivalent circuit of GaN HEMT device is simplified to a circuit model containing only capacitors. The S-parameters of the test device after de-embedding are given. The imaginary part of the Y-parameters of the de-embedding device has a linear relationship with the angular frequency as shown in the following formula: ； The extraction of parasitic capacitance is optimized using an annealing algorithm, wherein... C pg , C pd , C pgd External parasitic capacitance C gs , C ds , C gd This represents the channel capacitance under off-state conditions. When the device is in the off-state, the depletion region widths of the gate-source and gate-drain are assumed to be the same. C gs = C gd = C b and C ds =0; First, initialize capacitor C. pg C pd C b The value is set to a minimum, and the value is gradually adjusted by comparing the error between simulation calculations and measured data to finally obtain the optimal capacitance value. Next, optimize C. pgd The initial value was set to 0, and C was obtained by adjusting it to the minimum error through simulation. pgd Finally, optimize C. gs and C gd C is obtained through annealing algorithm gs C gd Finally, the optimized external parasitic capacitance value is obtained.

4. The parameter extraction method for the equivalent circuit model of GaN HEMT devices according to claim 2, characterized in that, Step S2, when extracting the external parasitic inductance, includes the following steps: Under cold-cutoff conditions, the equivalent circuit model at high frequencies neglects capacitive reactance and considers the channel distributed resistance R. c The influence of this is addressed by deriving the expression for the imaginary part of the Z-parameters in the equivalent circuit, and then... x-axis, imaginary part Plot the curve on the ordinate; from this, the three parasitic inductances can be extracted from the slope of the curve. The specific extraction formula for the value is as follows: ； in, R g , R s , R d This is the parasitic resistance value. L g , L s , L d The parasitic inductance value, C g , C s , C d The parasitic capacitance value; multiply both sides of the above three equations by the angular frequency. It can be obtained Z The imaginary part of the parameter is: ； by x-axis A straight line is drawn with the imaginary part of the equation as the vertical axis, and the slope of the line is the extracted value of the three parasitic inductances.

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