Grid wire repairing circuit and method and display panel

Abstract

The invention discloses a grid line repairing circuit and method and a display panel, and relates to the technical field of display, the circuit comprises a logic control module, a double-broken-line detection module and a plurality of grid lines, the logic control module provides broken line detection signals for the double-broken-line detection module, and the double-broken-line detection module provides broken line detection signals for the grid lines; after receiving the disconnection detection signal sent by the logic control module, the double-disconnection detection module determines a grid disconnection fault according to a preset wiring anomaly detection mode and the disconnection detection signal, and sends the grid disconnection fault to the logic control module, so that the logic control module performs disconnection repair operation according to the grid disconnection fault. According to the invention, the display quality of the panel is improved by optimizing the circuit design of the broken line repair of the grid line.

Description

Technical Field

[0001] This application relates to the field of display technologies, and in particular, to a gate trace repair circuit, a method thereof, and a display panel. Background Art

[0002] In the field of liquid crystal display technologies, especially for large-sized display panels with high resolutions and high refresh rates, such as UHD (Ultra High Definition), 5K, 8K, etc., and products adopting the DRD (dual rate data) architecture and supporting high refresh rates such as 100Hz to 240Hz, higher requirements are put forward for the stability and reliability of Gate traces (i.e., gate traces).

[0003] The Gate (gate) trace design of large-sized display panels usually adopts a horizontal double-drive mode, that is, the scan lines on both sides are interconnected to ensure stable signal transmission. However, in the actual production and manufacturing process, due to factors such as thin film transistor abnormalities or Gate trace corrosion and fracture, the problems of Gate trace disconnection or dark lines frequently occur, and the specific position of the disconnection is extremely uncertain and may appear at any position on the panel, which undoubtedly increases the difficulty of repairing Gate trace disconnections. The current mainstream repair solutions rely on manual microscope observation and laser repair technologies, which are not only inefficient and costly, but also face multiple challenges such as poor connection, unstable repair effect, difficult selection of OP (Operational Amplifier), signal delay, and limited repair line resources. Especially when the Gn signals (i.e., gate scan signals) on both sides of the double drive are disconnected, the existing solutions simply cannot achieve effective repair.

[0004] Therefore, how to optimize the circuit design for repairing Gate trace disconnections to improve the display quality of the display panel is a technical problem that needs to be solved urgently at present. Summary of the Invention

[0005] The main purpose of this application is to provide a gate trace repair circuit, a method thereof, and a display panel, aiming to optimize the circuit design for repairing Gate trace disconnections to improve the display quality of the display panel.

[0006] To achieve the above purpose, this application provides a gate trace repair circuit, and the gate trace repair circuit includes: Multiple gate traces; A logic control module, which is configured to provide a disconnection detection signal; Double open - circuit detection module. One open - circuit detection module in the double open - circuit detection module is the first open - circuit detection component, and the other open - circuit detection module in the double open - circuit detection module is the second open - circuit detection component. Two sides of the first open - circuit detection component are electrically connected to the first voltage side of the logic control module and the first wire ends of each of the gate traces respectively. Two sides of the second open - circuit detection component are electrically connected to the second voltage side of the logic control module and the second wire ends of each of the gate traces respectively. The control ends of the first open - circuit detection component and the second open - circuit detection component are electrically connected to the detection control end of the logic control module respectively; The double open - circuit detection module is configured to determine a gate open - circuit fault according to a preset wire - path abnormal detection mode and the open - circuit detection signal after receiving the open - circuit detection signal sent by the logic control module, and send the gate open - circuit fault to the logic control module, so that the logic control module enables the logic control module to perform an open - circuit repair operation according to the gate open - circuit fault.

[0007] In one embodiment, the first open - circuit detection component includes a first shift register and first thin - film transistors corresponding to each of the first wire ends. Gate terminals of each of the first thin - film transistors are electrically connected to the driving side of the first shift register. First path ends of each of the first thin - film transistors are all electrically connected to the first voltage side. Each of the first wire ends is electrically connected to the second path end of the corresponding first thin - film transistor; The second open - circuit detection component includes a second shift register and second thin - film transistors corresponding to each of the second wire ends. Gate terminals of each of the second thin - film transistors are electrically connected to the driving side of the second shift register. First path ends of each of the second thin - film transistors are all electrically connected to the second voltage side. Each of the second wire ends is electrically connected to the second path end of the corresponding second thin - film transistor.

[0008] In one embodiment, the gate trace repair circuit includes a bilateral gate driving module. One gate driving module in the bilateral gate driving module is the first gate driving component, and the other gate driving module in the bilateral gate driving module is the second gate driving component; The first gate driving component is arranged on one side of the first shift register close to multiple gate traces arranged along the row direction. The second gate driving component is arranged on one side of the second shift register close to multiple gate traces arranged along the row direction; The first gate driving component is electrically connected to the first wire end of each of the gate traces respectively. The second gate driving component is electrically connected to the second wire end of each of the gate traces respectively.

[0009] In addition, to achieve the above object, the present application further provides a gate trace repair method, which is applied to the gate trace repair circuit described in any one of the above, and the gate trace repair method includes: Obtain a disconnection detection signal of the logic control module through the double disconnection detection module; Determine a gate disconnection fault according to a preset trace abnormality detection mode and the disconnection detection signal, and enable the logic control module to perform a disconnection repair operation according to the gate disconnection fault.

[0010] In an embodiment, when the trace abnormality detection mode is a disconnection detection mode, the step of determining a gate disconnection fault according to a preset trace abnormality detection mode and the disconnection detection signal includes: In response to the disconnection detection signal, sequentially conduct the connection paths on both sides of the same gate trace to the double disconnection detection module to form a disconnection detection path from the first disconnection detection component to the second disconnection detection component via the gate trace; When the first voltage side of the logic control module sequentially provides a first voltage to the gate trace, detect whether a voltage value is output after the first voltage passes through the disconnection detection path through the second voltage side of the logic control module; If no voltage value is output after the first voltage passes through the disconnection detection path, determine that the gate disconnection fault is a break in the body of the gate trace.

[0011] In an embodiment, when the trace abnormality detection mode is a single-sided fault detection mode, the step of determining a gate disconnection fault according to a preset trace abnormality detection mode and the disconnection detection signal includes: In response to the disconnection detection signal, enable the first disconnection detection component not to work when the first gate driving component provides a first gate voltage signal to the gate target trace, and synchronously enable the second disconnection detection component to be connected to the gate target trace when the second gate driving component does not work, so as to form a first single-sided detection path from the first gate driving component to the second disconnection detection component via the gate target trace, and determine the voltage output result after the first gate voltage signal passes through the first single-sided detection path; When the trace abnormality detection mode is switched from the single-sided fault detection mode to the double-sided fault detection mode, determine a gate disconnection fault according to the double-sided fault detection mode and the voltage output result.

[0012] In an embodiment, the step of determining a gate disconnection fault according to the double-sided fault detection mode and the voltage output result includes: Enable the second disconnection detection component to be inoperative when the second gate driving component provides a second gate voltage signal to the gate target trace, and simultaneously enable the first disconnection detection component to be connected to the gate target trace when the first gate driving component is inoperative, so as to form a second single-sided detection path from the second gate driving component through the gate target trace to the first disconnection detection component; If no voltage value is output after the second gate voltage signal passes through the second single-sided detection path, and the voltage output result is that no voltage value is output after the first gate voltage signal passes through the first single-sided detection path, it is determined that the gate disconnection fault is a failure of the bilateral gate driving module; If no voltage value is output after the second gate voltage signal passes through the second single-sided detection path, and the voltage output result is that a voltage value is output after the first gate voltage signal passes through the first single-sided detection path, it is determined that the gate disconnection fault is a failure of the second gate driving component; If a voltage value is output after the second gate voltage signal passes through the second single-sided detection path, and the voltage output result is that no voltage value is output after the first gate voltage signal passes through the first single-sided detection path, it is determined that the gate disconnection fault is a failure of the first gate driving component.

[0013] In one embodiment, the steps of enabling the logic control module to perform a disconnection repair operation according to the gate disconnection fault include: Control the logic control module to respond to the gate disconnection fault being a break in the body of the gate trace, determine the display partition where the gate disconnection is located, and determine the compensation average voltage of the gate disconnection according to the block compensation voltage corresponding to each gate trace in the display partition and the number of gate lines of all the gate traces in the display partition; When connecting the gate disconnection to the first disconnection detection component, simultaneously connect the gate disconnection to the second disconnection detection component, so that when the logic control module provides the compensation average voltage to the side of the gate disconnection close to the first disconnection detection component, the compensation average voltage is simultaneously provided to the side of the gate disconnection close to the second disconnection detection component.

[0014] In one embodiment, the steps of enabling the logic control module to perform a disconnection repair operation according to the gate disconnection fault include: Control the logic control module to respond to the gate disconnection fault being a failure of the first gate driving component. When providing a second gate scanning voltage to the gate target trace through the second gate driving component, simultaneously connect the gate target trace to the first disconnection detection component, so that the logic control module provides a first voltage identical to the second gate scanning voltage to the gate target trace through the first disconnection detection component; or, When the logic control module controls the second gate driver to fail in response to the gate wire break fault, when providing a first gate scan voltage to the gate target trace through the first gate driver, the connection between the gate target trace and the second wire break detection component is synchronously turned on, so that the logic control module provides a second voltage identical to the first gate scan voltage to the gate target trace via the second wire break detection component; or, When the logic control module controls the bilateral gate driver module to fail in response to the gate wire break fault, when turning on the connection between the gate target trace and the first wire break detection component, the connection between the gate target trace and the second wire break detection component is synchronously turned on, so that when the logic control module provides a repair compensation voltage to the side of the gate target trace close to the first wire break detection component, the repair compensation voltage is synchronously provided to the side of the gate target trace close to the second wire break detection component.

[0015] In addition, to achieve the above object, the present application further provides a display panel, which includes a color filter substrate, a liquid crystal layer, and an array substrate. The liquid crystal layer is disposed between the array substrate and the color filter substrate, and the array substrate includes the gate trace repair circuit described in any one of the above.

[0016] In order to optimize the circuit design for repairing broken gate traces and improve the display quality of a display panel, the present application provides a gate trace repair circuit. Through the collaborative work of a dual broken line detection module integrating a first broken line detector and a second broken line detector and a logic control module, the gate trace repair circuit realizes efficient and accurate detection and full-automatic repair of broken gate trace faults. Specifically, the first broken line detector is electrically connected between the first voltage side of the logic control module and the first trace ends of all gate traces, and the second broken line detector is electrically connected between the second voltage side of the logic control module and the second trace ends of all gate traces. Next, the dual broken line detection module controls the first broken line detector and the second broken line detector to work respectively based on the broken line detection signal provided by the detection control end of the logic control module and a preset trace abnormality detection mode, so as to synchronously detect or individually detect both ends of each gate trace, and then quickly locate whether the broken gate trace fault is a break in the body of the gate trace, a failure of the single-side gate drive module of the gate trace, or a failure of the double-side gate drive modules of the gate trace. Thus, the accuracy and efficiency of detecting broken gate trace faults are greatly improved. Compared with the traditional detection method, there is no need for manual row-by-row inspection, saving a large amount of time and labor costs, and at the same time avoiding possible omissions in manual detection, providing accurate and reliable data support for the subsequent broken line repair work of the logic control module. Subsequently, the logic control module realizes a fully automated broken line repair operation based on the broken gate trace fault sent by the dual broken line detection module, compressing the process that takes several hours for traditional manual laser repair to be automatically completed in milliseconds, significantly improving the repair efficiency of the faulty gate trace, making the performance of the gate trace after repairing the broken gate trace fault consistent with that of a normal gate trace, and thus effectively improving the display quality of the display panel applied to this gate trace repair circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings herein are incorporated into and constitute a part of this specification, showing embodiments consistent with the present application and, together with the specification, are used to explain the principles of the present application.

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0019] Figure 1 is a schematic diagram of a dual-drive structure in the horizontal direction of the display panel; Figure 2 is a block diagram of the first embodiment of the gate trace repair circuit of the present application; Figure 3 is a schematic diagram of the circuit principle of the gate trace repair circuit involved in the embodiment solution of the present application; Figure 4 It is a schematic diagram of GOA damage detection involved in the solution of the embodiment of the present application; Figure 5 It is a schematic diagram of the circuit of the gate driving module involved in the solution of the embodiment of the present application; Figure 6 Schematic diagram of the gate breakage partition repair structure involved in the solution of the embodiment of the present application; Figure 7 It is a schematic diagram of the breakage repair waveform involved in the solution of the embodiment of the present application; Figure 8 It is a schematic diagram of the structure of the display device involved in the solution of the embodiment of the present application.

[0020] Explanation of the reference numerals in the drawings: 10, logic control module; 20, double breakage detection module; 21, first breakage detection component; 22, second breakage detection component; 210, first shift register; T1, first thin film transistor; 220, second shift register; T2, second thin film transistor; 31, first gate driving component; 32, second gate driving component; T3, third thin film transistor; T4, fourth thin film transistor; T5, fifth thin film transistor; T6, sixth thin film transistor.

[0021] The realization, functional features and advantages of the purpose of the present application will be further described with reference to the embodiments and the accompanying drawings. Specific embodiments

[0022] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0023] It should be noted that if there are directional indications (such as up, down, left, right, front, back...) involved in the embodiments of the present application, the directional indications are only used to explain the relative position relationship and movement conditions between components in a specific posture (as shown in the drawings). If the specific posture changes, the directional indications will also change accordingly.

[0024] In addition, if the descriptions such as "first" and "second" are involved in the embodiments of the present application, the descriptions of "first", "second", etc. are for descriptive purposes only, and should not be construed as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions between various embodiments may be combined with each other, but it must be based on the ability of those of ordinary skill in the art to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present application.

[0025] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application.

[0026] In the field of liquid crystal display technology, especially for large-size display panels with high resolution and high refresh rate, such as UHD (Ultra High Definition), 5K, 8K, etc., and products adopting the DRD architecture and supporting high refresh rates such as 100Hz to 240Hz, higher requirements are put forward for the stability and reliability of Gate traces (i.e., gate traces).

[0027] In the manufacturing process of large-size display panels, the Gate trace design often adopts the horizontal double-drive mode, that is, the signal is stably transmitted by using the scanning lines connected to each other on both sides. This horizontal double-drive mode is in Figure 1It is visually demonstrated, where two GOA (Gate Driven on Array) units constitute the core of this dual-drive mode. However, in the actual production process, problems such as broken or dark Gate traces may occur, resulting in only one-sided Gate lines being able to be normally turned on. For small-sized and low-resolution panels, the problem of broken lines may not be very obvious. But in the current market, high-resolution products such as UHD, 5K, 8K, and large-sized TVs with high refresh rates of 100Hz, 120Hz, 144Hz, 165Hz, 240Hz, etc. using the DRD architecture have become the mainstream. These products face shorter charging times, and the signal transmission distance from one side scan line to the other side scan line of the large-sized panel is relatively long. Therefore, when a break occurs, the sub-pixels on the side of the broken part may not reach the target gray-scale voltage level due to insufficient charging, resulting in obvious boundary differences during display. Given the high cost and high repair value of such products, accurate positioning and repair of the broken line position are particularly important. However, the position of the broken line is uncertain and may occur in any position area of the panel, which undoubtedly increases the difficulty of repair.

[0028] Existing Gate trace break repair solutions mainly rely on microscope observation and laser repair technology. The existing technical process includes: first, using a microscope to locate the specific broken scan line, and then connecting the broken scan line to the repair line through laser technology to establish a repair path. Finally, the Gn signal is collected from the side without abnormalities in the dual-drive, processed by an operational amplifier (OP), and then sent back. However, there are many drawbacks in the existing Gate trace break repair solutions: 1. For each panel, it is necessary to manually observe and determine the specific position of the broken line before performing laser repair, which is inefficient and costly; 2. There may be poor connection during the laser connection process, resulting in poor repair effects; 3. The required operational amplifier needs to withstand a large pressure difference, making it difficult to select the type; 4. Delays will be introduced when the signal is collected and then sent back; 5. If the Gn signals on both sides of the dual-drive are disconnected, effective repair cannot be carried out; 6. Limited by the number of glass traces, each repair of a Gate break requires occupying a repair line, so at most only 1 or 2 broken lines can be repaired.

[0029] The above content is only used to assist in understanding the technical solution of this application and does not represent an admission that the above content is prior art.

[0030] To solve the technical defects existing in the above content, this application provides a gate trace repair circuit, its method, and a display panel.

[0031] An embodiment of this application provides a gate trace repair circuit. Referring to Figure 2 as shown, Figure 2It is a structural block diagram of the first embodiment of the gate trace repair circuit of the present application. The gate trace repair circuit includes: Multiple gate traces.

[0032] In this embodiment, referring to Figure 2 , Figure 2 G1, G2, G3, G4, G5, G6, G7, ……, Gn-1, Gn, Gn+1 shown can represent multiple gate traces.

[0033] Logic control module 10, the logic control module 10 is configured to provide a broken wire detection signal.

[0034] In this embodiment, the logic control module 10 set in the present application is configured to provide a broken wire detection signal to the double broken wire detection module 20, thereby significantly improving the automation degree and accuracy of the broken wire detection of the gate traces in the display panel, effectively reducing the need for manual intervention. At the same time, it also significantly increases the ability of the logic control module 10 to cooperate with the double broken wire detection module 20 to quickly respond to and efficiently repair the broken wire fault of the gate traces.

[0035] In a specific embodiment, the logic control module 10 can be directly set on the Figure 3 PCBA (Printed Circuit Board Assembly) board shown. The logic control module 10 can also be encapsulated in a SOC chip (System-on-a-Chip), and the SOC chip is set on the PCBA board. And Figure 3 The circles R, G, and B shown respectively represent red sub-pixels, green sub-pixels, and blue sub-pixels.

[0036] Double broken wire detection module 20. One broken wire detection module in the double broken wire detection module 20 is the first broken wire detection component 21, and the other broken wire detection module in the double broken wire detection module 20 is the second broken wire detection component 22. The two sides of the first broken wire detection component 21 are respectively electrically connected to the first voltage side of the logic control module 10 and the first wire ends of each of the gate traces. The two sides of the second broken wire detection component 22 are respectively electrically connected to the second voltage side of the logic control module 10 and the second wire ends of each of the gate traces. The control ends of the first broken wire detection component 21 and the second broken wire detection component 22 are respectively electrically connected to the detection control end of the logic control module 10.

[0037] In this embodiment, the double broken wire detection module 20 set in the present application realizes the efficient detection of the broken wire fault of the gate traces by integrating the first broken wire detection component 21 and the second broken wire detection component 22. Specifically, referring to Figure 2, the first disconnection detection component 21 is electrically connected between the first voltage side of the logic control module 10 (i.e., the V1 side shown in Figure 2 ) and the first wiring ends of all gate traces, and the second disconnection detection component 22 is electrically connected between the second voltage side of the logic control module 10 (i.e., the V2 side shown in Figure 2 ) and the second wiring ends of all gate traces, and controls the operation of the first disconnection detection component 21 and the second disconnection detection component 22 respectively based on the disconnection detection signal provided by the detection control end of the logic control module 10, so as to synchronously detect or separately detect both ends of each gate trace, thereby quickly locating the gate disconnection fault and determining whether it is a break in the body of the gate trace, or an abnormality in the first gate driver near the first wiring end, or an abnormality in the second gate driver near the second wiring end, or even abnormalities in the gate drivers on both sides of the gate trace, thus greatly improving the accuracy and efficiency of gate disconnection fault detection. Compared with the traditional detection method, it does not require manual row-by-row inspection, saving a large amount of time and labor costs, and at the same time avoiding possible omissions in manual detection, providing accurate and reliable data support for the subsequent disconnection repair work of the logic control module 10.

[0038] The dual disconnection detection module 20 is configured to determine a gate disconnection fault according to a preset trace abnormality detection mode and the disconnection detection signal after receiving the disconnection detection signal sent by the logic control module 10, and send the gate disconnection fault to the logic control module 10 for the logic control module 10 to enable the logic control module to perform a disconnection repair operation according to the gate disconnection fault.

[0039] In this embodiment, after receiving the disconnection detection signal sent by the logic control module 10, the dual disconnection detection module 20 realizes full-scenario coverage diagnosis of the gate trace fault based on a preset trace abnormality detection mode (including a disconnection detection mode, a unilateral fault detection mode, and a bilateral fault detection mode) and the disconnection detection signal; next, after the dual disconnection detection module 20 real-time transmits the gate disconnection fault to the logic control module 10, the logic control module 10 automatically switches the disconnection repair compensation path according to the specific fault type corresponding to the gate disconnection fault, realizing fully automated disconnection repair operation, compressing the process that takes several hours for traditional manual laser repair to be automatically completed in milliseconds, significantly improving the repair efficiency of the faulty gate trace, making the performance of the gate trace after gate disconnection fault repair consistent with that of a normal gate trace, and thus effectively improving the display quality of the display panel applied to this gate trace repair circuit.

[0040] Further, in some feasible embodiments, referring to Figure 3, the first open-circuit detection component 21 includes a first shift register 210 and first thin-film transistors T1 corresponding to each of the first wiring ends. The gate electrodes of each of the first thin-film transistors T1 are electrically connected to the driving side of the first shift register 210. The first conduction ends of each of the first thin-film transistors T1 are all electrically connected to the first voltage side. Each of the first wiring ends is electrically connected to the second conduction end of the corresponding first thin-film transistor T1.

[0041] In this embodiment, referring to Figure 3 , the present application is configured such that the first open-circuit detection component 21 integrates the first shift register 210 and a plurality of first thin-film transistors T1, and an electrical connection is established between the driving side of the first shift register 210 and the gate electrodes of the first thin-film transistors T1 whose first wiring ends are electrically connected to each gate wiring, so that the first shift register 210 drives the corresponding first thin-film transistors T1 in each row to switch from the cut-off state to the conduction state in accordance with a preset gate row driving sequence, so as to determine that each first wiring end of the gate wiring can establish a path with the first voltage side of the logic control module 10 through the corresponding first thin-film transistor T1.

[0042] It should be noted that the integration of the first shift register 210 and a plurality of first thin-film transistors T1 in the first open-circuit detection component 21 can be represented by Figure 3 the first shift register 210, the first thin-film transistors T1-(n - 1), the first thin-film transistor T1-n, and the first thin-film transistor T1-(n + 1) shown. The number of the first thin-film transistors T1 is the same as the number of gate wirings, and each first thin-film transistor T1 is correspondingly connected to one gate wiring. Specifically, the first thin-film transistor T1-(n - 1) is correspondingly connected to the first wiring end of the gate wiring Gn-1, the first thin-film transistor T1-n is correspondingly connected to the first wiring end of the gate wiring Gn, and the first thin-film transistor T1-(n + 1) is correspondingly connected to the first wiring end of the gate wiring Gn+1.

[0043] The second open-circuit detection component 22 includes a second shift register 220 and second thin-film transistors T2 corresponding to each of the second wiring ends. The gate electrodes of each of the second thin-film transistors T2 are electrically connected to the driving side of the second shift register 220. The first conduction ends of each of the second thin-film transistors T2 are all electrically connected to the second voltage side. Each of the second wiring ends is electrically connected to the second conduction end of the corresponding second thin-film transistor T2.

[0044] In this embodiment, referring to Figure 3, in the present application, the second disconnection detection component 22 is integrated with a second shift register 220 and a plurality of second thin film transistors T2, and an electrical connection is established between the driving side of the second shift register 220 and the gate terminals of the second thin film transistors T2 whose drain terminals are electrically connected to the second wiring ends of each gate trace, so that the second shift register 220 drives the corresponding second thin film transistors T2 in each row to switch from the cut-off state to the conducting state in accordance with a preset gate row driving sequence, so as to ensure that the second wiring end of each gate trace can establish a path with the second voltage side of the logic control module 10 through the corresponding second thin film transistor T2.

[0045] It should be noted that the second disconnection detection component 22 integrated with the second shift register 220 and a plurality of second thin film transistors T2 can be represented by Figure 3 the second shift register 220, the second thin film transistors T2-(n - 1), the second thin film transistors T2-n, and the second thin film transistors T2-(n + 1) shown. The number of the second thin film transistors T2 is the same as the number of gate traces, and each second thin film transistor T2 is correspondingly connected to the second wiring end of a gate trace. Specifically, the second thin film transistor T2-(n - 1) is correspondingly connected to the second wiring end of the gate trace Gn-1, the second thin film transistor T2-n is correspondingly connected to the second wiring end of the gate trace Gn, and the second thin film transistor T2-(n + 1) is correspondingly connected to the second wiring end of the gate trace Gn+1.

[0046] Furthermore, in some other feasible embodiments, referring to Figure 3 , the gate trace repair circuit includes a bilateral gate driving module. One gate driving module in the bilateral gate driving module is a first gate driving component 31, and the other gate driving module in the bilateral gate driving module is a second gate driving component 32; the first gate driving component 31 is disposed on one side of the first shift register 210 close to a plurality of the gate traces arranged along the row direction, and the second gate driving component 32 is disposed on one side of the second shift register 220 close to a plurality of the gate traces arranged along the row direction; the first gate driving component 31 is electrically connected to the first wiring end of each gate trace respectively, and the second gate driving component 32 is electrically connected to the second wiring end of each gate trace respectively.

[0047] In this embodiment, referring to Figure 2 , for large-size display panels with high resolution and high refresh rate, such as UHD, 5K, 8K, etc., and display panels adopting the DRD architecture and supporting high refresh rates such as 100Hz to 240Hz, GOA units (i.e., the first gate driving component and the second gate driving component) with the same driving timing are provided at both ends of each gate trace. Specifically, referring to Figure 4, the gate trace repair circuit provided in this application enables the first shift register 210 to turn off the first thin-film transistor T1-n electrically connected to the gate trace Gn when the first gate driver 31 provides the first gate voltage signal (i.e., GN_L shown in Figure 4 ) to the gate target line (i.e., the gate trace Gn shown in Figure 4 ), and synchronously enables the second shift register 220 to turn on the second thin-film transistor T2-n connected to the gate trace Gn when the second gate driver 32 is not working, thereby forming a first unilateral detection path from the first gate driver 31 through the gate trace Gn to the second shift register 220 to detect whether the first gate driver fails, so as to achieve the detection of the open-circuit fault of the first gate driver.

[0048] Alternatively, the gate trace repair circuit provided in this application enables the second shift register 220 to turn off the second thin-film transistor T2-n electrically connected to the gate trace Gn when the second gate driver 32 provides the second gate voltage signal (i.e., GN_R shown in Figure 4 ) to the gate target line (i.e., the gate trace Gn shown in Figure 4 ), and synchronously enables the first shift register 210 to turn on the first thin-film transistor T1-n connected to the gate trace Gn when the first gate driver 31 is not working, thereby forming a second unilateral detection path from the second gate driver 32 through the gate trace Gn to the first shift register 210 to detect whether the second gate driver fails, so as to achieve the detection of the open-circuit fault of the second gate driver.

[0049] That is to say, the gate trace repair circuit provided in this application, through the cooperative control of the first / second shift register on the corresponding side gate driving module, cuts off the thin-film transistor on the same side and turns on the thin-film transistor on the opposite side to form a unidirectional detection loop when the unilateral gate driving module drives, improving the precise positioning accuracy of the open-circuit fault to the level of the unilateral driving unit, and effectively avoiding misjudgment caused by signal interference in the traditional bidirectional driving mode.

[0050] Furthermore, in some other feasible embodiments, referring to Figure 5 , Figure 5It is a schematic diagram of a gate driving module circuit involved in the embodiment of the present application. The first gate driving component and the second gate driving component are both the same gate driving module. The gate driving module includes a third thin-film transistor T3, a fourth thin-film transistor T4, a fifth thin-film transistor T5, and a sixth thin-film transistor T6. The first conduction end and the gate end of the third thin-film transistor T3 are respectively electrically connected to the first gate scanning end. The second conduction end of the third thin-film transistor T3 is respectively electrically connected to the gate end of the fourth thin-film transistor T4 and the first conduction end of the fifth thin-film transistor T5. The first conduction end of the fourth thin-film transistor T4 is electrically connected to the stage output end. The second conduction end of the fourth thin-film transistor T4 is electrically connected to the first conduction end of the sixth thin-film transistor T6. The gate end of the sixth thin-film transistor T6 is electrically connected to the gate end of the fifth thin-film transistor T5. The second conduction end of the fifth thin-film transistor T5 and the second conduction end of the sixth thin-film transistor T6 are respectively electrically connected to the low potential end. The connection node where the second conduction end of the fourth thin-film transistor T4 is electrically connected to the first conduction end of the sixth thin-film transistor T6 is electrically connected to the second gate scanning end. The connection node where the gate end of the sixth thin-film transistor T6 is electrically connected to the gate end of the fifth thin-film transistor T5 is electrically connected to the third scanning end.

[0051] In this embodiment, Figure 5 The 4 shown thin-film transistors (the third thin-film transistor T3, the fourth thin-film transistor T4, the fifth thin-film transistor T5, and the sixth thin-film transistor T6) form a single-stage GOA basic circuit (i.e., the gate driving module). Among them, the second gate scanning end is used to provide the gate scanning signal of the current row gate trace (i.e., Figure 5The output turn-on signal G(N) of the current row gate trace shown, the step-by-step output terminal is used to provide the signal CK / XCK for controlling the step-by-step output of the signal G(N), and the signal VSS provided by the low potential terminal is set to pull down the low potential of the signal G(N) to the output of the low potential terminal; the first gate scanning terminal is used to provide the signal G(N-1) of the previous row gate trace of the current row gate trace; the third gate scanning terminal is used to provide the signal G(N+1) of the next row gate trace of the current row gate trace. Exemplarily, when the gate driving component is working normally, the third thin film transistor T3 drives the voltage provided by the first gate scanning terminal to the gate terminal of the fourth thin film transistor T4 under the action of the signal G(N-1), so as to switch the fourth thin film transistor T4 from the cut-off state to the conducting state, enabling the second gate scanning terminal to be pulled up to the voltage value corresponding to the signal CK / XCK in the step-by-step output terminal, so as to provide the signal G(N) for the current row gate trace, until the fifth thin film transistor T5 and the sixth thin film transistor T6 are enabled to conduct simultaneously under the drive of the signal G(N+1) provided by the third gate scanning terminal, so as to pull down the signal G(N-1) provided by the first gate scanning terminal and the signal G(N) provided by the second gate scanning terminal to the low potential terminal, so as to end the gate drive of each sub-pixel electrically connected to the current row gate trace. However, when the gate driving component works abnormally, that is Figure 5 the third thin film transistor T3 and the fourth thin film transistor T4 shown are abnormal. Exemplarily, if Figure 5 the third thin film transistor T3 shown is damaged and cannot provide a gate drive signal to the gate terminal of the fourth thin film transistor T4 under the action of the signal G(N-1), and / or Figure 5 the fourth thin film transistor T4 shown cannot conduct under the gate drive signal provided when the third thin film transistor T3 is normal due to damage, resulting in no signal G(N) output at the second gate scanning terminal, and further resulting in abnormal display of each sub-pixel electrically connected to the current row gate trace, there is a dark line or a broken line situation.

[0052] In summary, in order to optimize the circuit design for repairing broken gate traces to improve the display quality of a display panel, the present application provides a gate trace repair circuit. The gate trace repair circuit realizes efficient and accurate detection and full-automatic repair of gate trace breakage faults through the collaborative work of a dual breakage detection module 20 integrating a first breakage detection component 21 and a second breakage detection component 22 and a logic control module 10. Specifically, the first breakage detection component 21 is electrically connected between the first voltage side of the logic control module 10 and the first trace ends of all gate traces, and the second breakage detection component 22 is electrically connected between the second voltage side of the logic control module 10 and the second trace ends of all gate traces; Next, the dual breakage detection module 20 controls the first breakage detection component 21 and the second breakage detection component 22 to work respectively based on the breakage detection signal provided by the detection control end of the logic control module 10 and a preset trace abnormality detection mode, so as to synchronously detect or separately detect both ends of each gate trace, and then quickly locate whether the gate breakage fault is a break in the body of the gate trace, or a failure of the gate driving module on one side of the gate trace, or a failure of the gate driving modules on both sides of the gate trace, thereby greatly improving the accuracy and efficiency of gate breakage fault detection. Compared with the traditional detection method, there is no need for manual row-by-row inspection, saving a large amount of time and labor costs, and at the same time avoiding possible omissions in manual detection, providing accurate and reliable data support for the subsequent breakage repair work of the logic control module 10; Subsequently, the logic control module 10 realizes a fully automatic breakage repair operation according to the gate breakage fault sent by the dual breakage detection module 20, compressing the process that takes several hours in traditional manual laser repair to be automatically completed in milliseconds, significantly improving the repair efficiency of the faulty gate trace, making the performance of the gate trace after repairing the gate breakage fault consistent with that of a normal gate trace, and thus effectively improving the display quality of the display panel applied to the gate trace repair circuit.

[0053] Furthermore, based on the first embodiment of the gate trace repair circuit of the present application, a second embodiment of the gate trace repair method of the present application is proposed.

[0054] The gate trace repair method of the present application is applied to the gate trace repair circuit in any of the above items. The gate trace repair method of the present application is executed by a terminal device (such as a display device) that drives and controls the gate trace repair circuit. The gate trace repair method of the present application includes the following implementation steps S10 to step S20.

[0055] Step S10: Obtain the breakage detection signal of the logic control module through the dual breakage detection module.

[0056] In this embodiment, during the device startup and power-on stage of the display panel, the double-open wire detection module receives the open wire detection signal actively provided by the logic control module, so that the double-open wire detection module automatically performs gate open wire fault detection under the drive of the open wire detection signal, thereby effectively reducing the dependence on manual intervention and greatly improving the automation degree and accuracy of the open wire detection of the gate traces in the display panel.

[0057] Step S20: Determine the gate open wire fault according to the preset trace anomaly detection mode and the open wire detection signal, and enable the logic control module to perform open wire repair operation according to the gate open wire fault.

[0058] In this embodiment, after receiving the open wire detection signal sent by the logic control module, the double-open wire detection module realizes the full-scenario coverage diagnosis of the gate trace fault based on the preset trace anomaly detection mode (including the open wire detection mode, the single-side fault detection mode, and the double-side fault detection mode) and the open wire detection signal; Next, after the double-open wire detection module transmits the gate open wire fault to the logic control module in real time, the logic control module automatically switches the open wire repair compensation path according to the specific fault type corresponding to the gate open wire fault (that is, the break of the gate trace body, the failure of the single-side gate drive module of the gate trace, or the failure of the double-side gate drive module of the gate trace), realizing a fully automated open wire repair operation, so as to compress the process of traditional manual laser repair that takes several hours to milliseconds automatically, significantly improving the repair efficiency of the faulty gate trace, making the performance of the gate trace after the gate open wire fault repair consistent with that of the normal gate trace, and thus effectively improving the display quality of the display panel applied to the gate trace repair circuit.

[0059] Further, in some other feasible embodiments, when the trace anomaly detection mode is the open wire detection mode, the above step S20: Determine the gate open wire fault according to the preset trace anomaly detection mode and the open wire detection signal, and further includes the following implementation steps S201 to S203.

[0060] Step S201: In response to the open wire detection signal, conduct the connection paths on both sides of the same gate trace to the double-open wire detection module row by row to form an open wire detection path from the first open wire detection component to the second open wire detection component via the gate trace.

[0061] In this embodiment, refer to Figure 4, the dual wire break detection module 20 provided in this application realizes efficient detection of gate trace wire break faults by integrating a first wire break detection component 21 including a first shift register 210 and a plurality of first thin film transistors T1 and a second wire break detection component 22 including a second shift register 220 and a plurality of second thin film transistors T2. Specifically, when the wire trace abnormality detection mode is the wire break detection mode, according to the electrical connection between the detection control terminal of the logic control module 10 and the first shift register 210 and the second shift register 220 respectively, when the first shift register 210 drives each first thin film transistor T1 electrically connected to the first wire end of each gate trace to conduct row by row under the drive of the wire break detection signal provided by the detection control terminal of the logic control module 10, the second shift register 220 is synchronously enabled to conduct the second thin film transistor T2 electrically connected to the second wire end of the same gate trace under the drive of the wire break detection signal provided by the detection control terminal of the logic control module 10, so as to form a wire break detection path for each gate trace from the first voltage side (i.e., the V1 side shown in Figure 4 to the second voltage side (i.e., the V2 side shown in Figure 4 ) of the logic control module 10 via its own wire body, so that the logic control module 10 can detect whether the corresponding gate trace is unobstructed row by row based on the wire break detection path of each gate trace, thereby significantly improving the detection efficiency and accuracy of gate trace wire break faults.

[0062] Step S202: When the first voltage side of the logic control module provides the first voltage to the gate trace row by row, detect whether there is a voltage value output after the first voltage passes through the wire break detection path through the second voltage side of the logic control module.

[0063] In this embodiment, after establishing the wire break detection path of each gate trace, taking the gate trace Gn as an example, when scanning the gate trace Gn row by row, the first voltage side of the logic control module provides the first voltage to the gate trace Gn, and the second voltage side of the logic control module detects whether there is a voltage value output after the first voltage passes through the wire break detection path, so as to realize the wire break detection of the gate trace body.

[0064] Step S203: If there is no voltage value output after the first voltage passes through the wire break detection path, determine that the gate wire break fault is the break of the gate trace body.

[0065] In this embodiment, during the row-by-row scanning process, when scanning the gate trace Gn row by row, the logic control module actively injects the first voltage through the first voltage side, and synchronously uses the second voltage side to detect the output feedback of the wire break detection path in real time. If the voltage output after the first voltage passes through the wire break detection path is missing, it can be directly and quickly determined that the gate trace Gn is broken, and the break of the gate trace Gn can be represented by Figure 3The cross symbol denoted by the label F1 shown realizes the detection efficiency and accuracy of the broken gate trace, thereby improving the efficiency of subsequent repair of the broken gate trace.

[0066] Further, in some feasible embodiments, when the trace anomaly detection mode is the single-sided fault detection mode, the above step S20: determining the gate breakage fault according to the preset trace anomaly detection mode and the broken line detection signal may further include the following implementation steps A10 to step A20.

[0067] Step A10: In response to the broken line detection signal, enable the first broken line detector not to work when the first gate driver provides the first gate voltage signal to the gate target trace, and synchronously enable the second broken line detector to be connected to the gate target trace when the second gate driver does not work, so as to form a first single-sided detection path from the first gate driver through the gate target trace to the second broken line detector, and determine the voltage output result after the first gate voltage signal passes through the first single-sided detection path.

[0068] In this embodiment, the gate target trace can be any one of multiple gate traces. Specifically, taking Figure 4 the shown gate trace Gn as the gate target trace, when the trace anomaly detection mode is the single-sided fault detection mode, the double broken line detection module 20 responds to the broken line detection signal, enables the first shift register 210 not to conduct the first thin film transistor T1-n electrically connected to the gate trace Gn when the first gate driver 31 provides the first gate voltage signal (i.e., Figure 4 the shown GN_L) to the gate trace Gn, and synchronously enables the second shift register 220 to conduct the second thin film transistor T2-n connected to the gate trace Gn when the second gate driver 32 does not work, thereby forming a first single-sided detection path from the first gate driver 31 through the gate trace Gn to the second shift register 220; next, detect whether there is a voltage output after the first gate voltage signal passes through the first single-sided detection path. If there is no voltage output after the first gate voltage signal passes through the first single-sided detection path, determine that the voltage output result is no voltage value output; if there is a voltage output after the first gate voltage signal passes through the first single-sided detection path, determine that the voltage output result is a voltage value output, so as to detect whether the first gate driver fails according to the voltage output result, thereby realizing the accurate detection of the broken line fault of the first gate driver.

[0069] Step A20: When the trace anomaly detection mode switches from the single-sided fault detection mode to the double-sided fault detection mode, determine the gate breakage fault according to the double-sided fault detection mode and the voltage output result.

[0070] In this embodiment, when the wiring anomaly detection mode switches from the single-sided fault detection mode to the double-sided fault detection mode, based on the double-sided fault detection mode and the voltage output result, the gate disconnection fault can be accurately determined, thereby realizing the comprehensiveness of the disconnection fault detection of the display panel.

[0071] Further, in some other feasible embodiments, the above step A20: determining the gate disconnection fault based on the double-sided fault detection mode and the voltage output result may further include the following implementation steps A201 to A204.

[0072] Step A201: Enable the second disconnection detector not to work when the second gate driver provides a second gate voltage signal to the gate target trace, and synchronously enable the first disconnection detector to be connected to the gate target trace when the first gate driver does not work, so as to form a second single-sided detection path from the second gate driver through the gate target trace to the first disconnection detector.

[0073] In this embodiment, after determining the disconnection detection of the first gate driver 31 in the single-sided fault detection mode, when the wiring anomaly detection mode switches from the single-sided fault detection mode to the double-sided fault detection mode, the double disconnection detection module 20 immediately responds to the disconnection detection signal, enables the second shift register 220 not to conduct the second thin film transistor T2-n electrically connected to the gate trace Gn when the second gate driver 32 provides a second gate voltage signal (i.e., Figure 4 the GN_R shown) to the gate target line (i.e., Figure 4 the gate trace Gn shown), and synchronously enables the first shift register 210 to conduct the first thin film transistor T1-n connected to the gate trace Gn when the first gate driver 31 does not work, thereby forming a second single-sided detection path from the second gate driver 32 through the gate trace Gn to the first shift register 210 to detect whether the second gate driver fails, thereby realizing the disconnection fault detection of the second gate driver.

[0074] Step A202: If no voltage value is output after the second gate voltage signal passes through the second single-sided detection path, and the voltage output result is that no voltage value is output after the first gate voltage signal passes through the first single-sided detection path, it is determined that the gate disconnection fault is the failure of the bilateral gate driver module.

[0075] In this embodiment, after the first unilateral detection path and the second unilateral detection path are constructed, the voltage output conditions of the first gate voltage signal via the first unilateral detection path and the voltage output conditions of the second gate voltage signal via the second unilateral detection path are respectively judged. If there is no voltage value output after the second gate voltage signal passes through the second unilateral detection path, and the voltage output result is that there is no voltage value output after the first gate voltage signal passes through the first unilateral detection path, it is determined that the gate open circuit fault is the failure of the bilateral gate drive module, that is, both the first gate driver and the second gate driver have failed.

[0076] Step A203: If there is no voltage value output after the second gate voltage signal passes through the second unilateral detection path, and the voltage output result is that there is a voltage value output after the first gate voltage signal passes through the first unilateral detection path, it is determined that the gate open circuit fault is the failure of the second gate driver.

[0077] In this embodiment, after the first gate voltage signal and the second gate voltage signal are respectively detected by using the first unilateral detection path and the second gate driver, if it is detected that there is no voltage value output after the second gate voltage signal passes through the second unilateral detection path, and the voltage output result is that there is a voltage value output after the first gate voltage signal passes through the first unilateral detection path, it is determined that the gate open circuit fault is the failure of the second gate driver.

[0078] Step A204: If there is a voltage value output after the second gate voltage signal passes through the second unilateral detection path, and the voltage output result is that there is no voltage value output after the first gate voltage signal passes through the first unilateral detection path, it is determined that the gate open circuit fault is the failure of the first gate driver.

[0079] In this embodiment, after the first gate voltage signal and the second gate voltage signal are respectively detected by using the first unilateral detection path and the second gate driver, if it is detected that there is a voltage value output after the second gate voltage signal passes through the second unilateral detection path, and the voltage output result is that there is no voltage value output after the first gate voltage signal passes through the first unilateral detection path, it is determined that the gate open circuit fault is the failure of the first gate driver.

[0080] In summary, the bilateral gate drive failure diagnosis mechanism proposed in this embodiment realizes accurate classification and rapid positioning of fault types through multi-condition logic criteria. Specifically, when there is no voltage feedback in both the first and second unilateral detection paths, the overall failure of the bilateral drive module can be clearly determined through the gate trace repair circuit, avoiding the problem of double false alarms caused by unilateral signal interference in the traditional scheme; in addition, the voltage output states of the two detection paths are cross-validated (such as locking the failure of the second gate driver when only the second unilateral detection path has no feedback), thereby significantly improving the efficiency of fault source orientation identification.

[0081] Further, in some feasible embodiments, the above-mentioned step S20: enabling the logic control module to perform a wire break repair operation according to the gate wire break fault may further include the following implementation steps B10 to B20.

[0082] Step B10: When the logic control module responds to the gate wire break fault as the body break of the gate trace, determine the display partition where the gate wire break is located, and determine the compensation average voltage of the gate wire break according to the block compensation voltage corresponding to each gate trace in the display partition and the number of gate lines of all gate traces in the display partition.

[0083] In this embodiment, refer to Figure 6 , Figure 6 The schematic diagram of the gate wire break partition repair structure involved in the embodiment solution of the present application. Specifically, divide the display panel into partitions. For example, divide the gate traces arranged row by row into Figure 6 The 5 blocks shown. These 5 blocks are block 1, block 2, block 3, block 4, and block 5 respectively. According to the response of the logic control module to the body break of the gate trace as the gate wire break fault, determine the display partition where the gate wire break is located, and obtain the first trace end voltage V11 and the second trace end voltage V22 of each gate trace in this display partition row by row; next, determine the voltage drop between the first trace end voltage V11 and the second trace end voltage V22, and calculate this voltage drop and the first trace end voltage V11 according to the preset compensation voltage calculation algorithm, and the gate compensation voltage of each gate trace can be accurately obtained; next, perform a summation calculation on the gate compensation voltages of each gate trace in this display partition to obtain the compensation sum voltage, and perform an averaging process according to this compensation sum voltage and the number of gate lines of all gate traces in this display partition, and the compensation average voltage of the gate wire break can be accurately obtained.

[0084] It should be noted that the gate wire break can be understood as the gate trace with a body break.

[0085] The expression of the preset compensation voltage calculation algorithm is: Vcomp = V11 + (V11 - V22) / 2, where Vcomp represents the gate compensation voltage, V11 represents the first trace end voltage of the corresponding gate trace, and V22 represents the second trace end voltage of the corresponding gate trace.

[0086] Step B20: When connecting the gate wire break to the first wire break detection component, synchronously connect the gate wire break to the second wire break detection component, so that when the logic control module provides the compensation average voltage to the side of the gate wire break close to the first wire break detection component, synchronously provide the compensation average voltage to the side of the gate wire break close to the second wire break detection component.

[0087] In this embodiment, when a gate line break is scanned line by line, the gate driving components on both sides of the gate line break are disabled. At this time, when the logic control module provides a compensation average voltage to the first wiring end of the gate line break through the first voltage side when the first line break detection component conducts the electrical connection between the gate line break and the corresponding thin film transistor, the logic control module simultaneously provides a compensation average voltage to the second wiring end of the gate line break through the second voltage side when the second line break detection component conducts the electrical connection between the gate line break and the corresponding thin film transistor, so as to achieve immediate repair of the gate line break fault where the gate wiring body is broken.

[0088] Further, in some feasible embodiments, the above step S20: enabling the logic control module to perform a line break repair operation according to the gate line break fault may further include the following implementation steps C10 to step C30.

[0089] Step C10: Control the logic control module to respond to the gate line break fault that the first gate driving component fails. When providing a second gate scan voltage to the gate target wiring through the second gate driving component, simultaneously conduct the connection between the gate target wiring and the first line break detection component, so that the logic control module can provide a first voltage identical to the second gate scan voltage to the gate target wiring via the first line break detection component.

[0090] In this embodiment, once the logic control module confirms that the first gate driving component fails when scanning the gate target wiring line by line, when providing a second gate scan voltage to the gate target wiring through the second gate driving component, simultaneously enable the first shift register to conduct the electrical connection between the gate target wiring and the corresponding thin film transistor in the same driving timing as the second gate driving component to access the first voltage identical to the second gate scan voltage provided by the logic control module to the gate target wiring via the first voltage side, so as to achieve immediate replacement of the faulty gate driving component, enabling the repaired display panel to be used normally, and thus significantly improving the display quality of the display panel.

[0091] Step C20: Control the logic control module to respond to the gate line break fault that the second gate driving component fails. When providing a first gate scan voltage to the gate target wiring through the first gate driving component, simultaneously conduct the connection between the gate target wiring and the second line break detection component, so that the logic control module can provide a second voltage identical to the first gate scan voltage to the gate target wiring via the second line break detection component.

[0092] In this embodiment, once the logic control module confirms that the second gate driving component fails to scan the gate target trace row by row, when the first gate driving component provides the first gate scanning voltage to the gate target trace, the second shift register is synchronously enabled to conduct the electrical connection between the gate target trace and the corresponding thin film transistor under the same driving timing as the first gate driving component, so as to access the second voltage that is the same as the first gate scanning voltage provided by the logic control module to the gate target trace via the second voltage side, thereby realizing an immediate replacement of the faulty gate driving component, enabling the repaired display panel to be used normally, and thus significantly improving the display quality of the display panel.

[0093] Step C30: Control the logic control module to respond that the gate disconnection fault causes the failure of both-sided gate driving modules. When conducting the connection between the gate target trace and the first disconnection detection component, synchronously conduct the connection between the gate target trace and the second disconnection detection component, so that when the logic control module provides a repair compensation voltage to the side of the gate target trace close to the first disconnection detection component, it synchronously provides a repair compensation voltage to the side of the gate target trace close to the second disconnection detection component.

[0094] In this embodiment, once the logic control module confirms that both the first gate driving component and the second gate driving component fail to scan the gate target trace (i.e., the disconnection row shown in Figure 7 ), specifically, disconnect the electrical connections between both ends of the gate target trace and the corresponding side gate driving components respectively. When enabling the first shift register to conduct the electrical connection between the gate target trace and the corresponding thin film transistor under the driving timing corresponding to the gate target trace to access the repair compensation voltage provided by the logic control module to the gate target trace via the first voltage side (i.e., the V1 side), synchronously enable the second shift register to conduct the electrical connection between the gate target trace and the corresponding thin film transistor under the same driving timing as the first shift register to access the same repair compensation voltage provided by the logic control module to the gate target trace via the second voltage side (i.e., the V2 side), so as to Figure 7 provide the same repair compensation voltage to both sides of the disconnection row shown in Figure 7 to present the display effect of the repaired row shown in

[0095] Furthermore, to achieve the above object, the present application also provides a display panel, which includes a color filter substrate, a liquid crystal layer, and an array substrate. The liquid crystal layer is disposed between the array substrate and the color filter substrate, and the array substrate includes the gate trace repair circuit described in any one of the above.

[0096] In addition, the present application also provides a display device. Please refer to Figure 8 , Figure 8This is a schematic structural diagram of a display device involved in the solution of an embodiment of the present application. The display device in the embodiment of the present application can specifically be a device that locally runs a gate line repair method.

[0097] As Figure 8 shown, the display device in the embodiment of the present application may include: the above-mentioned gate line repair circuit; or, a processor 1001, such as a CPU, a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. Among them, the communication bus 1002 is used to realize the connection and communication between these components. The user interface 1003 may include a display screen (Display) and an input unit such as a keyboard (Keyboard). Optionally, the user interface 1003 may further include a standard wired interface and a wireless interface. The network interface 1004 may optionally include a standard wired interface and a wireless interface (such as a Wi-Fi interface).

[0098] The memory 1005 is arranged on the main body of the display device. A program is stored on the memory 1005, and when the program is executed by the processor 1001, corresponding operations are realized. The memory 1005 is also used to store parameters for the display device. The memory 1005 may be a high-speed RAM memory or a stable memory (non-volatile memory), such as a disk memory. Optionally, the memory 1005 may also be a storage device independent of the aforementioned processor 1001.

[0099] Those skilled in the art can understand that Figure 8 the display device structure shown in

[0100] As Figure 8 shown, the memory 1005 as a storage medium may include an operating system, a network communication module, a user interface module, and a gate line repair program.

[0101] In Figure 8 the display device shown, the processor 1001 may be used to call the gate line repair program stored in the memory 1005 and execute the steps of the gate line repair method as described above.

[0102] It should be noted that in this text, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, article or system comprising a series of elements not only includes those elements but also other elements not expressly listed, or elements inherent to such process, method, article or system. Without further limitation, an element defined by the statement "comprising one..." does not exclude the existence of additional identical elements in the process, method, article or system comprising such element.

[0103] The serial numbers of the embodiments of the present application above are for description only and do not represent the superiority or inferiority of the embodiments.

[0104] Through the description of the above embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation. Based on such understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art can be embodied in the form of a software product. The computer software product is stored in a storage medium as described above (such as ROM / RAM, magnetic disk, optical disc), and includes several instructions to enable a display device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present application.

[0105] The above are only the preferred embodiments of the present application, and do not limit the patent scope of the present application accordingly. Any equivalent structure or equivalent process transformation made by using the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present application.

Claims

1. A gate wiring repair circuit, characterized in that: The gate wiring repair circuit comprises: Multiple gate traces; A logic control module, wherein the logic control module is configured to provide a disconnection detection signal; A double disconnection detection module, wherein one disconnection detection module in the double disconnection detection module is a first disconnection detection element, and the other disconnection detection module in the double disconnection detection module is a second disconnection detection element, two sides of the first disconnection detection element are respectively electrically connected to a first voltage side of the logic control module and a first routing end of each gate routing, two sides of the second disconnection detection element are respectively electrically connected to a second voltage side of the logic control module and a second routing end of each gate routing, and a control end of the first disconnection detection element and a control end of the second disconnection detection element are respectively electrically connected to a detection control end of the logic control module; The dual disconnection detection module is configured to determine a gate disconnection fault according to a preset routing abnormality detection mode and the disconnection detection signal after receiving the disconnection detection signal sent by the logic control module, and send the gate disconnection fault to the logic control module so that the logic control module can enable the logic control module to perform a disconnection repair operation according to the gate disconnection fault.

2. The gate wiring repair circuit according to claim 1, characterized in that: The first disconnection detection element includes a first shift register and first thin film transistors corresponding to each of the first wiring ends, the gate end of each of the first thin film transistors is electrically connected to the driving side of the first shift register, the first channel end of each of the first thin film transistors is electrically connected to the first voltage side, and each of the first wiring ends is electrically connected to the second channel end of the corresponding first thin film transistor; The second disconnection detection device includes a second shift register and second thin film transistors corresponding to each second wiring end, the gate end of each second thin film transistor is electrically connected to the driving side of the second shift register, the first channel end of each second thin film transistor is electrically connected to the second voltage side, and each second wiring end is electrically connected to the second channel end of the corresponding second thin film transistor.

3. The gate wiring repair circuit according to claim 2, characterized in that: The gate wiring repair circuit comprises a double-sided gate driving module, one of the double-sided gate driving modules is a first gate driving component, and the other gate driving module in the double-sided gate driving module is a second gate driving component; The first gate driver is disposed on a side of the first shift register close to the plurality of gate wirings arranged along the row direction, and the second gate driver is disposed on a side of the second shift register close to the plurality of gate wirings arranged along the row direction; The first gate driver is electrically connected to a first routing end of each gate routing, and the second gate driver is electrically connected to a second routing end of each gate routing.

4. A gate wiring repair method, characterized in that: The gate wiring repair method comprises: Obtain the disconnection detection signal of the logic control module through the dual disconnection detection module; A gate disconnection fault is determined according to a preset abnormal wiring detection mode and the disconnection detection signal, and the logic control module is enabled to perform a disconnection repair operation according to the gate disconnection fault.

5. The gate wiring repair method according to claim 4, characterized in that: When the wiring abnormality detection mode is the wire break detection mode, the step of determining the gate wire break fault according to the preset wiring abnormality detection mode and the wire break detection signal includes: In response to the disconnection detection signal, the connection paths from both sides of the same gate line to the double disconnection detection module are turned on row by row to form a disconnection detection path from the first disconnection detection element to the second disconnection detection element via the gate line; When the first voltage side of the logic control module provides the first voltage to the gate wiring row by row, the second voltage side of the logic control module detects whether the first voltage has a voltage value output after passing through the disconnection detection path; If the first voltage has no voltage value output after passing through the disconnection detection path, it is determined that the gate disconnection fault is caused by the main body of the gate wiring being broken.

6. The gate wiring repair method according to claim 4, characterized in that: When the wiring abnormality detection mode is a unilateral fault detection mode, the step of determining a gate disconnection fault according to the preset wiring abnormality detection mode and the disconnection detection signal includes: In response to the disconnection detection signal, the first disconnection detection element is enabled not to work when the first gate driver provides the first gate voltage signal to the gate target wiring, and the second disconnection detection element is simultaneously enabled to communicate with the gate target wiring when the second gate driver is not working, so as to form a first unilateral detection path from the first gate driver to the second disconnection detection element via the gate target wiring, and determine a voltage output result of the first gate voltage signal after passing through the first unilateral detection path; When the wiring abnormality detection mode is switched from the single-side fault detection mode to the double-side fault detection mode, a gate disconnection fault is determined according to the double-side fault detection mode and the voltage output result.

7. The gate wiring repair method according to claim 6, characterized in that: The step of determining a gate disconnection fault according to the bilateral fault detection mode and the voltage output result comprises: enabling the second disconnection detection element to not work when the second gate driver provides the second gate voltage signal to the gate target wiring, and simultaneously enabling the first disconnection detection element to communicate with the gate target wiring when the first gate driver does not work, so as to form a second single-side detection path from the second gate driver to the first disconnection detection element via the gate target wiring; If the second gate voltage signal has no voltage value output after passing through the second unilateral detection path, and the voltage output result is that the first gate voltage signal has no voltage value output after passing through the first unilateral detection path, it is determined that the gate disconnection fault is a failure of the double-sided gate drive module; If the second gate voltage signal has no voltage value output after passing through the second unilateral detection path, and the voltage output result is that the first gate voltage signal has a voltage value output after passing through the first unilateral detection path, it is determined that the gate disconnection fault is a failure of the second gate driver; If the second gate voltage signal has a voltage value output after passing through the second unilateral detection path, and the voltage output result is that the first gate voltage signal has no voltage value output after passing through the first unilateral detection path, it is determined that the gate disconnection fault is a failure of the first gate driver.

8. The gate wiring repair method according to claim 4, characterized in that: The step of enabling the logic control module to perform a disconnection repair operation according to the gate disconnection fault comprises: Control the logic control module to determine the display partition where the gate break is located in response to the gate break fault being the break of the gate wiring body, and determine the compensation mean voltage of the gate break according to the block compensation voltage corresponding to each gate wiring in the display partition and the number of gate lines of all the gate wirings in the display partition; When the connection between the gate break and the first break detection device is turned on, the connection between the gate break and the second break detection device is turned on simultaneously, so that when the logic control module provides the compensation mean voltage to the side of the gate break close to the first break detection device, the compensation mean voltage is simultaneously provided to the side of the gate break close to the second break detection device.

9. The gate wiring repair method according to claim 4, characterized in that: The step of enabling the logic control module to perform a disconnection repair operation according to the gate disconnection fault comprises: Controlling the logic control module to respond to the gate disconnection fault as a failure of the first gate driver, and synchronously conducting the connection between the gate target line and the first disconnection detection element when providing the second gate scanning voltage to the gate target line through the second gate driver, so that the logic control module can provide the first voltage that is the same as the second gate scanning voltage to the gate target line through the first disconnection detection element; or, Controlling the logic control module to respond to the gate disconnection fault as the failure of the second gate driver, and synchronously conducting the connection between the gate target line and the second disconnection detection element when providing the first gate scanning voltage to the gate target line through the first gate driver, so that the logic control module can provide the second voltage that is the same as the first gate scanning voltage to the gate target line through the second disconnection detection element; or, The logic control module is controlled to respond to the gate disconnection fault as a failure of the double-sided gate drive module, and when the connection between the gate target wiring and the first disconnection detection device is turned on, the connection between the gate target wiring and the second disconnection detection device is simultaneously turned on, so that when the logic control module provides a repair compensation voltage to the side of the gate target wiring close to the first disconnection detection device, the repair compensation voltage is simultaneously provided to the side of the gate target wiring close to the second disconnection detection device.

10. A display panel, characterized in that: The display panel includes a color filter substrate, a liquid crystal layer and an array substrate, wherein the liquid crystal layer is arranged between the array substrate and the color filter substrate, and the array substrate includes the gate wiring repair circuit according to any one of claims 1 to 3.

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