Flash memory chip testing method

Abstract

The application discloses a flash memory chip testing method, which comprises the following steps: providing a plurality of flash memory chips; performing dynamic power consumption testing on the plurality of flash memory chips during an erasing operation to obtain power consumption values corresponding to the flash memory chips; performing outlier statistics on the power consumption values of the plurality of flash memory chips to determine outlier flash memory chips; and removing the outlier flash memory chips. According to the application, the flash memory chips with some process defects can be removed in the yield testing stage, so that the quality of the flash memory chips flowing into the end users is ensured.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of flash memory testing, and in particular to a flash memory chip testing method. BACKGROUND

[0002] As an integrated circuit memory device, flash memory is widely used in electronic products such as portable computers, mobile phones, digital music players and the like due to its function of electrically erasable storage of information and the fact that the stored information will not be lost after power-off.

[0003] In a power supply scheme design, a plurality of charge pumps are usually designed on a flash memory chip to provide corresponding voltages for each storage unit in the flash memory. When the charge pump is working at a high frequency, some process defects can cause some devices in the charge pump to fail in frequent use, thereby causing device damage, such as high-voltage NMOS burnout, flash memory region leakage and the like. In the existing flash memory yield testing, the conventional trimming of erase voltage VEE and programming voltage VEP and other flash memory function tests are difficult to simulate the case of frequent use of the charge pump at the terminal. Once a chip with such defects is shipped as a normal sample, it is put into the terminal market, and in the continuous use of the terminal user, it can cause the charge pump to fail quickly, thereby becoming a terminal reliability failure event. SUMMARY

[0004] Embodiments of the present application provide a flash memory chip testing method to remove as many flash memory chips with process defects as possible in the yield testing stage, thereby ensuring the quality of flash memory chips flowing into the terminal user.

[0005] Embodiments of the present application provide a flash memory chip testing method, which comprises:

[0006] providing a plurality of flash memory chips;

[0007] performing dynamic power consumption testing on the plurality of flash memory chips during an erase operation to obtain a power consumption value corresponding to each flash memory chip;

[0008] performing outlier statistics on the power consumption values of the plurality of flash memory chips to determine an outlier flash memory chip;

[0009] removing the outlier flash memory chip.

[0010] Optionally, the dynamic power consumption testing on the plurality of flash memory chips during the erase operation to obtain a power consumption value corresponding to each flash memory chip comprises:

[0011] performing dynamic power consumption testing on the plurality of flash memory chips during an erase operation before the conventional function test to obtain a power consumption value corresponding to each flash memory chip; and / or

[0012] The dynamic power consumption test of the plurality of flash memory chips when performing the erase operation obtains power consumption values corresponding to each flash memory chip.

[0013] Optionally, the method further comprises:

[0014] Before the dynamic power consumption test of the plurality of flash memory chips when performing the erase operation, direct current characteristics and parameter trimming tests are performed on the plurality of flash memory chips.

[0015] After the tests pass, the operation of the dynamic power consumption test when performing the erase operation is executed.

[0016] Optionally, the routine function test comprises any one or more of the following tests: read test, write test, erase test, logic test, performance test, programming, and interference test.

[0017] Optionally, the dynamic power consumption test of the plurality of flash memory chips when performing the erase operation obtains power consumption values corresponding to each flash memory chip comprises:

[0018] The power supply end of the flash memory chip is connected to a working power supply, an erase voltage is applied to all word lines for a certain period of time, and the current flowing through the power supply end is measured;

[0019] According to the voltage of the working power supply and the measured current, the power consumption value of the flash memory chip is calculated.

[0020] Optionally, the outlier statistics according to the power consumption values of the plurality of flash memory chips to determine the outlier flash memory chip comprises:

[0021] The mean and standard deviation of the power consumption values of the plurality of flash memory chips are calculated;

[0022] The outlier flash memory chip is determined according to the mean and standard deviation.

[0023] Optionally, the determination of the outlier flash memory chip according to the mean and standard deviation comprises determining the outlier flash memory chip based on the 3-sigma principle according to the mean and standard deviation.

[0024] Optionally, the dynamic power consumption test of the plurality of flash memory chips when performing the erase operation comprises:

[0025] The dynamic power consumption test of the plurality of flash memory chips when performing the erase operation before the routine function test obtains first power consumption values corresponding to each flash memory chip;

[0026] The dynamic power consumption test of the plurality of flash memory chips when performing the erase operation after the routine function test obtains second power consumption values corresponding to each flash memory chip;

[0027] The outlying statistics according to the power consumption values of the plurality of flash memory chips comprises:

[0028] The outlying statistics according to the first power consumption value and the second power consumption value of the plurality of flash memory chips respectively, determines the outlying flash memory chip.

[0029] Optionally, the flash memory chip comprises a storage unit array, the storage unit array comprises a plurality of storage units arranged in a matrix, and the storage unit is a split-gate flash memory unit; each storage unit comprises a floating gate and a bit line; the storage units in each column share the bit line.

[0030] Optionally, the split-gate flash memory unit comprises two storage structures sharing a source region and symmetrically distributed; the storage structure comprises a drain region in a substrate and the source region, the drain region is connected to the bit line, the floating gate and the word line are formed on the substrate between the source region and the drain region, the floating gate tip is formed on the side of the floating gate close to the word line, and a tunneling oxide layer is formed between the floating gate and the word line.

[0031] The flash memory chip test method provided by the embodiment of the application can effectively improve the reliability of the flash memory chip, greatly reduce the risk of the flash memory chip with potential problems, especially charge pump leakage, flowing into the terminal market, and then causing the terminal to fail.

[0032] Further, the dynamic power consumption test of the plurality of flash memory chips when being erased can be performed before the regular function test or after the regular function test, and the implementation manner is flexible and various.

[0033] Further, the dynamic power consumption test of the plurality of flash memory chips when being erased can be performed before the regular function test or after the regular function test, and the implementation manner is flexible and various. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 is a flow chart of the flash memory test method provided by the embodiment of the application;

[0035] Figure 2 is a structural schematic diagram of the flash memory in the embodiment of the application;

[0036] Figure 3 is a principle schematic diagram of the flash memory in the embodiment of the application. DETAILED DESCRIPTION

[0037] In order to make the above objects, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application are described in detail below with reference to the drawings.

[0038] It should be noted that, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application.

[0039] The terms "first", "second", etc. are used only for the purpose of description and should not be understood as indicating or implying relative importance or implying the number of the technical features indicated. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise stated, the meaning of "a plurality of" is two or more.

[0040] Through statistical analysis of some application flash memory chip terminal failure samples, it can be known that for terminal failure caused by process defects, the following two commonalities usually exist:

[0041] (1) The charge pump of the flash memory chip works abnormally;

[0042] (2) Some data during flash memory erasing and programming are obviously different from normal flash memory chips, and this phenomenon is more obvious during flash memory erasing.

[0043] In view of the above problems and based on the statistical analysis of terminal failure samples, the embodiments of the present application provide a flash memory testing method. In the CP (Chip Probing, chip probe testing) testing stage, the dynamic power consumption of the flash memory chip during erasing is tested, and the dynamic power consumption value obtained by testing is analyzed for outliers to screen out outlier samples. Although the abnormality of the outlier sample is not caused by the failure of the charge pump, by this way, flash memory chips with potential risks caused by various process defects can be screened out to some extent, so as to avoid them from being shipped as normal samples.

[0044] The CP test is for uncut wafers, which needs to contact the test pads on the wafer with a probe, and a single or multiple Die (die) on the wafer can be tested at a time. The CP test generally includes three stages of testing, i.e. CP1 test basic storage read-write function, and write certain content in the storage chip; then the wafer is baked at high temperature, and CP2 test is performed to detect whether the data written before can be maintained; finally, the logic function test of the MCU (main control unit) part is performed.

[0045] The test flow of CP1 mainly includes:

[0046] (1) DC parameters and trim test:

[0047] The DC parameter test mainly includes: short circuit, open circuit, maximum current, leakage current, output drive current, turn-on level, etc. For example, the open / short test is mainly used to find out whether there is a short circuit between the pins of the chip and whether there is a lack of bonding wire during the packaging of the chip; the leakage current test is to detect the leakage current of the input pins of the chip when a voltage is applied.

[0048] Trim is a process of adjusting some parameters inside the circuit during chip testing. These parameters can be reference voltage, bias current, bandgap voltage, and / or oscillator frequency, etc. The trim test can measure the values of some parameters in the circuit, and if the values of the parameters deviate from the target values, the parameters can be corrected and adjusted to meet the requirements of the parameter indicators. After trimming the parameters, the yield of the chip can be greatly improved. The trim test in the chip adjusts the parameters by increasing or decreasing the resistance value of the corresponding resistance network.

[0049] (2) Flash regular function test:

[0050] Mainly includes but not limited to: read test, write test, erase test, logic test, performance test, programming and interference test, etc. For example, the erase / read test is mainly used to screen out those chips that cannot complete the basic erase, program and read / write operations. During the test, the chip is subjected to erase and program operations on a single sector or the entire flash array at different operating voltages, and then the chip is read to determine whether it can pass the test.

[0051] (3) Write a flag into NVR1 and erase the chip

[0052] During this process, all sectors will be erased.

[0053] The CP2 test is mainly a function test of the baked chip to detect its data retention capability. Generally, the CP2 test process mainly includes the following steps:

[0054] (1) Open / short test and leakage test

[0055] Similar to the corresponding steps in the CP1 test, the open / short test is mainly used to find out whether there is a short circuit between the pins of the chip and whether there is a lack of bonding wire during the packaging of the chip; the leakage current test is to detect the leakage current of the input pins of the chip when a voltage is applied.

[0056] (2) NVR1 verification

[0057] Used to verify that the flags written to NVR1 during the CP1 test are correct.

[0058] (3) Data retention capability and durability testing

[0059] Data retention capability refers to the ability of a storage unit to maintain its programmed state for an acceptable period of time.

[0060] Durability testing is used to characterize the maximum number of program / erase (P / E) cycles a memory cell can withstand without failure.

[0061] The flash memory testing method provided in this application adds a dynamic power consumption test during the erasure of the flash memory chip in the CP1 test stage. This test process can be to perform a dynamic power consumption test during the erasure of the multiple flash memory chips before the regular functional test to obtain the power consumption value of each flash memory chip; and / or to perform a dynamic power consumption test during the erasure of the multiple flash memory chips after the regular functional test to obtain the power consumption value of each flash memory chip.

[0062] It should be noted that the specific items and testing methods of the conventional functional tests may vary depending on the type and manufacturer of the flash memory chip, and this application embodiment does not limit them.

[0063] The following is combined Figure 1 The flash memory testing method provided in the embodiments of this application will be described in detail.

[0064] like Figure 1 The diagram shown is a flowchart of a flash memory testing method provided in an embodiment of this application, including the following steps:

[0065] Step 101: Provide multiple flash memory chips.

[0066] The flash memory chip includes a memory cell array, which comprises a plurality of memory cells arranged in a matrix. The memory cells can be grid-type flash memory cells or memory cells with other structures involving charge pumps; this embodiment of the application does not limit the specific type of memory cell. Each memory cell includes a floating gate and a bit line.

[0067] The flash memory chip can be NAND type (memory cells connected in series) or NOR type (memory cells connected in parallel, i.e., each column of memory cells is connected to the same bit line), and this application embodiment does not limit this.

[0068] The following section uses a grid-type flash memory cell as an example to briefly explain its structure and principle. (See also...) Figure 2 and Figure 3 ,in, Figure 2 This is a schematic diagram of a flash memory structure in one embodiment of this application. Figure 3Fig. 1 is a schematic diagram of a flash memory according to an embodiment of the present application.

[0069] The flash memory includes a memory cell array, which includes a plurality of memory cells A arranged in a matrix. Each memory cell is a split-gate flash memory cell. Each memory cell includes a floating gate 11 and a bit line 13. Each column of memory cells shares a bit line 13. A plurality of split-gate flash memory cells are formed on a semiconductor substrate. The semiconductor substrate can be made of silicon, germanium, silicon germanium, silicon carbide, or other materials such as Silicon-On-Insulator (SOI) or Germanium-on-Insulator (GOI), or other materials such as gallium arsenide or other Group III-V compounds.

[0070] In this embodiment, each split-gate flash memory cell includes two memory structures that share a source region 14 and are symmetrically distributed. Each split-gate flash memory cell includes a drain region 15 and a source region 14 formed in the semiconductor substrate, and a source line (not shown) formed on the semiconductor substrate and connected to the source region 14. The source line is located above the source region 14. The drain region 15 is connected to the bit line 13. A word line 21 is formed between the source region 14 and the drain region 15. Two word lines 21 of the same split-gate flash memory cell are formed on the two sides of the source line. A floating gate oxide layer, a floating gate 11, and a sidewall are formed on the semiconductor substrate between the source line and the word line 21. A tunneling oxide layer is formed between the floating gate 11 and the word line 21. The floating gate 11, the word line 21, and the source line can all be made of polysilicon. A floating gate tip is formed on the side of the floating gate 11 that is close to the word line 21. The left memory structure and the right memory structure are symmetrically distributed and share the source line. In this embodiment, the source region 14 and the drain region 15 are both N-type doped.

[0071] When the split-gate flash memory cell is programmed, the word line 21 acts as a control gate. A high voltage is applied to the source region 14, a voltage that can open the channel is applied to the word line 21, and a constant current is applied through the drain region 15. The source region 14 is at a high potential. Under the action of the high potential, on one hand, hot electrons are generated in the channel, and on the other hand, the high potential is coupled to the floating gate 11, and the floating gate 11 generates a coupling voltage. Under the action of the coupling voltage, electrons are injected from the channel to the floating gate 11, thereby achieving programming. Programming is also referred to as a write "0" operation.

[0072] As mentioned above, the dynamic power consumption test process of the flash memory chips during erasing in the flash memory chip test method provided by the present application can be performed before the regular function test to obtain the power consumption values corresponding to the flash memory chips, and / or can be performed after the regular function test to obtain the power consumption values corresponding to the flash memory chips.

[0073] Accordingly, in some embodiments, the plurality of flash memory chips can be flash memory chips that have passed the DC parameter and trim test but have not yet undergone the regular function test.

[0074] In other embodiments, the plurality of flash memory chips can be flash memory chips that have passed the regular function test but have not yet had the flag written into the NVR1.

[0075] At step 102, dynamic power consumption test is performed on the plurality of flash memory chips when being erased, to obtain a power consumption value corresponding to each flash memory chip.

[0076] Specifically, the power supply terminal of each flash memory chip is connected to a working power supply, an erase voltage is applied on all word lines for a certain time, and the current flowing through the power supply terminal is measured; and according to the voltage of the working power supply and the measured current, the power consumption value of each flash memory chip is calculated.

[0077] In the regular CP test, the normal erase voltage VEE applied on the word line is, for example, 12V.

[0078] Referring to Figure 2 and Figure 3 When the split-gate flash memory cell is erased, an erase voltage VEE is applied on all word lines, and the tip of the floating gate lowers the channel voltage of the tunneling effect through the tip discharge principle, so that electrons can pass through the tunneling oxide layer from the tip of the floating gate 11 to the word line 21. After the storage cell is erased, the storage bit of the storage cell is in a "1" state, i.e., all the storage cells of the flash memory are erased to "1".

[0079] Since the duration of a complete erase process is very short, in order to obtain an accurate current measurement value, the erase voltage can be maintained for a certain time (for example, 5-10 ms) after being applied, so that the current flowing through the power supply terminal reaches a stable state.

[0080] It should be noted that the above test process can be completed by some existing test machines.

[0081] At step 103, the outlying flash memory chip is determined according to the outlying statistics of the power consumption values of the plurality of flash memory chips.

[0082] In some embodiments, the outlying statistics of the power consumption values can adopt the 3sigma principle, which is based on the normal distribution assumption, calculates the deviation value of the data points from the mean value, and divides the data points into two categories of abnormal values and normal values according to the size of the deviation.

[0083] The process of determining the outlier flash memory chip is as follows: first, the mean and standard deviation of the power consumption values of the plurality of flash memory chips are calculated; then, the outlier flash memory chip is determined according to the mean and standard deviation, specifically, the deviation value of each power consumption value from the mean is calculated, and for the power consumption value whose deviation value is greater than 3 times the standard deviation, it is determined as an abnormal value, and then the flash memory chip corresponding to the power consumption value is determined as the outlier flash memory chip.

[0084] In some embodiments, other outlier statistical algorithms can also be used to determine the outlier flash memory chip, such as: Dixon algorithm, Grubbs algorithm, box plot, Mahalanobis distance, local outlier factor (LOF) algorithm, etc., which are not limited by the embodiments of the present application.

[0085] Step 104: rejecting the outlier flash memory chip.

[0086] It should be noted that in the specific implementation, the above test can be performed on all to-be-tested flash memory chips to reject the outlier flash memory chip; or all to-be-tested flash memory chips are divided into multiple groups, and the above test is performed on each group to reject the outlier flash memory chip, which is not limited by the embodiments of the present application.

[0087] In some embodiments, for the same group of to-be-tested flash memory chips, the above dynamic power consumption test during erasing can be performed before the conventional function test, to obtain the first power consumption value corresponding to each flash memory chip, and the outlier flash memory chip is screened out and rejected according to the first power consumption value. Then, the conventional function test is performed on the flash memory chips remaining after rejecting the outlier flash memory chip, and the above dynamic power consumption test during erasing is performed again on the flash memory chips that pass the test, to obtain the second power consumption value corresponding to each flash memory chip, and the outlier flash memory chip is screened out and rejected according to the second power consumption value. Through the two dynamic power consumption tests and screening processes, the flash memory chips with some process defects can be more fully rejected in the yield test stage, to ensure the quality of the flash memory chips flowing into the end users.

[0088] The flash memory chip test method provided by the embodiments of the present application performs dynamic power consumption test on the flash memory chip during erasing in the CP test stage, to simulate the dynamic power consumption of the flash memory chip when used in the terminal product, and through the outlier statistics of the test results, the flash memory chip with power consumption outlier is screened out and rejected in the yield test stage, which effectively improves the reliability of the flash memory chip, greatly reduces the risk of the flash memory chip with potential problems, especially charge pump leakage, flowing into the terminal market, and then causing the terminal to fail.

[0089] It should be understood that the term "and / or" herein only describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " herein represents an "or" relationship between the front and rear associated objects.

[0090] The "multiple" appearing in the embodiments of the present application refers to two or more than two.

[0091] The first, second and the like appearing in the embodiments of the present application are only for the purpose of description and distinguishing the description objects, and do not have the order, and do not represent the special limitation of the number of devices in the embodiments of the present application, and cannot constitute any limitation on the embodiments of the present application.

[0092] Those skilled in the art can understand that all or part of the steps of the foregoing method embodiments can be completed by a program instruction related hardware. The foregoing program can be stored in a computer readable storage medium. The program executes to perform the steps of the foregoing method embodiments: the foregoing storage medium can include: ROM, RAM, magnetic disk or optical disk and various storage medium capable of storing program codes.

[0093] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various modifications and changes without departing from the spirit and scope of the present application, and therefore the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A method of testing a flash memory chip, the method comprising: The method comprises: providing a plurality of flash memory chips; performing dynamic power consumption test on the plurality of flash memory chips during an erase operation to obtain power consumption values corresponding to each flash memory chip; the normal function test comprises an erase test; performing outlier statistics on the power consumption values of the plurality of flash memory chips to determine outlier flash memory chips; rejecting the outlier flash memory chips.

2. The flash memory chip testing method of claim 1, wherein, The method further comprises: performing dynamic power consumption test on the plurality of flash memory chips before the normal function test to obtain power consumption values corresponding to each flash memory chip.

3. The flash memory chip testing method of claim 1, wherein, The method further comprises: performing DC characteristics and parameter trimming test on the plurality of flash memory chips before performing dynamic power consumption test on the plurality of flash memory chips during the erase operation; after the test passes, performing dynamic power consumption test during the erase operation.

4. The flash memory chip testing method of claim 2, wherein, The normal function test further comprises any one or more of the following tests: read test, write test, logic test, performance test, programming, and interference test.

5. The flash memory chip testing method of claim 1, wherein, The dynamic power consumption test on the plurality of flash memory chips during the erase operation to obtain power consumption values corresponding to each flash memory chip comprises: connecting the power supply terminal of the flash memory chip to the working power supply, applying an erase voltage on all word lines for a certain period of time, and measuring the current flowing through the power supply terminal; calculating the power consumption value of the flash memory chip according to the voltage of the working power supply and the measured current.

6. The flash memory chip testing method of claim 1, wherein, The outlier statistics on the power consumption values of the plurality of flash memory chips to determine outlier flash memory chips comprises: calculating the mean and standard deviation of the power consumption values of the plurality of flash memory chips; determining outlier flash memory chips according to the mean and standard deviation.

7. The flash memory chip testing method of claim 6, wherein, The determination of outlier flash memory chips according to the mean and standard deviation comprises: determining outlier flash memory chips based on the 3-sigma principle according to the mean and standard deviation.

8. The flash memory chip test method of claim 2, wherein The outlier statistics on the power consumption values of the plurality of flash memory chips to determine outlier flash memory chips comprises: performing outlier statistics on the first power consumption values obtained by performing dynamic power consumption test on the plurality of flash memory chips before the normal function test to determine outlier flash memory chips; performing outlier statistics on the second power consumption values obtained by performing dynamic power consumption test on the plurality of flash memory chips after the normal function test to determine outlier flash memory chips.

9. The flash memory chip testing method of any one of claims 1 to 8, wherein, The flash memory chip comprises a storage cell array, the storage cell array comprises a plurality of storage cells arranged in a matrix, and the storage cells are split-gate flash memory cells; each storage cell comprises a floating gate and a bit line; and the storage cells in each column share the bit line.

10. The flash memory chip testing method of claim 9, wherein, The split-gate flash memory cell comprises two storage structures that share a source region and are symmetrically distributed; the storage structure comprises a drain region in a substrate and the source region, the drain region is connected to the bit line, the floating gate and the word line are formed on the substrate between the source region and the drain region, the floating gate has a floating gate tip formed on the side close to the word line, and a tunneling oxide layer is formed between the floating gate and the word line.

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