Method and structure for bonding and packaging upper and lower cover clamping pieces of MOS (Metal Oxide Semiconductor) tube

Abstract

The embodiment of the invention discloses an MOS (Metal Oxide Semiconductor) tube upper and lower cover clamping piece bonding packaging method and packaging structure, a heat dissipation lower cover and a heat dissipation upper cover are respectively arranged on two sides of a chip and are attached to the two sides of the chip, so that heat generated by the chip can be conducted to the outside through the heat dissipation upper cover and the heat dissipation lower cover; the heat dissipation efficiency of the MOS tube is improved, the electrical performance is enhanced, the mechanical reliability is enhanced, and the size is miniaturized. During heat dissipation, the lower heat dissipation cover is used for making contact with the chip or the radiator so as to conduct generated heat to the outside, the heat dissipation effect is achieved, meanwhile, the upper heat dissipation cover is attached to the other side of the chip, heat generated on the chip can be conducted to the outside through the upper heat dissipation cover, and therefore efficient heat dissipation is achieved. The method for bonding and packaging the upper cover and the lower cover of the MOS tube through the clamping pieces is suitable for a power MOSFET, compared with traditional single chip packaging, the mode of bonding and packaging the upper heat dissipation cover and the lower heat dissipation cover through the clamping pieces is adopted, the heat dissipation efficiency is improved, the electrical performance is enhanced, the mechanical reliability is enhanced, and the size is small.

Description

Technical Field

[0001] The present invention relates to the technical field of MOS tube packaging, and in particular to a MOS tube upper and lower cover clip bonding packaging method and a packaging structure. Background Art

[0002] There are many ways to package MOS tubes, which are usually selected based on factors such as the usage environment, power requirements, and electrical performance.

[0003] The existing MOS tube packaging method often adopts the traditional single chip packaging method. A single chip package usually has only one chip. Due to the current flow and switching operation in the chip, a certain amount of power loss will occur. The power loss not only affects the working efficiency of the chip, but also causes heat generation.

[0004] When the circuit is static (no switching operation), it still consumes a certain amount of power, which is mainly caused by factors such as leakage current and gate capacitance.

[0005] When a circuit is operating, the switching action causes rapid changes in current, resulting in power consumption.

[0006] At the same time, as the integration of chips increases, chips of the same size can accommodate more transistors and circuit components, which will lead to an increase in power density per unit area. If the heat dissipation effect is not good, it will further lead to heat accumulation in the chip.

[0007] However, single chip packages are often small in size and the thermal capacity of the package itself is limited. Heat is not easy to diffuse into the surrounding environment, which can easily lead to local overheating.

[0008] The operating performance of semiconductor components is closely related to temperature. When the temperature is too high, the chip may enter thermal throttling mode, which automatically reduces the operating frequency to avoid overheating damage. This can cause system performance to degrade or even shut down completely.

[0009] Secondly, high temperatures can affect the materials inside the chip, causing changes in the physical properties of the components and generating electrical instabilities. For example, the resistance of a conductor increases as the temperature rises, which can cause the circuit to malfunction or fail.

[0010] High temperatures will accelerate the aging of materials inside the chip and reduce the life of the chip. Most failure mechanisms of electronic components are directly related to temperature. Long-term high temperatures will cause thermal fatigue and the chip may eventually fail. Summary of the invention

[0011] Based on this, it is necessary to address the above problems and propose a MOS tube upper and lower cover clip bonding packaging method and packaging structure.

[0012] An embodiment of the present application provides a method for bonding and encapsulating the upper and lower covers of a MOS transistor. The method includes:

[0013] Fix the lower heat sink cover on one side of the substrate;

[0014] Fix the chip on the side of the lower heat sink cover away from the substrate and make the lower heat sink cover fit with the chip;

[0015] Connect the gate of the chip and the pin of the substrate with a bonding wire;

[0016] Fix the upper heat sink cover on the source electrode of the chip and the pin of the substrate and make the upper heat sink cover fit with the chip to obtain a pre-processed assembly;

[0017] Wrap the pre-processed assembly with a plastic encapsulation material and perform a curing process to form an encapsulated MOS component.

[0018] In at least one embodiment of the present application, the steps before fixing the lower heat sink cover on one side of the substrate further include:

[0019] Clean and activate the surface of the substrate.

[0020] In at least one embodiment of the present application, the specific steps of fixing the chip on the side of the lower heat sink cover away from the substrate and making the lower heat sink cover fit with the chip include:

[0021] Paste the chip on the side of the lower heat sink cover away from the substrate through an adhesive layer;

[0022] And fix the chip to the lower heat sink cover by means of high-temperature reflow soldering.

[0023] In at least one embodiment of the present application, the specific steps of wrapping the pre-processed assembly with a plastic encapsulation material and performing a curing process to form an encapsulated MOS component include:

[0024] Put the pre-processed assembly into a mold, inject a plastic encapsulation material into the mold, and make the plastic encapsulation material wrap the chip, the bonding wire, the upper heat sink cover and the lower heat sink cover, so that the plastic encapsulation material forms an encapsulation shell outside the chip, the bonding wire, the upper heat sink cover and the lower heat sink cover to obtain an encapsulated MOS component;

[0025] Wherein, the injection pressure range is 5 - 10 MPa.

[0026] In at least one embodiment of the present application, the method further includes:

[0027] The side of the substrate away from the upper heat sink cover is an exposed surface;

[0028] Exposing the exposed surface of the substrate in the packaged MOS device, and electroplating the exposed surface and the pins to form an electroplating layer on the exposed surface and the pins to obtain a packaged strip;

[0029] Wherein, the thickness of the electroplating layer is 3-5um.

[0030] In at least one embodiment of the present application, the method further includes:

[0031] Cutting the packaged strips to obtain individual MOS tube packages, and cleaning each of the MOS tube packages;

[0032] Among them, the cutting speed is 50-100mm / s.

[0033] In at least one embodiment of the present application, the thickness of the adhesive layer is 20-50 um.

[0034] In at least one embodiment of the present application, the diameter of the bonding wire is 1-2 mil.

[0035] An embodiment of the present application provides a MOS tube upper and lower cover clip bonding packaging structure, which is applied to the MOS tube upper and lower cover clip bonding packaging method as described in any one of the above, and the MOS tube upper and lower cover clip bonding packaging structure includes:

[0036] a base plate having a mounting side;

[0037] A heat dissipation lower cover, arranged on the mounting side of the substrate;

[0038] A chip is fixed on a side of the heat dissipation lower cover away from the substrate;

[0039] A bonding wire, one end of which is connected to the gate of the chip, and the other end of which is connected to the pin of the substrate;

[0040] A heat dissipation cover, one end of which is fixed to the source electrode of the chip, and the other end of which is fixed to the pin of the substrate;

[0041] The plastic packaging material is wrapped around the chip, the bonding wires, the heat dissipation upper cover and the heat dissipation lower cover.

[0042] In at least one embodiment of the present application, the substrate has an exposed side on a side away from the mounting side, and the exposed side and a side of the substrate pin close to the exposed side are both provided with an electroplating layer;

[0043] The MOS tube upper and lower cover clip bonding packaging structure also includes:

[0044] The paste layer is attached to the chip at one end and to the side of the lower heat sink away from the substrate at the other end.

[0045] Implementing the MOS transistor upper and lower cover clip bonding and encapsulation method and encapsulation structure of this embodiment will have at least the following beneficial effects:

[0046] For the MOS transistor upper and lower cover clip bonding and encapsulation method and encapsulation structure provided above, by separately installing the lower heat sink and the upper heat sink on both sides of the chip and attaching them to both sides of the chip, the heat generated by the chip can be conducted to the outside through the upper heat sink and the lower heat sink, so as to improve the heat dissipation efficiency of the MOS transistor, enhance electrical performance, strengthen mechanical reliability, and miniaturize the volume, etc.

[0047] During heat dissipation, the lower heat sink is used to contact the chip or the radiator to conduct the generated heat to the outside to achieve the heat dissipation effect. At the same time, the upper heat sink is attached to the other side of the chip, and the heat generated on the chip can be conducted to the outside through the upper heat sink, thus realizing efficient heat dissipation.

[0048] This MOS transistor upper and lower cover clip bonding and encapsulation method is applicable to power MOSFETs. Compared with the traditional single-chip encapsulation, the method of using clip bonding and encapsulation with the upper heat sink and the lower heat sink can improve heat dissipation efficiency, enhance electrical performance, strengthen mechanical reliability, and miniaturize the volume, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0050] Among them:

[0051] Figure 1 is a three-dimensional view of the MOS transistor upper and lower cover clip bonding and encapsulation structure in an embodiment;

[0052] Figure 2 is another three-dimensional view of the MOS transistor upper and lower cover clip bonding and encapsulation structure in an embodiment;

[0053] Figure 3 is an exploded view of the MOS transistor upper and lower cover clip bonding and encapsulation structure in an embodiment;

[0054] Figure 4 is a flowchart of the MOS transistor upper and lower cover clip bonding and encapsulation method in an embodiment.

[0055] 100. MOS transistor upper and lower cover clip bonding and encapsulation structure;

[0056] 110. Heat dissipation lower cover;

[0057] 120. Chip; 121. Gate; 122. Source;

[0058] 130. Bonding wire;

[0059] 140. Substrate; 150. Pin; 140a. Exposed surface; 140b. Mounting side;

[0060] 160. Encapsulation material;

[0061] 170. Adhesive layer;

[0062] 180. Heat dissipation upper cover. Detailed implementation manners

[0063] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0064] An embodiment of the present application provides a method for bonding and encapsulating the upper and lower covers of a MOS transistor, and the method includes:

[0065] Fix the heat dissipation lower cover 110 on one side of the substrate 140;

[0066] Fix the chip 120 on the side of the heat dissipation lower cover 110 away from the substrate 140, and make the heat dissipation lower cover 110 fit with the chip 120;

[0067] Connect the gate 121 of the chip 120 and the pin 150 of the substrate 140 by using a bonding wire 130;

[0068] Fix the heat dissipation upper cover 180 on the source 122 of the chip 120 and the pin 150 of the substrate 140, and make the heat dissipation upper cover 180 fit with the chip 120 to obtain a pre-processed assembly;

[0069] Wrap the pre-processed assembly with an encapsulation material 160 and perform a curing treatment to form an encapsulated MOS component.

[0070] Please refer to Figures 1 - 4, in this embodiment, by separately installing the heat dissipation lower cover 110 and the heat dissipation upper cover 180 on both sides of the chip 120 and fitting them to both sides of the chip 120, the heat generated by the chip 120 can be conducted to the outside through the heat dissipation upper cover 180 and the heat dissipation lower cover 110, so as to improve the heat dissipation efficiency of the MOS transistor, enhance the electrical performance, strengthen the mechanical reliability, and miniaturize the volume, etc.

[0071] During heat dissipation, the heat dissipation lower cover 110 is used to contact the chip 120 or the radiator to conduct the generated heat to the outside to achieve the heat dissipation effect. At the same time, the heat dissipation upper cover 180 is fitted to the other side of the chip 120, and the heat generated on the chip 120 can be conducted to the outside through the heat dissipation upper cover 180, thereby realizing efficient heat dissipation.

[0072] The upper and lower cover clip bonding encapsulation of this MOS transistor is applicable to power MOSFETs. Compared with the traditional single-chip 120 encapsulation, the method of using the heat dissipation upper cover 180 and the heat dissipation lower cover 110 for clip bonding encapsulation has improved heat dissipation efficiency, enhanced electrical performance, strengthened mechanical reliability, and miniaturized volume, etc.

[0073] By simultaneously contacting the heat dissipation upper cover 180 and the heat dissipation lower cover 110 with the radiator, the thermal resistance is reduced by 30%-50% compared with the single-sided heat dissipation encapsulation.

[0074] It should be noted that the heat dissipation upper cover 180 and the heat dissipation lower cover 110 are simultaneously in contact with the radiator or heat sink, so that the thermal resistance is significantly lower than that of the traditional encapsulation, and the junction temperature distribution of the chip 120 is more uniform, avoiding the problem of excessive local temperature caused by local hot spots, thereby extending the service life of the device.

[0075] It should be further noted that the heat dissipation upper cover 180 is made of a metal material or a high thermal conductivity plastic, and the general shape of the heat dissipation upper cover 180 is a patch, which is used to protect the chip 120 and assist in heat dissipation.

[0076] The heat dissipation lower cover 110 is made of a metal (such as metal copper, aluminum, etc.) or a ceramic material, and the general shape of the heat dissipation lower cover 110 is a patch, which directly contacts the radiator and the chip 120 and is used to dissipate heat from the chip 120.

[0077] The chip 120 is a MOSFET chip 120.

[0078] The package size can optimize the volume reduction by 70% compared with the traditional package, which is suitable for use in space-constrained ultra-thin devices. The package integrates a drive IC or a temperature sensor, is optimized for SiC / GaN devices, and supports power module IPM and higher switching.

[0079] The plastic encapsulation material 160 is epoxy resin.

[0080] The outer shape of the substrate 140 is generally rectangular, and the material is a copper substrate 140 or a ceramic substrate 140.

[0081] In at least one embodiment of the present application, the steps before fixing the heat dissipation lower cover 110 to one side of the substrate 140 further include:

[0082] Cleaning and activating the surface of the substrate 140.

[0083] Please refer to Figures 1 - 4 , in this embodiment, the substrate 140 is prepared, a copper substrate 140 or a ceramic substrate 140 is prepared, and the surface of the substrate 140 is cleaned and activated to prevent dust or foreign objects from existing on the substrate 140, and to avoid electrical abnormalities and dust-electricity effects during the encapsulation process.

[0084] In at least one embodiment of the present application, the specific steps of fixing the chip 120 to the side of the heat dissipation lower cover 110 away from the substrate 140 and making the heat dissipation lower cover 110 fit the chip 120 include:

[0085] Pasting the chip 120 to the side of the heat dissipation lower cover 110 away from the substrate 140 through the adhesive layer 170;

[0086] And fixing the chip 120 to the heat dissipation lower cover 110 by means of high-temperature reflow soldering.

[0087] In at least one embodiment of the present application, the thickness of the adhesive layer 170 is 20 - 50 um.

[0088] In at least one embodiment of the present application, the diameter of the bonding wire 130 is 1 - 2 mil.

[0089] Please refer to Figures 1 - 4 , in this embodiment, during the chip 120 mounting process, first, the heat dissipation lower cover 110 is fixed to one side of the substrate 140 by welding or bonding to fix the heat dissipation lower cover 110 to the substrate 140.

[0090] Then, a layer of adhesive layer 170 with a thickness of 20 - 50 um is coated on the heat dissipation lower cover 110, and then the chip 120 is pasted to the heat dissipation lower cover 110 through the adhesive layer 170 to minimize the thermal resistance and contact resistance between the chip 120, the heat dissipation lower cover 110, and the substrate 140.

[0091] Next, the chip 120 is fixed on the heat dissipation lower cover 110 by means of high-temperature reflow soldering. During the soldering process, the reflow temperature curve needs to conform to the melting point of the adhesive layer 170.

[0092] The chip 120 can be fixed on the lower heat sink cover 110, facilitating the direct conduction of the heat on the subsequent chip 120 to the lower heat sink cover 110, and the lower heat sink cover 110 conducts heat dissipation treatment.

[0093] After fixing the chip 120 to the lower heat sink cover 110, the two ends of the bonding wire 130 are respectively fixed to the gate 121 of the chip 120 and the pin 150 of the substrate 140 by using ultrasonic bonding technology or thermocompression bonding technology to complete the installation and connection of the bonding wire 130, so as to ensure the bonding strength and the reliability of the electrical connection.

[0094] It should be noted that the material of the bonding wire 130 is made of gold, copper or aluminum material.

[0095] After the connection of the bonding wire 130 is completed, the upper heat sink cover 180 is fixed to the source 122 of the chip 120 and the pin 150 of the substrate 140 by welding or bonding, so as to complete the installation and fixation of the upper heat sink cover 180 and obtain the initially processed assembly.

[0096] It should be noted that the paste layer 170 is made of a soft solder material (such as tin-silver alloy) or a conductive adhesive material to minimize the thermal resistance and contact resistance between the chip 120, the lower heat sink cover 110 and the substrate 140.

[0097] In at least one embodiment of the present application, the specific steps of wrapping the initially processed assembly with the encapsulation material 160 and performing a curing treatment to form an encapsulated MOS component include:

[0098] Put the initially processed assembly into a mold, inject the encapsulation material 160 into the mold, and make the encapsulation material 160 wrap the chip 120, the bonding wire 130, the upper heat sink cover 180 and the lower heat sink cover 110, so that the encapsulation material 160 forms an encapsulation shell outside the chip 120, the bonding wire 130, the upper heat sink cover 180 and the lower heat sink cover 110 to obtain an encapsulated MOS component;

[0099] Among them, the injection pressure range is 5 - 10 MPa.

[0100] Please refer to Figures 1 - 4 , in this embodiment, in the encapsulation molding stage, the encapsulation material 160 is injected using a mold, so that the injected encapsulation material 160 wraps the chip 120, the bonding wire 130, the upper heat sink cover 180 and the lower heat sink cover 110 of the initially processed assembly, and is cured to form an encapsulation shell to obtain an encapsulated MOS component.

[0101] The encapsulation molding material 160 (epoxy resin) is cured in a high-temperature environment to ensure the mechanical strength and thermal stability of the encapsulation structure. At the same time, the encapsulation molding material 160 has high thermal conductivity and low coefficient of thermal expansion, enhancing the electrical performance.

[0102] Through the short pin 150 or no-pin 150 design, the inductance after encapsulation is < 5 nH, reducing the parasitic inductance during the switching process and enabling it to be applicable to high-frequency application environments.

[0103] The substrate 140 and the low-resistance interconnection technology reduce the conduction-generated resistance to below 1 mΩ.

[0104] At the same time, through the metal shielding of the heat dissipation upper cover 180, the electromagnetic interference is reduced to meet the electromagnetic interference level standard.

[0105] Using this method for encapsulation optimizes the layout inside the encapsulation, reduces signal reflection, and effectively improves the switching speed in product applications.

[0106] Since the encapsulation molding material 160 is used outside the chip 120, the bonding wire 130, the heat dissipation upper cover 180, and the heat dissipation lower cover 110 to form an encapsulation shell, and the heat dissipation upper cover 180 and the heat dissipation lower cover 110 are combined, the overall mechanical strength is increased to 2 times that of the traditional encapsulation.

[0107] Since the encapsulation molding material 160 is made of epoxy resin material, the water absorption rate is < 0.1%.

[0108] At the same time, the combination of the heat dissipation upper cover 180 and the heat dissipation lower cover 110 makes the overall vibration resistance and high-temperature resistance performance higher.

[0109] In at least one embodiment of the present application, the method further includes:

[0110] One side of the substrate 140 away from the heat dissipation upper cover 180 is the exposed surface 140a;

[0111] The exposed surface 140a of the substrate 140 in the encapsulated MOS component is subjected to an exposure treatment, and the exposed surface 140a and the pins 150 are electroplated so that an electroplated layer is formed on the exposed surface 140a and the pins 150 to obtain an encapsulated strip;

[0112] Among them, the thickness of the electroplated layer is 3 - 5 μm.

[0113] Please refer to Figures 1 - 4 , in this embodiment, the substrate 140 is made of copper material. The exposed surface 140a of the substrate 140 is subjected to a copper leakage treatment, that is, a large area of metal copper leakage is reserved at the bottom of the encapsulation, enabling it to be directly welded to the PCB and suitable for SMT soldering.

[0114] Meanwhile, electroplating is performed on the copper leakage area of the exposed surface 140a, and electroplating treatment is performed on the pins 150 of the substrate 140 to form an electroplated layer on the exposed surface 140a and the pins 150, and the electroplated layer is used to improve conductivity and corrosion resistance.

[0115] It should be further noted that the thickness of the electroplated layer is 3 - 5 μm, so that the thickness of the electroplated layer will not be too thin or too thick, avoiding the problem of too low corrosion resistance caused by being too thin, and at the same time avoiding affecting the overall volume due to being too thick.

[0116] It should be further noted that the material of the electroplated layer is nickel or tin.

[0117] In at least one embodiment of the present application, the method further includes:

[0118] Performing a cutting process on the encapsulated strip to obtain individual MOS transistor packages, and cleaning each of the MOS transistor packages;

[0119] Wherein, the cutting speed is 50 - 100 mm / s.

[0120] Please refer to Figures 1 - 4 , in this embodiment, after electroplating, the encapsulated strip has multiple MOS transistor packages. Laser cutting or mechanical cutting is used to cut the encapsulated strip to obtain the cut individual MOS transistor packages, and each MOS transistor package is cleaned to ensure the cleanliness of the encapsulation surface.

[0121] It should be noted that the cutting speed is 50 - 100 mm / s, so as to avoid the problem of damage to the plastic encapsulation material 160 of the package due to too fast cutting speed, and at the same time avoid the problem of affecting the processing efficiency due to too slow cutting speed.

[0122] It should be further noted that in this encapsulation method, the heat dissipation upper cover 180 is joined and fitted to the source electrode 122 of the chip 120, making the process simpler. Compared with the existing process that requires wire bonding on the chip 120 first and then performing a wire bonding operation with the source electrode 122 of the chip 120, the processing efficiency is higher.

[0123] Secondly, wire bonding is completed on the gate 121 in the WB, the heat dissipation upper cover 180 is welded on the chip 120, and the extension feet of the heat dissipation upper cover 180 are bonded to the source electrode 122 of the chip 120, thereby reducing the existence of inductance residue generated by the traditional wire bonding method.

[0124] It should be further noted that at the same time, in this method, an integrated three-dimensional heat dissipation upper cover 180 is adopted, which is attached to the chip 120 over a large area. The bent foot part at the other end is connected to the source electrodes 122S1, 122S2, and 122S3, and the overall packaging is formed according to the actual scenario. After the exposed part of the heat dissipation upper cover 180 after packaging is molded, plastic encapsulation is carried out, and then electroplating is carried out, so as to effectively prevent failure caused by water vapor and external humidity factors.

[0125] The heat dissipation upper cover 180 is attached to the chip 120 over a large area, making the heat dissipation effect of the chip 120 better. Since it is attached to the chip 120 over a large area, the inductance generated by wire bonding is reduced.

[0126] In the traditional method, the formed substrate 140 is directly attached to an external radiator for heat dissipation. In this method, the heat dissipation upper cover 180, the heat dissipation lower cover 110, and the substrate 140 are simultaneously attached to the heat sink to achieve higher heat dissipation.

[0127] An embodiment of the present application provides a MOS transistor upper and lower cover clip bonding and encapsulation structure 100, which is applied to the MOS transistor upper and lower cover clip bonding and encapsulation as described in any one of the above. The MOS transistor upper and lower cover clip bonding and encapsulation structure 100 includes:

[0128] A substrate 140 having an installation side 140b;

[0129] A heat dissipation lower cover 110 provided on the installation side 140b of the substrate 140;

[0130] A chip 120 fixed on the side of the heat dissipation lower cover 110 away from the substrate 140;

[0131] A bonding wire 130, one end of which is connected to the gate 121 of the chip 120, and the other end is connected to the pin 150 of the substrate 140;

[0132] A heat dissipation upper cover 180, one end of which is fixed on the source electrode 122 of the chip 120, and the other end is fixed on the pin 150 of the substrate 140;

[0133] A plastic encapsulation material 160 wrapped outside the chip 120, the bonding wire 130, the heat dissipation upper cover 180, and the heat dissipation lower cover 110.

[0134] Please refer to Figures 1 - 4In this embodiment, the chip 120 is sandwiched and bonded by the heat dissipation lower cover 110 and the heat dissipation upper cover 180, thereby optimizing the heat dissipation effect of the chip 120. The heat dissipation lower cover 110 and the heat dissipation upper cover 180 are both in contact with the heat sink, thereby reducing thermal resistance. The heat dissipation lower cover 110 and the heat dissipation upper cover 180 are layered and double-sided for heat dissipation, thereby improving heat dissipation efficiency. The bonding wires 130 are used for interconnection, thereby reducing the vertical thermal resistance path, thereby improving heat dissipation efficiency.

[0135] Secondly, a short pin 150 or a pinless 150 design is used to make the package inductance less than 5nH, reducing the parasitic inductance during the switching process, making it suitable for high-frequency fields.

[0136] The heat dissipation cover 180 shields the chip 120 , thereby reducing electromagnetic interference.

[0137] The heat dissipation upper cover 180 and the heat dissipation lower cover 110 are combined and sealed in plastic, so as to strengthen the overall structure and make the overall mechanical strength higher.

[0138] The packaging volume using this structure is smaller than that of the traditional one.

[0139] By optimizing the packaging process, the yield rate can be higher.

[0140] The upper and lower cover clip bonding packaging technology structure is adopted to achieve the optimal balance between power density, efficiency and reliability.

[0141] In at least one embodiment of the present application, the substrate 140 has an exposed side on a side away from the mounting side 140 b , and the exposed side and a side of the pin 150 of the substrate 140 close to the exposed side are both provided with an electroplating layer;

[0142] The MOS tube upper and lower cover clip bonding packaging structure 100 also includes:

[0143] The adhesive layer 170 has one end attached to the chip 120 , and the other end attached to a side of the heat dissipation lower cover 110 away from the substrate 140 .

[0144] Please refer to Figures 1 - 4 In this embodiment, the pin 150 and the exposed side are covered by a plating layer, thereby improving the overall conductivity and corrosion resistance.

[0145] The chip 120 is fixed on the heat dissipation lower cover 110 by reflow soldering through the adhesive layer 170 , ensuring that the thermal resistance and contact resistance between the chip 120 , the heat dissipation lower cover 110 and the substrate 140 are minimized.

[0146] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0147] The above-described embodiments merely represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A method for bonding and packaging upper and lower cover clips of a MOS tube, characterized in that: The method comprises: Fix the heat dissipation lower cover to one side of the substrate; Fixing the chip on the side of the heat dissipation lower cover away from the substrate, and making the heat dissipation lower cover fit the chip; Connecting the gate of the chip to the pin of the substrate using bonding wires; Fixing a heat dissipation cover to the source electrode of the chip and the pins of the substrate, and fitting the heat dissipation cover to the chip to obtain a pre-processed assembly; The preliminarily processed assembly is wrapped with a plastic packaging material and cured to form a packaged MOS component.

2. The MOS tube upper and lower cover clip bonding packaging method according to claim 1, characterized in that: The step before fixing the heat dissipation lower cover to one side of the substrate also includes: The surface of the substrate is cleaned and activated.

3. The MOS tube upper and lower cover clip bonding packaging method according to claim 1, characterized in that: The specific steps of fixing the chip on the side of the heat dissipation lower cover away from the substrate and making the heat dissipation lower cover fit the chip include: Adhere the chip to a side of the heat dissipation lower cover away from the substrate through an adhesive layer; The chip is fixed to the heat dissipation lower cover by high-temperature reflow soldering.

4. The MOS tube upper and lower cover clip bonding packaging method according to claim 1, characterized in that: The specific steps of using a plastic packaging material to wrap the pre-processed assembly and performing a curing treatment to form a packaged MOS component include: Placing the preliminarily processed assembly into a mold, injecting a plastic encapsulation material into the mold, and wrapping the chip, the bonding wire, the heat dissipation upper cover and the heat dissipation lower cover with the plastic encapsulation material, so that the plastic encapsulation material forms a packaging shell outside the chip, the bonding wire, the heat dissipation upper cover and the heat dissipation lower cover to obtain a packaged MOS component; Among them, the injection pressure range is 5-10MPa.

5. The MOS tube upper and lower cover clip bonding packaging method according to claim 4, characterized in that: The method further comprises: A side of the substrate away from the heat dissipation upper cover is an exposed surface; Exposing the exposed surface of the substrate in the packaged MOS device, and electroplating the exposed surface and the pins to form an electroplating layer on the exposed surface and the pins to obtain a packaged strip; Wherein, the thickness of the electroplating layer is 3-5um.

6. The MOS tube upper and lower cover clip bonding packaging method according to claim 5, characterized in that: The method further comprises: Cutting the packaged strips to obtain individual MOS tube packages, and cleaning each of the MOS tube packages; Among them, the cutting speed is 50-100mm / s.

7. The MOS tube upper and lower cover clip bonding packaging method according to claim 3, characterized in that: The thickness of the adhesive layer is 20-50 um.

8. The MOS tube upper and lower cover clip bonding packaging method according to claim 1, characterized in that: The diameter of the bonding wire is 1-2 mil.

9. A MOS tube upper and lower cover clip bonding packaging structure, applied to the MOS tube upper and lower cover clip bonding packaging method as described in any one of claims 1 to 8, characterized in that: The MOS tube upper and lower cover clip bonding packaging structure comprises: a base plate having a mounting side; A heat dissipation lower cover, arranged on the mounting side of the substrate; A chip is fixed on a side of the heat dissipation lower cover away from the substrate; A bonding wire, one end of which is connected to the gate of the chip, and the other end of which is connected to the pin of the substrate; A heat dissipation cover, one end of which is fixed to the source electrode of the chip, and the other end of which is fixed to the pin of the substrate; The plastic packaging material is wrapped around the chip, the bonding wires, the heat dissipation upper cover and the heat dissipation lower cover.

10. The MOS tube upper and lower cover clip bonding packaging structure according to claim 9, characterized in that: The substrate has an exposed side on a side away from the mounting side, and the exposed side and a side of the substrate pin close to the exposed side are both provided with an electroplating layer; The MOS tube upper and lower cover clip bonding packaging structure also includes: The adhesive layer has one end attached to the chip and the other end attached to a side of the heat dissipation lower cover away from the substrate.

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