A clamping drive circuit for a dual-phase configuration applied to a forward active-clamp PWM controller

Abstract

The present invention relates to a clamping drive circuit with a dual-phase configuration applied to a forward active-clamp PWM controller. The present invention includes a bidirectional resistor-to-current module connected to an external resistor RSET for converting the external resistor RSET into an internal bias current linearly corresponding to the resistance value of the external resistor RSET; a current direction detection module for detecting and outputting a circuit configuration signal according to the direction of the internal bias current; a dead-time delay module for receiving the output signal of an RS flip-flop and delaying the output signal of the RS flip-flop by a rising edge or a falling edge according to the circuit configuration signal to generate a delay time; and a signal logic output module for outputting a drive control signal and a clamping control signal that meet the requirements of high-side clamping or low-side clamping according to the delay time and the circuit configuration signal. The present invention is compatible with the requirements of high-side clamping and low-side clamping, reducing costs.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly to a clamped drive circuit for a forward active-clamp PWM controller in a dual-phase configuration. Background Art

[0002] In the switching power supply topology, the forward converter has been widely used in fields such as communication power supplies and industrial power supplies due to its structural simplicity and low output ripple characteristics. However, the forward converter faces a technical problem of transformer core reset in practical applications. Specifically, after each switching cycle ends, the magnetizing current of the transformer must be reset to zero to prevent core saturation, and this process has a decisive impact on the efficiency and stability of the power supply system. Although the traditional RCD clamping technology can solve this problem, its significant heat loss causes the system efficiency to decrease by about 2 - 5%. The forward active-clamp technology was proposed and patented by VICOR Corporation in 1982 and has attracted much attention due to its excellent operating efficiency and high power density. Since the expiration of the patent protection period in 2002, this technology has been widely adopted by major module power supply manufacturers.

[0003] The forward active-clamp technology is mainly divided into two topological structures: high-side clamping and low-side clamping. The circuit configuration of the high-side clamping technology is as Figure 1 shown. The clamping switch tube and the capacitor are connected in series and then paralleled to the high-voltage side of the primary of the transformer. In this topology, the clamping signal and the main switch signal need to maintain a 180° phase difference to ensure the normal operation of the system. The circuit configuration of the low-side clamping technology is as Figure 2 shown. The clamping switch tube and the capacitor are connected in series and then paralleled to the main switch tube. In this topology, the clamping signal and the main switch tube signal are in the same phase.

[0004] To avoid damage to the inductor caused by the simultaneous conduction of the main switch and the clamping switch, a dead time needs to be set between them. The configuration of the dead time needs to comprehensively consider the peripheral circuit parameters. Therefore, in the design of the drive chip, a specific dead-time control circuit module is usually integrated. By adjusting the resistance value of R SET in the peripheral circuit, a programmable dead time can be achieved. As Figure 3 shown, the dead-time control circuit module is based on a unity-gain negative feedback circuit, which fixes the voltage drop across the clamping access resistor R ` SET to a specific potential, thereby setting an internal current that linearly changes with the resistance value of R SET . This internal current charges the capacitor to generate the required delay, that is, the dead time.

[0005] Since the forward active-clamp technology is divided into high-side clamping and low-side clamping, there are significant differences in the phase relationship between its control signal and the drive control signal. Therefore, implementing these two solutions on a single drive control chip usually requires additional pins for phase configuration, which will increase the system cost. Summary of the Invention

[0006] To this end, the present invention provides a clamped drive circuit with a dual-phase configuration for a forward active-clamped PWM controller, which can support dual-phase configuration without adding pins, be compatible with the requirements of high-side clamping and low-side clamping, optimize the circuit design and reduce the overall cost; through an innovative circuit architecture, it achieves a balance between the flexibility of phase configuration and cost-effectiveness; through a single-pin external resistor R SET , not only can the dead time be set, but also the phase of the clamped drive signal can be configured simultaneously, realizing the dual-parameter coordinated configuration of the dead time and the phase of the drive signal.

[0007] To solve the above technical problems, the present invention provides a clamped drive circuit with a dual-phase configuration for a forward active-clamped PWM controller, including:

[0008] A bidirectional resistor-to-current module, connected to the external resistor RSET, is used to convert the external resistor RSET into an internal bias current linearly corresponding to the resistance value of the external resistor RSET. Among them, by connecting the negative pole of the external resistor RSET to the power supply level or the ground level, the selection of the direction of the internal bias current is realized;

[0009] A current direction detection module, connected to the bidirectional resistor-to-current module, is used to detect and output a circuit configuration signal according to the direction of the internal bias current, and the circuit configuration signal is used to characterize the phase relationship between the drive control signal and the clamped control signal;

[0010] A dead-time delay module, respectively connected to the bidirectional resistor-to-current module and the current direction detection module, is used to receive the output signal of the RS flip-flop, and according to the circuit configuration signal, delay the output signal of the RS flip-flop by the rising edge or the falling edge, and generate a delay time;

[0011] A signal logic output module, respectively connected to the current direction detection module and the dead-time delay module, is used to output a drive control signal and a clamped control signal that meet the requirements of high-side clamping or low-side clamping according to the delay time and the circuit configuration signal.

[0012] In an embodiment of the present invention, the bidirectional resistor-to-current module includes a resistor R101, a resistor R102, an operational amplifier A103, an NMOS transistor N104, a PMOS transistor P105, an NMOS transistor N106, and a PMOS transistor P107;

[0013] Among them, one end of the resistor R101 is connected to the power supply voltage, and the other end of the resistor R101 is respectively connected to one end of the resistor R102 and the positive input terminal of the operational amplifier A103, and the other end of the resistor R102 is grounded;

[0014] The source of PMOS transistor P107 is connected to the power supply voltage, and the drain of PMOS transistor P107 is connected to its own gate and the drain of NMOS transistor N104 respectively;

[0015] The gates of NMOS transistor N104 and PMOS transistor P105 are connected to the output terminal of operational amplifier A103 respectively;

[0016] The sources of NMOS transistor N104 and PMOS transistor P105 and the negative input terminal of operational amplifier A103 are all connected to the positive pole of off-chip resistor RSET;

[0017] The drain of NMOS transistor N106 is connected to its own gate and the drain of PMOS transistor P105 respectively, and the source of NMOS transistor N106 is grounded.

[0018] In an embodiment of the present invention, the resistance values of resistor R101 and resistor R102 are equal.

[0019] In an embodiment of the present invention, the current direction detection module includes PMOS transistor P401, resistor R402, NMOS transistor N403, resistor R404 and AND gate A405;

[0020] Wherein, the gate of PMOS transistor P401 is connected to the gate of PMOS transistor P107, the source of PMOS transistor P401 is connected to the power supply voltage, the drain of PMOS transistor P401 is connected to the first input terminal of AND gate A405 and one end of resistor R402 respectively, and the other end of resistor R402 is grounded;

[0021] The gate of NMOS transistor N403 is connected to the gate of NMOS transistor N106, the drain of NMOS transistor N403 is connected to the power supply voltage through resistor R404 and the second input terminal of AND gate A405 respectively, and the source of NMOS transistor N403 is grounded; the output terminal of AND gate A405 outputs a circuit configuration signal.

[0022] In an embodiment of the present invention, when the off-chip resistor R SET is connected to the power supply level, the circuit configuration signal is "0", and when the off-chip resistor R SET is grounded, the circuit configuration signal is "1".

[0023] In an embodiment of the present invention, the dead zone delay module includes inverter A215, two pairs of first delay circuits and second delay circuits with the same structure;

[0024] The first delay circuit includes PMOS transistor P201, NMOS transistor N202, PMOS transistor P203, PMOS transistor P205, NMOS transistor N204, NMOS transistor N206, and capacitor C207;

[0025] The second delay circuit includes PMOS transistor P209, NMOS transistor N210, PMOS transistor P211, PMOS transistor P213, NMOS transistor N212, NMOS transistor N214, and capacitor C208;

[0026] Among them, the input terminal of inverter A215 is connected to the output signal of the RS flip-flop;

[0027] The output terminal of inverter A215 is connected to the gates of PMOS transistor P211 and NMOS transistor N204 respectively;

[0028] The gates of PMOS transistor P201 and PMOS transistor P209 are respectively connected to the gate of PMOS transistor P401;

[0029] The sources of PMOS transistor P201, PMOS transistor P203, PMOS transistor P209, and PMOS transistor P211 are connected to the power supply voltage;

[0030] The sources of NMOS transistor N202, NMOS transistor N204, NMOS transistor N210, and NMOS transistor N212 are grounded;

[0031] The gates of NMOS transistor N202 and NMOS transistor N210 are respectively connected to the gate of NMOS transistor N403;

[0032] The gates of PMOS transistor P203 and NMOS transistor N212 are connected to the input terminal of inverter A215;

[0033] The drain of PMOS transistor P201 is connected to the drain of NMOS transistor N202; the drain of PMOS transistor P203 is connected to the source of PMOS transistor P205; the drain of PMOS transistor P205 is connected to the drain of NMOS transistor N206; the source of NMOS transistor N206 is connected to the drain of NMOS transistor N204;

[0034] One end of capacitor C207 is respectively connected between the drain of PMOS transistor P201 connected to the drain of NMOS transistor N202 and between the drain of PMOS transistor P205 connected to the drain of NMOS transistor N206, and the other end of capacitor C207 is grounded;

[0035] The drain of PMOS transistor P209 is connected to the drain of NMOS transistor N210; the drain of PMOS transistor P211 is connected to the source of PMOS transistor P213; the drain of PMOS transistor P213 is connected to the drain of NMOS transistor N214, and the source of NMOS transistor N214 is connected to the drain of NMOS transistor N212;

[0036] One end of capacitor C208 is respectively connected between the drain of PMOS transistor P209 connected to the drain of NMOS transistor N210 and between the drain of PMOS transistor P213 connected to the drain of NMOS transistor N214, and the other end of capacitor C208 is grounded.

[0037] In an embodiment of the present invention, the capacitance values of capacitor C207 and capacitor C208 are equal.

[0038] In an embodiment of the present invention, the signal logic output module includes operational amplifier A301, operational amplifier A302, inverter A303, inverter A304 and multiplexer A305;

[0039] The negative input terminals of operational amplifier A301 and operational amplifier A302 are respectively connected between resistor R101 and resistor R102;

[0040] The positive input terminal of operational amplifier A301 is connected to one end of capacitor C208;

[0041] The positive input terminal of operational amplifier A302 is connected to one end of capacitor C207;

[0042] The output terminal of operational amplifier A301 is connected to the input terminal of inverter A303, and the output terminal of inverter A303 outputs a clamping control signal;

[0043] The output terminal of operational amplifier A302 is connected to the input terminal of inverter A304, the output terminal of inverter A304 is connected to the first data input terminal of multiplexer A305, and the output terminal of multiplexer A305 outputs a drive control signal;

[0044] The second data input terminal of multiplexer A305 is connected to the input terminal of inverter A304;

[0045] The selection control terminal of multiplexer A305 is respectively connected to the output terminal of AND gate A405, the gates of PMOS transistor P205 and NMOS transistor N206, and the gates of PMOS transistor P213 and NMOS transistor N214.

[0046] The above technical solutions of the present invention have the following advantages compared with the prior art:

[0047] A clamping drive circuit with a dual-phase configuration for a forward active-clamp PWM controller according to the present invention can support dual-phase configuration without adding pins, be compatible with the requirements of high-side clamping and low-side clamping, optimize the circuit design and reduce the overall cost; through an innovative circuit architecture, it achieves a balance between the flexibility of phase configuration and cost-effectiveness; through the external resistor RSET of a single pin, not only can the dead time be set, but also the phase of the clamping drive signal can be configured simultaneously, realizing the co-configuration of two parameters, namely the dead time and the phase of the drive signal. Description of the Drawings

[0048] In order to make the content of the present invention easier to be clearly understood, the following further details the present invention according to specific embodiments of the present invention in conjunction with the drawings.

[0049] Figure 1 It is a circuit of the existing high-side clamping technology for forward active-clamp.

[0050] Figure 2 It is a circuit of the existing low-side clamping technology for forward active-clamp.

[0051] Figure 3 It is an existing internal dead-time control circuit for forward active-clamp applied to low-side clamping.

[0052] Figure 4 It is a schematic diagram of the functional modules of the clamping circuit with a dual-phase configuration for a forward active-clamp PWM controller according to the present invention.

[0053] Figure 5 It is an embodiment of the clamping circuit with a dual-phase configuration for a forward active-clamp PWM controller according to the present invention.

[0054] Figure 6 It is a waveform diagram of important nodes in the clamping circuit with a dual-phase configuration for a forward active-clamp PWM controller according to the present invention.

[0055] Explanation of the reference numerals in the drawings of the specification:

[0056] 100. Bidirectional resistor-to-current module; 200. Dead-time delay module; 300. Signal logic output module; 400. Current direction detection module. Detailed Embodiments

[0057] The following further illustrates the present invention in conjunction with the drawings and specific embodiments, so that those skilled in the art can better understand the present invention and be able to implement it, but the embodiments cited do not limit the present invention.

[0058] In the present invention, the meaning of "several" is one or more, the meaning of "multiple" is two or more, and understandings such as "greater than", "less than", and "exceeding" do not include the corresponding number; understandings such as "above", "below", and "within" include the corresponding number. In the description of the present invention, if there is a description of "first" and "second", they are only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or implicitly indicating the sequence relationship of the indicated technical features.

[0059] In the present invention, unless otherwise clearly defined, terms such as "arranged", "installed", and "connected" should be understood in a broad sense. For example, they can be directly connected, or indirectly connected through an intermediate medium; they can be fixedly connected, or detachably connected, or integrally formed; they can be mechanically connected, or electrically connected or capable of communicating with each other; they can be the communication inside two components or the interaction relationship between two components. Those skilled in the art can reasonably determine the specific meanings of the above terms in the present invention in combination with the specific content of the technical solution.

[0060] Refer to Figure 4 As shown, a clamping drive circuit with a dual-phase configuration applied to a forward active-clamped PWM controller in this embodiment includes:

[0061] A bidirectional resistor-to-current module 100, connected to an external resistor RSET, is used to convert the external resistor RSET into an internal bias current linearly corresponding to the resistance value of the external resistor RSET. Among them, by connecting the negative electrode of the external resistor RSET to the power supply level or the ground level, the selection of the direction of the internal bias current is realized;

[0062] A current direction detection module 400, connected to the bidirectional resistor-to-current module 100, is used to detect and output a circuit configuration signal according to the direction of the internal bias current. The circuit configuration signal is used to characterize the phase relationship between the drive control signal and the clamping control signal, providing a basis for subsequent logical operations;

[0063] A dead-time delay module 200, respectively connected to the bidirectional resistor-to-current module 100 and the current direction detection module 400, is used to receive the output signal of the RS flip-flop, and according to the circuit configuration signal, delay the rising edge or falling edge of the output signal of the RS flip-flop, and generate a delay time, and this delay time is the dead time;

[0064] The signal logic output module 300 is respectively connected to the current direction detection module 400 and the dead zone delay module 200, and is configured to perform necessary logic operations according to the delay time and the circuit configuration signal, and output drive control signals and clamping control signals that meet the requirements of high-side clamping or low-side clamping, so as to ensure efficient and safe switching under the forward active clamping topology.

[0065] Specifically, the bidirectional resistor-to-current module 100 includes a resistor R101, a resistor R102, an operational amplifier A103, an NMOS transistor N104, a PMOS transistor P105, an NMOS transistor N106, and a PMOS transistor P107;

[0066] One end of the resistor R101 is connected to the power supply voltage, and the other end of the resistor R101 is respectively connected to one end of the resistor R102 and the positive input terminal of the operational amplifier A103, and the other end of the resistor R102 is grounded;

[0067] The source of the PMOS transistor P107 is connected to the power supply voltage, and the drain of the PMOS transistor P107 is respectively connected to its own gate and the drain of the NMOS transistor N104;

[0068] The gates of the NMOS transistor N104 and the PMOS transistor P105 are connected to the output terminal of the operational amplifier A103;

[0069] The sources of the NMOS transistor N104 and the PMOS transistor P105 and the negative input terminal of the operational amplifier A103 are all connected to the positive pole of the off-chip resistor RSET;

[0070] The drain of the NMOS transistor N106 is respectively connected to its own gate and the drain of the PMOS transistor P105, and the source of the NMOS transistor N106 is grounded.

[0071] Specifically, the resistor R101 and the resistor R102 are two resistors with equal and matching resistance values, which divide the power supply voltage VDD by half.

[0072] It should be noted that the operational amplifier A103 is connected in a unity-gain negative feedback configuration. Different from the traditional connection method, the output terminal of the operational amplifier A103 is not directly connected back to its negative input terminal, but is connected back to the negative input terminal through the source follower connection of the NMOS transistor N104 and the PMOS transistor P105. The sources of the NMOS transistor N104 and the PMOS transistor P105 are connected to each other and are connected to the positive pole of the off-chip resistor R SET When the off-chip resistor R SET is connected to the power supply level, the NMOS transistor N104 is in the off state, the PMOS transistor P105 is in the on state, and the current mirror NMOS transistor N106 starts to work and generates an internal bias current. When the off-chip resistor R SETWhen the ground level is reached, the PMOS transistor P105 is in the off state, the NMOS transistor N104 is in the on state, and the current mirror PMOS transistor P107 starts to work and generates an internal bias current. Regardless of how the external resistor R SET is connected, the magnitude of the generated internal bias current is .

[0073] Therefore, when the negative terminal of the external resistor R SET is connected to the power supply level, a bias current with the output direction of the NMOS as the current mirror is formed inside; when the negative terminal of the external resistor R SET is connected to the ground level, a bias current with the output direction of the PMOS current mirror is formed. Through this differential connection method of the external resistor, the flexible selection of the internal current direction is realized.

[0074] Specifically, the current direction detection module 400 includes a PMOS transistor P401, a resistor R402, an NMOS transistor N403, a resistor R404, and an AND gate A405;

[0075] Among them, the gate of the PMOS transistor P401 is connected to the gate of the PMOS transistor P107, the source of the PMOS transistor P401 is connected to the power supply voltage, and the drain of the PMOS transistor P401 is respectively connected to the first input terminal of the AND gate A405 and one end of the resistor R402, and the other end of the resistor R402 is grounded;

[0076] The gate of the NMOS transistor N403 is connected to the gate of the NMOS transistor N106, the drain of the NMOS transistor N403 is respectively connected to the power supply voltage through the resistor R404 and connected to the second input terminal of the AND gate A405, and the source of the NMOS transistor N403 is grounded; the output terminal of the AND gate A405 outputs a circuit configuration signal.

[0077] It should be noted that the current source PMOS transistor P401 and the load resistor R402 implement a current direction detection function. When the current mirror PMOS transistor P107 works, the drain of the PMOS transistor P401 outputs a high-level "1" signal to the first input terminal of the AND gate A405. The current source NMOS transistor N403 and the load resistor R404 implement a second current direction detection function. When the NMOS transistor current mirror N106 works, the drain of the NMOS transistor N403 outputs a ground-level "0" signal to the second input terminal of the AND gate A405. Finally, the output terminal of the AND gate A405 outputs a circuit configuration signal. When the external resistor R SET is connected to the power supply level, the circuit configuration signal is "0", and when the external resistor R SET is connected to the ground level, the circuit configuration signal is "1".

[0078] Specifically, the dead zone delay module 200 includes an inverter A215, two pairs of first delay circuits and second delay circuits with the same structure;

[0079] The first delay circuit includes a PMOS transistor P201, an NMOS transistor N202, a PMOS transistor P203, a PMOS transistor P205, an NMOS transistor N204, an NMOS transistor N206, and a capacitor C207;

[0080] The second delay circuit includes a PMOS transistor P209, an NMOS transistor N210, a PMOS transistor P211, a PMOS transistor P213, an NMOS transistor N212, an NMOS transistor N214, and a capacitor C208;

[0081] Wherein, the input end of the inverter A215 is connected to the output signal of the RS flip-flop;

[0082] The output end of the inverter A215 is connected to the gates of the PMOS transistor P211 and the NMOS transistor N204 respectively;

[0083] The gates of the PMOS transistor P201 and the PMOS transistor P209 are respectively connected to the gate of the PMOS transistor P401;

[0084] The sources of the PMOS transistor P201, the PMOS transistor P203, the PMOS transistor P209, and the PMOS transistor P211 are connected to the power supply voltage;

[0085] The sources of the NMOS transistor N202, the NMOS transistor N204, the NMOS transistor N210, and the NMOS transistor N212 are grounded;

[0086] The gates of the NMOS transistor N202 and the NMOS transistor N210 are respectively connected to the gate of the NMOS transistor N403;

[0087] The gates of the PMOS transistor P203 and the NMOS transistor N212 are connected to the input end of the inverter A215;

[0088] The drain of the PMOS transistor P201 is connected to the drain of the NMOS transistor N202; the drain of the PMOS transistor P203 is connected to the source of the PMOS transistor P205; the drain of the PMOS transistor P205 is connected to the drain of the NMOS transistor N206; the source of the NMOS transistor N206 is connected to the drain of the NMOS transistor N204;

[0089] One end of the capacitor C207 is respectively connected between the drain of the PMOS transistor P201 connected to the drain of the NMOS transistor N202 and between the drain of the PMOS transistor P205 connected to the drain of the NMOS transistor N206, and the other end of the capacitor C207 is grounded;

[0090] The drain of PMOS transistor P209 is connected to the drain of NMOS transistor N210; the drain of PMOS transistor P211 is connected to the source of PMOS transistor P213; the drain of PMOS transistor P213 is connected to the drain of NMOS transistor N214, and the source of NMOS transistor N214 is connected to the drain of NMOS transistor N212;

[0091] One end of capacitor C208 is respectively connected between the drain of PMOS transistor P209 and the drain of NMOS transistor N210, and between the drain of PMOS transistor P213 and the drain of NMOS transistor N214, and the other end of capacitor C208 is grounded.

[0092] Specifically, the capacitance values of capacitor C207 and capacitor C208 are equal.

[0093] It should be noted that when the input circuit configuration signal is "0", a falling-edge delay is achieved, and when the input circuit configuration signal is "1", a rising-edge delay is achieved. After the RS flip-flop output signal is received, it is directly connected to the dead-time delay module 200, and at the same time, a reverse signal is generated through inverter A215 and then connected to the dead-time delay module 200, so that both rising-edge and falling-edge delays of the RS flip-flop output signal can be achieved regardless of whether the circuit configuration signal is "0" or "1".

[0094] Specifically, the signal logic output module 300 includes operational amplifier A301, operational amplifier A302, inverter A303, inverter A304, and multiplexer A305;

[0095] The negative input terminals of operational amplifier A301 and operational amplifier A302 are respectively connected between resistor R101 and resistor R102;

[0096] The positive input terminal of operational amplifier A301 is connected to one end of capacitor C208;

[0097] The positive input terminal of operational amplifier A302 is connected to one end of capacitor C207;

[0098] The output terminal of operational amplifier A301 is connected to the input terminal of inverter A303, and the output terminal of inverter A303 outputs a clamping control signal;

[0099] The output terminal of operational amplifier A302 is connected to the input terminal of inverter A304, the output terminal of inverter A304 is connected to the first data input terminal (input terminal A) of multiplexer A305, and the output terminal of multiplexer A305 outputs a drive control signal;

[0100] The second data input terminal (input terminal B) of multiplexer A305 is connected to the input terminal of inverter A304;

[0101] The selection control terminals of the multiplexer A305 are respectively connected to the output terminal of the AND gate A405, the gates of the PMOS transistor P205 and the NMOS transistor N206 respectively, and the gates of the PMOS transistor P213 and the NMOS transistor N214 respectively.

[0102] It should be noted that the functions of the operational amplifiers A302 and A301 are comparators, and the signal at their negative input terminals is the signal obtained by resistive voltage division of the power supply voltage VDD. When the input circuit configuration signal of the multiplexer A305 is "0", the output signal is the signal at input terminal A. When the input circuit configuration signal is "1", the output signal is the signal at input terminal B. The finally generated dead time is . Among them is the capacitance value of the capacitor C207.

[0103] Referring to Figure 6 as shown, it is the signal waveform diagram of important nodes of a dual-phase configuration clamping drive circuit applied to a forward active clamp PWM controller disclosed in this embodiment under different external resistor R SET connection conditions. It can be seen that this dual-phase configuration clamping drive circuit can support dual-phase configuration without adding pins, be compatible with the requirements of high-side clamping and low-side clamping, optimize the circuit design and reduce the overall cost; through an innovative circuit architecture, it realizes the balance between the flexibility of phase configuration and cost-effectiveness; through the external resistor RSET of a single pin, not only can the dead time be set, but also the phase of the clamping drive signal can be configured simultaneously, realizing the dual-parameter coordinated configuration of the dead time and the phase of the drive signal.

[0104] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the examples, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention, and they should all be covered by the scope of the claims of the present invention.

Claims

1. A clamping drive circuit with a dual-phase configuration applied to a forward active-clamp PWM controller, characterized in that, Comprising: Bidirectional resistor-to-current module, connected to an external resistor R SET , for converting the external resistor R SET into an internal bias current linearly corresponding to the resistance value of the external resistor R SET , wherein, by connecting the negative electrode of the external resistor R SET to a power supply level or a ground level, the selection of the direction of the internal bias current is realized; A current direction detection module, connected to the bidirectional resistor-to-current module, for detecting and outputting a circuit configuration signal according to the direction of the internal bias current, the circuit configuration signal being used to characterize the phase relationship between the drive control signal and the clamp control signal; A dead-time delay module, respectively connected to the bidirectional resistor-to-current module and the current direction detection module, for receiving the output signal of the RS flip-flop, and according to the circuit configuration signal, delaying the rising edge or falling edge of the RS flip-flop output signal, and generating a delay time; A signal logic output module, respectively connected to the current direction detection module and the dead-time delay module, for outputting a drive control signal and a clamp control signal that meet the high-side clamp or low-side clamp requirements according to the delay time and the circuit configuration signal.

2. The clamping drive circuit with a bipolar configuration applied to a forward active clamp PWM controller according to claim 1, wherein The bidirectional resistor-to-current module includes resistor R101, resistor R102, operational amplifier A103, NMOS transistor N104, PMOS transistor P105, NMOS transistor N106, and PMOS transistor P107; Wherein, one end of resistor R101 is connected to the power supply voltage, the other end of resistor R101 is respectively connected to one end of resistor R102 and the positive input terminal of operational amplifier A103, and the other end of resistor R102 is grounded; The source of PMOS transistor P107 is connected to the power supply voltage, and the drain of PMOS transistor P107 is respectively connected to its own gate and the drain of NMOS transistor N104; The gates of NMOS transistor N104 and PMOS transistor P105 are connected to the output terminal of operational amplifier A103; The source electrodes of NMOS transistor N104 and PMOS transistor P105 and the negative input terminal of operational amplifier A103 are all connected to the positive electrode of external resistor R SET of the positive electrode; The drain of NMOS transistor N106 is respectively connected to its own gate and the drain of PMOS transistor P105, and the source of NMOS transistor N106 is grounded.

3. The clamping drive circuit of the dual-phase configuration applied to the forward active clamp PWM controller according to claim 2, wherein, The resistance values of resistor R101 and resistor R102 are equal.

4. A clamping drive circuit with a dual-phase configuration applied to a forward active clamp PWM controller according to claim 3, characterized in that, The current direction detection module includes PMOS transistor P401, resistor R402, NMOS transistor N403, resistor R404, and AND gate A405; Wherein, the gate of PMOS transistor P401 is connected to the gate of PMOS transistor P107, the source of PMOS transistor P401 is connected to the power supply voltage, the drain of PMOS transistor P401 is respectively connected to the first input terminal of AND gate A405 and one end of resistor R402, and the other end of resistor R402 is grounded; The gate of NMOS transistor N403 is connected to the gate of NMOS transistor N106, the drain of NMOS transistor N403 is respectively connected to the power supply voltage through resistor R404 and connected to the second input terminal of AND gate A405, and the source of NMOS transistor N403 is grounded; the output terminal of AND gate A405 outputs a circuit configuration signal.

5. A clamping drive circuit with a bipolar configuration applied to a forward active clamp PWM controller according to claim 4, characterized in that When the external resistor R SET is connected to the power supply level, the circuit configuration signal is "0". When the external resistor R SET is grounded, the circuit configuration signal is "1".

6. A clamped drive circuit with a dual-phase configuration applied to a forward active-clamp PWM controller according to claim 4, characterized in that, The dead-time delay module includes inverter A215, two pairs of first delay circuits and second delay circuits with the same structure; The first delay circuit includes PMOS transistor P201, NMOS transistor N202, PMOS transistor P203, PMOS transistor P205, NMOS transistor N204, NMOS transistor N206, and capacitor C207; The second delay circuit includes a PMOS transistor P209, an NMOS transistor N210, a PMOS transistor P211, a PMOS transistor P213, an NMOS transistor N212, an NMOS transistor N214, and a capacitor C208; Among them, the input terminal of the inverter A215 is connected to the output signal of the RS flip-flop; The output terminal of the inverter A215 is connected to the gates of the PMOS transistor P211 and the NMOS transistor N204 respectively; The gates of the PMOS transistor P201 and the PMOS transistor P209 are respectively connected to the gate of the PMOS transistor P401; The sources of the PMOS transistor P201, the PMOS transistor P203, the PMOS transistor P209, and the PMOS transistor P211 are connected to the power supply voltage; The sources of the NMOS transistor N202, the NMOS transistor N204, the NMOS transistor N210, and the NMOS transistor N212 are grounded; The gates of the NMOS transistor N202 and the NMOS transistor N210 are respectively connected to the gate of the NMOS transistor N403; The gates of the PMOS transistor P203 and the NMOS transistor N212 are connected to the input terminal of the inverter A215; The drain of the PMOS transistor P201 is connected to the drain of the NMOS transistor N202; the drain of the PMOS transistor P203 is connected to the source of the PMOS transistor P205; the drain of the PMOS transistor P205 is connected to the drain of the NMOS transistor N206; the source of the NMOS transistor N206 is connected to the drain of the NMOS transistor N204; One end of the capacitor C207 is connected between the drain of the PMOS transistor P201 and the drain of the NMOS transistor N202, and between the drain of the PMOS transistor P205 and the drain of the NMOS transistor N206, and the other end of the capacitor C207 is grounded; The drain of the PMOS transistor P209 is connected to the drain of the NMOS transistor N210; the drain of the PMOS transistor P211 is connected to the source of the PMOS transistor P213; the drain of the PMOS transistor P213 is connected to the drain of the NMOS transistor N214, and the source of the NMOS transistor N214 is connected to the drain of the NMOS transistor N212; One end of the capacitor C208 is connected between the drain of the PMOS transistor P209 and the drain of the NMOS transistor N210, and between the drain of the PMOS transistor P213 and the drain of the NMOS transistor N214, and the other end of the capacitor C208 is grounded.

7. A clamping drive circuit with a bipolar configuration applied to a forward active clamp PWM controller according to claim 6, characterized in that The capacitance values of the capacitor C207 and the capacitor C208 are equal.

8. A clamped drive circuit for a dual-phase configuration applied to a forward active-clamp PWM controller according to claim 6, characterized in that, The signal logic output module includes an operational amplifier A301, an operational amplifier A302, an inverter A303, an inverter A304, and a multiplexer A305; The negative input terminals of the operational amplifier A301 and the operational amplifier A302 are respectively connected between the resistor R101 and the resistor R102; The positive input terminal of the operational amplifier A301 is connected to one end of the capacitor C208; The positive input terminal of the operational amplifier A302 is connected to one end of the capacitor C207; The output terminal of the operational amplifier A301 is connected to the input terminal of the inverter A303, and the output terminal of the inverter A303 outputs a clamping control signal; The output terminal of the operational amplifier A302 is connected to the input terminal of the inverter A304, and the output terminal of the inverter A304 is connected to the first data input terminal of the multiplexer A305. The output terminal of the multiplexer A305 outputs a drive control signal; The second data input terminal of the multiplexer A305 is connected to the input terminal of the inverter A304; The selection control terminals of the multiplexer A305 are respectively connected to the output terminal of the AND gate A405, the gates of the PMOS transistor P205 and the NMOS transistor N206, and the gates of the PMOS transistor P213 and the NMOS transistor N214.

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