Circuit system capable of saving layout area and operation method thereof

Abstract

The invention relates to a layout area saving circuit system and an operation method thereof. The circuit system comprises an amplifier, a variable capacitor and a switching circuit. The amplifier comprises a first input end, a second input end and an output end. The output end is used for generating output voltage. The variable capacitor is coupled to the first input end. The switching circuit is coupled to the amplifier and the variable capacitor. The switching circuit is used for disconnecting the second input end and the output end in a correction phase, so that the amplifier operates as a comparator. The capacitance value of the variable capacitor is corrected according to the output voltage in the correction stage, so that the voltage of the first input end approaches the voltage of the second input end. The switching circuit is used for electrically connecting the second input end and the output end in the power supply stage to form a negative feedback loop of the amplifier, so that the negative feedback loop of the amplifier is used for stabilizing the output voltage.

Description

Technical Field

[0001] This disclosure document relates to integrated circuit technology, and particularly to a circuit system for saving layout area and an operation method thereof. Background Art

[0002] Capacitive elements for various purposes are provided in current chips. Affected by process variations, the capacitance values of these capacitive elements may vary within a quite large range. In addition, the resistance values of the resistive elements in the chip may also change with the change of the operating temperature. Therefore, a common practice in the industry is to add an automatic capacitance correction mechanism in the chip to achieve precise control of the ratio of the capacitance value to the resistance value. The correction circuit usually needs to occupy a relatively large space. However, the correction circuit is usually not used during most of the running time of the chip, which considerably reduces the space utilization efficiency of the chip. Summary of the Invention

[0003] This disclosure document provides a circuit system, which includes an amplifier, a variable capacitor, and a switching circuit. The amplifier includes a first input terminal, a second input terminal, and an output terminal. The output terminal is used to generate an output voltage. The variable capacitor is coupled to the first input terminal. The switching circuit is coupled to the amplifier and the variable capacitor. The switching circuit is used to disconnect the second input terminal and the output terminal during the correction phase, so that the amplifier operates as a comparator. The capacitance value of the variable capacitor is corrected according to the output voltage during the correction phase, so that the voltage at the first input terminal approaches the voltage at the second input terminal. The switching circuit is used to electrically connect the second input terminal and the output terminal during the power supply phase to form a negative feedback loop of the amplifier, so as to stabilize the output voltage using the negative feedback loop of the amplifier.

[0004] This disclosure document is used to provide an operation method, which is applicable to the circuit system. The circuit system includes an amplifier, a variable capacitor, and a switching circuit. The switching circuit is coupled to the amplifier and the variable capacitor. The amplifier includes a first input terminal, a second input terminal, and an output terminal, and the output terminal is used to generate an output voltage. The operation method includes the following steps: during the correction phase, using the switching circuit to disconnect the second input terminal and the output terminal, so that the amplifier operates as a comparator; during the correction phase, correcting the capacitance value of the variable capacitor according to the output voltage, so that the voltage at the first input terminal approaches the voltage at the second input terminal; during the power supply phase, using the switching circuit to electrically connect the second input terminal and the output terminal to form a negative feedback loop of the amplifier; and during the power supply phase, stabilizing the output voltage using the negative feedback loop of the amplifier.

[0005] One of the advantages of the above circuit system and operation method is to improve the space utilization efficiency of the chip. Brief Description of the Drawings

[0006] Figure 1 It is a simplified functional block diagram of a circuit system according to an embodiment of this disclosure document.

[0007] Figure 2 It is a flowchart of an operation method according to an embodiment of the present disclosure document.

[0008] Figure 3 It is a detailed flowchart of the steps of an operation method according to an embodiment of the present disclosure document.

[0009] Figure 4 It is a detailed flowchart of the steps of an operation method according to an embodiment of the present disclosure document.

[0010] Figure 5 It is a simplified functional block diagram of a noise suppression circuit according to an embodiment of the present disclosure document.

[0011] Figure 6 It is a detailed flowchart of the steps of an operation method according to an embodiment of the present disclosure document.

[0012] Figure 7 It is a simplified functional block diagram of a noise suppression circuit according to an embodiment of the present disclosure document.

[0013] Symbol Explanation

[0014] 100: Circuit system

[0015] 110: Amplifier

[0016] 120: Variable capacitor

[0017] 130: Logic circuit

[0018] 140: Switching circuit

[0019] 150: Voltage source

[0020] 160: Noise suppression circuit

[0021] BC: Digital code

[0022] CK: Clock signal

[0023] VI: Input voltage

[0024] VO: Output voltage

[0025] N1, N2: Nodes

[0026] RCK, RCKB: Control signals

[0027] R1, R2: Resistors

[0028] I1, I2: Current sources

[0029] IO: Output current

[0030] LD: Load

[0031] SW1 - SW5: Switch

[0032] 200: Operation method

[0033] S210 - S240: Steps

[0034] S240’: Step

[0035] S410 - S440: Steps

[0036] 500: Noise suppression circuit

[0037] 510: Transconductance circuit

[0038] 520: Delay circuit

[0039] VDD: Operating voltage

[0040] S610 - S650: Steps

[0041] 700: Noise suppression circuit

[0042] 710: Canceling circuit

[0043] 720: Multiplier

[0044] 730: Transconductance circuit

[0045] VC: Canceling signal Specific implementation manners

[0046] The embodiments of the present disclosure document will be described below in conjunction with the relevant drawings. In the drawings, the same reference numerals denote the same or similar elements or method flows.

[0047] Figure 1 FIG. 53 is a simplified functional block diagram of a circuit system 100 according to an embodiment of the present disclosure document. The circuit system 100 includes an amplifier 110, a variable capacitor 120, a logic circuit 130, a switch circuit 140, a voltage source 150, a noise suppression circuit 160, current sources I1 - I2, and resistors R1 - R2. The circuit system 100 can be disposed inside a chip. The circuit system 100 is configured to generate an output current IO that is insensitive to temperature changes based on an input voltage VI to drive a load LD in the chip. In some embodiments, the circuit system 100 is configured to calibrate the variable capacitor 120 and, based on the calibration result of the variable capacitor 120, further calibrate other capacitor elements (not shown) in the chip.

[0048] Amplifier 110 includes a first input terminal (e.g., non-inverting input terminal), a second input terminal (e.g., inverting input terminal), and an output terminal, where the output terminal is used to generate an output voltage VO. Variable capacitor 120 is coupled to the first input terminal of amplifier 110. Specifically, the first input terminal is coupled between the first end of variable capacitor 120 and current source I1 through node N1, where the second end of variable capacitor 120 is used to receive a reference voltage. Variable capacitor 120 is also coupled to logic circuit 130 and is used to adjust the capacitance value according to the control of logic circuit 130. Current source I2 is serially coupled to resistor R1, and the second input terminal of amplifier 110 is coupled between current source I2 and the first end of resistor R1 through node N2, where the second end of resistor R1 is used to receive a reference voltage.

[0049] Switching circuit 140 is coupled to amplifier 110, variable capacitor 120, logic circuit 130, voltage source 150, and noise suppression circuit 160. Through the switching operation of switching circuit 140, circuit system 100 operates in a calibration phase and a power supply phase in sequence. For example, switching circuit 140 is used to disconnect the second input terminal and the output terminal of amplifier 110 in the calibration phase, so that amplifier 110 operates as a comparator, where switching circuit 140 also transfers output voltage VO to logic circuit 130, so that the capacitance value of variable capacitor 120 is calibrated according to output voltage VO in the calibration phase. In the calibration phase of variable capacitor 120, the voltage at the first input terminal gradually approaches the voltage at the second input terminal. Also for example, switching circuit 140 is used to electrically connect the second input terminal and the output terminal of amplifier 110 in the power supply phase to form a negative feedback loop of amplifier 110, so as to stabilize output voltage VO using the negative feedback loop of amplifier 110. Switching circuit 140 also provides output voltage VO to noise suppression circuit 160 to generate an output current IO for driving load LD in the power supply phase.

[0050] Specifically, the switch circuit 140 includes switches SW1 to SW5. Switches SW1, SW3, and SW4 are controlled by a control signal RCKB, and switch SW5 is controlled by a control signal RCK, where the control signals RCKB and RCK are inverted signals. Additionally, switch SW2 is controlled by a clock signal CK. Switch SW1 and resistor R2 are sequentially connected in series between a voltage source 150 and a node N1. Specifically, a first end of resistor R2 is connected to the voltage source 150, and a second end of resistor R2 is connected to a first input terminal of the variable capacitor 120 and the amplifier 110. Switch SW2 is connected between a first end (i.e., node N1) and a second end of the variable capacitor 120. Switch SW3 is connected between a second input terminal (i.e., node N2) of the amplifier 110 and the output terminal. Switch SW4 is connected between the noise suppression circuit 160 and the output terminal of the amplifier 110. Switch SW5 is connected between the logic circuit 130 and the output terminal of the amplifier 110.

[0051] Figure 2 FIG. 4 is a flowchart of an operation method 200 according to an embodiment of the present disclosure. The operation method 200 is applicable to Figure 1 the circuit system 100. In some embodiments, any combination of the features of the operation method 200 can be implemented as a plurality of instructions stored in a non-transitory computer-readable storage medium. When these instructions are executed by one or more processors, these instructions will cause part or all of the operation method 200 to be executed.

[0052] Please refer to Figures 1 to 2 , the circuit system 100 operates in a calibration phase in steps S210 to S220. Switches SW1, SW3, and SW4 that receive the control signal RCKB are turned off in the calibration phase, and switch SW5 that receives the control signal RCK is turned on in the calibration phase. Additionally, switch SW2 is conditionally (e.g., periodically) turned on in the calibration phase. Therefore, in step S210, the switch circuit 140 disconnects the second input terminal and the output terminal of the amplifier 110 in the calibration phase, causing the amplifier 110 to operate as a comparator. In step S220, the logic circuit 130 calibrates the capacitance value of the variable capacitor 120 based on the output voltage VO in the calibration phase, causing the voltage at the first input terminal of the amplifier 110 to approach the voltage at the second input terminal. The logic circuit 130 is further configured to generate a digital code BC corresponding to the capacitance value of the variable capacitor 120.

[0053] After the end of step S220, the circuit system 100 operates in the power supply stage and executes steps S230 to S240. The switches SW1, SW3, and SW4 that receive the control signal RCKB are turned on in the power supply stage, and the switch SW5 that receives the control signal RCK is turned off in the power supply stage. Additionally, the switch SW2 remains off in the power supply stage, that is, the clock signal CK can be switched to a fixed voltage in the power supply stage to use the variable capacitor 120 as a bypass capacitor for filtering. Therefore, in step S230, the switch circuit 140 is electrically connected to the output terminal and the second input terminal (i.e., node N2) of the amplifier 110 to form a negative feedback loop of the amplifier 110. In step S240, the amplifier 110 stabilizes the output voltage VO using the negative feedback loop.

[0054] Figure 3 FIG. 4 is a detailed flowchart of step S220 according to an embodiment of the present disclosure, and step S220 includes steps S310 to S350. In step S310, the current sources I1 and I2 are enabled. The current source I1 charges the first end of the variable capacitor 120 to determine the voltage of the first input terminal (i.e., node N1) of the amplifier 110. The capacitance value of the variable capacitor 120 corresponds to the digital code BC stored in the logic circuit 130. The current source I2 determines the voltage of the second input terminal (i.e., node N2) of the amplifier 110 by generating a voltage difference across the resistor R1. Additionally, the current sources I1 and I2 are disabled in the power supply stage described later.

[0055] In step S320, the switch circuit 140 is electrically connected to the logic circuit 130 and the output terminal of the amplifier 110, and the logic circuit 130 determines whether the voltage of the first input terminal of the amplifier 110 is approximately the same as the voltage of the second input terminal based on the output voltage VO, where the switch circuit 140 disconnects the logic circuit 130 from the output terminal of the amplifier 110 in the power supply stage. For example, when the output voltage VO switches from a high voltage to a low voltage, or from a low voltage to a high voltage, the logic circuit 130 determines whether the voltage of the first input terminal of the amplifier 110 is approximately the same as the voltage of the second input terminal in step S320.

[0056] If the determination in step S320 is "No", the logic circuit 130 will change the capacitance value of the variable capacitor 120 and correspondingly change the digital code BC in step S330, so that the digital code BC can represent the changed capacitance value. Then, in step S340, the switch SW2 will be turned on to reset the voltage at the first input terminal (i.e., node N1) of the amplifier 110. After step S340 ends, the circuit system 100 will repeat step S310. In some embodiments, when the circuit system 100 repeats steps S310 - S340, the logic circuit 130 can increase or decrease the capacitance value of the variable capacitor 120 in sequence. In some embodiments, the switch circuit 140 (e.g., switch SW2) is used to periodically reset the voltage at the first input terminal during the calibration phase. For example, switch SW2 can be turned off in steps S310 - S320 and turned on in steps S330 - S340.

[0057] On the other hand, if the determination in step S320 is "Yes", the logic circuit 130 will execute step S350 to lock the current digital code BC (i.e., no longer change the digital code BC) and end the execution of step S220. In some embodiments, the logic circuit 130 determines the capacitance values of other capacitor elements (not shown) in the chip based on the digital code BC obtained at the end of step S220.

[0058] Figure 4 FIG. S240 is a detailed flowchart of step S240 according to an embodiment of the present disclosure, where step S240 includes steps S410 - S440. In step S410, the switch circuit 140 electrically connects the voltage source 150 to the first input terminal (i.e., node N1) of the amplifier 110 through the resistor R2, so that the first input terminal of the amplifier 110 receives the input voltage VI. The switch circuit 140 disconnects the voltage source 150 from the first input terminal of the amplifier 110 during the aforementioned calibration phase. In some embodiments, the input voltage VI is a bandgap voltage, and the circuit system 100 operates as a bandgap voltage reference circuit during the power supply phase. In some embodiments, the voltage source 150 may include a circuit with a positive voltage temperature coefficient and a circuit with a negative voltage temperature coefficient, and generates a bandgap voltage through the mutual compensation of these two circuits, but the present disclosure is not limited thereto.

[0059] The following will be combined with Figure 5 to illustrate steps S420 - S440, where Figure 5 FIG. Noise suppression circuit 500 is a simplified functional block diagram of a noise suppression circuit 500 according to an embodiment of the present disclosure. The noise suppression circuit 500 can be used to implement Figure 1a noise suppression circuit 160, and includes a transconductance circuit 510 and a delay circuit 520. The transconductance circuit 510 is coupled to the output terminal of the amplifier 110 through a switching circuit 140 (e.g., switch SW4), and is coupled between the delay circuit 520 and the load LD. In some embodiments, the delay circuit 520 includes a plurality of inverters connected in series.

[0060] In step S420, the switching circuit 140 electrically connects the transconductance circuit 510 and the output terminal of the amplifier 110 to transfer the output voltage VO to the transconductance circuit 510. The switching circuit 140 disconnects the transconductance circuit 510 and the output terminal of the amplifier 110 during the aforementioned calibration phase.

[0061] In step S430, the delay circuit 520 transfers the operating voltage VDD to the transconductance circuit 510. The operating voltage VDD is the highest voltage received by the transconductance circuit 510 in some embodiments. In some embodiments, due to the voltage coupling effect, a clock signal (not shown) around the circuit system 100 may cause noise in the operating voltage VDD, and the delay circuit 520 is used to reduce the energy of these noises to provide a stable operating voltage VDD to the transconductance circuit 510. Then, in step S440, the transconductance circuit 510 converts the output voltage VO into an output current IO.

[0062] In some embodiments, Figure 2 step S240 of Figure 6 can be replaced by Figure 6 step S240' of Figure 6 step S610 of Figure 4 is similar to step S410 of

[0063] The following will be described in conjunction with Figure 7 steps S620 to S650, where Figure 7 is a simplified functional block diagram of a noise suppression circuit 700 according to an embodiment of the present disclosure. The noise suppression circuit 700 can be used to implement Figure 1 the noise suppression circuit 160 of

[0064] In step S620, the switch circuit 140 electrically connects the cancellation circuit 710 and the multiplier 720 to the output terminal of the amplifier 110 to transfer the output voltage VO to the cancellation circuit 710 and the multiplier 720. The switch circuit 140 disconnects the cancellation circuit 710 from the output terminal of the amplifier 110 and disconnects the multiplier 720 from the output terminal of the amplifier 110 during the aforementioned calibration phase.

[0065] In step S630, the cancellation circuit 710 generates a cancellation signal VC associated with the ripple of the output voltage VO. For example, the cancellation circuit 710 can generate the cancellation signal VC including a component that is in antiphase with the ripple of the output voltage VO by a feedforward technique, but the present disclosure is not limited thereto.

[0066] Next, in step S640, the multiplier 720 generates the product of the output voltage VO and the cancellation signal VC. In step S650, the transconductance circuit 730 converts the product of the output voltage VO and the cancellation signal VC into an output current IO. In some embodiments, due to the voltage coupling effect, a clock signal (not shown) around the circuit system 100 may cause a ripple in the output voltage VO, where the cancellation signal VC of the cancellation circuit 710 is used to offset the ripple in the output voltage VO to provide a stable output voltage VO to the transconductance circuit 510.

[0067] In some embodiments, during steps S230 - S240 of the power supply phase of the circuit system 100, the variable capacitor 120 is switched to the maximum capacitance value, thereby improving the filtering effect of the low-pass filter formed by the variable capacitor 120 and the resistor R2.

[0068] In some embodiments, when the circuit system 100 is enabled (e.g., when powered on), the circuit system 100 first executes steps S210 - S220 of the calibration phase, then executes steps S230 - S240 of the power supply phase, and the circuit system 100 does not repeat the calibration phase, that is, steps S210 - S220 are each executed only once.

[0069] In summary, the circuit system 100 can reuse the amplifier 110 and the variable capacitor 120 during the execution of the calibration phase and the power supply phase. Therefore, the circuit system 100 saves the layout area of at least one amplifier and one variable capacitor, which helps to save costs and improve the space utilization efficiency of the chip.

[0070] As used herein, the terms "about", "approximately" or "substantially about" generally typically refer to an error or range of within twenty percent of a numerical value, preferably within ten percent, and more preferably within five percent. Unless otherwise specified in the text, the numerical values mentioned therein are regarded as approximate values, i.e., the error or range indicated by "about", "approximately" or "substantially about".

[0071] In the specification and claims, certain terms are used to refer to specific elements. However, those skilled in the art should understand that the same element may be referred to by different names. The specification and claims do not use the difference in names as a way to distinguish elements, but rather use the difference in the functions of the elements as the basis for distinction. The term "comprising" mentioned in the specification and claims is an open-ended term and should be interpreted as "comprising but not limited to". In addition, "coupled" herein includes any direct and indirect connection means. Therefore, if the text describes that the first element is coupled to the second element, it means that the first element can be directly connected to the second element through electrical connection, wireless transmission, optical transmission or other signal connection means, or indirectly electrically or signal-connected to the second element through other elements or connection means.

[0072] In addition, unless specifically specified in the specification, any singular term also includes the plural meaning.

[0073] The above are only the preferred embodiments of the present disclosure document. Without departing from the scope or concept of the present disclosure document, various modifications and equivalent changes can be made to the present disclosure document. In summary, all modifications and equivalent changes made to the present disclosure document within the scope of the following claims are covered by the present disclosure document.

Claims

1. A circuit system, comprising: an amplifier, including a first input terminal, a second input terminal, and an output terminal, wherein the output terminal is configured to generate an output voltage; a variable capacitor, coupled to the first input terminal; and a switch circuit, coupled between the amplifier and the variable capacitor, wherein the switch circuit is configured to disconnect the second input terminal from the output terminal during a calibration phase, such that the amplifier operates as a comparator, wherein a capacitance value of the variable capacitor is calibrated according to the output voltage during the calibration phase, so that a voltage at the first input terminal approaches a voltage at the second input terminal, wherein the switch circuit is configured to electrically connect the second input terminal to the output terminal during a power supply phase to form a negative feedback loop of the amplifier, so as to stabilize the output voltage using the negative feedback loop of the amplifier.

2. The circuit system according to claim 1, further comprising: a first current source, coupled to the first input terminal, configured to be enabled during the calibration phase to charge the variable capacitor, and configured to be disabled during the power supply phase; a first resistor; and a second current source, serially coupled to the first resistor, wherein the second input terminal is coupled between the first resistor and the second current source, and wherein the second current source is configured to be enabled during the calibration phase, and configured to be disabled during the power supply phase.

3. The circuit system according to claim 2, wherein the switch circuit is configured to periodically reset the voltage at the first input terminal during the calibration phase.

4. The circuit system according to claim 1, further comprising: a logic circuit, coupled to the output terminal through the switch circuit, configured to correct the capacitance value of the variable capacitor according to the output voltage, and configured to generate a digital code corresponding to the capacitance value of the variable capacitor, wherein the switch circuit is configured to electrically connect the logic circuit to the output terminal during the calibration phase, and configured to disconnect the logic circuit from the output terminal during the power supply phase.

5. The circuit system according to claim 1, further comprising: a voltage source, coupled to the variable capacitor and the first input terminal through the switch circuit, configured to provide an input voltage, wherein the switch circuit is configured to disconnect the voltage source from the first input terminal during the calibration phase, and configured to electrically connect the voltage source to the first input terminal during the power supply phase such that the first input terminal receives the input voltage.

6. The circuit system according to claim 5, further comprising: a second resistor, wherein a first end of the second resistor is coupled to the voltage source, and a second end of the second resistor is coupled to the variable capacitor and the first input terminal.

7. The circuit system according to claim 1, further comprising: a transconductance circuit, coupled to the output terminal through the switch circuit, configured to convert the output voltage into an output current; and a delay circuit, coupled to the transconductance circuit, configured to provide an operating voltage to the transconductance circuit, wherein the switch circuit is configured to disconnect the transconductance circuit from the output terminal during the calibration phase, and configured to electrically connect the transconductance circuit to the output terminal during the power supply phase.

8. The circuit system according to claim 1, further comprising: a cancellation circuit, coupled to the output terminal through the switch circuit, configured to generate a cancellation signal associated with the ripple at the output terminal; A multiplier, coupled to the output terminal through the switching circuit and coupled to the cancellation circuit, for generating a product of the output voltage and the cancellation signal; and A transconductance circuit, coupled to the multiplier, for converting the product of the output voltage and the cancellation signal into an output current, wherein the switching circuit is configured to disconnect the cancellation circuit from the output terminal and disconnect the multiplier from the output terminal during the calibration phase, and is configured to electrically connect the output terminal to the cancellation circuit and the multiplier during the power supply phase.

9. The circuit system according to claim 1, wherein the variable capacitor is switched to a maximum capacitance value during the power supply phase.

10. An operating method, applicable to a circuit system, wherein the circuit system includes an amplifier, a variable capacitor, and a switching circuit, the switching circuit is coupled to the amplifier and the variable capacitor, the amplifier includes a first input terminal, a second input terminal, and an output terminal, and the output terminal is configured to generate an output voltage, wherein the operating method includes: During a calibration phase, using the switching circuit to disconnect the second input terminal from the output terminal so that the amplifier operates as a comparator; During the calibration phase, calibrating a capacitance value of the variable capacitor according to the output voltage so that a voltage at the first input terminal approaches a voltage at the second input terminal; During a power supply phase, using the switching circuit to electrically connect the second input terminal to the output terminal to form a negative feedback loop of the amplifier; and During the power supply phase, stabilizing the output voltage using the negative feedback loop of the amplifier.

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