Phase frequency detector of charge pump phase-locked loop with low in-band noise, method and phase-locked loop

Abstract

The invention provides a phase frequency detector for a charge pump phase-locked loop with low in-band noise, and the phase-locked loop at least comprises a first trigger (D1) and a second trigger (D2), and is characterized in that the output of the first trigger (D1) and the output of the second trigger (D2) are respectively used as the input of a first time amplifier (1) and the input of a second time amplifier (2); the first time amplifier (1) and the second time amplifier (2) at least comprise a phase generation module (11) and an edge detection module (12), the phase generation module (11) at least comprises a three-stage ring oscillator, and the edge detection module (12) at least comprises two cascaded synchronous edge D flip-flops, namely a third D flip-flop (D3) and a fourth D flip-flop (D4). The invention also provides a low-in-band noise charge pump phase-locked loop and a corresponding control method. The problem of compromise among capacitance, magnification times and power consumption is solved, and the method is easy to implement and low in cost.

Description

Technical Field

[0001] The present invention belongs to the field of chips, specifically, to the field of display driver chips, especially to the field of phase-locked loop circuits, and specifically relates to a frequency discriminator and phase detector of a low in-band noise charge pump phase-locked loop, a control method for reducing in-band noise based on the frequency discriminator and phase detector, and a corresponding low in-band noise charge pump phase-locked loop. Background Art

[0002] A phase-locked loop (PLL) is a very important functional system, which can provide clocks with one or more frequency requirements in a chip system, generate local oscillator signals in a receiver, maintain synchronization in a communication system, etc. For these systems, the phase noise of the phase-locked loop is a very important indicator. The magnitude of the phase noise determines the quality and speed of signal transmission and reception. Therefore, the optimization of phase noise has always been the goal of the design of the phase-locked loop system. However, there is a close trade-off relationship between phase noise and the architecture, power consumption, loop bandwidth, area, etc. of the phase-locked loop. Therefore, the optimization of phase noise has always been one of the difficulties in the design of the phase-locked loop.

[0003] With the continuous development of phase-locked loop technology, phase-locked loops are divided into analog phase-locked loops, digital phase-locked loops, digital-analog hybrid phase-locked loops and other types of phase-locked loops. Among the above-mentioned phase-locked loops, the charge pump phase-locked loop (CPPLL, Charge Pump Phase Looked Loop) is the most widely used, and it belongs to a type of digital-analog hybrid phase-locked loop. As Figure 1 shown, the CPPLL is composed of a frequency discriminator and phase detector (PFD), a charge pump (CP), a loop filter (LPF), a voltage-controlled oscillator (VCO) and a frequency divider (DIV). Its working principle is that the input reference signal F_REF and the signal F_DIV fed back by the frequency divider are processed by the frequency discriminator and phase detector, and a pulse signal UP or DN proportional to the phase difference between these two signals will be generated. The pulse signal drives the charge pump to charge and discharge. When the phase of F_REF leads the phase of F_DIV, the UP signal of the frequency discriminator and phase detector becomes logic 1, and the loop filter is charged under the action of the charging current of the charge pump, increasing V ctrl ctrl, thereby increasing the output signal frequency of the VCO, thereby reducing the phase difference between F_REF and F_DIV. When the phase of F_REF lags behind the phase of F_DIV, the DN signal of the frequency discriminator and phase detector becomes logic 1, and the loop filter is discharged under the action of the discharging current of the charge pump, Vctrl decreases, and then the output signal frequency of the VCO decreases, and then the phase difference between F_REF and F_DIV is reduced. The frequency discriminator and phase detector compares the phase difference between F_REF and F_DIV, switches the loop between two working states, gradually reduces the phase difference between F_REF and F_DIV, and finally realizes the locking of the phase-locked loop circuit.

[0004] After the phase-locked loop (PLL) locks, the PLL system can be approximated as a linear system, and its phase noise model can be analyzed equivalently using Figure 2 The equivalent model of the phase-frequency detector (PFD) + charge pump (CP) is K pd = I cp / 2π. The equivalent noise model of the low-pass filter (LPF) is its transfer function, and the equivalent noise model of the voltage-controlled oscillator (VCO) is K vco / s , where K vco is the voltage-controlled gain of the VCO, that is, the ratio of the change in the oscillation frequency to the change in the control voltage. The noise model of the frequency divider is equivalent to 1 / N. The noise of the PFD + CP is shaped by the LPF and shows a low-pass characteristic at the output, so it dominates the in-band noise of the PLL. While the VCO shows a high-pass characteristic and dominates the out-of-band noise.

[0005] From Figure 2 the phase noise of the PLL can be calculated as:

[0006]

[0007] Let By derivation, we get:

[0008]

[0009] It can be seen that the phase noise at the output is modulated by the transfer function. The phase noise of the VCO shows a high-pass function at the output, the phase noise of the LPF shows a band-pass function, the phase noise of the reference source and the frequency divider shows a low-pass function, and the phase noise of the PFD + CP also shows a low-pass function and is affected by the two coefficients N and K pd .

[0010] Therefore, the phase-frequency detector and the charge pump play a key role in the entire PLL system, and their phase noise determines the noise level at the low-frequency part of the output phase noise of the PLL. Currently, the research on reducing the phase noise of the PLL continues. Generally, the phase noise of the PLL is mainly contributed by the VCO. However, with the development of the PLL, the contribution of the phase noise of the VCO gradually becomes the same as or even lower than the contribution of the noise of the PFD + CP. Therefore, the optimization of the noise contribution of the PFD + CP also needs to be further studied.

[0011] The current in-band noise optimization technology mainly reduces the thermal noise of the PFD + CP by increasing the charge pump current Icp, and has no inhibitory effect on its flicker noise, with limited efficiency. The flicker noise can be optimized by increasing the area of the CP, which increases the cost.

[0012] To alleviate the trade-off between in-band noise, power consumption, and cost, Gao Xiang proposed a sub-sampling charge pump phase-locked loop in the prior art "X. Gao, E. A. M. Klumperink, M. Bohsali and B. Nauta, 'A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD / CP Noise is Not Multiplied by $N^{2}$,' in IEEE Journal of Solid-State Circuits, vol. 44, no. 12, pp. 3253-3263, Dec. 2009, doi: 10.1109 / JSSC.2009.2032723.” By changing the structure of the traditional charge pump phase-locked loop, this structure changes the equivalent transmission model of the phase-locked loop, so that the phase noise of PFD+CP is no longer amplified by N^2 times, effectively reducing the in-band noise. However, due to the phase detection range of this structure being only [-pi / 2, pi / 2], a frequency-locked loop is required to assist in locking, and the charge pump is vulnerable to process, power supply, and temperature fluctuations (PVT).

[0013] To solve the problem of the weak acquisition ability of the sub-sampling phase-locked loop, Geng Xinlin proposed a charge pump phase-locked loop based on a time-amplifying phase-frequency detector (TAPFD) in "X. Geng, Y. Tian, Y. Xiao, Z. Ye, Q. Xie and Z. Wang, 'A 25.8GHz Integer-N PLL With Time-Amplifying Phase-Frequency Detector Achieving 60fs rms Jitter, -252.8dB FoM J, and Robust Lock Acquisition Performance,' 2022 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2022, pp. 388-390, doi: 10.1109 / ISSCC42614.2022.9731578. (For the sake of convenience of expression, referred to as: prior art document 2)" From another perspective, the transfer function of the phase-locked loop is changed, that is, the value of K pd is changed, so that the phase noise of PFD+CP is suppressed by K pd times at the output.

[0014] The sub-sampling phase-locked loop reduces the noise of PFD+CP by eliminating N by N^2 times, while TAPFD changes from Kpd Starting from this, the phase noise is also reduced by a factor of K tapfd ^2 times.

[0015] The core of this structure is to replace the traditional PFD with a TAPFD that can amplify the error pulse. In this way, the equivalent transfer function of the PFD + CP during locking is K tapfd *I cp / 2π, where K tapfd is the amplification factor of the TAPFD for the error pulse. The difference between this structure and the subsampling phase-locked loop is that, in theory, it can retain the phase discrimination ability of the traditional PFD, and at the same time suppress the in-band noise by changing the transfer function.

[0016] However, the structure in the existing technical literature 2 has certain problems. First of all, the principle of amplifying the error pulse is capacitor charging and discharging, which is not friendly to low-frequency and small-size processes. Because for MOS transistors and capacitors in low-frequency and small-size processes, the leakage problem needs to be considered, which will affect the precise mathematical calculations using capacitor charging and discharging. Secondly, since this structure uses current charging and discharging to amplify the pulse error, the amplification factor of the current mirror will introduce a large amount of noise. Moreover, due to the strong relationship between the capacitance size, current size, and amplification factor, it is difficult to make a compromise. If a large amplification factor is required, a large current ratio is needed, and a larger capacitor is required to maintain the charging and discharging time. However, if the charging and discharging time is too large, non-ideal effects will also occur during reset. Since this structure amplifies the signal through the time error of current discharge, there is a blind area, which is related to the discharge time and also needs to be compromised with the amplification factor. These effects make the blind area of this structure up to 40% at high frequencies, just on the verge of being able to detect the frequency. If the influence of PVT is further considered, the stability of the phase-locked loop circuit is a problem.

[0017] Generally speaking, there are at least three problems in the existing technology:

[0018] 1. Currently, the technology for reducing in-band noise mainly reduces the thermal noise of the CP by increasing the charge pump current.

[0019] 2. The SSPLL evolved from the CPPLL reduces the in-band noise by changing the structure.

[0020] 3. The CPPLL structure using a time-amplifying frequency discriminator and phase discriminator suppresses the in-band noise by increasing Kpd.

[0021] Currently, in the existing technology, the control method for the in-band noise of the charge pump phase-locked loop is not good enough. There is a need for a charge pump phase-locked loop that can better solve the in-band noise, as well as the corresponding internal structure and control method. This is the technical task of the present invention. Summary of the Invention

[0022] In view of the technical defects existing in the prior art, the object of the present invention is to provide a frequency discriminator and phase detector for a low in-band noise charge pump phase-locked loop, which is used to reduce the in-band noise of the charge pump phase-locked loop. The phase-locked loop at least includes a first flip-flop D1 and a second flip-flop D2. It is characterized in that the outputs of the first flip-flop D1 and the second flip-flop D2 are respectively used as the inputs of a first time amplifier 1 and a second time amplifier 2. The first time amplifier 1 and the second time amplifier 2 at least include a phase generation module 11 and an edge detection module 12. The phase generation module 11 at least includes a three-stage ring oscillator, and the edge detection module 12 at least includes two cascaded synchronous edge D flip-flops, namely a third D flip-flop D3 and a fourth D flip-flop D4.

[0023] Preferably, the three-stage ring oscillator is composed of three groups of NAND groups connected in series, and each group of NAND groups is respectively composed of a unit NAND111 and N unit NAND112 connected in parallel.

[0024] Preferably, a small capacitor 113 is also connected to the output node of each group of NAND groups.

[0025] Preferably, the capacitance range of the small capacitor 113 is greater than 8 fF.

[0026] Preferably, the W / L dimension of the N unit NAND112 is N times that of the unit NAND111.

[0027] Preferably, the range of N is between 2 and 20.

[0028] Preferably, a group of NAND at least includes a first PMOS transistor MP0, a second PMOS transistor MP1, a third PMOS transistor MP2, a first NMOS transistor MN0, a second NMOS transistor MN1, and a third NMOS transistor MN2. The third PMOS transistor MP2 and the third NMOS transistor MN2 are respectively switching transistors, the source ends are respectively connected to VDD and GND, the drain ends are connected to the first PMOS transistor MP0, the second PMOS transistor MP1, and the second NMOS transistor MN1, the drain end of the second NMOS transistor MN1 is connected to the source end of the first NMOS transistor MN0, and the drain ends of the first NMOS transistor MN0 and the first PMOS transistor MP0 and the second PMOS transistor MP1 are used as outputs.

[0029] Preferably, the input end of the third D flip-flop D3 is fixed to VDD, the output end of the third D flip-flop D3 is connected to the input end of the fourth D flip-flop D4, the inverted signal CK_TA of the output CK1 of the first group of NAND is used as the clock signal of the third D flip-flop D3 and the fourth D flip-flop D4, and the reset end is connected to the reset signal generated by TAPFD to control the output reset of the third D flip-flop D3 and the fourth D flip-flop D4.

[0030] Preferably, the frequency discriminator and phase detector further includes at least a third buffer B3 and a fourth buffer B4 connected to the output terminal of the edge detection module 12, which are at least used for shaping the pulse signal and increasing the driving ability.

[0031] Preferably, the frequency discriminator and phase detector further includes a delay array module 13 composed of at least an inverter and an NMOS capacitor connected to the output terminal of the edge detection module 12, and the output of the delay array module 13 is connected to the reset terminal of the frequency discriminator and phase detector.

[0032] Preferably, the outputs of the first flip-flop D1 and the second flip-flop D2 pass through a NOR gate to enable the driving switching signals of the first time amplifier 1 and the second time amplifier 2.

[0033] According to another aspect of the present invention, there is also provided a charge pump phase-locked loop with low in-band noise, which at least includes a first flip-flop D1 and a second flip-flop D2, and also includes the above-mentioned frequency discriminator and phase detector.

[0034] According to still another aspect of the present invention, there is also provided a low in-band noise control method for the above-mentioned frequency discriminator and phase detector, which includes the following steps:

[0035] Step a. When F_REF is ahead, the rising edge of REF_TA causes the first time amplifier 1 to start working with strong driving ability, and the second time amplifier 2 does not work;

[0036] Step b. When F_DIV arrives, make EN_TA high level, and make the first time amplifier 1 and the second time amplifier 2 work with weak driving ability;

[0037] Step c. When working with weak driving ability and the second rising edge of CK_TA2 arrives, the outputs of the first time amplifier 1 and the second time amplifier 2 are both high level;

[0038] Step d. Reset the first flip-flop D1, the second flip-flop D2, the first time amplifier 1 and the second time amplifier 2 to their initial states, and one control cycle is completed.

[0039] Preferably, it further includes the following step: taking the inverted signal at the output terminal of the first group of NAND112 as CK_TA.

[0040] The frequency discriminator and phase detector, the corresponding charge pump phase-locked loop and the corresponding control method provided by the present invention are applied to optimize the performance of the traditional charge pump phase-locked loop. By changing the transfer function of the PFD+CP, the phase noise is reduced by about Ktapfd times after being shaped by the transfer function. Generally speaking, the advantages of the present invention at least further include:

[0041] 1. Overcomes the replication error of the analog current mirror.

[0042] By using the relative magnitude of the oscillator period to amplify the error pulse, which is accomplished through edge sampling, there is no amplification error, avoiding a series of problems brought by analog current mirror replication, and overcoming the amplification of input noise by the current mirror replication factor.

[0043] 2. Overcomes the problems of the capacitor charge and discharge mode.

[0044] By adopting a new TA architecture, it no longer relies on the charge and discharge of the capacitor, but amplifies the error pulse through the digital angle, which is more universal. The working frequency of the reference literature is very high, and non-ideal effects such as leakage in small-size processes do not need to be considered. The TA architecture adopted by the present invention can be used not only in high-frequency and large-size processes, but also in low-frequency and small-size processes, etc., with a wider application scenario and better stability.

[0045] 3. Overcomes the trade-off problem among capacitor size, amplification factor, and power consumption.

[0046] The reset of the reference literature is an operation to charge the capacitor, while the amplification process of the error is an operation to discharge the capacitor. The operation time required for reset is short, while a longer discharge time is required for amplification, which results in a large difference in current between the two working modes. Also, because the amplification factor is provided by the current ratio, the current during the amplification stage is very large, and a larger current is required during the reset stage. The structure adopted by the present invention only needs to pay attention to the multiple of two oscillation periods, does not require a large capacitor and current, and the relationship between the amplification factor and power consumption is also weak, because the amplification factor can be changed by simultaneously changing the relative magnitude of the two periods.

[0047] 4. Reasonably compromises parameters such as blind zone, amplification factor, and power consumption.

[0048] Although the blind zone design of the prior art literature introduced in the background art section is better than the sub-sampling performance, the blind zone ratio also reaches 40%, with a risk of loss of lock. The blind zone ratio of the present invention is only 14%, which is very close to the frequency discrimination ability of the traditional PFD.

[0049] The implementation method of the present invention is simple and cost-effective, can effectively solve the above technical problems, and has extremely high commercial value. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] By reading the detailed description of the non-limiting embodiments with reference to the following drawings, other features, objects, and advantages of the present invention will become more apparent:

[0051] Figure 1Schematic diagram of a charge pump phase-locked loop architecture in the prior art;

[0052] Figure 2 Schematic diagram of a phase noise model of a charge pump phase-locked loop in the prior art;

[0053] Figure 3 Schematic diagram of the circuit structure of a frequency discriminator and phase detector for a low in-band noise charge pump phase-locked loop according to a specific embodiment of the present invention, which includes a time amplifier;

[0054] Figure 4 Schematic diagram of the circuit structure of time amplifier 1 in the frequency discriminator and phase detector for a low in-band noise charge pump phase-locked loop according to the first embodiment of the present invention;

[0055] Figure 5 Schematic diagram of the circuit structure of the phase difference generating delay unit of time amplifier 1 in the frequency discriminator and phase detector for a low in-band noise charge pump phase-locked loop according to the first embodiment of the present invention.

[0056] Figure 6 Schematic diagram of the key node timing diagram of a low in-band noise charge pump phase-locked loop in the working state according to the first embodiment of the present invention;

[0057] Figure 7 Schematic diagram of the output phase error curve of TAPFD of a low in-band noise charge pump phase-locked loop according to the first embodiment of the present invention;

[0058] Figure 8 Schematic diagram of the comparison between the output current noise density spectrum of TAPFD+CP and the output current noise density spectrum of traditional PFD+CP of a low in-band noise charge pump phase-locked loop according to the first embodiment of the present invention; and

[0059] Figure 9 Schematic diagram of the measurement result of the TAPFD blind area of a low in-band noise charge pump phase-locked loop according to a specific embodiment of the present invention. Specific Embodiment

[0060] In order to better represent the technical solution of the present invention clearly, the present invention will be further described below with reference to the accompanying drawings.

[0061] To solve the above problems in the prior art, based on the research of various time amplifiers, the present invention proposes a digital architecture TAPFD, that is, the low in-band noise charge pump phase-locked loop provided by the present invention, a PFD with a time amplifier, which no longer relies on the charging and discharging of capacitors, but realizes the amplification of pulse errors through the phase difference between two oscillation frequencies. This avoids the static phase error of the current mirror mismatch noise and the noise multiplication introduced by the current mirror amplification factor. At the same time, the application scenario is more flexible, suitable for low-frequency and small-size processes, and can also be used for high-frequency and large-size processes.

[0062] As Figure 3 shown, it is applied to a low in-band noise charge pump phase-locked loop, including a traditional PFD part and a time amplifier (TA) part. Specifically, Figure 3 the two D flip-flops on the left in

[0063] are the main body of the traditional PFD, namely the first D flip-flop D1 and the second D flip-flop D2. F_REF and F_DIV are input to the first D flip-flop D1 and the second D flip-flop D2. When there is a phase error between the two, the output waveforms also have the same phase error. The outputs are the inputs REF_TA and DIV_TA of the first time amplifier 1 and the second time amplifier 2 respectively. After receiving the rising edge of the error signal, the TA amplifies the error signal according to different driving modes.

[0064] It should be noted that the delay array Delay_array module between RST and RST_TA is composed of a numerically controlled delay array, and the reset pulse width of the PFD can be adjusted digitally. The pulse width should be large enough to enable the CP to be normally turned on and eliminate the dead zone between the PFD and the CP. Since this pulse width is positively correlated with the phase noise introduced by the PFD, it cannot be too large and needs to be controlled within a reasonable range.

[0065] It should be noted that the amplification dead zone of the TAPFD is different from the dead zone of the traditional PFD. The amplification dead zone of the TAPFD refers to the interval in which the TAPFD loses the ability to amplify pulse errors. Reasonable design of the delay of EN_TA can eliminate the amplification dead zone. The specific design idea is to make the rising edge of EN_TA coincide with or slightly advance the rising edge of DIV_TA, so that the weak driving mode can be directly switched when the rising edge of DIV_TA arrives, and there will be no situation where the driving mode cannot be switched when the errors of F_REF and F_DIV are very small.

[0066] It should be noted that the functions of NOR3 and I1 are to add the enable signal of the overall PFD and control whether the entire TAPFD provided by the present invention works. At the same time, they also play the role of resetting the correct initial signal for the TAPFD.

[0067] It should be noted that the functions of the first buffer B1 and the second buffer B2 at the input end of the TAPFD, and the third buffer B3 and the second buffer B4 at the output end of the TAPFD are to shape the pulse signal and increase the driving ability, and increase the slew rate (SR) of the signal flip to reduce the phase noise.

[0068] Furthermore, Figure 4 The specific circuit structure of the TA of the present invention is given, which mainly consists of two parts, namely a phase generation module and an edge detection module. The phase generation module consists of three groups of NANDs connected in series to form a three-stage ring oscillator. Each group of NANDs is composed of a unit NAND111 and N unit NAND112 connected in parallel. The output node of each group of NANDs is connected to a small capacitor 113 to ensure that the oscillation frequency is within a reasonable range. The edge detection module is mainly composed of two cascaded synchronous edge third D flip-flops D3 and fourth D flip-flops D4. The input end of the third D flip-flop D3 is fixed to VDD. The output end of the third D flip-flop D3 is connected to the input end of the fourth D flip-flop D4. The clocks of the third D flip-flop D3 and the fourth D flip-flop D4 are connected to the inverted signal CK_TA of CK1, and the reset ends are connected to the reset signal generated by the TAPFD to control the output reset of the third D flip-flop D3 and the fourth D flip-flop D4.

[0069] It should be noted that the functions of the first buffer B1 at the input end, the second buffer B2 at the output end, and the inverter I2 are the same as those of the buffers in the TAPFD circuit, which are to shape the pulse signal, increase the driving ability, and reduce the phase noise. The function of the input end I1 is not only to flip the signal but also to perform impedance transformation. In order to drive the three-stage N unit NAND112, sufficient driving ability is required to make the SR of EN large enough to eliminate the amplification dead zone.

[0070] Furthermore, Figure 5The circuit diagram with an enabled NAND group is given. Keeping the same L, the W / L dimension of the N-unit NAND112 is N times that of the single-unit NAND111. The current flowing through the N-unit NAND112 is N times that of the single-unit NAND111. Due to the large external capacitance, the change in load capacitance caused by the dimension is ignored. From ΔT = ΔI / C, the delay ratio between the single-unit and the N-unit is the current ratio N. Among them, the third NMOS transistor MN2 and the third PMOS transistor MP2 are switching transistors, and their dimensions should be designed as small as possible to avoid affecting the transmission characteristics of the NAND. The first NMOS transistor MN0 and the second NMOS transistor MN1 have the same dimension, and the first PMOS transistor MP0 and the second PMOS transistor MP1 have the same dimension. The transmission characteristics are better when the ratio of PMOS to NMOS is between 2 and 3, which is consistent with the design concept of the inverter.

[0071] It should be noted that the output capacitance load connected to the output terminal of each NAND group should be larger than the equivalent output capacitance of the NAND to prevent the loading effect, that is, as the NAND dimension increases, the delay not only does not decrease, but instead, due to the excessive capacitance introduced by the larger dimension, the delay increases.

[0072] Furthermore, the timing control of the circuit needs to be elaborated in detail. The initial state of the circuit is as Figure 6 shown, EN is at a high level, and all other signals in the figure are at a low level.

[0073] When F_REF is advanced, the rising edge of REF_TA causes TA1 to start working. At this time, since EN_TA is at a low level, the driving ability of TA is strong and the oscillation period is small. When F_DIV arrives, EN_TA is at a high level, the driving ability of TA is weak and the oscillation period is large. Since the phase difference between F_REF and F_DIV is Tin, after two different delays, the phase difference is amplified by N + 1 times, where N is the driving ability ratio of the two different driving modes. When the outputs of the first time amplifier 1 and the first time amplifier 2 are both at a high level, the NOR logic of their output inverted signal QB is 1, that is, the reset signal RST is 1. After passing through the delay array, RST_TA is 1, and the main part of the PFD and the time amplifier are both reset to the initial state and start waiting for the next group of F_REF and F_DIV. One TAPFD cycle is completed.

[0074] Further illustrate the timing of the phase generation circuit module: When the NAND is used as a delay unit, when one end voltage is 0, the output must be 1. So when F_REF and F_DIV are 0, the output of the first group of NANDs is 1. Since the other end of the second group of NANDs is fixed at VDD, the output of the second group of NANDs is 0. Similarly, for the third group of NANDs, because there is a 0 in the input, the output is 1, and the NAND output of F_REF and F_DIV is 1, which belongs to the steady state. When F_REF and F_DIV are 0, since the NAND has a steady state, it will not oscillate, and it provides an initial state storage signal for the oscillation of the NAND. When F_REF or F_DIV is 1, since the other initial state of the first group of NANDs is 1, the output of the first group of NANDs becomes 0 with the rising edge of F_REF or F_DIV. In this way, the inputs of the second group of NANDs are 0 and 1 respectively, and the output becomes 1. Similarly, the two inputs of the third group of NANDs are both 1, and the output becomes 0, which changes the initial state of the first group of NANDs. So the inputs of the first group of NANDs are 0 and 1, the output becomes 1, the output flips, and a cycle is completed.

[0075] Further, in order to reduce the propagation delay from F_REF or F_DIV to CK_TA, the inverted signal at the output of the first group of NANDs is taken as CK_TA. Since the initial state of the output of the first group of NANDs is 1 and becomes 0 after startup, the inverted signal is a rising edge as the clock of the edge detection module.

[0076] Further illustrate the timing of the edge detection circuit module: The output of the first delay unit is inverted and used as the clock input of the edge detection module. So QTA_1 becomes high level with the sampling of CK_TA1.

[0077] At this time, since the initial state of the output of the edge detection module is 0, the input of the second D flip-flop of the edge detection module is still 0. When the second rising edge of CK_TA arrives, the output of the second D flip-flop of the edge detection module is 1, and OUT outputs 1.

[0078] Similarly, the second time amplifier 2 (abbreviation: TA2) receives the rising edge of DIV_TA after Tin time. Since F_REF and F_DIV are both 1 at this time, EN becomes 0, switches to the low drive mode, and the oscillation period increases to N + 1 times. Like the first time amplifier 1 (abbreviation: TA1), the output is 1 only when the second CK_TA arrives. At this time, the outputs of the first time amplifier 1 and the second time amplifier 2 are both 1, RST is 1, the time amplifier and PFD are both reset, and at this time each voltage node is reset to the initial state until the rising edges of the next group of F_REF and F_DIV arrive, and the next cycle of flipping is carried out.

[0079] Due to the different delays of the two driving modes, Tin is amplified by N + 1 times, realizing the amplification of the error pulse.

[0080] It should be noted that the noise introduced by the TAPFD designed in the present invention cannot be greater than the noise suppressed by the amplification factor of the TAPFD. Therefore, the low-noise design is the key to the high efficiency of this structure. The structure used in the present invention is simple, and basically digital signal transmission is involved, so the introduced phase noise is relatively small.

[0081] The amplification factor K of the TAPFD provided by the present invention tapfd As Figure 7 shown, the simulation step size is 10 ps, and it can be seen that the values near the zero point are relatively stable. When N = 7, the theoretical K tapfd is approximately 8, and the measured K tapfd is around 9 - 10. The amplification factor is larger at the near-zero end, and the waveform at the near-zero point is similar to the sine waveform of the subsampling phase-locked loop. It should be noted that if the design of the CP leads to a large current mismatch, there will be a very small static phase error between F_REF and F_DIV at the final lock-in. The amplification factor at this error is the effective Ktapfd of the transfer function. Therefore, it is necessary to ensure that the static phase error at lock-in is not greater than the linear range of the error pulse amplification of the TAPFD.

[0082] The output current noise density spectrum of the PFD + CP is as Figure 8 shown. This figure compares the output current noise density spectra of using the TAPFD provided by the present invention (i.e., the charge pump phase-locked loop with a time amplifier) and the traditional PFD. It can be seen from the figure that the noise introduced by the TAPFD using the time amplifier is smaller compared to the noise suppressed by the TAPFD. Because when only calculating the benefit brought by K tapfd when K tapfd = 8, the noise is suppressed by 8^2 times, that is, 18 dB. And the noise of the TAPFD itself is not greater than 18 dB compared to the PFD at low frequencies from 10 Hz to 1 MHz. Coupled with the fact that the loop bandwidth can be appropriately increased due to the amplification factor of the TAPFD, further suppressing the VCO noise, and the power consumption and area consumed by this invention are both very small, so the overall benefit is considerable. Therefore, the TAPFD of this invention can be used for suppressing the in-band noise of the charge pump phase-locked loop.

[0083] The dead zone of the TAPFD of this invention is not much different from that of the traditional PFD. The simulation results are as Figure 9 shown. The phase discrimination direction flips at 14 - 15 ns. Since the reference period is 60 MHz, the phase discrimination range is approximately 14n / (1 / 60M) = 85.6%, which is very close to the frequency discrimination ability of the traditional PFD.

[0084] Although the present invention uses a three-stage ring oscillator to generate different periodic signals, it is also possible to directly use different periodic signals from other sources, which are all within the scope of the present invention.

[0085] The specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various deformations or modifications within the scope of the claims, which do not affect the essence of the present invention.

Claims

1. A phase frequency detector for a low in-band noise charge pump phase-locked loop, which is used to reduce the in-band noise of the charge pump phase-locked loop, the phase-locked loop at least comprising a first trigger (D1) and a second trigger (D2), characterized in that: The outputs of the first trigger (D1) and the second trigger (D2) are respectively used as inputs of a first time amplifier (1) and a second time amplifier (2); the first time amplifier (1) and the second time amplifier (2) at least comprise a phase generation module (11) and an edge detection module (12); the phase generation module (11) comprises at least a three-stage ring oscillator; and the edge detection module (12) comprises at least two cascaded synchronous edge D triggers, namely a third D trigger (D3) and a fourth D trigger (D4).

2. The phase frequency detector according to claim 1, characterized in that: The three-stage ring oscillator is composed of three groups of NAND connected in series, and each group of NAND is composed of one unit NAND (111) and N units NAND (112) connected in parallel.

3. The phase frequency detector according to claim 2, characterized in that: The output node of each NAND group is also connected to a small capacitor (113).

4. The phase frequency detector according to claim 3, characterized in that: The capacitance range of the small capacitor (113) is greater than 8fF.

5. The phase frequency detector according to any one of claims 2 to 4, characterized in that: The W / L size of the N-unit NAND (112) is N times that of the one-unit NAND (111).

6. The phase frequency detector according to claim 5, characterized in that: The range of N is between 2-20.

7. The phase frequency detector according to any one of claims 2 to 6, characterized in that: The group of NAND at least comprises a first PMOS tube (MP0), a second PMOS tube (MP1), a third PMOS tube (MP2), a first NMOS tube (MN0), a second NMOS tube (MN1), and a third NMOS tube (MN2); the third PMOS tube (MP2) and the third NMOS tube (MN2) are switch tubes respectively, and their source ends are respectively connected to VDD and GND, and their drain ends are connected to the first PMOS tube (MP0), the second PMOS tube (MP1), and the second NMOS tube (MN1); the drain end of the second NMOS tube (MN1) is connected to the source end of the first NMOS tube (MN0); and the drain ends of the first NMOS tube (MN0) and the first PMOS tube (MP0) and the second PMOS tube (MP1) are used as outputs.

8. The phase frequency detector according to any one of claims 1 to 7, characterized in that: The input end of the third D flip-flop (D3) is fixed to VDD, the output end of the third D flip-flop (D3) is connected to the input end of the fourth D flip-flop (D4), the inverted signal CK_TA of the output CK1 of the first group of NAND is used as the clock signal of the third D flip-flop (D3) and the fourth D flip-flop (D4), and the reset end is connected to the reset signal generated by TAPFD to control the output reset of the third D flip-flop (D3) and the fourth D flip-flop (D4).

9. The phase frequency detector according to any one of claims 1 to 8, characterized in that: The frequency and phase detector at least further comprises a third buffer (B3) and a fourth buffer (B4) connected to the output end of the edge detection module (12), which are at least used for shaping the pulse signal and increasing the driving capability.

10. The phase frequency detector according to any one of claims 1 to 9, characterized in that: The phase frequency detector at least further comprises a delay array module (13) connected to the output end of the edge detection module (12) and at least consisting of an inverter and an NMOS capacitor, wherein the output of the delay array module (13) is connected to the reset end of the phase frequency detector.

11. The phase frequency detector according to any one of claims 1 to 10, characterized in that: The outputs of the first trigger (D1) and the second trigger (D2) are used to generate driving switching enable signals for the first time amplifier (1) and the second time amplifier (2) through a NOR gate.

12. A low in-band noise charge pump phase-locked loop, comprising at least a first trigger (D1) and a second trigger (D2), characterized in that: It also comprises a phase frequency detector according to any one of claims 1 to 11.

13. A method for controlling low in-band noise of a phase frequency detector according to claim 12, characterized in that: The steps include: Step a. When F_REF is ahead, the rising edge of REF_TA causes the first time amplifier (1) to start working with a strong driving capability, and the second time amplifier (2) does not work; Step b. When F_DIV arrives, EN_TA is set to a high level, and the first time amplifier (1) and the second time amplifier (2) operate with a weak driving capability; Step c. When operating with weak driving capability, when the second rising edge of CK_TA2 arrives, the outputs of the first time amplifier (1) and the second time amplifier (2) are both high level; Step d. The first trigger (D1), the second trigger (D2), the first time amplifier (1) and the second time amplifier (2) are reset to an initial state, and a control cycle is completed.

14. The control method according to claim 13, characterized in that: The method further comprises the following steps: taking an inverted signal at the output end of the first group of NAND (112) as CK_TA.

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