Modulation circuit and modulator

Abstract

The invention is suitable for the technical field of modulators, and provides a modulation circuit and a modulator. The modulation circuit comprises a first switched capacitor module, a second switched capacitor module, a third switched capacitor module, a fourth switched capacitor module, a first quantization output module, a second quantization output module, a first operational amplifier module and a second operational amplifier module, and the first switched capacitor module is connected with the second switched capacitor module and the first operational amplifier module. The second switched capacitor module is respectively connected with the first quantization output module and the second operational amplifier module, the third switched capacitor module is respectively connected with the fourth switched capacitor module and the first operational amplifier module, and the fourth switched capacitor module is respectively connected with the second quantization output module and the second operational amplifier module. According to the modulation circuit, the first switched capacitor module and the third switched capacitor module share the first operational amplifier module, the second switched capacitor module and the fourth switched capacitor module share the second operational amplifier module, the use number of the operational amplifier modules is reduced, and the area of the modulator is reduced.

Description

Technical Field

[0001] This application belongs to the technical field of modulators, and particularly relates to a modulation circuit and a modulator. Background Art

[0002] High-precision battery parameter monitoring is the basis for the normal operation of a Battery Management System (BMS) chip. The voltage and current of a battery are analog quantities, so a high-precision Analog-to-Digital Converter (ADC) is a key module of the BMS chip. Although traditional Nyquist ADCs have a high conversion rate, they have high requirements for device matching, are difficult to achieve more than 12-bit effective precision, and have high power consumption, making them unsuitable for circuit monitoring systems. In contrast, Delta Sigma ADCs use oversampling and noise shaping techniques to reduce the requirements for analog circuits, trading speed for precision, and can maintain low power consumption while achieving more than 16-bit effective precision. The battery parameters in a BMS change slowly and have low requirements for the ADC conversion speed, so Delta Sigma ADCs are very suitable. However, BMS chips usually need to measure the voltage and current of the battery separately. The traditional method is to use two single-channel Delta Sigma modulators, and each modulator needs to be configured with the same number of operational amplifier modules as its internal switched-capacitor module, which in turn leads to relatively large areas for both the modulator and the BMS chip. Summary of the Invention

[0003] The embodiments of this application provide a modulation circuit and a modulator, which can solve the problem that the existing BMS chips use two modulators, and each modulator needs to be configured with the same number of operational amplifier modules as its internal switched-capacitor module, resulting in relatively large areas for both the modulator and the BMS chip.

[0004] In a first aspect, the embodiments of this application provide a modulation circuit, including a first switched-capacitor module, a second switched-capacitor module, a third switched-capacitor module, a fourth switched-capacitor module, a first quantization output module, a second quantization output module, a first operational amplifier module, and a second operational amplifier module. The first switched-capacitor module is electrically connected to the second switched-capacitor module and the first operational amplifier module respectively. The second switched-capacitor module is electrically connected to the first quantization output module and the second operational amplifier module respectively. The third switched-capacitor module is electrically connected to the fourth switched-capacitor module and the first operational amplifier module respectively. The fourth switched-capacitor module is electrically connected to the second quantization output module and the second operational amplifier module respectively.

[0005] The first switched-capacitor module is configured to receive a first input signal and output a first output signal to the second switched-capacitor module according to the first input signal. The first switched-capacitor module is further configured to output a first signal to the first operational amplifier module according to the first input signal. The second switched-capacitor module is configured to output a second signal to the second operational amplifier module and output a second output signal to the first quantization output module according to a first superimposed signal, where the first superimposed signal is a signal obtained by superimposing the first output signal and a first operational amplifier signal. The first quantization output module is configured to output a first target signal according to the second output signal and a second superimposed signal, where the second superimposed signal is a signal obtained by superimposing the second output signal and a second operational amplifier signal.

[0006] The third switched-capacitor module is configured to receive a second input signal and output a third output signal to the fourth switched-capacitor module according to the second input signal. The third switched-capacitor module is further configured to output a third signal to the first operational amplifier module according to the second input signal. The fourth switched-capacitor module is configured to output a fourth signal to the second operational amplifier module and output a fourth output signal to the second quantization output module according to a third superimposed signal, where the third superimposed signal is a signal obtained by superimposing the third output signal and the first operational amplifier signal. The second quantization output module is configured to output a second target signal according to the fourth output signal and a fourth superimposed signal, where the fourth superimposed signal is a signal obtained by superimposing the fourth output signal and the second operational amplifier signal.

[0007] The first operational amplifier module is configured to output the first operational amplifier signal to the second switched-capacitor module and the fourth switched-capacitor module according to the first signal and the third signal respectively. The second operational amplifier module is configured to output the second operational amplifier signal to the first quantization output module and the second quantization output module according to the second signal and the fourth signal respectively.

[0008] In a possible implementation of the first aspect, the first quantization output module is electrically connected to the first switched-capacitor module and the second switched-capacitor module respectively. The first switched-capacitor module includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a first capacitor, and a second capacitor. The first end of the first switch is grounded. The first end of the second switch is used to be electrically connected to a first power supply. The first end of the third switch is electrically connected to the second end of the first switch, the second end of the second switch, and the first quantization output module respectively. The second end of the third switch is electrically connected to the second end of the fourth switch and the first end of the first capacitor respectively. The first end of the fourth switch is used to receive the first input signal. The first end of the fifth switch is used to be electrically connected to a second power supply. The second end of the fifth switch is electrically connected to the second end of the first capacitor, the first end of the second capacitor, and the first operational amplifier module respectively. The first end of the sixth switch is electrically connected to the second end of the second capacitor. The second end of the sixth switch is electrically connected to the second switched-capacitor module and the first operational amplifier module respectively. The control end of the first switch is used to receive a first control signal. The control end of the second switch is used to receive a second control signal. The control end of the third switch is used to receive a second delay signal. The control end of the fourth switch is used to receive a first delay signal. The control end of the fifth switch is used to receive a first preset clock signal. The control end of the sixth switch is used to receive a second preset clock signal.

[0009] In a possible implementation of the first aspect, the second switched-capacitor module includes a seventh switch, an eighth switch, a ninth switch, a tenth switch, an eleventh switch, a twelfth switch, a third capacitor, and a fourth capacitor. The first terminal of the seventh switch is grounded. The first terminal of the eighth switch is used to be electrically connected to the first power supply. The first terminal of the ninth switch is respectively electrically connected to the second terminal of the seventh switch, the second terminal of the eighth switch, and the first quantization output module. The second terminal of the ninth switch is respectively electrically connected to the second terminal of the tenth switch and the first terminal of the third capacitor. The first terminal of the tenth switch is respectively electrically connected to the first switched-capacitor module and the first operational amplifier module. The first terminal of the eleventh switch is used to be electrically connected to the second power supply. The second terminal of the eleventh switch is respectively electrically connected to the second terminal of the third capacitor, the first terminal of the fourth capacitor, and the second operational amplifier module. The first terminal of the twelfth switch is electrically connected to the second terminal of the fourth capacitor. The second terminal of the twelfth switch is respectively electrically connected to the first quantization output module and the second operational amplifier module. The control terminal of the seventh switch is used to receive a third control signal. The control terminal of the eighth switch is used to receive a fourth control signal. The control terminal of the ninth switch is used to receive the first delay signal. The control terminal of the tenth switch is used to receive the second delay signal. The control terminal of the eleventh switch is used to receive the second preset clock signal. The control terminal of the twelfth switch is used to receive the first preset clock signal.

[0010] In a possible implementation of the first aspect, the second quantization output module is electrically connected to the third switched-capacitor module and the fourth switched-capacitor module respectively. The third switched-capacitor module includes a thirteenth switch, a fourteenth switch, a fifteenth switch, a sixteenth switch, a seventeenth switch, an eighteenth switch, a fifth capacitor, and a sixth capacitor. The first terminal of the thirteenth switch is grounded. The first terminal of the fourteenth switch is used to be electrically connected to a first power supply. The first terminal of the fifteenth switch is electrically connected to the second terminal of the thirteenth switch, the second terminal of the fourteenth switch, and the second quantization output module respectively. The second terminal of the fifteenth switch is electrically connected to the second terminal of the sixteenth switch and the first terminal of the fifth capacitor respectively. The first terminal of the sixteenth switch is used to receive the second input signal. The first terminal of the seventeenth switch is used to be electrically connected to a second power supply. The second terminal of the seventeenth switch is electrically connected to the second terminal of the fifth capacitor, the first terminal of the sixth capacitor, and the first operational amplifier module respectively. The first terminal of the eighteenth switch is electrically connected to the second terminal of the sixth capacitor. The second terminal of the eighteenth switch is electrically connected to the fourth switched-capacitor module and the first operational amplifier module respectively. The control terminal of the thirteenth switch is used to receive a fifth control signal. The control terminal of the fourteenth switch is used to receive a sixth control signal. The control terminal of the fifteenth switch is used to receive a first delay signal. The control terminal of the sixteenth switch is used to receive a second delay signal. The control terminal of the seventeenth switch is used to receive a second preset clock signal. The control terminal of the eighteenth switch is used to receive a first preset clock signal.

[0011] In a possible implementation of the first aspect, the fourth switched-capacitor module includes a nineteenth switch, a twentieth switch, a twenty-first switch, a twenty-second switch, a twenty-third switch, a twenty-fourth switch, a seventh capacitor, and an eighth capacitor. The first terminal of the nineteenth switch is grounded. The first terminal of the twentieth switch is configured to be electrically connected to the first power supply. The first terminal of the twenty-first switch is respectively electrically connected to the second terminal of the nineteenth switch, the second terminal of the twentieth switch, and the second quantization output module. The second terminal of the twenty-first switch is respectively electrically connected to the second terminal of the twenty-second switch and the first terminal of the seventh capacitor. The first terminal of the twenty-second switch is respectively electrically connected to the third switched-capacitor module and the first operational amplifier module. The first terminal of the twenty-third switch is configured to be electrically connected to the second power supply. The second terminal of the twenty-third switch is respectively electrically connected to the second terminal of the seventh capacitor, the first terminal of the eighth capacitor, and the second operational amplifier module. The first terminal of the twenty-fourth switch is electrically connected to the second terminal of the eighth capacitor. The second terminal of the twenty-fourth switch is respectively electrically connected to the second quantization output module and the second operational amplifier module. The control terminal of the nineteenth switch is configured to receive a seventh control signal. The control terminal of the twentieth switch is configured to receive an eighth control signal. The control terminal of the twenty-first switch is configured to receive the second delay signal. The control terminal of the twenty-second switch is configured to receive the first delay signal. The control terminal of the twenty-third switch is configured to receive the first preset clock signal. The control terminal of the twenty-fourth switch is configured to receive the second preset clock signal.

[0012] In a possible implementation of the first aspect, the first quantization output module includes a twenty-fifth switch, a first comparator, and a first flip-flop. The first terminal of the twenty-fifth switch is respectively electrically connected to the second switched-capacitor module and the second operational amplifier module. The second terminal of the twenty-fifth switch is electrically connected to the first input terminal of the first comparator. The second input terminal of the first comparator is configured to be electrically connected to the second power supply. The output terminal of the first comparator is electrically connected to the input terminal of the first flip-flop. The enable terminal of the first comparator is configured to receive the second preset clock signal. The output terminal of the first flip-flop is configured to output the first target signal. The clock input terminal of the first flip-flop is configured to receive the first preset clock signal.

[0013] In a possible implementation of the first aspect, the second quantization output module includes a twenty-sixth switch, a second comparator, and a second flip-flop. The first end of the twenty-sixth switch is electrically connected to the fourth switched-capacitor module and the second operational amplifier module respectively. The second end of the twenty-sixth switch is electrically connected to the first input terminal of the second comparator. The second input terminal of the second comparator is used to be electrically connected to a second power supply. The output terminal of the second comparator is electrically connected to the input terminal of the second flip-flop. The enable terminal of the second comparator is used to receive a first preset clock signal. The output terminal of the second flip-flop is used to output the second target signal. The clock input terminal of the second flip-flop is used to receive a second preset clock signal.

[0014] In a possible implementation of the first aspect, the first operational amplifier module includes a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, and a first operational amplifier. The gates of the first switching transistor and the fourth switching transistor are both used to receive a first preset clock signal. The source of the first switching transistor is electrically connected to the first switched-capacitor module, the drain of the first switching transistor, and the source of the second switching transistor respectively. The gates of the second switching transistor and the third switching transistor are both used to receive a second preset clock signal. The drain of the second switching transistor is electrically connected to the drain of the fourth switching transistor and the first input terminal of the first operational amplifier respectively. The source of the third switching transistor is electrically connected to the third switched-capacitor module, the drain of the third switching transistor, and the source of the fourth switching transistor respectively. The second input terminal of the first operational amplifier is used to be electrically connected to a second power supply. The output terminal of the first operational amplifier is electrically connected to the first switched-capacitor module, the second switched-capacitor module, the third switched-capacitor module, and the fourth switched-capacitor module respectively.

[0015] In a possible implementation of the first aspect, the second operational amplifier module includes a fifth switching transistor, a sixth switching transistor, a seventh switching transistor, an eighth switching transistor, and a second operational amplifier. The gates of the fifth switching transistor and the eighth switching transistor are both used to receive a second preset clock signal. The source of the fifth switching transistor is electrically connected to the second switched-capacitor module, the drain of the fifth switching transistor, and the source of the sixth switching transistor respectively. The gates of the sixth switching transistor and the seventh switching transistor are both used to receive a first preset clock signal. The drain of the sixth switching transistor is electrically connected to the drain of the eighth switching transistor and the first input terminal of the second operational amplifier respectively. The source of the seventh switching transistor is electrically connected to the fourth switched-capacitor module, the drain of the seventh switching transistor, and the source of the eighth switching transistor respectively. The second input terminal of the second operational amplifier is used to be electrically connected to a second power supply. The output terminal of the second operational amplifier is electrically connected to the second switched-capacitor module, the fourth switched-capacitor module, the first quantization output module, and the second quantization output module respectively.

[0016] In a second aspect, an embodiment of the present application provides a modulator, including the modulation circuit described in any one of the first aspects.

[0017] The beneficial effects of the embodiments of the present application compared with the prior art are as follows:

[0018] The modulation circuit provided by the embodiment of the present application includes a first switched-capacitor module, a second switched-capacitor module, a third switched-capacitor module, a fourth switched-capacitor module, a first quantization output module, a second quantization output module, a first operational amplifier module, and a second operational amplifier module. Since the first operational amplifier module can receive a first signal and a third signal, and determine whether the first signal or the third signal takes effect according to a first preset clock signal and a second preset clock signal, so as to output a first operational amplifier signal to the second switched-capacitor module or the fourth switched-capacitor module, therefore, the first operational amplifier module can be shared by the first switched-capacitor module and the third switched-capacitor module. Similarly, since the second operational amplifier module can receive a second signal and a fourth signal, and determine whether the second signal or the fourth signal takes effect according to the first preset clock signal and the second preset clock signal, so as to output a second operational amplifier signal to the first quantization output module or the second quantization output module, therefore, the second operational amplifier module can be shared by the second switched-capacitor module and the fourth switched-capacitor module. It can be seen therefrom that in the modulation circuit provided by the embodiment of the present application, the first switched-capacitor module and the third switched-capacitor module can share the first operational amplifier module, and the second switched-capacitor module and the fourth switched-capacitor module can share the second operational amplifier module, thereby reducing the number of operational amplifier modules used, reducing the area of the modulator, and further reducing the area of the BMS chip.

[0019] It can be understood that for the beneficial effects of the above second aspect, reference can be made to the relevant descriptions in the above first aspect, and details are not described herein again. Description of the Drawings

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments or the prior art descriptions. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0021] Figure 1 It is a schematic block diagram of a modulation circuit provided by an embodiment of the present application;

[0022] Figure 2 It is a schematic block diagram of a modulation circuit provided by another embodiment of the present application;

[0023] Figure 3 It is a schematic circuit connection diagram of a modulation circuit provided by an embodiment of the present application;

[0024] Figure 4 It is a waveform diagram of a preset clock signal provided by an embodiment of the present application.

[0025] In the figure, 101 is the first switched-capacitor module; 102 is the second switched-capacitor module; 103 is the third switched-capacitor module; 104 is the fourth switched-capacitor module; 105 is the first quantization output module; 106 is the second quantization output module; 107 is the first operational amplifier module; 108 is the second operational amplifier module. Detailed implementation manners

[0026] In the following description, for the purpose of illustration rather than limitation, specific details such as specific system architectures and technologies are presented to thoroughly understand the embodiments of the present application. However, those skilled in the art should clearly understand that the present application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid unnecessary details from interfering with the description of the present application.

[0027] It should be understood that when used in the specification of the present application and the appended claims, the term "comprising" indicates the presence of the described features, wholes, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.

[0028] It should also be understood that the term "and / or" as used in the specification of the present application and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0029] As used in the specification of the present application and the appended claims, the term "if" can be interpreted as "when" or "once" or "in response to determining" or "in response to detecting" according to the context. Similarly, the phrase "if determined" or "if detecting [the described condition or event]" can be interpreted as meaning "once determined" or "in response to determining" or "once detecting [the described condition or event]" or "in response to detecting [the described condition or event]" according to the context.

[0030] In addition, in the description of the specification of the present application and the appended claims, the terms "first", "second", "third", etc. are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.

[0031] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that specific features, structures, or characteristics described in connection with that embodiment are included in one or more embodiments of this application. Thus, statements such as "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments", etc. that appear in different places in this specification do not necessarily all refer to the same embodiment, but rather mean "one or more but not all embodiments", unless otherwise specifically emphasized. The terms "comprising", "including", "having" and their variants all mean "including but not limited to", unless otherwise specifically emphasized.

[0032] BMS chips usually need to measure the voltage and current of the battery separately. The traditional method is to use two single-channel Delta Sigma modulators, and each modulator needs to be configured with the same number of operational amplifier modules as its internal switched-capacitor module, which in turn results in relatively large areas for both the modulator and the BMS chip.

[0033] Based on the above problems, the modulation circuit provided in the embodiments of this application includes a first switched-capacitor module, a second switched-capacitor module, a third switched-capacitor module, a fourth switched-capacitor module, a first quantization output module, a second quantization output module, a first operational amplifier module, and a second operational amplifier module. Since the first operational amplifier module can receive the first signal and the third signal, and determine whether the first signal or the third signal takes effect according to the first preset clock signal and the second preset clock signal, so as to output a first operational amplifier signal to the second switched-capacitor module or the fourth switched-capacitor module, therefore, the first operational amplifier module can be shared by the first switched-capacitor module and the third switched-capacitor module. Similarly, since the second operational amplifier module can receive the second signal and the fourth signal, and determine whether the second signal or the fourth signal takes effect according to the first preset clock signal and the second preset clock signal, so as to output a second operational amplifier signal to the first quantization output module or the second quantization output module, therefore, the second operational amplifier module can be shared by the second switched-capacitor module and the fourth switched-capacitor module. It can be seen that in the modulation circuit provided in the embodiments of this application, the first switched-capacitor module and the third switched-capacitor module can share the first operational amplifier module, and the second switched-capacitor module and the fourth switched-capacitor module can share the second operational amplifier module, thereby reducing the number of operational amplifier modules used, reducing the area of the modulator, and further reducing the area of the BMS chip.

[0034] In order to illustrate the technical solutions described in this application, the following will be described through specific embodiments.

[0035] Figure 1 The principle block diagram of the modulation circuit provided in an embodiment of this application is shown. Refer to Figure 1As shown, the modulation circuit includes a first switched-capacitor module 101, a second switched-capacitor module 102, a third switched-capacitor module 103, a fourth switched-capacitor module 104, a first quantization output module 105, a second quantization output module 106, a first operational amplifier module 107, and a second operational amplifier module 108. The first switched-capacitor module 101 is electrically connected to the second switched-capacitor module 102 and the first operational amplifier module 107 respectively. The second switched-capacitor module 102 is electrically connected to the first quantization output module 105 and the second operational amplifier module 108 respectively. The third switched-capacitor module 103 is electrically connected to the fourth switched-capacitor module 104 and the first operational amplifier module 107 respectively. The fourth switched-capacitor module 104 is electrically connected to the second quantization output module 106 and the second operational amplifier module 108 respectively.

[0036] The first switched-capacitor module 101 is configured to receive a first input signal Cin1 and output a first output signal to the second switched-capacitor module 102 according to the first input signal Cin1. The first switched-capacitor module 101 is further configured to output a first signal T1 to the first operational amplifier module 107 according to the first input signal Cin1. The second switched-capacitor module 102 is configured to output a second signal T2 to the second operational amplifier module 108 according to the first superimposed signal and output a second output signal to the first quantization output module 105 according to the first superimposed signal. The first superimposed signal is a signal obtained by superimposing the first output signal and a first operational amplifier signal Cout1. The first quantization output module 105 is configured to output a first target signal BS1d according to the second output signal, the second superimposed signal, a first preset clock signal Φ1, and a second preset clock signal Φ2. The second superimposed signal is a signal obtained by superimposing the second output signal and a second operational amplifier signal Cout2.

[0037] The third switched-capacitor module 103 is configured to receive a second input signal Cin2 and output a third output signal to the fourth switched-capacitor module 104 according to the second input signal Cin2. The third switched-capacitor module 103 is further configured to output a third signal T3 to the first operational amplifier module 107 according to the second input signal Cin2. The fourth switched-capacitor module 104 is configured to output a fourth signal T4 to the second operational amplifier module 108 according to the third superimposed signal and output a fourth output signal to the second quantization output module 106 according to the third superimposed signal. The third superimposed signal is a signal obtained by superimposing the third output signal and the first operational amplifier signal Cout1. The second quantization output module 106 is configured to output a second target signal BS2d according to the fourth output signal, the fourth superimposed signal, the first preset clock signal Φ1, and the second preset clock signal Φ2. The fourth superimposed signal is a signal obtained by superimposing the fourth output signal and the second operational amplifier signal Cout2.

[0038] The first operational amplifier module 107 is configured to output a first operational amplifier signal Cout1 to the second switched-capacitor module 102 and the fourth switched-capacitor module 104 respectively according to a first preset clock signal Φ1, a second preset clock signal Φ2, a first signal T1, and a third signal T3; the second operational amplifier module 108 is configured to output a second operational amplifier signal Cout2 to the first quantization output module 105 and the second quantization output module 106 respectively according to the first preset clock signal Φ1, the second preset clock signal Φ2, a second signal T2, and a fourth signal T4.

[0039] Specifically, since the first operational amplifier module 107 can receive the first signal T1 and the third signal T3, and determine whether the first signal T1 or the third signal T3 takes effect according to the first preset clock signal Φ1 and the second preset clock signal Φ2, so as to output the first operational amplifier signal Cout1 to the second switched-capacitor module 102 or the fourth switched-capacitor module 104, therefore, the first operational amplifier module 107 can be shared by the first switched-capacitor module 101 and the third switched-capacitor module 103. Similarly, since the second operational amplifier module 108 can receive the second signal and the fourth signal T4, and determine whether the second signal T2 or the fourth signal T4 takes effect according to the first preset clock signal Φ1 and the second preset clock signal Φ2, so as to output the second operational amplifier signal Cout2 to the first quantization output module 105 or the second quantization output module 106, therefore, the second operational amplifier module 108 can be shared by the second switched-capacitor module 102 and the fourth switched-capacitor module 104. It can be seen that in the modulation circuit provided by the embodiment of the present application, the first switched-capacitor module 101 and the third switched-capacitor module 103 can share the first operational amplifier module 107, and the second switched-capacitor module 102 and the fourth switched-capacitor module 104 can share the second operational amplifier module 108, thereby reducing the number of operational amplifier modules used, reducing the area of the modulator, and further reducing the area of the BMS chip.

[0040] It should be noted that the first input signal Cin1 and the second input signal Cin2 are both analog signals to be measured, and the first target signal BS1d and the second target signal BS2d are both converted digital signals. As Figure 2As shown in the figure, the first quantization output module 105 is also electrically connected to the first switched-capacitor module 101 and the second switched-capacitor module 102, and can feedback the output first target signal BS1d to the first switched-capacitor module 101 for further processing. At the same time, the BS1 signal output by the first quantization output module 105 is feedback to the second switched-capacitor module 102 for further processing. The second quantization output module 106 is also electrically connected to the third switched-capacitor module 103 and the fourth switched-capacitor module 104, and can feedback the output second target signal BS2d to the third switched-capacitor module 103 for further processing. At the same time, the BS2 signal output by the second quantization output module 106 is feedback to the fourth switched-capacitor module 104 for further processing. The above reprocessing of the target signal can ensure the accuracy of the finally output digital signal.

[0041] It should be noted that the first switched-capacitor module 101, the second switched-capacitor module 102 and the first quantization output module 105 serve as the first channel CH1 of the modulator, and the third switched-capacitor module 103, the fourth switched-capacitor module 104 and the second quantization output module 106 serve as the second channel CH2 of the modulator. The first switched-capacitor module 101 and the first operational amplifier module 107 can serve as the first stage of the first channel CH1, the second switched-capacitor module 102 and the second operational amplifier module 108 can serve as the second stage of the first channel CH1, the third switched-capacitor module 103 and the first operational amplifier module 107 can serve as the first stage of the second channel CH2, and the fourth switched-capacitor module 104 and the second operational amplifier module 108 can serve as the second stage of the second channel CH2. Thus, this application multiplexes the first operational amplifier module 107 and the second operational amplifier module 108, reducing the number of used operational amplifier modules, and reducing the area and cost of the modulator. This application uses a two-channel second-order modulator to simultaneously measure the voltage and current of the battery in the BMS chip, greatly reducing the area of the modulator, and thus reducing the area of the BMS chip.

[0042] In an embodiment of this application, as Figure 3As shown in the figure, the first switched-capacitor module 101 includes a first switch Q1, a second switch Q2, a third switch Q3, a fourth switch Q4, a fifth switch Q5, a sixth switch Q6, a first capacitor C1, and a second capacitor C2. The first end of the first switch Q1 is grounded. The first end of the second switch Q2 is used to be electrically connected to a first power supply VH. The first end of the third switch Q3 is respectively electrically connected to the second end of the first switch Q1, the second end of the second switch Q2, and the first quantization output module 105. The second end of the third switch Q3 is respectively electrically connected to the second end of the fourth switch Q4 and the first end of the first capacitor C1. The first end of the fourth switch Q4 is used to receive a first input signal Cin1. The first end of the fifth switch Q5 is used to be electrically connected to a second power supply VCM. The second end of the fifth switch Q5 is respectively electrically connected to the second end of the first capacitor C1, the first end of the second capacitor C2, and the first operational amplifier module 107. The first end of the sixth switch Q6 is electrically connected to the second end of the second capacitor C2. The second end of the sixth switch Q6 is respectively electrically connected to the second switched-capacitor module 102 and the first operational amplifier module 107. The control end of the first switch Q1 is used to receive a first control signal. The control end of the second switch Q2 is used to receive a second control signal. The control end of the third switch Q3 is used to receive a second delay signal Φ2d of a second preset clock signal Φ2. The control end of the fourth switch Q4 is used to receive a first delay signal Φ1d of a first preset clock signal Φ1. The control end of the fifth switch Q5 is used to receive the first preset clock signal Φ1. The control end of the sixth switch Q6 is used to receive the second preset clock signal Φ2.

[0043] Specifically, the first switch Q1, the second switch Q2, the third switch Q3, the fourth switch Q4, the fifth switch Q5, and the sixth switch Q6 all serve as switching devices and can be turned on or off according to the signals received at the control ends. Among them, the first switch Q1, the fifth switch Q5, and the sixth switch Q6 can all be set as NMOS transistors and are turned on only when the signals received at the control ends are high-level signals. The second switch Q2 can be set as a PMOS transistor and is turned on only when the signal received at the control end is a low-level signal. The third switch Q3 and the fourth switch Q4 can both be set as CMOS transistors and are turned on only when the signals received at the control ends are high-level signals. The first capacitor C1 and the second capacitor C2 both serve as energy storage devices and can store and release energy. When both the first preset clock signal Φ1 and the first delay signal Φ1d of the first preset clock signal Φ1 are high-level signals, and both the second preset clock signal Φ2 and the second delay signal Φ2d of the second preset clock signal Φ2 are low-level signals, the fourth switch Q4 and the fifth switch Q5 are both turned on, and the first input signal Cin1 and the second power supply VCM are connected across the first capacitor C1. At this time, the first signal T1 transmitted to the first operational amplifier module 107 will not act on the first operational amplifier module 107. At this time, the first switched-capacitor module 101 is in a sampling state, and the first capacitor C1 is the sampling capacitor.

[0044] It should be noted that the waveform diagrams of the first preset clock signal Φ1, the second preset clock signal Φ2, the first delay signal Φ1d of the first preset clock signal Φ1, and the second delay signal Φ2d of the second preset clock signal Φ2 are as follows Figure 4 shown. The first preset clock signal Φ1 and the second preset clock signal Φ2 are two-phase non-overlapping clock signals, and the first delay signal Φ1d of the first preset clock signal Φ1 and the second delay signal Φ2d of the second preset clock signal Φ2 are two-phase non-overlapping clock signals. In order to further optimize the system performance in this application, after a certain time of falling-edge delay of the first preset clock signal Φ1 and the second preset clock signal Φ2, the first delay signal Φ1d of the first preset clock signal Φ1 and the second delay signal Φ2d of the second preset clock signal Φ2 are generated, and these delay signals are used to control the sampling process of the lower plate of the capacitor in the switched-capacitor module. Through such a design, the channel charge injection effect related to the input signal can be effectively reduced, ensuring high precision and stability of the system during the conversion process.

[0045] It should be noted that this application can implement a 1-bit feedback DAC to convert digital signals into analog levels, namely VH and VL. This conversion process ensures the accurate conversion of signals from digital to analog. Through this feedback mechanism and conversion method, the system can efficiently process and quantify input signals in multiple stages, ensuring the accuracy and stability of the signals. Among them, Figure 3 VL represents grounding, and the first power supply VH can be set to twice the second power supply VCM.

[0046] It should be noted that the first target signal BS1d output by the first quantization output module 105 is fed back to the first switched-capacitor module 101, and the first switched-capacitor module 101 can subtract the first target signal BS1d from the first input signal Cin1.

[0047] In an embodiment of this application, as Figure 3As shown, the second switched-capacitor module 102 includes a seventh switch Q7, an eighth switch Q8, a ninth switch Q9, a tenth switch Q10, an eleventh switch Q11, a twelfth switch Q12, a third capacitor C3, and a fourth capacitor C4. The first terminal of the seventh switch Q7 is grounded. The first terminal of the eighth switch Q8 is used to be electrically connected to the first power supply VH. The first terminal of the ninth switch Q9 is respectively electrically connected to the second terminal of the seventh switch Q7, the second terminal of the eighth switch Q8, and the first quantization output module 105. The second terminal of the ninth switch Q9 is respectively electrically connected to the second terminal of the tenth switch Q10 and the first terminal of the third capacitor C3. The first terminal of the tenth switch Q10 is respectively electrically connected to the first switched-capacitor module 101 and the first operational amplifier module 107. The first terminal of the eleventh switch Q11 is used to be electrically connected to the second power supply VCM. The second terminal of the eleventh switch Q11 is respectively electrically connected to the second terminal of the third capacitor C3, the first terminal of the fourth capacitor C4, and the second operational amplifier module 108. The first terminal of the twelfth switch Q12 is electrically connected to the second terminal of the fourth capacitor C4. The second terminal of the twelfth switch Q12 is respectively electrically connected to the first quantization output module 105 and the second operational amplifier module 108. The control terminal of the seventh switch Q7 is used to receive a third control signal. The control terminal of the eighth switch Q8 is used to receive a fourth control signal. The control terminal of the ninth switch Q9 is used to receive a first delayed signal Φ1d of the first preset clock signal Φ1. The control terminal of the tenth switch Q10 is used to receive a second delayed signal Φ2d of the second preset clock signal Φ2. The control terminal of the eleventh switch Q11 is used to receive the second preset clock signal Φ2. The control terminal of the twelfth switch Q12 is used to receive the first preset clock signal Φ1.

[0048] Specifically, the seventh switch Q7, the eighth switch Q8, the ninth switch Q9, the tenth switch Q10, the eleventh switch Q11, and the twelfth switch Q12 all serve as switching devices and can be turned on or off according to the signals received at the control terminals. Among them, the seventh switch Q7, the eleventh switch Q11, and the twelfth switch Q12 can all be set as NMOS transistors, which are turned on only when the signals received at the control terminals are high-level signals. The eighth switch Q8 can be set as a PMOS transistor, which is turned on only when the signals received at the control terminals are low-level signals. The ninth switch Q9 and the tenth switch Q10 can both be set as CMOS transistors, which are turned on only when the signals received at the control terminals are high-level signals. The third capacitor C3 and the fourth capacitor C4 both serve as energy storage devices and can store and release energy. When the first preset clock signal Φ1 and the first delayed signal Φ1d of the first preset clock signal Φ1 are both high-level signals, and the second preset clock signal Φ2 and the second delayed signal Φ2d of the second preset clock signal Φ2 are both low-level signals, the ninth switch Q9 and the twelfth switch Q12 are both turned on. Assuming that the BS1 signal output by the first quantization output module 105 is a low-level signal, the seventh switch Q7 is turned on. At this time, VL is connected to the first end of the third capacitor C3 through the turned-on seventh switch Q7 and ninth switch Q9. The second end of the third capacitor C3 is connected to the first end of the fourth capacitor C4 and the second operational amplifier module 108. The first end of the fourth capacitor C4 can be connected to the second operational amplifier module 108 and the first quantization output module 105 through the turned-on twelfth switch Q12. During this process, the second signal T2 transmitted to the second operational amplifier module 108 will act on the second operational amplifier module 108. At this time, the second switched-capacitor module 102 is in an integrating state, and the third capacitor C3, the fourth capacitor C4, and the second operational amplifier module 108 form an integrating circuit for signal integration processing.

[0049] In summary, it can be seen that the first switched-capacitor module 101 and the first operational amplifier module 107 serve as the first stage of the first channel CH1, and the second switched-capacitor module 102 and the second operational amplifier module 108 serve as the second stage of the first channel CH1. When the first preset clock signal Φ1 and the first delayed signal Φ1d of the first preset clock signal Φ1 are both high-level signals, and the second preset clock signal Φ2 and the second delayed signal Φ2d of the second preset clock signal Φ2 are both low-level signals, the first stage of the first channel CH1 is in a sampling state, and the second stage of the first channel CH1 is in an integrating state.

[0050] In an embodiment of the present application, as Figure 3As shown, the second quantization output module 106 is electrically connected to the third switched-capacitor module 103 and the fourth switched-capacitor module 104 respectively. The third switched-capacitor module 103 includes a thirteenth switch Q13, a fourteenth switch Q14, a fifteenth switch Q15, a sixteenth switch Q16, a seventeenth switch Q17, an eighteenth switch Q18, a fifth capacitor C5 and a sixth capacitor C6. The first terminal of the thirteenth switch Q13 is grounded. The first terminal of the fourteenth switch Q14 is used to be electrically connected to the first power supply VH. The first terminal of the fifteenth switch Q15 is electrically connected to the second terminal of the thirteenth switch Q13, the second terminal of the fourteenth switch Q14 and the second quantization output module 106 respectively. The second terminal of the fifteenth switch Q15 is electrically connected to the second terminal of the sixteenth switch Q16 and the first terminal of the fifth capacitor C5 respectively. The first terminal of the sixteenth switch Q16 is used to receive the second input signal Cin2. The first terminal of the seventeenth switch Q17 is used to be electrically connected to the second power supply VCM. The second terminal of the seventeenth switch Q17 is electrically connected to the second terminal of the fifth capacitor C5, the first terminal of the sixth capacitor C6 and the first operational amplifier module 107 respectively. The first terminal of the eighteenth switch Q18 is electrically connected to the second terminal of the sixth capacitor C6. The second terminal of the eighteenth switch Q18 is electrically connected to the fourth switched-capacitor module 104 and the first operational amplifier module 107 respectively. The control terminal of the thirteenth switch Q13 is used to receive the fifth control signal. The control terminal of the fourteenth switch Q14 is used to receive the sixth control signal. The control terminal of the fifteenth switch Q15 is used to receive the first delayed signal Φ1d of the first preset clock signal Φ1. The control terminal of the sixteenth switch Q16 is used to receive the second delayed signal Φ2d of the second preset clock signal Φ2. The control terminal of the seventeenth switch Q17 is used to receive the second preset clock signal Φ2. The control terminal of the eighteenth switch Q18 is used to receive the first preset clock signal Φ1.

[0051] Specifically, the thirteenth switch Q13, fourteenth switch Q14, fifteenth switch Q15, sixteenth switch Q16, seventeenth switch Q17, and eighteenth switch Q18 are all used as switching devices and can be turned on or off according to the signals received at the control terminals. Among them, the thirteenth switch Q13, seventeenth switch Q17, and eighteenth switch Q18 can all be set as NMOS transistors and are turned on only when the signals received at the control terminals are high-level signals. The fourteenth switch Q14 can be set as a PMOS transistor and is turned on only when the signals received at the control terminals are low-level signals. The fifteenth switch Q15 and sixteenth switch Q16 can both be set as CMOS transistors and are turned on only when the signals received at the control terminals are high-level signals. The fifth capacitor C5 and sixth capacitor C6 are both used as energy storage devices and can store and release energy. When the first preset clock signal Φ1 and the first delayed signal Φ1d of the first preset clock signal Φ1 are both high-level signals, and the second preset clock signal Φ2 and the second delayed signal Φ2d of the second preset clock signal Φ2 are both low-level signals, the fifteenth switch Q15 and eighteenth switch Q18 are both turned on. Assuming that the second target signal BS2d output by the second quantization output module 106 is a high-level signal, the fourteenth switch Q14 is turned on. At this time, the first power supply VH can be connected to the first end of the fifth capacitor C5 through the turned-on fourteenth switch Q14 and fifteenth switch Q15. The second end of the fifth capacitor C5 is connected to the first end of the sixth capacitor C6 and the second operational amplifier module 108. The first end of the sixth capacitor C6 can be connected to the first operational amplifier module 107 and the second switched-capacitor module 102 through the turned-on eighteenth switch Q18. During this process, the third signal T3 transmitted to the first operational amplifier module 107 acts on the first operational amplifier module 107. At this time, the third switched-capacitor module 103 is in an integration state. The fifth capacitor C5, sixth capacitor C6, and first operational amplifier module 107 form an integration circuit for signal integration processing.

[0052] It should be noted that the second target signal BS2d output by the second quantization output module 106 is fed back to the third switched-capacitor module 103, and the third switched-capacitor module 103 can subtract the second target signal BS2d from the second input signal Cin2.

[0053] In an embodiment of the present application, as Figure 3As shown, the fourth switched-capacitor module 104 includes the nineteenth switch Q19, the twentieth switch Q20, the twenty-first switch Q21, the twenty-second switch Q22, the twenty-third switch Q23, the twenty-fourth switch Q24, the seventh capacitor C7, and the eighth capacitor C8. The first terminal of the nineteenth switch Q19 is grounded. The first terminal of the twentieth switch Q20 is used to be electrically connected to the first power supply VH. The first terminal of the twenty-first switch Q21 is respectively electrically connected to the second terminal of the nineteenth switch Q19, the second terminal of the twentieth switch Q20, and the second quantization output module 106. The second terminal of the twenty-first switch Q21 is respectively electrically connected to the second terminal of the twenty-second switch Q22 and the first terminal of the seventh capacitor C7. The first terminal of the twenty-second switch Q22 is respectively electrically connected to the third switched-capacitor module 103 and the first operational amplifier module 107. The first terminal of the twenty-third switch Q23 is used to be electrically connected to the second power supply VCM. The second terminal of the twenty-third switch Q23 is respectively electrically connected to the second terminal of the seventh capacitor C7, the first terminal of the eighth capacitor C8, and the second operational amplifier module 108. The first terminal of the twenty-fourth switch Q24 is electrically connected to the second terminal of the eighth capacitor C8. The second terminal of the twenty-fourth switch Q24 is respectively electrically connected to the second quantization output module 106 and the second operational amplifier module 108. The control terminal of the nineteenth switch Q19 is used to receive the seventh control signal. The control terminal of the twentieth switch Q20 is used to receive the eighth control signal. The control terminal of the twenty-first switch Q21 is used to receive the second delay signal Φ2d of the second preset clock signal Φ2. The control terminal of the twenty-second switch Q22 is used to receive the first delay signal Φ1d of the first preset clock signal Φ1. The control terminal of the twenty-third switch Q23 is used to receive the first preset clock signal Φ1. The control terminal of the twenty-fourth switch Q24 is used to receive the second preset clock signal Φ2.

[0054] Specifically, the nineteenth switch Q19, the twentieth switch Q20, the twenty-first switch Q21, the twenty-second switch Q22, the twenty-third switch Q23, and the twenty-fourth switch Q24 all serve as switching devices and can be turned on or off according to the signals received at the control terminals. Among them, the nineteenth switch Q19, the twenty-third switch Q23, and the twenty-fourth switch Q24 can all be set as NMOS transistors and are turned on only when the signals received at the control terminals are high-level signals. The twentieth switch Q20 can be set as a PMOS transistor and is turned on only when the signals received at the control terminals are low-level signals. The twenty-first switch Q21 and the twenty-second switch Q22 can both be set as CMOS transistors and are turned on only when the signals received at the control terminals are high-level signals. The seventh capacitor C7 and the eighth capacitor C8 both serve as energy storage devices and can store and release energy. When the first preset clock signal Φ1 and the first delay signal Φ1d of the first preset clock signal Φ1 are both high-level signals, and the second preset clock signal Φ2 and the second delay signal Φ2d of the second preset clock signal Φ2 are both low-level signals, the twenty-second switch Q22 and the twenty-third switch Q23 are both turned on. The sixth capacitor C6 is connected to the first end of the seventh capacitor C7 through the turned-on eighteenth switch Q18 and twenty-second switch Q22, and the second power supply VCM is connected to the second end of the seventh capacitor C7 through the turned-on twenty-third switch Q23. At this time, the fourth signal T4 transmitted to the second operational amplifier module 108 does not act on the second operational amplifier module 108. At this time, the fourth switched-capacitor module 104 is in the sampling state, and the seventh capacitor C7 is the sampling capacitor.

[0055] In summary, the third switched-capacitor module 103 and the first operational amplifier module 107 serve as the first stage of the second channel CH2, and the fourth switched-capacitor module 104 and the second operational amplifier module 108 serve as the second stage of the second channel CH2. When the first preset clock signal Φ1 and the first delay signal Φ1d of the first preset clock signal Φ1 are both high-level signals, and the second preset clock signal Φ2 and the second delay signal Φ2d of the second preset clock signal Φ2 are both low-level signals, the first stage of the second channel CH2 is in the integration state, and the second stage of the second channel CH2 is in the sampling state.

[0056] It should be noted that, compared with the existing modulator, during the sampling stage, the operational amplifier module is in a non-operating state, that is, the operational amplifier module does not participate in any signal processing or operation. Only when the conversion process enters the integration stage, the operational amplifier module starts to execute its integration function and performs an integration operation on the analog signal. As a result, the operational amplifier module is not fully utilized, leading to high power consumption of the chip. In this application, when the first preset clock signal Φ1 and the first delay signal Φ1d of the first preset clock signal Φ1 are both high-level signals, and the second preset clock signal Φ2 and the second delay signal Φ2d of the second preset clock signal Φ2 are both low-level signals, the first stage of the first channel CH1 is in the sampling state, and the second stage of the first channel CH1 is in the integration state; the first stage of the second channel CH2 is in the integration state, and the second stage of the second channel CH2 is in the sampling state. With such a design, it is continuously repeated under the periodic control of the clock signal, thereby ensuring that the two channels alternate between sampling and integration. This can make full use of the first operational amplifier module 107 and the second operational amplifier module 108, effectively reducing power consumption.

[0057] It should be noted that, conversely, when the first preset clock signal Φ1 and the first delay signal Φ1d of the first preset clock signal Φ1 are both low-level signals, and the second preset clock signal Φ2 and the second delay signal Φ2d of the second preset clock signal Φ2 are both high-level signals, the first stage of the first channel CH1 is in the integration state, and the second stage of the first channel CH1 is in the sampling state; the first stage of the second channel CH2 is in the sampling state, and the second stage of the second channel CH2 is in the integration state. The working principle in this process is similar to the working principle described above and will not be elaborated here.

[0058] In an embodiment of the present application, as Figure 3 shown, the first quantization output module 105 includes a twenty-fifth switch Q25, a first comparator U1, and a first flip-flop F1. The first end of the twenty-fifth switch Q25 is electrically connected to the second switched-capacitor module 102 and the second operational amplifier module 108 respectively. The second end of the twenty-fifth switch Q25 is electrically connected to the first input terminal of the first comparator U1. The second input terminal of the first comparator U1 is used to be electrically connected to the second power supply VCM. The output terminal of the first comparator U1 is electrically connected to the input terminal of the first flip-flop F1. The enable terminal of the first comparator U1 is used to receive the second preset clock signal Φ2. The output terminal of the first flip-flop F1 is used to output a first target signal BS1d. The clock input terminal of the first flip-flop F1 is used to receive the first preset clock signal Φ1.

[0059] Specifically, the twenty-fifth switch Q25 can be set as an NMOS transistor for receiving the first preset clock signal Φ1. The first input terminal of the first comparator U1 is the negative input terminal of the first comparator U1, and the second input terminal of the first comparator U1 is the positive input terminal of the first comparator U1. When the first preset clock signal Φ1 is a high-level signal, the twenty-fifth switch Q25 conducts, and the second superimposed signal can be transmitted to the first input terminal of the first comparator U1. When the second preset clock signal Φ2 is a high-level signal, the first comparator U1 compares the second superimposed signal with the second power supply VCM signal output by the second power supply VCM and outputs a first comparison signal BS1 (i.e., the BS1 signal) to the first flip-flop F1. The first flip-flop F1 is used to output a first target signal BS1d according to the first preset clock signal Φ1 and the first comparison signal BS1. Among them, the first flip-flop F1 can be a D flip-flop.

[0060] It should be noted that according to the working principle of the D flip-flop, it can be obtained that the first comparison signal BS1 is delayed by half a cycle to obtain the first target signal BS1d.

[0061] In an embodiment of the present application, as Figure 3 shown, the second quantization output module 106 includes a twenty-sixth switch Q26, a second comparator U2, and a second flip-flop F2. The first end of the twenty-sixth switch Q26 is electrically connected to the fourth switched-capacitor module 104 and the second operational amplifier module 108 respectively. The second end of the twenty-sixth switch Q26 is electrically connected to the first input terminal of the second comparator U2. The second input terminal of the second comparator U2 is used to be electrically connected to the second power supply VCM. The output terminal of the second comparator U2 is electrically connected to the input terminal of the second flip-flop F2. The enable terminal of the second comparator U2 is used to receive the first preset clock signal Φ1. The output terminal of the second flip-flop F2 is used to output a second target signal BS2d. The clock input terminal of the second flip-flop F2 is used to receive the second preset clock signal Φ2.

[0062] Specifically, the twenty-sixth switch Q26 can be set as an NMOS transistor for receiving the second preset clock signal Φ2. The first input terminal of the second comparator U2 is the negative input terminal of the second comparator U2, and the second input terminal of the second comparator U2 is the positive input terminal of the second comparator U2. When the second preset clock signal Φ2 is a high-level signal, the twenty-sixth switch Q26 conducts, and the fourth superimposed signal can be transmitted to the first input terminal of the second comparator U2. When the first preset clock signal Φ1 is a high-level signal, the second comparator U2 compares the fourth superimposed signal with the second power supply VCM signal output by the second power supply VCM, and outputs a second comparison signal BS2 (i.e., the BS2 signal) to the second flip-flop F2. The second flip-flop F2 is used to output a second target signal BS2d according to the second preset clock signal Φ2 and the second comparison signal BS2. Among them, the second flip-flop F2 can be a D flip-flop.

[0063] It should be noted that according to the working principle of the D flip-flop, it can be obtained that the second comparison signal BS2 is delayed by half a cycle to obtain the second target signal BS2d.

[0064] In an embodiment of the present application, as Figure 3 shown, the first operational amplifier module 107 includes a first switching transistor M1, a second switching transistor M2, a third switching transistor M3, a fourth switching transistor M4, and a first operational amplifier module 107. The gates of the first switching transistor M1 and the fourth switching transistor M4 are both used to receive the first preset clock signal Φ1. The source of the first switching transistor M1 is electrically connected to the first switched-capacitor module 101, the drain of the first switching transistor M1, and the source of the second switching transistor M2 respectively. The gates of the second switching transistor M2 and the third switching transistor M3 are both used to receive the second preset clock signal Φ2. The drain of the second switching transistor M2 is electrically connected to the drain of the fourth switching transistor M4 and the first input terminal of the first operational amplifier module 107 respectively. The source of the third switching transistor M3 is electrically connected to the third switched-capacitor module 103, the drain of the third switching transistor M3, and the source of the fourth switching transistor M4 respectively. The second input terminal of the first operational amplifier module 107 is used to be electrically connected to the second power supply VCM. The output terminal of the first operational amplifier module 107 is electrically connected to the first switched-capacitor module 101, the second switched-capacitor module 102, the third switched-capacitor module 103, and the fourth switched-capacitor module 104 respectively.

[0065] Specifically, the first switching transistor M1, the second switching transistor M2, the third switching transistor M3, and the fourth switching transistor M4 can all be set as NMOS transistors. The first switching transistor M1 and the fourth switching transistor M4 are both used to receive the first preset clock signal Φ1, and the second switching transistor M2 and the third switching transistor M3 are both used to receive the second preset clock signal Φ2. The first input terminal of the first operational amplifier module 107 is the negative input terminal of the first operational amplifier module 107, and the second input terminal of the first operational amplifier module 107 is the positive input terminal of the first operational amplifier module 107. When the first preset clock signal Φ1 is a high-level signal and the second preset clock signal Φ2 is a low-level signal, the first switching transistor M1 and the fourth switching transistor M4 are both turned on, and the second switching transistor M2 and the third switching transistor M3 are both turned off. At this time, the third signal T3 output by the third switched-capacitor module 103 can be transmitted to the negative input terminal of the first operational amplifier module 107 through the turned-on fourth switching transistor M4, so that the first operational amplifier module 107 outputs the first operational amplifier signal Cout1 according to the third signal T3 and the second power supply VCM signal. That is, the third signal T3 acts on the first operational amplifier module 107. At this time, the first stage of the second channel CH2 is in the integration state, and the first stage of the first channel CH1 is in the sampling state.

[0066] In an embodiment of the present application, as Figure 3 shown, the second operational amplifier module 108 includes a fifth switching transistor M5, a sixth switching transistor M6, a seventh switching transistor M7, an eighth switching transistor M8, and a second operational amplifier OTA2. The gates of the fifth switching transistor M5 and the eighth switching transistor M8 are both used to receive the second preset clock signal Φ2. The source of the fifth switching transistor M5 is electrically connected to the second switched-capacitor module 102, the drain of the fifth switching transistor M5, and the source of the sixth switching transistor M6 respectively. The gates of the sixth switching transistor M6 and the seventh switching transistor M7 are both used to receive the first preset clock signal Φ1. The drain of the sixth switching transistor M6 is electrically connected to the drain of the eighth switching transistor M8 and the first input terminal of the second operational amplifier OTA2 respectively. The source of the seventh switching transistor M7 is electrically connected to the fourth switched-capacitor module 104, the drain of the seventh switching transistor M7, and the source of the eighth switching transistor M8 respectively. The second input terminal of the second operational amplifier OTA2 is used to be electrically connected to the second power supply VCM. The output terminal of the second operational amplifier OTA2 is electrically connected to the second switched-capacitor module 102, the fourth switched-capacitor module 104, the first quantization output module 105, and the second quantization output module 106 respectively.

[0067] Specifically, the fifth switching transistor M5, the sixth switching transistor M6, the seventh switching transistor M7, and the eighth switching transistor M8 can all be set as NMOS transistors. The fifth switching transistor M5 and the eighth switching transistor M8 are both used to receive the second preset clock signal Φ2, and the sixth switching transistor M6 and the seventh switching transistor M7 are both used to receive the first preset clock signal Φ1. The first input terminal of the second operational amplifier OTA2 is the negative input terminal of the second operational amplifier OTA2, and the second input terminal of the second operational amplifier OTA2 is the positive input terminal of the second operational amplifier OTA2. When the first preset clock signal Φ1 is a high-level signal and the second preset clock signal Φ2 is a low-level signal, both the sixth switching transistor M6 and the seventh switching transistor M7 are turned on, and both the fifth switching transistor M5 and the eighth switching transistor M8 are turned off. At this time, the second signal T2 output by the second switched-capacitor module 102 can be transmitted to the negative input terminal of the second operational amplifier OTA2 through the turned-on sixth switching transistor M6, so that the second operational amplifier OTA2 outputs a second operational amplifier signal Cout2 according to the second signal T2 and the second power supply VCM signal, that is, the second signal T2 will act on the second operational amplifier module 108. At this time, the second stage of the first channel CH1 is in the integration state, and the first stage of the second channel CH2 is in the sampling state.

[0068] It should be noted that in this application, the first stage of the two channels multiplexes the first operational amplifier module 107, and the second stage multiplexes the second operational amplifier module 108. By controlling the above eight switching transistors with two-phase non-overlapping first preset clock signal Φ1 and second preset clock signal Φ2, the first operational amplifier module 107 and the second operational amplifier module 108 are both alternately switched between the two channels. The main purpose of this clock control method is to prevent the two channels from being simultaneously turned on, thereby avoiding timing disorders and unnecessary power consumption.

[0069] It should be noted that since both the first preset clock signal Φ1 and the second preset clock signal Φ2 are periodic signals, in subsequent clock cycles, the system will continue to work in the above manner and complete a complete data conversion after multiple cycles, improving the conversion efficiency.

[0070] This application also discloses a modulator, including the above-mentioned modulation circuit. Among them, the modulator can be a Delta-Sigma modulator. The modulator adopts the above-mentioned modulation circuit, which can greatly reduce the power consumption and area of the modulator, and further reduce the area, cost, and power consumption of the BMS chip.

[0071] Since the processing and functions implemented by the modulator in this embodiment are basically corresponding to the embodiments, principles, and examples of the foregoing modulation circuit, for the details not described in the description of this embodiment, reference can be made to the relevant descriptions in the foregoing embodiments and will not be repeated here.

[0072] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit it; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A modulation circuit, characterized in that: It includes a first switch capacitor module, a second switch capacitor module, a third switch capacitor module, a fourth switch capacitor module, a first quantization output module, a second quantization output module, a first operational amplifier module and a second operational amplifier module, wherein the first switch capacitor module is electrically connected to the second switch capacitor module and the first operational amplifier module respectively, the second switch capacitor module is electrically connected to the first quantization output module and the second operational amplifier module respectively, the third switch capacitor module is electrically connected to the fourth switch capacitor module and the first operational amplifier module respectively, and the fourth switch capacitor module is electrically connected to the second quantization output module and the second operational amplifier module respectively; The first switch capacitor module is used to receive a first input signal, and output a first output signal to the second switch capacitor module according to the first input signal, and the first switch capacitor module is also used to output a first signal to the first operational amplifier module according to the first input signal; the second switch capacitor module is used to output a second signal to the second operational amplifier module according to the first superposition signal, and output a second output signal to the first quantization output module according to the first superposition signal, the first superposition signal is a signal obtained by superposition of the first output signal and the first operational amplifier signal; the first quantization output module is used to output a first target signal according to the second output signal and the second superposition signal, and the second superposition signal is a signal obtained by superposition of the second output signal and the second operational amplifier signal; The third switch capacitor module is used to receive a second input signal, and output a third output signal to the fourth switch capacitor module according to the second input signal, and the third switch capacitor module is also used to output a third signal to the first operational amplifier module according to the second input signal; the fourth switch capacitor module is used to output a fourth signal to the second operational amplifier module according to the third superposition signal, and output a fourth output signal to the second quantization output module according to the third superposition signal, and the third superposition signal is a signal obtained by superimposing the third output signal and the first operational amplifier signal; the second quantization output module is used to output a second target signal according to the fourth output signal and the fourth superposition signal, and the fourth superposition signal is a signal obtained by superimposing the fourth output signal and the second operational amplifier signal; The first operational amplifier module is used to output the first operational amplifier signal to the second switch capacitor module and the fourth switch capacitor module respectively according to the first signal and the third signal; the second operational amplifier module is used to output the second operational amplifier signal to the first quantization output module and the second quantization output module respectively according to the second signal and the fourth signal.

2. The modulation circuit according to claim 1, characterized in that: The first quantization output module is electrically connected to the first switch capacitor module and the second switch capacitor module respectively. The first switch capacitor module includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a first capacitor and a second capacitor. The first end of the first switch is grounded, the first end of the second switch is used to be electrically connected to a first power supply, the first end of the third switch is electrically connected to the second end of the first switch, the second end of the second switch and the first quantization output module respectively, the second end of the third switch is electrically connected to the second end of the fourth switch and the first end of the first capacitor respectively, the first end of the fourth switch is used to receive the first input signal, and the first end of the fifth switch is used to The first end of the sixth switch is electrically connected to the second end of the second capacitor, the second end of the sixth switch is electrically connected to the second switch capacitor module and the first operational amplifier module, the control end of the first switch is used to receive a first control signal, the control end of the second switch is used to receive a second control signal, the control end of the third switch is used to receive a second delay signal, the control end of the fourth switch is used to receive a first delay signal, the control end of the fifth switch is used to receive a first preset clock signal, and the control end of the sixth switch is used to receive a second preset clock signal.

3. The modulation circuit according to claim 2, characterized in that: The second switch capacitor module includes a seventh switch, an eighth switch, a ninth switch, a tenth switch, an eleventh switch, a twelfth switch, a third capacitor and a fourth capacitor. The first end of the seventh switch is grounded. The first end of the eighth switch is used to be electrically connected to the first power supply. The first end of the ninth switch is respectively electrically connected to the second end of the seventh switch, the second end of the eighth switch and the first quantization output module. The second end of the ninth switch is respectively electrically connected to the second end of the tenth switch and the first end of the third capacitor. The first end of the tenth switch is respectively electrically connected to the first switch capacitor module and the first operational amplifier module. The first end of the eleventh switch is used to be electrically connected to the second power supply. The second end of the switch is respectively electrically connected to the second end of the third capacitor, the first end of the fourth capacitor and the second operational amplifier module, the first end of the twelfth switch is electrically connected to the second end of the fourth capacitor, the second end of the twelfth switch is respectively electrically connected to the first quantization output module and the second operational amplifier module, the control end of the seventh switch is used to receive the third control signal, the control end of the eighth switch is used to receive the fourth control signal, the control end of the ninth switch is used to receive the first delay signal, the control end of the tenth switch is used to receive the second delay signal, the control end of the eleventh switch is used to receive the second preset clock signal, and the control end of the twelfth switch is used to receive the first preset clock signal.

4. The modulation circuit according to claim 1, characterized in that: The second quantization output module is electrically connected to the third switch capacitor module and the fourth switch capacitor module respectively, the third switch capacitor module includes a thirteenth switch, a fourteenth switch, a fifteenth switch, a sixteenth switch, a seventeenth switch, an eighteenth switch, a fifth capacitor and a sixth capacitor, the first end of the thirteenth switch is grounded, the first end of the fourteenth switch is used to be electrically connected to the first power supply, the first end of the fifteenth switch is electrically connected to the second end of the thirteenth switch, the second end of the fourteenth switch and the second quantization output module respectively, the second end of the fifteenth switch is electrically connected to the second end of the sixteenth switch and the first end of the fifth capacitor respectively, the first end of the sixteenth switch is used to receive the second input signal, and the first end of the seventeenth switch is used to receive the second input signal. The first end of the seventeenth switch is electrically connected to the second end of the fifth capacitor, the first end of the sixth capacitor and the first operational amplifier module, the first end of the eighteenth switch is electrically connected to the second end of the sixth capacitor, and the second end of the eighteenth switch is electrically connected to the fourth switch capacitor module and the first operational amplifier module, respectively. The control end of the thirteenth switch is used to receive the fifth control signal, the control end of the fourteenth switch is used to receive the sixth control signal, the control end of the fifteenth switch is used to receive the first delay signal, the control end of the sixteenth switch is used to receive the second delay signal, the control end of the seventeenth switch is used to receive the second preset clock signal, and the control end of the eighteenth switch is used to receive the first preset clock signal.

5. The modulation circuit according to claim 4, characterized in that: The fourth switch capacitor module includes a nineteenth switch, a twentieth switch, a twenty-first switch, a twenty-second switch, a twenty-third switch, a twenty-fourth switch, a seventh capacitor and an eighth capacitor. The first end of the nineteenth switch is grounded, the first end of the twenty-third switch is used to be electrically connected to the first power supply, the first end of the twenty-first switch is respectively electrically connected to the second end of the nineteenth switch, the second end of the twenty-third switch and the second quantization output module, the second end of the twenty-first switch is respectively electrically connected to the second end of the twenty-second switch and the first end of the seventh capacitor, the first end of the twenty-second switch is respectively electrically connected to the third switch capacitor module and the first operational amplifier module, the first end of the twenty-third switch is used to be electrically connected to the second power supply, and the The second end of the twenty-third switch is electrically connected to the second end of the seventh capacitor, the first end of the eighth capacitor and the second operational amplifier module respectively, the first end of the twenty-fourth switch is electrically connected to the second end of the eighth capacitor, the second end of the twenty-fourth switch is electrically connected to the second quantization output module and the second operational amplifier module respectively, the control end of the nineteenth switch is used to receive the seventh control signal, the control end of the twentieth switch is used to receive the eighth control signal, the control end of the twenty-first switch is used to receive the second delayed signal, the control end of the twenty-second switch is used to receive the first delayed signal, the control end of the twenty-third switch is used to receive the first preset clock signal, and the control end of the twenty-fourth switch is used to receive the second preset clock signal.

6. The modulation circuit according to claim 1, characterized in that: The first quantization output module includes a twenty-fifth switch, a first comparator and a first trigger, the first end of the twenty-fifth switch is electrically connected to the second switch capacitor module and the second op amp module respectively, the second end of the twenty-fifth switch is electrically connected to the first input end of the first comparator, the second input end of the first comparator is used to be electrically connected to a second power supply, the output end of the first comparator is electrically connected to the input end of the first trigger, the enable end of the first comparator is used to receive a second preset clock signal, the output end of the first trigger is used to output the first target signal, and the clock input end of the first trigger is used to receive a first preset clock signal.

7. The modulation circuit according to claim 1, characterized in that: The second quantization output module includes a twenty-sixth switch, a second comparator and a second trigger, the first end of the twenty-sixth switch is electrically connected to the fourth switch capacitor module and the second op amp module respectively, the second end of the twenty-sixth switch is electrically connected to the first input end of the second comparator, the second input end of the second comparator is used to be electrically connected to a second power supply, the output end of the second comparator is electrically connected to the input end of the second trigger, the enable end of the second comparator is used to receive a first preset clock signal, the output end of the second trigger is used to output the second target signal, and the clock input end of the second trigger is used to receive a second preset clock signal.

8. The modulation circuit according to claim 1, characterized in that: The first operational amplifier module includes a first switch tube, a second switch tube, a third switch tube, a fourth switch tube and a first operational amplifier. The gate of the first switch tube and the gate of the fourth switch tube are both used to receive a first preset clock signal. The source of the first switch tube is electrically connected to the first switch capacitor module, the drain of the first switch tube and the source of the second switch tube respectively. The gate of the second switch tube and the gate of the third switch tube are both used to receive a second preset clock signal. The drain of the second switch tube is electrically connected to the drain of the fourth switch tube and the first input end of the first operational amplifier respectively. The source of the third switch tube is electrically connected to the third switch capacitor module, the drain of the third switch tube and the source of the fourth switch tube respectively. The second input end of the first operational amplifier is used to be electrically connected to a second power supply. The output end of the first operational amplifier is electrically connected to the first switch capacitor module, the second switch capacitor module, the third switch capacitor module and the fourth switch capacitor module respectively.

9. The modulation circuit according to claim 1, characterized in that: The second operational amplifier module includes a fifth switch tube, a sixth switch tube, a seventh switch tube, an eighth switch tube and a second operational amplifier. The gate of the fifth switch tube and the gate of the eighth switch tube are both used to receive a second preset clock signal. The source of the fifth switch tube is electrically connected to the second switch capacitor module, the drain of the fifth switch tube and the source of the sixth switch tube respectively. The gate of the sixth switch tube and the gate of the seventh switch tube are both used to receive a first preset clock signal. The drain of the sixth switch tube is electrically connected to the drain of the eighth switch tube and the first input terminal of the second operational amplifier respectively. The source of the seventh switch tube is electrically connected to the fourth switch capacitor module, the drain of the seventh switch tube and the source of the eighth switch tube respectively. The second input terminal of the second operational amplifier is used to be electrically connected to a second power supply. The output terminal of the second operational amplifier is electrically connected to the second switch capacitor module, the fourth switch capacitor module, the first quantization output module and the second quantization output module respectively.

10. A modulator, characterized in that: The modulation circuit comprises the modulation circuit described in any one of claims 1 to 9.

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