A Communication Method and System between a Test Board and an Optical Module Based on the I3C Protocol

Abstract

A communication method and system between a test board and an optical module based on the I3C protocol, which relates to the field of communication technologies, includes that the test board receives an instruction sent by a host computer; configures the DMA channel of the test board and configures the I3C bus; if the instruction is a write instruction, the test board selects based on the transmit FIFO, adjusts the FIFO threshold according to the data volume size of the instruction, and sends a write command to the optical module through the I3C bus; if the optical module receives the write command, it works according to the command; if the instruction is a read instruction, the test board selects based on the receive FIFO, adjusts the FIFO threshold according to the data volume size of the instruction, and sends a read command to the optical module through the I3C bus; if the optical module receives the read command, it returns data to the test board according to the command; if the optical module receives a write command or a read command, or fails to receive or output correct data, the test board performs an error handling operation; it is used to solve the problems of low test efficiency of the optical module and poor stability of the I3C protocol in optical module testing.

Description

Technical Field

[0001] The present invention relates to the field of communication technologies, and particularly to a communication method and system between a test board and an optical module based on the I3C protocol. Background Art

[0002] As a key component in modern optical communication systems, the stability and reliability of the performance of optical modules are crucial for the operation of the entire system. Therefore, effective testing of optical modules has become one of the key steps to ensure system quality. Traditional optical module communication methods usually rely on the I2C (Inter-Integrated Circuit) communication protocol for the interaction of test data. However, with the growth of optical communication requirements and the development of technologies, the limitations of the I2C protocol in terms of bandwidth and power consumption have gradually emerged.

[0003] Firstly, in terms of bandwidth, the maximum communication rate of the I2C protocol is limited to Fast-Mode Plus (1Mbps). For application scenarios that require fast transmission of a large amount of data, such as firmware updates, when the host computer sends data and instructions to the optical module test board frame by frame via USB (Universal Serial Bus), and the optical module test board then performs firmware updates with the optical module based on the CDB (Command Data Block) format through I2C, the entire firmware will be divided into multiple data frames during the transmission process, forwarded to the test board via USB and then communicate with the module for updates, resulting in a long update time and low update efficiency, which obviously cannot meet the requirements. The low data exchange efficiency severely restricts the data processing speed during the testing process, leading to an extended testing time and low efficiency.

[0004] Secondly, from the perspective of power consumption, the relatively high power consumption of the I2C protocol has become a problem that cannot be ignored, especially in the case of large-scale device connections. This not only increases the operating cost of the system but also limits the expansion ability of the device. In addition, when traditional I2C controllers handle communication errors, they often require manual initialization to restore communication, which is a complex and time-consuming process and further reduces the testing efficiency.

[0005] In response to the above challenges, the I3C (Improved Inter-Integrated Circuit) protocol, as an emerging communication standard, provides a higher communication rate than I2C, supports up to 12.5Mbps SDR mode (Single Data Rate), and even 25Mbps HDR-DDR mode (High Data Rate-Double Data Rate), and has lower power consumption and stronger device expansion capabilities. Despite this, when the existing I3C controller attempts to communicate during the I3C interrupt period when the I3C target device turns off the I3C interrupt, the target device will not respond to the I3C controller, resulting in the communication process being blocked. The I3C controller needs to be reinitialized to resume normal communication, which also affects the stability and efficiency of the system.

[0006] The so-called "I3C target device turns off I3C interrupts" can be understood as after the I3C target device correctly completes the communication process (such as receiving commands and data) according to the I3C MIPI protocol, the I3C target device cannot send an interrupt signal to the MCU core, so the MCU core cannot know the completion status of these communication operations. Furthermore, since the MCU core cannot receive the interrupt signal, it cannot trigger the corresponding interrupt service routine (ISR) to execute subsequent control logic based on the MIPI protocol (such as reading the actual length of received and sent data, pre-filling the data sent by the I3C target device to the I3C controller, etc.); this will cause the I3C controller to fail to obtain the expected response.

[0007] Therefore, we propose a communication method and system between a test board and an optical module based on the I3C protocol. Summary of the invention

[0008] The object of the present invention is to provide a communication method and system between a test board and an optical module based on an I3C protocol, which is used to solve the problems of low efficiency in optical module testing and poor stability of the I3C protocol in optical module testing.

[0009] The present invention is achieved through the following technical solutions:

[0010] A communication method between a test board and an optical module based on an I3C protocol, comprising:

[0011] S1. The test board receives the command sent by the host computer;

[0012] S2. Configure the DMA (Direct Memory Access) channel of the test board and configure the I3C bus;

[0013] S3. If the instruction is a write instruction, the test board selects based on the transmitter FIFO (First In First Out, a data storage and buffering mechanism), adjusts the FIFO threshold according to the data volume of the instruction, and then sends a write command to the optical module via the I3C bus;

[0014] S4. If the optical module receives the write command, it works according to the command;

[0015] S5. If the instruction is a read instruction, the test board selects based on the receiver FIFO, adjusts the FIFO threshold according to the data volume of the instruction at the same time, and sends a read command to the optical module via the I3C bus;

[0016] S6. If the optical module receives the read command, it returns data to the test board according to the command;

[0017] S7. If the optical module does not receive the write command or the read command, or does not receive or output correct data, the test board performs error handling operations.

[0018] Further, the configuration steps of the DMA channel are specifically as follows:

[0019] S21 Configure the DMA channel of the transmitter on the I3C bus of the test board;

[0020] S211 Configure the transmitter DMA direction as memory to peripheral;

[0021] S212 Configure the transmitter DMA source address mode as auto-increment mode;

[0022] S213 Configure the transmitter DMA destination address mode as fixed mode;

[0023] S22 Configure the DMA channel of the receiver on the I3C bus of the test board;

[0024] S221 Configure the receiver DMA direction as peripheral to memory;

[0025] S222 Configure the receiver DMA source address mode as fixed mode;

[0026] S223 Configure the receiver DMA destination address mode as auto-increment mode;

[0027] S23 Configure the control end of the test board DMA channel;

[0028] S231 Configure the transmitter DMA direction as memory to peripheral;

[0029] S232 Configure the transmitter DMA source address mode as auto-increment mode;

[0030] S233 Configure the transmitter DMA destination address mode as fixed mode.

[0031] Further, the I3C bus supports dynamic bandwidth and rate adjustment functions.

[0032] Further, the configuration steps of the I3C bus are specifically as follows:

[0033] S24 configures the test board as an I3C controller;

[0034] S25 configures the I3C bus timing;

[0035] S251 sets the communication bandwidth in the I3C Push-pull mode;

[0036] S252 sets the communication bandwidth in the I3C Open-Drain mode;

[0037] S26 sets the high-impedance function of SDA (Serial Data Line).

[0038] Further, the steps for adjusting the FIFO threshold based on the transmitter FIFO are specifically as follows:

[0039] S31 The test board receives a write instruction sent by the host computer through USB;

[0040] S32 determines whether it is a small data volume write instruction for control or testing;

[0041] S321 If it is a small data volume write instruction, the test board sets the transmitter FIFO threshold to 1 byte and initiates a small data volume write transfer;

[0042] S3211 The hardware automatically determines whether there is at least one byte of empty slot in the transmitter FIFO. If so, it will initiate a DMA transfer of one byte from the source address to the transmitter FIFO;

[0043] S3212 determines whether the transfer is correct;

[0044] S32121 If it is correct, it determines whether the transfer is complete;

[0045] S321211 If the transfer is not complete, it returns to S3211;

[0046] S321212 If the transfer is complete, it continues to wait for the next instruction;

[0047] S32122 If it is incorrect, it performs the error handling operation of S7;

[0048] S322 If it is a large data volume write instruction for firmware update, the test board sets the transmitter FIFO threshold to 4 bytes and initiates a large data volume write instruction transfer;

[0049] The S3221 hardware automatically determines whether there are at least 4 - byte empty slots in the transmitting - end FIFO. If so, it initiates a DMA to transfer 4 bytes from the source address to the transmitting - end FIFO.

[0050] S3222 determines whether the transmission is correct.

[0051] S32221 If it is correct, it determines whether the transmission is complete.

[0052] S322211 If the transmission is not complete, it returns to S3221.

[0053] S322212 If the transmission is complete, it continues to wait for the next instruction.

[0054] S32222 If it is incorrect, it performs the error - handling operation of S7.

[0055] Furthermore, the write instruction further includes a bulk firmware update instruction.

[0056] Furthermore, the specific steps of the bulk firmware update instruction are as follows:

[0057] a. The test board receives the bulk firmware update instruction sent by the host computer through USB.

[0058] b. Check whether the firmware to be downloaded already exists in the MCU Flash (Microcontroller Unit Flash) of the test board.

[0059] b1. If it exists in the MCU Flash, then:

[0060] b11. Each time, read at most the firmware frames with the maximum byte length of the extended payload page of EPL (Extended Payload) in the CMIS protocol (Common Management Interface Specification) from the Flash.

[0061] b12. Based on the method that the threshold of the transmitting - end FIFO is 4 bytes, perform CDB firmware update.

[0062] b13. Repeat steps b11 and b12 based on the CDB protocol until the download is completed.

[0063] b2. If it does not exist in the MCU Flash, then:

[0064] b21. Prepare to receive the firmware sent by the host computer and store it in the MCU Flash.

[0065] b22. Continue to monitor subsequent batch download firmware instructions.

[0066] Further, the step of adjusting the FIFO threshold based on the receiving FIFO is specifically as follows:

[0067] S51 The test board receives the read instruction sent by the host computer through USB;

[0068] S52 Determine whether it is a small data volume read instruction;

[0069] S521 If it is a small data volume read instruction for control or testing, the test board sets the receiving FIFO threshold to 1 byte and initiates the transmission of the small data volume read instruction;

[0070] S5211 The hardware automatically determines whether there is at least one byte empty slot in the receiving FIFO. If so, it will initiate a DMA transfer of one byte from the receiving FIFO to the DMA destination address;

[0071] S5212 Determine whether the transmission is correct;

[0072] S52121 If it is correct, determine whether the transmission is complete;

[0073] S521211 If the transmission is not complete, return to S5211;

[0074] S521212 If the transmission is complete, continue to wait for the next instruction;

[0075] S52122 If it is incorrect, perform the error handling operation of S7;

[0076] S522 If it is a large data volume read instruction for firmware update, the test board sets the receiving FIFO threshold to 4 bytes and initiates the transmission of the large data volume read instruction;

[0077] S5221 The hardware will automatically determine whether there is at least 4 bytes empty slot in the receiving FIFO. If so, it will initiate a DMA transfer of 4 bytes from the receiving FIFO to the DMA destination address;

[0078] S5222 Determine whether the transmission is correct;

[0079] S52221 If it is correct, determine whether the transmission is complete;

[0080] S522211 If the transmission is not complete, return to S5221;

[0081] S522212 If the transmission is complete, continue to wait for the next instruction;

[0082] S52222 If it is incorrect, perform the error handling operation of S7.

[0083] Further, the steps of the error handling operation are specifically as follows:

[0084] Empty the I3C transmit FIFO, empty the I3C receive FIFO, empty the FIFO threshold adjustment, close the DMA control request, close the transmit DMA request, and close the receive DMA request in sequence, and re-initialize I3C.

[0085] Further, the I3C controller determines whether the trigger condition for the error handling operation occurs. If it occurs, the MCU of the test board automatically executes the error handling operation.

[0086] Further, when the test board sends a write command or a read command to the optical module through the I3C bus, I3C generates communication frames for random write, random read, and current read, and the optical module receives or outputs data according to the corresponding communication frame timing.

[0087] Further, the frame format of the random write is: start bit + optical module address + write flag + optical module acknowledgment bit + optical module register address + check bit + data 1 + check bit +...... data N + check bit + stop bit.

[0088] Further, the frame format of the random read is: start bit + optical module address + write flag + optical module acknowledgment bit + optical module register address + check bit + repeated start bit + optical module address + read flag bit + optical module acknowledgment bit + data 1 + end judgment bit +...... data N + end judgment bit + stop bit.

[0089] Further, the frame format of the current read is: start bit + optical module address + read flag bit + optical module acknowledgment bit + data 1 + end judgment bit +...... data N + end judgment bit + stop bit.

[0090] The technical solution of the present invention has at least the following advantages and beneficial effects:

[0091] The present invention discloses a communication method and system between a test board and an optical module based on the I3C protocol. By adopting the I3C protocol, the data communication rate between the test board and the optical module can be effectively improved, thereby solving the problem of low test efficiency of the optical module;

[0092] In addition, by distinguishing the transmit and receive FIFOs and adjusting the FIFO threshold according to the data volume, the stability of data transmission between the test board and the optical module can be improved. Description of the Drawings

[0093] Figure 1 It is a schematic flowchart of a method of the present invention;

[0094] Figure 2Schematic diagram of the batch firmware update instruction process of the present invention;

[0095] Figure 3 Schematic diagram of the read - write instruction process of the present invention;

[0096] Figure 4 Schematic diagram of the system structure of the present invention. Specific implementation mode

[0097] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Usually, the components of the embodiments of the present invention described and shown in the accompanying drawings here can be arranged and designed in various different configurations.

[0098] Embodiment 1

[0099] As Figure 1 shown, a communication method between a test board and an optical module based on the I3C protocol includes:

[0100] S1. The test board receives an instruction sent by the host computer;

[0101] S2. Configure the DMA channel of the test board and configure the I3C bus; among them, using the I3C protocol provides a higher rate compared with the traditional I2C protocol, and the I3C protocol can reach up to 12.5 Mbps in the SDR mode and up to 25 Mbps in the HDR - DDR mode, significantly improving the data transmission speed; and through the DMA technology, direct data transmission is realized without the intervention of the CPU (Central Processing Unit), reducing the burden on the CPU and enabling the system to process other tasks more efficiently;

[0102] When the test board sends data through the DMA technology, the data is transferred from the RAM (Random Access Memory) in the test board MCU to the I3C peripheral, and when receiving data, it is transferred from the I3C peripheral of the test board MCU to the RAM of the MCU and batch - parsed. And based on different test scenarios, different I3C peripheral FIFO threshold settings are used for transmission. When reading a small number of monitoring information of the DDM, that is, control or test instructions, a FIFO threshold of 1 byte is used for DMA transmission, and when performing a large - data - volume firmware update, a FIFO threshold of 4 bytes is used for DMA transmission;

[0103] It should be noted that the data transfer and control between the test board memory data and the I3C peripheral adopt the DMA method. Using DMA can improve the throughput and reduce the CPU load. Among them, the configuration control DMA channel has a high priority, the transmit DMA channel has a medium priority, and the receive DMA channel has a medium priority;

[0104] In addition, the I3C protocol supports dynamic bandwidth and rate adjustment. The test board can select different data transfer rates according to the test requirements and the communication capabilities of the test optical module to meet the needs of different test tasks; for low-speed test tasks, such as control instructions for collecting temperature data, etc., a lower communication rate can be adopted. For high-speed tasks, such as optical module firmware update, read instructions and write instructions such as IntL Deassert (Interrupt Low Deassert) status reporting, the rate can be increased to reduce latency.

[0105] The test board can obtain the communication capabilities of the optical module when allocating dynamic addresses to the optical module, including the maximum rate it supports, and dynamically configure the communication rate according to the requirements.

[0106] The configuration supports the SDR mode, and its rate ranges from 100 Kbps to 12.5 Mbps;

[0107] S3. If the instruction is a write instruction, the test board selects based on the transmitter FIFO. After adjusting the FIFO threshold according to the data volume of the instruction, it issues a write command to the optical module through the I3C bus;

[0108] S4. If the optical module receives the write command, it works according to the command;

[0109] S5. If the instruction is a read instruction, the test board selects based on the receiver FIFO. After adjusting the FIFO threshold according to the data volume of the instruction, it issues a read command to the optical module through the I3C bus;

[0110] S6. If the optical module receives the read command, it returns data to the test board according to the command; it should be noted that after the test board receives the returned data, it will transfer it back to the host computer;

[0111] S7. If the optical module does not receive the write command or the read command, or does not receive or output the correct data, the test board performs error handling operations.

[0112] In addition, dynamically adjusting the transmitter and receiver FIFO thresholds according to different data volume requirements improves the flexibility and performance of the system.

[0113] Embodiment 2

[0114] According to Embodiment 1, when the test board sends a write command or a read command to the optical module through the I3C bus, the I3C generates communication frames for random write, random read, and current read, and the optical module receives or outputs data according to the corresponding communication frame timing.

[0115] Among them, the communication frames for random write, random read, and current read are all designed based on the Management Memory map (management memory mapping mechanism) specified by the I3C protocol and the CMIS protocol.

[0116] And the frame format of random write is: start bit + optical module address + write flag + optical module acknowledgment bit + optical module register address + check bit + data 1 + check bit +...... data N + check bit + stop bit;

[0117] Among them, "data 1 + check bit + … data N + check bit + stop bit" is optional data. If this optional data is not sent, it means that the I3C controller on the test board only sends the optical module register address to the optical module through a private write operation, and then a private read operation of the I3C controller will be performed. If this optional data is sent, it means that data 1 to data N will be written sequentially starting from the optical module register address;

[0118] The frame format of random read is: start bit + optical module address + write flag + optical module acknowledgment bit + optical module register address + check bit + repeated start bit + optical module address + read flag bit + optical module acknowledgment bit + data 1 + end judgment bit +...... data N + end judgment bit + stop bit;

[0119] Random read includes the optical module register address sent by the private write operation. The private read operation with the repeated start bit as the start signal means that the I3C controller will sequentially read data 1 to data N from the optical module register address.

[0120] The frame format of current read is: start bit + optical module address + read flag bit + optical module acknowledgment bit + data 1 + end judgment bit +...... data N + end judgment bit + stop bit;

[0121] Current read starts with the start bit, and the timing is consistent with the second half of random read. It means that the I3C controller will read data 1 to data N at once from the current optical module register address;

[0122] Through the above three frame formats of "random write", "random read", and "current read", the test board realizes the read and write access to the Management Memory map of the optical module, and further realizes the test of the dynamic address mapping and management of the CMIS protocol.

[0123] It should be noted that taking the random read frame format as an example for illustration:

[0124] The meaning of the start bit (START) is as follows:

[0125] The start condition on the I3C bus, which is used to initiate a communication. Usually initiated by the master device, it indicates the start of a new transaction.

[0126] The meaning of the optical module address (Address) is as follows:

[0127] A 7-bit or dynamically allocated I3C device address, which is used to uniquely identify the location of the target slave device (optical module).

[0128] The meaning of the write bit (WriteBit) is as follows:

[0129] A value of 0 indicates that the master device will write data to the slave device (in this case, writing the register address).

[0130] The meaning of the optical module acknowledgment bit (ACK) is as follows:

[0131] The response bit of the slave device to the address and direction bits. Pulling it low indicates that the data has been successfully received and the device is ready for communication.

[0132] The meaning of the optical module register address (RegisterAddress) is as follows:

[0133] Specifies the register address to be read inside the slave device. This address will be used in subsequent reads.

[0134] The meaning of the parity bit (Paritybit) is as follows:

[0135] After the master device writes the optical module register address, an odd parity bit is appended for odd parity checking of this address byte, that is, it is required that the number of "1"s among all bits including the parity bit is odd. If the odd parity check fails, the slave device may not respond or return an error flag, thus ensuring the reliability of communication.

[0136] The meaning of the repeated start bit (RepeatedSTART) is as follows:

[0137] Restarts a frame of communication without sending STOP, which is used to switch from a write operation to a read operation.

[0138] The meaning of the optical module address (Address) is as follows:

[0139] Resends the target device address to prepare for the upcoming read operation.

[0140] The meaning of the read flag bit (ReadBit) is as follows:

[0141] A value of 1 indicates that the master device will read data from the slave device.

[0142] The meaning of the optical module response bit (ACK) is as follows:

[0143] The slave device re - confirms that it is ready to send data to the master device.

[0144] The meaning of Data1 is as follows:

[0145] The first - byte data read from the register, sent by the slave device.

[0146] The meaning of the end - judgment bit (Tbit) is as follows:

[0147] The response bit sent by the slave device, used to notify the master device whether the slave device continues to transmit data; and when Tbit = 1: continue to transmit data, and the transmission is ended by the stop signal; when Tbit = 0: it means that the slave device ends data transmission.

[0148] The meaning of DataN is as follows:

[0149] The last data byte.

[0150] The meaning of the stop bit (STOP) is as follows:

[0151] Indicates that the current communication is completed and the bus is released.

[0152] Embodiment 3

[0153] According to Embodiment 1, the configuration steps of the DMA channel are specifically as follows:

[0154] S21 Configure the DMA channel of the I3C bus transmitter on the test board;

[0155] S211 Configure the DMA direction of the transmitter as memory - to - peripheral;

[0156] S212 Configure the DMA source - address mode of the transmitter as the auto - increment mode;

[0157] S213 Configure the DMA destination - address mode of the transmitter as the fixed mode;

[0158] S22 Configure the DMA channel of the I3C bus receiver on the test board;

[0159] S221 Configure the DMA direction of the receiver as peripheral - to - memory;

[0160] S222 Configure the DMA source - address mode of the receiver as the fixed mode;

[0161] S223 Configure the DMA destination - address mode of the receiver as the auto - increment mode;

[0162] S23 Configure the control end of the test - board DMA channel;

[0163] S231 configures the DMA direction at the transmitting end to be from memory to peripheral;

[0164] S232 configures the DMA source address mode at the transmitting end to be the auto-increment mode;

[0165] S233 configures the DMA destination address mode at the transmitting end to be the fixed mode.

[0166] When sending data on the test board through DMA technology, the data is automatically transferred from the RAM (Random Access Memory) of the test board MCU to the I3C peripheral, and when receiving data, it is automatically transferred from the I3C peripheral of the test board MCU to the RAM of the MCU and batch-parsed, without the need for intermediate transfer by the CPU. When performing test tasks that require processing a large amount of data, such as firmware updates, the efficiency and performance of the system are greatly improved.

[0167] Example 4

[0168] According to Example 3, the configuration steps of the I3C bus are specifically as follows:

[0169] S24 configures the test board as an I3C controller;

[0170] S25 configures the I3C bus timing;

[0171] S251 sets the communication bandwidth in the I3C Pushpull mode;

[0172] S252 sets the communication bandwidth in the I3C OpenDrain mode;

[0173] S26 sets the SDA high-impedance function.

[0174] Among them, S251 and S252 are the dynamic bandwidth and rate adjustment functions of the I3C protocol. According to the requirements of the test task and the communication ability of the test optical module, different data transmission rates can be selected through these two steps to meet the requirements of different test tasks.

[0175] Example 5

[0176] According to Example 1 and Figure 3 , the steps for adjusting the FIFO threshold based on the transmitting end FIFO (TX-FIFO, Transmit First-In-First-Out) are specifically as follows:

[0177] S31 The test board receives the write instruction sent by the host computer through USB;

[0178] S32 determines whether it is a small data volume write instruction for control or testing;

[0179] If it is a small data volume write instruction, the test board sets the transmit FIFO threshold to 1 byte and initiates a small data volume write transfer;

[0180] S3211 The hardware automatically determines whether there is at least one byte of empty slot in the transmit FIFO. If so, it will initiate a DMA transfer of one byte from the source address to the transmit FIFO;

[0181] S3212 Determine whether the transfer is correct;

[0182] S32121 If it is correct, determine whether the transfer is complete;

[0183] S321211 If the transfer is not complete, return to S3211;

[0184] S321212 If the transfer is complete, continue to wait for the next instruction;

[0185] S32122 If it is incorrect, perform the error handling operation of S7;

[0186] S322 If it is a large data volume write instruction for firmware update, the test board sets the transmit FIFO threshold to 4 bytes and initiates a large data volume write instruction transfer;

[0187] S3221 The hardware will automatically determine whether there are at least 4 bytes of empty slots in the transmit FIFO. If so, it will initiate a DMA transfer of 4 bytes from the source address to the transmit FIFO;

[0188] S3222 Determine whether the transfer is correct;

[0189] S32221 If it is correct, determine whether the transfer is complete;

[0190] S322211 If the transfer is not complete, return to S3221;

[0191] S322212 If the transfer is complete, continue to wait for the next instruction;

[0192] S32222 If it is incorrect, perform the error handling operation of S7.

[0193] In addition, the steps for adjusting the FIFO threshold based on the receive FIFO (RX-FIFO, Receive First-In-First-Out buffer) are as follows:

[0194] S51 The test board receives the read instruction sent by the host computer through USB;

[0195] S52 Determine whether it is a small data volume read instruction;

[0196] If it is a small data volume read instruction for control or testing, the test board sets the receiver FIFO threshold to 1 byte and initiates the transmission of the small data volume read instruction;

[0197] S5211 The hardware automatically determines whether there is at least one byte of empty slot in the receiver FIFO. If so, it will initiate a DMA to transfer one byte from the receiver FIFO to the DMA destination address;

[0198] S5212 Determine whether the transmission is correct;

[0199] S52121 If it is correct, determine whether the transmission is complete;

[0200] S521211 If the transmission is not complete, return to S5211;

[0201] S521212 If the transmission is complete, continue to wait for the next instruction;

[0202] S52122 If it is incorrect, perform the error handling operation of S7;

[0203] S522 If it is a large data volume read instruction for firmware update, the test board sets the receiver FIFO threshold to 4 bytes and initiates the transmission of the large data volume read instruction;

[0204] S5221 The hardware will automatically determine whether there are at least 4 bytes of empty slots in the receiver FIFO. If so, it will initiate a DMA to transfer 4 bytes from the receiver FIFO to the DMA destination address;

[0205] S5222 Determine whether the transmission is correct;

[0206] S52221 If it is correct, determine whether the transmission is complete;

[0207] S522211 If the transmission is not complete, return to S5221;

[0208] S522212 If the transmission is complete, continue to wait for the next instruction;

[0209] S52222 If it is incorrect, perform the error handling operation of S7.

[0210] The application of the FIFO management mechanism provides an efficient and flexible data sending mechanism, which is particularly suitable for the I3C optical module test board that needs to execute various tasks and communicate frequently.

[0211] Example 6

[0212] According to Embodiment 5, the instructions include control instructions and test instructions. The control instructions are specifically instructions to start the optical module to perform work, and the test instructions include read instructions and write instructions. The read instructions and write instructions are respectively used to control the test board to read or write data to the optical module, and the write instructions also include a bulk firmware update instruction.

[0213] Among them, the control instructions sent by the test board to the optical module through the I3C protocol include, for example, adjusting the optical power or collecting test data, and then receiving the data fed back by the optical module in real time, such as temperature and optical power. The control instructions and some read instructions and write instructions are generally small data volume instructions, while the bulk firmware update instruction in the write instructions involves firmware upgrade, and the IntLDeassert status report in the read instructions involves a large amount of data reading, so they are large data volume instructions.

[0214] In addition, the bulk firmware update instruction is used to perform a bulk update on the optical module. The specific update process is as follows:

[0215] The host computer sends the optical module firmware to the test board through USB. The test board saves the optical module firmware in the Flash of the MCU, then extracts the optical module firmware from the Flash through the CDB mechanism in the CMIS protocol, and uses the DMA method to send it to the optical module through the I3C bus to complete the firmware update. When performing a bulk firmware update, this method can save the time for the host computer to transfer the firmware to the test board through USB, so as to save the time for bulk firmware update and improve production efficiency. Refer to Figure 2 , the specific steps are as follows:

[0216] a The test board receives the bulk download firmware instruction sent by the host computer through UB;

[0217] b Check whether the firmware to be downloaded already exists in the MCU Flash of the test board;

[0218] b1 If it exists in the MCU Flash, then:

[0219] b11 Each time, read at most the firmware frame with the maximum byte length of the EPL extended payload page based on the CMIS protocol from the Flash;

[0220] b12 Perform CDB firmware update based on the method with a transmit FIFO threshold of 4 bytes;

[0221] b13 Repeat steps b11 and b12 based on the CDB protocol until the download is complete;

[0222] b2 If it does not exist in the MCU Flash, then:

[0223] b21 Prepare to receive the firmware sent by the host computer and store it in the MCU Flash;

[0224] b22 continues to monitor subsequent bulk download firmware instructions.

[0225] Embodiment 7

[0226] According to any one of Embodiments 1-6, the steps of the error handling operation are specifically as follows:

[0227] Successively perform the closing of the I3C interrupt, the clearing of the I3C transmit FIFO, the clearing of the I3C receive FIFO, the clearing of the FIFO threshold adjustment, the closing of the DMA control end request, the closing of the transmit DMA request, and the closing of the receive DMA request, and re-initialize the I3C; in addition, the I3C controller determines whether the trigger condition for the error handling operation appears. If it appears, the MCU of the test board automatically executes the error handling operation, that is, when the I3C controller determines that a write command or a read command has not been received, or when correct data has not been received or output, the MCU of the test board automatically executes the specific error handling operation to solve the communication error. Compared with the traditional situation of manually re-initializing the I3C test board, the processing efficiency has been greatly improved; the I3C communication function of the test board is quickly and automatically restored after a communication error, the communication efficiency is improved, the system delay is reduced, and it is applicable to error recovery caused by, but not limited to, the I3C interrupt disabling scenario when the I3C optical module programs the Flash.

[0228] In addition, the scenarios where the I3C peripheral terminal is disabled are as follows: for example, when the I3C optical module executes the code writing task and needs to erase and program the Flash, the I3C optical module needs to disable some interrupts including the I3C peripheral interrupt; and when the I3C peripheral interrupt of the I3C optical module is disabled, the test board performs I3C communication with the optical module. At this time, the I3C optical module does not respond to the I3C controller, which in turn causes the test board I3C to enter an error interrupt.

[0229] Embodiment 8

[0230] According to any one of the above Embodiments 1-6, and Figure 4 , an I3C protocol-based optical module test system includes a host computer, an optical module test board, and multiple optical modules. The host computer is signal-connected to the test board through USB, and the test board is communicatively connected to the multiple optical modules through the I3C bus.

[0231] Among them, the optical module can also be called an I3C optical module, and the test board is the optical module test board, which can also be called the I3C optical module test board. It includes an MCU, a DSP (Digital Signal Processor), an electrical interface of the optical module, and a USB interface. The MCU serves as the control center of the test board and is responsible for overall coordination to ensure the efficient operation of the test board. It mainly has the following functions: 1. Receive instructions and data from the host computer through the USB transceiver; 2. Communicate with the I3C optical module through the I3C bus of the electrical interface; 3. Control the control pins related to the optical module in the electrical interface; 4. Manage test tasks.

[0232] The DSP has the functions of: 1. Receiving the electrical signals generated during the optical module test process, and performing signal processing and analysis; 2. Sending the electrical signals required for testing to the optical module.

[0233] The electrical interface of the optical module is the physical connection carrier between the test board and the optical module, including the following three types:

[0234] 1. Multiple low-speed signal control pins, such as Modsel (Module Select, module selection signal) (optional), LPMode (Low Power Mode, low power mode), IntL (Interrupt Low, interrupt signal), ResetL (ResetLow, reset signal), and ModPrsL (Module Present Low, module presence detection signal (low level valid)), to achieve functions such as module selection, power consumption control, status indication, reset control, and presence status indication;

[0235] 2. High-speed signal data pins, including differential signal pairs at the transmitting end of Tx1, Tx2...Txn (representing multiple independent transmission channels of the optical module), and differential signal pairs at the receiving end of Rx1, Rx2...Rxn (representing multiple independent receiving channels of the optical module);

[0236] 3. The SCL (Serial Clock Line, clock signal line) clock and SDA data signal line of the I3C bus are used for communication between the test board and the I3C optical module;

[0237] The USB interface is used to connect to the USB cable of the host computer.

[0238] Before the system starts running, it is also necessary to initialize each module, that is:

[0239] S01: Initialize the low-speed control pins of the electrical interface of the optical module;

[0240] S02: Initialize the USB and configure it into the HID+CDC mode (Human Interface Device + Communication Device Class, a combination of two modes of the USB interface).

[0241] S03: Initialize the Flash. This Flash serves as a temporary storage area during the bulk download of the optical module firmware, which will greatly improve the download speed.

[0242] S04: By default, initialize the I3C, initialize the I3C peripheral of the test board as an I3C controller, and configure it into the DMA communication mode.

[0243] S05: Initialize peripherals such as the ADC (Analog-to-Digital Converter) and DAC (Digital-to-Analog Converter), as well as chips such as the DSP and DC-DC (Direct Current - Direct Current Converter).

[0244] S06: Start the test task management, listen for the test instructions from the host computer and transfer data through the USB.

[0245] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A communication method between a test board and an optical module based on the I3C protocol, characterized in that: include: S1. The test board receives the command sent by the host computer; S2. Configure the DMA channel of the test board and configure the I3C bus; S3. If the instruction is a write instruction, the test board selects the FIFO based on the transmitting end, adjusts the FIFO threshold according to the data size of the instruction, and sends a write command to the optical module through the I3C bus; S4. If the optical module receives a write command, it works according to the command; S5. If the instruction is a read instruction, the test board selects the receiving end FIFO, adjusts the FIFO threshold according to the data size of the instruction, and sends a read command to the optical module through the I3C bus; S6. If the optical module receives the read command, it returns data to the test board according to the command; S7. If the optical module does not receive a write command or a read command, or does not receive or output correct data, the test board performs an error handling operation.

2. The communication method between the test board and the optical module based on the I3C protocol according to claim 1, characterized in that: The configuration steps of the DMA channel are as follows: S21 configures the DMA channel at the I3C bus initiator on the test board; S211 configures the DMA direction of the sending end to be from memory to peripherals; S212 configures the DMA source address mode of the sending end to be a self-increment mode; S213 configures the DMA destination address mode of the sending end to be a fixed mode; S22 configures the DMA channel of the I3C bus receiving end on the test board; S221 configures the receiving end DMA direction from peripheral to memory; S222 configures the receiving end DMA source address mode to a fixed mode; S223 configures the receiving end DMA destination address mode to be a self-increment mode; S23 configures the control end of the DMA channel of the test board; S231 configures the DMA direction of the sending end to be from memory to peripherals; S232 configures the source address mode of the DMA at the sending end to be the self-increment mode; S233 configures the DMA destination address mode of the transmitting end to be a fixed mode.

3. The communication method between the test board and the optical module based on the I3C protocol according to claim 2, characterized in that: The configuration steps of the I3C bus are as follows: S24 configures the test board as an I3C controller; S25 configures I3C bus timing; S251 sets the communication bandwidth in I3C Pushpull mode; S252 sets the communication bandwidth in I3C OpenDrain mode; S26 sets the SDA high impedance function.

4. The communication method between the test board and the optical module based on the I3C protocol according to claim 1, characterized in that: The I3C bus supports dynamic bandwidth and rate adjustment functions.

5. The communication method between the test board and the optical module based on the I3C protocol according to claim 1, characterized in that: The steps of adjusting the FIFO threshold based on the transmitting end FIFO and according to the data volume of the instruction are as follows: The S31 test board receives the write command sent by the host computer via USB; S32 determines whether it is a small data write instruction for control or testing; If S321 is a small data write instruction, the test board sets the sender FIFO threshold to 1 byte and initiates a small data write transmission; The S3211 hardware automatically determines whether there is at least one byte empty slot in the sender FIFO. If so, it will initiate DMA to transfer a byte from the source address to the sender FIFO; S3212 determines whether the transmission is correct; If S32121 is correct, determine whether the transmission is complete; If S321211 is not transferred, it returns to S3211; S321212 If the transmission is completed, continue to wait for the next instruction; If S32122 is incorrect, the error handling operation of S7 is performed; If S322 is a large data volume write instruction for firmware update, the test board sets the transmitting end FIFO threshold to 4 bytes and initiates the transmission of the large data volume write instruction; The S3221 hardware will automatically determine whether the sender FIFO has at least 4 bytes of empty slots. If so, it will initiate DMA to transfer 4 bytes from the source address to the sender FIFO; S3222 determines whether the transmission is correct; If S32221 is correct, determine whether the transmission is complete; If S322211 is not transferred, it returns to S3221; S322212 If the transmission is completed, continue to wait for the next instruction; If S32222 is incorrect, perform error handling operation of S7.

6. The communication method between the test board and the optical module based on the I3C protocol according to claim 5, characterized in that: The write instructions also include batch firmware update instructions.

7. The communication method between the test board and the optical module based on the I3C protocol according to claim 6, characterized in that: The specific steps of the batch firmware update instruction are: a. The test board receives the batch firmware update command sent by the host computer via USB; b. Check whether the firmware to be downloaded already exists in the MCU Flash of the test board; b1. If it exists in MCU Flash, then: b11. Each time, a firmware frame of at most the maximum byte length of the EPL extended load page in the CMIS protocol is read from the Flash; b12. CDB firmware update based on the sending FIFO threshold of 4 bytes; b13. Repeat steps b11 and b12 based on the CDB protocol until the download is complete; b2. If it does not exist in the MCU Flash, then: b21. Prepare to receive the firmware sent by the host computer and store it in the MCU Flash; b22. Continue to monitor the subsequent batch firmware download instructions.

8. The communication method between the test board and the optical module based on the I3C protocol according to claim 1, characterized in that: The steps of adjusting the FIFO threshold based on the receiving end FIFO and according to the data volume of the instruction are as follows: The S51 test board receives the read command sent by the host computer via USB; S52 determines whether it is a small data read instruction; If S521 is a small data read instruction for control or test, the test board sets the receiving end FIFO threshold to 1 byte and initiates the transmission of the small data read instruction; The S5211 hardware automatically determines whether there is at least one byte empty slot in the receiving FIFO. If so, it will initiate DMA to transfer a byte from the receiving FIFO to the DMA destination address; S5212 determines whether the transmission is correct; If S52121 is correct, determine whether the transmission is completed; If S521211 is not transferred, then return to S5211; S521212 If the transmission is completed, continue to wait for the next instruction; If S52122 is incorrect, the error handling operation of S7 is performed; If it is a large data volume read instruction for firmware update, the test board sets the receiving end FIFO threshold to 4 bytes and initiates the transmission of the large data volume read instruction; The S5221 hardware will automatically determine whether the receiving FIFO has at least 4 bytes of empty slots. If so, it will initiate DMA to transfer 4 bytes from the receiving FIFO to the DMA destination address; S5222 determines whether the transmission is correct; If S52221 is correct, determine whether the transmission is completed; If S522211 is not transferred, return to S5221; S522212 If the transmission is completed, continue to wait for the next instruction; If S52222 is incorrect, perform error handling operation of S7.

9. The communication method between the test board and the optical module based on the I3C protocol according to any one of claims 1 to 8, characterized in that: The steps of the error handling operation are specifically: Clear the I3C sender FIFO, clear the I3C receiver FIFO, clear the FIFO threshold adjustment, turn off the DMA control end request, turn off the sender DMA request and turn off the receiver DMA request in sequence, and reinitialize I3C.

10. The communication method between the test board and the optical module based on the I3C protocol according to claim 9, characterized in that: The I3C controller determines whether a trigger condition for an error handling operation occurs. If so, the MCU of the test board automatically performs the error handling operation.

11. The communication method between the test board and the optical module based on the I3C protocol according to claim 1, characterized in that: When the test board sends a write command or a read command to the optical module through the I3C bus, the I3C generates random write, random read, and current read communication frames, and the optical module receives or outputs data according to the corresponding communication frame timing.

12. The communication method between the test board and the optical module based on the I3C protocol according to claim 11, characterized in that: The frame format of the random write is: start bit+optical module address+write flag+optical module response bit+optical module register address+check bit+data 1+check bit+...data N+check bit+stop bit.

13. The communication method between the test board and the optical module based on the I3C protocol according to claim 11, characterized in that: The frame format of the random read is: start bit + optical module address + write flag + optical module response bit + optical module register address + check bit + repeat start bit + optical module address + read flag bit + optical module response bit + data 1 + end judgment bit + ... data N + end judgment bit + stop bit.

14. The communication method between the test board and the optical module based on the I3C protocol according to claim 11, characterized in that: The currently read frame format is: start bit+optical module address+read flag bit+optical module response bit+data 1+end judgment bit+...data N+end judgment bit+stop bit.

15. A communication system between a test board and an optical module based on an I3C protocol, implementing the communication method between a test board and an optical module based on an I3C protocol as claimed in claim 1, characterized in that: The system comprises a host computer, a test board and a plurality of optical modules. The host computer is connected to the test board signal via a USB, and the test board is connected to the plurality of optical modules via an I3C bus.

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