High-speed imaging device based on T20F324I4

Abstract

The invention discloses a high-speed imaging device based on T20F324I4, and belongs to the technical field of communication. The imaging device comprises an image data acquisition and processing circuit; the device is composed of a focal panel, a signal board and an interface board. The interface board supplies power to the signal board and the focal panel and provides internal and external interface circuits. The interface circuit comprises three LVDS circuits, one RS422 circuit and two CAN circuits. The signal board is used for processing image data and consists of a domestic FPGA (Field Programmable Gate Array) chip T20F324I4 minimum system; the focal panel is used for acquiring image data in different states and is composed of an IMX334 module; the invention provides a novel high-speed imaging device based on T20F324I4, and the processing efficiency, the stability and the real-time performance of image data are effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of communication technologies, and particularly to a high-speed imaging device based on T20F324I4. Background Art

[0002] With the rapid development of space technologies, the functions of on-board devices have become increasingly complex, and the data transmission requirements have increased significantly. However, due to limited satellite resources, traditional data transmission methods have gradually revealed bottlenecks in terms of timeliness and bus utilization. Especially in the case of concurrent execution of multiple tasks, how to ensure that the data between on-board devices can be transmitted efficiently and in a timely manner, while maximizing the use of limited bus bandwidth, has become a key issue restricting the performance improvement of satellite systems. Therefore, an innovative technical solution is needed to optimize the bus resource allocation while meeting the real-time requirements, so as to adapt to the needs of modern satellites for high-efficiency data processing and transmission. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to ensure the timeliness of data transmission between on-board devices and improve the bus utilization rate between on-board devices.

[0004] To solve the above technical problem, the present invention provides a principle and solution for a high-speed imaging device based on T20F324I4. The device consists of a focal plane board, a signal board, and an interface board. The signal board configures the registers of the IMX334 focal plane sensor through the I2C protocol. The interface board supplies power to each module of the system and provides a communication interface for the data acquisition and processing circuit. After the whole machine is powered on, two CAN interface circuits are used to send and receive instructions, and one RS422 circuit is used to receive the second pulse signal. When the device operates in the low-speed mode, the device will identify the object, and the IMX334 lens module will transmit the corresponding image data to the T20F324I4 data processing module through the low-speed mode of the MIPI interface; after the device switches to the high-speed state, it will monitor the state of the identified object in real time. The IMX334 module will send the corresponding image data to the data processing circuit for storage and processing through the high-speed mode of the MIPI interface. At the same time, the device will transmit the processed image data to the satellite communication system through the LVDS interface, so that the system can monitor the object state in real time.

[0005] The present invention mainly realizes high-speed acquisition and processing of high-resolution images, and is composed of a data acquisition circuit, a data processing circuit, a power distribution unit circuit and an interface circuit. The interface board supplies power to the signal board and the focal plane board and realizes the internal and external interface circuits. The interface circuit includes three-way LVDS circuits, one-way RS422 circuit, two-way CAN circuits and a power distribution circuit. The data processing circuit uses the domestic FPGA chip T20F324I4 as the core processor to realize high-speed data processing, instruction parsing, etc. The focal plane board is an image acquisition circuit, which is composed of one-way IMX334 module to realize the image acquisition of the device. The signal board selects one DDR3 and one NOR FLASH as the storage circuit.

[0006] The interface board of the present invention is composed of two parts: a power distribution circuit and an interface circuit. According to the requirements of relevant circuit technical indicators, the present invention selects DS90LV031AT, DS26LV32AT, SJA1000T and PCA82C250T as the main devices for the LVDS interface, RS422 interface and CAN instruction interface, and selects AO3401A as the power distribution switch for each module.

[0007] The system block diagram of the power distribution unit of the present invention is as Figure 3 shown. The external connector accesses the +12V primary power, and directly inputs the +12V into the signal board after passing through the soft start circuit. After the signal board is powered on and works, it will control the power-on of the interface board and the IMX334 focal plane module respectively according to the timing. Among them, the power supply voltages of the IMX334 focal plane module are +3.3V, +2.9V, +1.8V, +1.2V, and the power distribution unit bottom board is +12V, +5V and +3.3V.

[0008] On the interface bottom board of the present invention, LVDS interfaces, RS422 interfaces and CAN instruction interfaces are designed. Among them, the LVDS interface is used for the device to transmit image data outward, the RS422 interface is used to receive the second pulse signal, and the CAN interface is used to send and receive instructions.

[0009] The present invention uses the LVDS interface to send image data to the system. There are three-way LVDS interfaces in total, namely data signal, clock signal and gating signal, and transmits image data to the satellite communication system through the formulated protocol.

[0010] The second pulse module of the present invention is used to provide a unified time reference for multiple cameras on the bus to ensure that they trigger the acquisition or record data at strictly synchronized time points.

[0011] For the power control module of the present invention, the power supply for the whole machine is connected through the external connector of the interface board. After receiving the +12V power supply from the interface board, the signal board obtains each power rail and the power-on sequence through the power management chips TPS82130, NCP59744, and LP5912-1.8. The focal plane panel obtains the +5V voltage through the inter-board connector with the signal board, and then independently obtains each power rail and the power-on sequence through the power management chip respectively but does not power on immediately. After the signal board works normally, T20F324I4 controls the power-on of the focal plane panel and the interface board respectively.

[0012] The image data processing circuit of the present invention is composed of the T20F324I4 chip. According to the technical index requirements of the high-speed image processing circuit, the present invention selects T20F324I4, IS43TR81024BL-125KBLI, and MT25QU512ABB8ESF as the devices of CPU, DDR3, and NOR FLASH, and selects chips such as TPS82130, NCP59744, LP5912-1.8, and TPS51200DRCR as the power management chips to supply power to the signal processing circuit; this circuit realizes functions such as high-speed reception, data framing, data forwarding, and instruction parsing.

[0013] The focal plane module of the present invention uses the IMX334 focal plane sensor to collect images. IMX334 transmits data with the signal board through the MIPI protocol and the I2C protocol, including a 4-lane data channel, a 1-lane clock channel, and a group of SCL and SDA sensor control signals; the IMX334 module is powered by +5V from the signal board, and then two TPS79301 chips, one TPS82130 chip, and one TPS79501 chip supply 3.3V, 2.9V, 1.8V, and 1.2V direct current to the IMX334 focal plane sensor respectively. The IMX334 sensor has strict power-on sequence requirements. When powering on, 5V is converted to 3.3V by TPS82130 and powered on first, and then 1.2V, 1.8V, and 2.9V are powered on by TPS79501 and two TPS79301 chips in sequence. The power-on sequence is realized by the RC delay circuit acting on the EN pin of the chip. The switching circuit composed of the S8050 triode and the AO3401A PMOS tube controls the power-on and power-off of the focal plane panel, and the switching circuit is controlled by the IO of T20F324I4. IMX334 also supports the standby mode. By writing "1" into the standby control register, the standby mode is entered to reduce power consumption. After power-on or other system reset operations, the standby mode will also be established.

[0014] The interface circuit in the interface board of the present invention consists of three LVDS circuits, one RS422 circuit, and two CAN circuits. DS90LV031AT is selected as the driving chip for LVDS, which can convert single-ended signals into differential signals in the LVDS interface standard. There are three LVDS signals in the present invention, including a gating signal, a clock signal, and a data signal. DS26LV32AT is selected as the RS422 interface receiving chip for the RS422 circuit to receive the second pulse signal. Since the IO level of the selected T20F324I4BANK for the CAN circuit is 3.3V, it is necessary to first perform level conversion to convert the IO level to 5V. The selected level conversion chip model is SN74ALVC164245DGGR. The CAN controller model is selected as SJA1000T, and the CAN transceiver model is selected as PCA82C250T. The power supply of the interface board is +12V through the power supply of the external connector, and then converted to 5V and 3.3V by two TPS82130s to supply power to the interface chips. A switching circuit composed of a triode and a MOS tube is also equipped and its power-on and power-off are controlled by the IO of T20F324I4. Description of the Drawings

[0015] Figure 1 Shown is the system block diagram of the high-speed imaging device; Figure 2 Shown is the relationship between the system structure and communication interface of the high-speed imaging device; Figure 3 Shown is the power tree of the high-speed imaging device system; Detailed Implementation Manner The present invention will be further described below in conjunction with the drawings, but it is not a limitation to the present invention: As Figure 1 Shown, according to the design function requirements and design index requirements, the target state monitoring circuit consists of three parts: the power supply and distribution interface board, the data acquisition board, and the data processing board. Among them, the power supply and distribution interface board realizes the internal and external interface circuits. The interface circuit includes three LVDS circuits, one RS422 circuit, two CAN circuits, and a power distribution circuit; the data processing board selects T20F324I4 as the core controller to realize high-speed data transceiver, data processing, instruction parsing, etc.; the data acquisition board selects IMX334 as the focal plane sensor, which can realize high-speed high-resolution image acquisition.

[0016] As Figure 2 、 Figure 3The external connector shown is connected to a +12V voltage and powered on through a soft-start circuit controlled by AO3401A and S8050 on the interface board. After the 12V power is applied, 12V power is supplied to the signal board through the connector. The interface board supplies power to corresponding interface chips such as LVDS, RS422, and CAN through the TPS82130 power chip. The signal board supplies power to T20F324I4 through power management chips such as TPS82130, LP5912-1.8, and NCP59744. The power-on sequence is achieved by adding an RC delay circuit to the EN pin of the power chip. Since the IMX334 sensor on the focus panel has a regulated power-on sequence, an RC delay circuit also needs to be added to the enable terminal of the power management chip, and it is necessary to wait for the signal board to work and then use the IO to control the power-on of the interface board and the focus panel.

[0017] Among them, the power supply voltage of the data acquisition and processing module is +12V 1.5A; the power supply voltages of the IMX334 lens module are +3.3V, +2.9V, +1.8V, and +1.2V; the bottom plate of the power distribution unit is +12V, +5V, and +3.3V.

[0018] As Figure 1 shown, the data acquisition and processing circuit realizes the remote control and telemetry of the IMX334 lens module. The bottom plate of the power distribution unit supplies power to each module of the system and sends instructions and provides data interfaces to the data acquisition and processing circuit.

[0019] Specifically, after the whole machine is powered on, when the system works in the low-speed state, the device transmits the data of the IMX334 lens module to the T20F324I4 processor module through the low-speed mode of the MIPI interface for target recognition. When switched to the high-speed state to monitor the target state, IMX334 sends the image data of the target state to the T20F324I4 processor through the high-speed mode of the MIPI interface and stores the data. At the same time, the storage module forwards the processed image data to the satellite communication system through the LVDS interface.

[0020] The device receives CAN remote control instructions from the host and comprehensively controls the IMX334 focus module and the T20F324I4 board. Through the CAN instruction interface, instructions such as changing the exposure time, exposure mode, and setting the resolution are sent to the IMX334 focus component.

[0021] Specifically, the satellite communication system issues instructions such as changing the exposure time, exposure mode, and setting the resolution to the IMX334 focal plane module through the CAN instruction interface. The IMX334 focal plane module transmits RAW format image data to the T20F324I4 through the MIPI interface. The T20F324I4 compresses the RAW format data transmitted by the focal plane sensor into the JPEG format and then downloads it to the image acquisition card in the system through the LVDS interface. The decoder inside the acquisition card converts the compressed JPEG format into the RGB format and then transmits it to the host computer through Gigabit Ethernet for real-time image display.

[0022] The above are only the preferred implementation embodiments of the present invention, and do not limit the scope of implementation of the present invention. Any equivalent structure or equivalent process transformation made using the content of the specification and drawings of the present invention, or directly or indirectly applied in other related technical fields, shall similarly be included in the patent protection scope of the present invention.

Claims

1. A high-speed imaging device based on T20F324I4, characterized in that: It includes the following components: The interface circuit and the power distribution unit circuit provide power to the signal board and the focus panel and realize the internal and external interface circuits. The interface circuit includes three LVDS circuits, one RS422 circuit, two CAN circuits and a power distribution circuit; The image data processing circuit is implemented by the minimum system of the domestically produced FPGA chip T20F324I4; The image acquisition circuit is implemented by an IMX334 module, which collects image data in low-speed and high-speed states.

2. The high-speed imaging device based on T20F324I4 according to claim 1, characterized in that: The image data processing circuit uses T20F324I4, IS43TR81024BL-125KBLI, MT25QU512ABB8ESF as CPU, DDR3 and NORFLASH devices, and uses TPS82130, NCP59744, LP5912-1.8, TPS51200DRCR and other chips as power management chips to power the signal processing circuit; this circuit realizes high-speed transmission and reception, data framing, data forwarding and instruction parsing.

3. The high-speed imaging device based on T20F324I4 according to claim 1, characterized in that: The focus panel and the signal board use the MIPI CSI-2 protocol to transmit image data. CSI defines a high-speed serial interface between the CPU and the camera module, and has a high frequency and a data rate of up to 1.5 Gbps / lane. This reduces the complexity of the design and increases the design flexibility, thereby achieving efficient transmission, reception and response of image signals.

4. The high-speed imaging device based on T20F324I4 according to claim 1, characterized in that: The LVDS circuit uses low voltage difference differential signal transmission to transmit the image data processed by T20F324I4 to the satellite communication system.

5. The high-speed imaging device based on T20F324I4 according to claim 1, characterized in that: The RS422 circuit adopts differential signal transmission, can realize long-distance communication, and is used for receiving second pulse signals.

6. According to the high-speed imaging device based on T20F324I4 as described in claim 1, the two CAN bus circuits are command transceiver modules. The CAN bus is a multi-master serial communication bus. The basic design specifications require high bit rate, high anti-electromagnetic interference, and the ability to detect any errors that occur.

7. According to the high-speed imaging device based on T20F324I4 as claimed in claim 1, the power distribution circuit is used to supply power to each module of the device and to power on and off according to the power-on timing requirements of the device.

8. According to the high-speed imaging device based on T20F324I4 of claim 1, an RC delay circuit is added to the enable end of some power chips to configure the power-on timing; the interface board supplies power to the signal board and the focus panel; the signal board and the focus panel are independently configured with a power-on timing, and after the T20F324I4 of the signal board is powered on, the focal plane module IMX334 and the interface circuit are powered on through the IO pin, and the whole machine is powered normally at this time.

9. The high-speed imaging device based on T20F324I4 according to claim 1, characterized in that: The focus panel uses the IMX334 lens module to capture images at low speed and high speed; different states are controlled by commands sent by the communication system.

Images