Flash memory device and preparation method thereof
By performing multi-step decomposition and real-time online monitoring of the trench isolation thickness in the cleaning process of NORD flash memory devices, the leakage problem caused by wet etching is solved, and the insulation characteristics and reliability of the device are improved.
Patent Information
- Application Number
- CN202510238131.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-28
- Publication Date
- 2025-06-03
AI Technical Summary
During the wet etching process of NORD flash memory devices, the wet pre-cleaning process of the gate oxide layer before the gate oxide layer causes the trench isolation to be wet sideways, resulting in the distance between the control gate layer and the word line, causing leakage problems.
Before forming the gate oxide layer, the cleaning process is decomposed into multiple steps, and the thickness of the trench isolation is monitored online in real time, and the cleaning process parameters are dynamically adjusted to avoid side digging problems caused by wet cleaning.
It effectively avoids trench isolation being wet-sided, increases the distance between the word line and the control gate layer, improves the insulation characteristics, and improves the reliability and performance of flash memory devices.
Smart Images
Figure CN120091562A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and particularly to a flash memory device and a method for manufacturing the same. Background Art
[0002] As a non-volatile memory device, a flash memory device controls the switching of a gate channel by changing the critical voltage of a transistor or a memory cell, thereby achieving the purpose of storing data so that the data stored in the memory will not be lost due to a power interruption.
[0003] For NORD flash memory devices, the trench isolation (such as a shallow trench isolation structure, STI) used to isolate different active region stripes has a faster etching rate of the insulating material (such as oxide) contained therein during the wet etching process after the ion implantation and etching processes of the NORD flash memory device. Therefore, the wet pre-cleaning process before forming the gate oxide layer is bound to cause the problem that the trench isolation is wet-etched laterally and the control gate layer and the word line located on the trench isolation are too close to each other, resulting in leakage. Summary of the Invention
[0004] The purpose of the present invention is to provide a flash memory device and a method for manufacturing the same, so as to avoid the problem that the control gate layer and the word line are too close to each other and leakage occurs due to the wet lateral etching of the trench isolation by decomposing the cleaning process before forming the gate oxide layer into multiple steps and combining with real-time on-line monitoring of the thickness of the trench isolation.
[0005] In a first aspect, to solve the above technical problems, the present invention provides a method for manufacturing a flash memory device, which at least includes the following steps:
[0006] Provide a substrate;
[0007] Form a floating gate layer on the substrate;
[0008] Form a plurality of trench isolations in the floating gate layer and a part of the substrate, and define active regions adjacent to the trench isolations in the substrate, and the top surface of the trench isolation is flush with the top surface of the floating gate layer;
[0009] Form an interlayer dielectric layer, a control gate layer and a sidewall stacked in sequence on the floating gate layer and the trench isolation, and an opening exposing a part of the substrate or a part of the trench isolation is formed in the sidewall;
[0010] Perform a heat treatment on the substrate to change the density of the trench isolation exposed at the opening;
[0011] Perform a first cleaning process on the substrate to remove part of the residues on the active regions;
[0012] Measure the thickness of the trench isolation exposed at the opening, and perform a second cleaning process on the substrate.
[0013] Optionally, the method for manufacturing the flash memory device may further include:
[0014] Form a gate oxide layer on the inner surface of the opening;
[0015] Form a word line on the gate oxide layer, and the word line fills the opening.
[0016] Optionally, the heat treatment may include an annealing process.
[0017] Optionally, the step of performing heat treatment on the substrate may include:
[0018] Introduce oxygen into the reaction chamber carrying the substrate, and heat the temperature of the reaction chamber to a preset temperature.
[0019] Optionally, the preset temperature range may be: 900° - 1100°, and the duration may be: 28s - 35s.
[0020] Optionally, the duration of the first cleaning process may be less than the duration of the second cleaning process.
[0021] Optionally, the first cleaning process and the second cleaning process may include a wet etching process.
[0022] Optionally, before forming the floating gate layer on the substrate, the manufacturing method may further include:
[0023] Form a coupling oxide layer on the substrate.
[0024] Optionally, the flash memory device may include a plurality of memory cells, and the memory cells may be a dual - storage - bit structure sharing a word line.
[0025] In a second aspect, based on the same inventive concept, the present invention also provides a flash memory device, which can be specifically manufactured by using the method for manufacturing the flash memory device as described above.
[0026] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:
[0027] The present invention provides a method for manufacturing a flash memory device, comprising: providing a substrate, forming a floating gate layer on the substrate, forming a plurality of trench isolations in the floating gate layer and a part of the substrate, and defining an active region adjacent to the trench isolations in the substrate, wherein the top surface of the trench isolations is flush with the top surface of the floating gate layer, forming an interlayer dielectric layer, a control gate layer and a sidewall stacked in sequence on the floating gate layer and the trench isolations, an opening is formed in the sidewall to expose a part of the substrate or a part of the trench isolations at the bottom, performing a heat treatment on the substrate to change the density of the trench isolations exposed at the opening, performing a first cleaning process on the substrate to remove a part of the residues on the active region, measuring the thickness of the trench isolations exposed at the opening, and performing a second cleaning process on the substrate.
[0028] In the present invention, on the one hand, before forming the gate oxide layer, a heat treatment is first performed on the substrate formed with trench isolations, so as to utilize the characteristic that the density of the insulating material (such as oxide) in the trench isolations can be changed during the heat treatment process, avoid side etching of the trench isolations during subsequent wet cleaning (the first cleaning process and the second cleaning process), and increase the distance between the word line and the control gate layer on the trench isolations, improving the problem of leakage due to the too-close distance between the control gate layer and the word line, that is, ensuring the insulating characteristics of the trench isolations.
[0029] On the other hand, before forming the gate oxide layer, the pre-cleaning process of the substrate is decomposed into two steps and combined with real-time online monitoring of the thickness of the trench isolations, so as to dynamically adjust process parameters such as the duration of the two cleaning processes by using the actual thickness of the trench isolations monitored in real time, avoid side etching of the trench isolations caused by the wet cleaning process, and remove the residues (such as excess oxides) on the active region at the same time, that is, improving the reliability and performance of the NORD flash memory device. Description of the Drawings
[0030] Figure 1 It is a SEM diagram of a part of the structure on the active region of the NORD flash memory device in the prior art.
[0031] Figure 2 It is a SEM diagram of a part of the structure on the trench isolations of the NORD flash memory device in the prior art.
[0032] Figure 3 It is a schematic flow diagram of the method for manufacturing a flash memory device in an embodiment of the present invention.
[0033] Figure 4 It is a partial top view of a part of the flash memory device in an embodiment of the present invention.
[0034] Figure 5 For Figure 4Partial schematic view of the flash memory device shown along the AA tangent.
[0035] Figure 6 is Figure 4 Partial schematic view of the flash memory device shown along the BB tangent.
[0036] Figure 7 is the Figure 3 Partial schematic view of the flash memory device along the AA tangent after forming sidewalls by the manufacturing method of the flash memory device shown.
[0037] Figure 8 is the Figure 3 Partial schematic view of the flash memory device along the BB tangent after forming sidewalls by the manufacturing method of the flash memory device shown.
[0038] Figure 9 is the Figure 3 Partial schematic view of the flash memory device along the AA tangent after forming word lines by the manufacturing method of the flash memory device shown.
[0039] Figure 10 is the Figure 3 Partial schematic view of the flash memory device along the BB tangent after forming word lines by the manufacturing method of the flash memory device shown.
[0040] Among them, in Figures 1 to 10 :
[0041] 100 - Substrate; AR - Active region; 110 - Coupling oxide layer; 120 - Floating gate layer; 130 - Trench isolation; 140 - Interlayer dielectric layer; 150 - Control gate layer; 160 - Hard mask layer; 170 - Sidewall; 171 - First sidewall; 172 - Second sidewall; 173 - Third sidewall; 101 - Opening; 180 - Gate oxide layer; 190 - Word line. Detailed implementation manners
[0042] In order to make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further elaborated in detail below in conjunction with the drawings and embodiments. Although the exemplary implementation methods of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the implementation manners described herein. On the contrary, these implementation manners are provided to enable a more thorough understanding of the present invention and to be able to convey the scope of the present invention completely to those skilled in the art.
[0043] The present invention will be described more specifically by way of example with reference to the accompanying drawings in the following paragraphs. The advantages and features of the present invention will become clearer based on the following description and the claims. It should be noted that the accompanying drawings are all in very simplified forms and use non-precise scales, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It can be understood that the meanings of "on...", "above...", and "overhead..." in the present invention should be interpreted in the broadest way, so that "on..." not only means "on" something "without any intermediate features or layers (i.e., directly on something)", but also includes the meaning of having intermediate features or layers "on" something.
[0044] In addition, for the sake of convenience of description, spatial relative terms such as "on...", "above...", "overhead...", "upper", "upper part", etc. may be used herein to describe the relationship between an element or feature shown in the figure and another element or feature. Except for the orientation depicted in the accompanying drawings, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein can be interpreted accordingly.
[0045] In the embodiments of the present invention, terms such as "first", "second", etc. are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be noted that the technical solutions described in the embodiments of the present invention can be combined arbitrarily without conflict.
[0046] It should be noted that as long as the method for preparing the flash memory device provided in the embodiments of the present invention is a preparation process for preparing a dual-bit flash memory device with a shared word line, under this setting, the following will take the structure of the flash memory device with a shared word line in the accompanying drawings as an example to draw the accompanying drawings and explain the process of the preparation method.
[0047] Please refer to Figure 1 and Figure 2 , in which Figure 1 what is shown is a SEM image of a partial structure on the active region of a NORD flash memory device in the prior art, Figure 2 what is shown is a SEM image of a partial structure on the trench isolation of a NORD flash memory device in the prior art.
[0048] As Figure 1 and Figure 2 shown, in the prior art, during the process of directly treating the NORD flash memory device using a wet cleaning process before forming the gate oxide layer, the trench isolation will be wet-etched on the side, which in turn leads to the problem that the control gate layer and the word line located on the trench isolation are too close and leakage occurs, as Figure 2 indicated by the area circled by the white solid line.
[0049] In view of the above problems, in an embodiment of the present invention, a flash memory device and a method for manufacturing the same are provided. By decomposing the cleaning process before forming the gate oxide layer into multiple steps and combining real-time on-line monitoring of the thickness of the trench isolation, the problem of leakage caused by the too-close distance between the control gate layer and the word line derived from wet side etching of the trench isolation is avoided.
[0050] First, the method for manufacturing the flash memory device provided in the embodiment of the present invention will be introduced below.
[0051] Please refer to Figure 3 , Figure 3 The flowchart of the method for manufacturing the flash memory device in an embodiment of the present invention is shown. The manufacturing method provided by the present invention may at least include:
[0052] Step S301: Provide a substrate.
[0053] Step S202: Form a floating gate layer on the substrate.
[0054] Step S303: Form a plurality of trench isolations in the floating gate layer and part of the substrate, and define an active region adjacent to the trench isolation in the substrate. The top surface of the trench isolation is flush with the top surface of the floating gate layer.
[0055] Step S304: Form a sequentially stacked interlayer dielectric layer, a control gate layer, and a sidewall on the floating gate layer and the trench isolation. An opening is formed in the sidewall to expose part of the substrate or part of the trench isolation at the bottom.
[0056] Step S305: Perform a heat treatment on the substrate to change the density of the trench isolation exposed at the opening.
[0057] Step S306: Perform a first cleaning process on the substrate to remove part of the residues on the active region.
[0058] Step S307: Measure the thickness of the trench isolation exposed at the opening, and perform a second cleaning process on the substrate.
[0059] In order to enable those of ordinary skill in the technical field to which the present invention pertains to easily understand the method for manufacturing the flash memory device in the embodiment of the present invention, the method for manufacturing the flash memory device proposed by the present invention will be further described below in combination with the structural diagrams of each structure in the manufacturing process. Please refer to Figures 4 to 10 As shown, the structural diagram in the manufacturing process of the method for manufacturing the semiconductor device provided in the embodiment of the present invention is shown.
[0060] As Figures 4 to 6As shown, perform the above step S301: Provide a substrate 100 for forming a flash memory device, such as a NORD flash memory device. The NORD flash memory device may include a plurality of memory cells, and each memory cell may be a dual-bit structure sharing a word line. Without departing from the spirit of the present invention, the present invention can also be applied to other types of memories. In one embodiment, the substrate 100 may be, for example, a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, a glass substrate, or a group III-V compound substrate (such as a silicon nitride substrate or a gallium arsenide substrate), a silicon carbide substrate, or a stacked structure thereof, or a diamond substrate, or other semiconductor material substrates well known to those skilled in the art. Exemplarily, the substrate 100 is a silicon substrate, but not limited thereto.
[0061] Next, perform the above step S302: Use a deposition process, such as at least one of chemical vapor deposition process, physical vapor deposition process, and atomic layer deposition process, to sequentially form a coupling oxide layer 110 and a floating gate layer 120 on the substrate 100 from bottom to top. In one embodiment, the material of the coupling oxide layer 110 may be an oxide, such as silicon dioxide, and the material of the floating gate layer 120 may be a conductive material, such as polysilicon, but not limited thereto.
[0062] Continue to refer to Figures 4 to 6 As shown, perform the above step S303: Use an etching process, such as at least one of a dry etching process or a wet etching process, to etch the floating gate layer 120, the coupling oxide layer 110, and a part of the substrate 100 downward in a direction perpendicular to the surface of the substrate 100 (hereinafter simply referred to as the vertical direction) to form a plurality of trenches (not shown) in the substrate 100; then use a deposition process, such as chemical vapor deposition process, to fill an insulating material, such as silicon dioxide, in the plurality of trenches to form a plurality of trench isolations 130 that define or define a plurality of active regions AR in the substrate 100. As Figure 4 As shown, in one embodiment, the plurality of active regions AR may be arranged at intervals in a direction parallel to the surface of the substrate 100 (hereinafter simply referred to as the horizontal direction), and a trench isolation 130 is provided between adjacent active regions AR. The floating gate layer 120 may also be a combination of a plurality of independent strip structures, and the floating gate layer 120 extends horizontally across the plurality of active regions AR. Exemplarily, the shape of the active region AR may be a long strip shape, the shape of the trench isolation 130 may also be a long strip shape, and the top surface of the trench isolation 130 may be flush with the top surface of the floating gate layer 120, but not limited thereto.
[0063] As Figures 7 to 8As shown, the above-mentioned step S304 is performed: an interlayer dielectric layer 140, a control gate layer 150, a hard mask layer 160, and sidewalls 170 are sequentially formed from bottom to top on the substrate 100 by a deposition process such as chemical vapor deposition. In one embodiment, the interlayer dielectric layer 140 may specifically include a three-layer film structure, such as an ONO structure of oxide-nitride-oxide stack, but not limited thereto. The hard mask layer 160 is located on a part of the top surface of the control gate layer 150. The sidewalls 170 may also specifically include a three-layer film structure, such as a first sidewall 171, a second sidewall 172, and a third sidewall 173. Among them, the first sidewall 171 is located on one side of the hard mask layer 160 on a part of the top surface of the control gate layer 150, and the bottom is in direct contact with the control gate layer 150. The second sidewall 172 is located on the sidewalls of the first sidewall 171, the control gate layer 150, and the interlayer dielectric layer 140. The third sidewall 173 is located on the sidewall of the second sidewall 172. In one embodiment, the materials of the first sidewall 171, the second sidewall 172, and the third sidewall 173 may be different insulating materials. For example, the first sidewall 171 is silicon dioxide, the second sidewall 171 is silicon nitride, and the third sidewall 171 is silicon oxynitride or silicon dioxide, but not limited thereto.
[0064] It should be understood that when the flash memory device in the embodiment of the present invention is a NORD device, it may include multiple memory cells, and each of its memory cells may be a dual-bit structure sharing a word line. Based on this, after forming the control gate layer 150 and the hard mask layer 160, an opening (not labeled) may be formed in the hard mask layer 160, the control gate layer 150, and the interlayer dielectric layer 140 by an etching process such as dry etching process. Then, the sidewalls 170 are formed, and then etching is continued downward along the opening to remove part of the floating gate layer 120 and the coupling oxide layer 110, that is, an opening 101 as shown in Figure 7 or Figure 8 is formed. The bottom of the opening 101 exposes the substrate 100 on the active region AR, and the bottom on the trench isolation 130 exposes the trench isolation 130.
[0065] Next, perform the above-mentioned step S305: The substrate 100 formed with structures such as the opening 101 can be heat-treated to change the material (such as silicon dioxide) of the trench isolation 101 exposed at the bottom of the opening 101 through a heat treatment with continuous oxygen injection, so as to transform it into an insulating material with enhanced density, thereby avoiding side etching of the trench isolation 130 during subsequent wet cleaning (the first cleaning process and the second cleaning process), and ensuring the insulating characteristics of the trench isolation. In an embodiment, the process of heat-treating the substrate 100 formed with structures such as the opening 101 can be to inject oxygen (O 2 ) into the reaction chamber carrying the substrate 100, and heat the temperature of the reaction chamber to a preset temperature, that is, perform an annealing treatment on it; preferably, the temperature range of the annealing treatment (or the temperature range of the preset temperature) can be 900° to 1100°, such as 900°, 950°, 1000°, 1050°, 1100°, and preferably 1000°, but not limited thereto. The duration of the heat treatment or annealing treatment is approximately: 28s to 35s, such as 28s, 29s, 30s, 31s, 32s, 33s, 34s, 35s, and preferably 30s, but not limited thereto.
[0066] Next, perform the above-mentioned step S306: Perform the first cleaning process before depositing the gate oxide layer on the heat-treated substrate 100, such as a wet etching process, to remove residues existing on the active region AR, such as residual oxides; in an embodiment, the actual duration of the first cleaning process can be relatively short, so as to only remove a small amount of residues, so as to avoid side etching of the trench isolation 130 when the actual thickness of the trench isolation 130 is unknown; and, since the film layer structure on the substrate 100 is heat-treated before the first cleaning process in the embodiment of the present invention, the density of the insulating material of the trench isolation 130 is enhanced, thereby avoiding side etching very well.
[0067] Thereafter, perform the above-mentioned step S307: First, monitor the actual thickness of the trench isolation 130 on the substrate 100 in real time online, and then determine the duration of the second cleaning process based on this actual thickness, so as to remove all the residual oxides remaining on the active region AR while avoiding the problem of side etching of the trench isolation 130 caused by too long cleaning time, and further avoiding the distance between the word line formed on the trench isolation 130 and the control gate layer 150 in the subsequent formation, that is, it can also achieve the problem of leakage caused by the too close distance between the control gate layer and the word line. In one embodiment, the duration of the first cleaning process is less than the duration of the second cleaning process, but this is not limiting. It should be understood that when adjusting the duration of the cleaning process by the real-time online monitoring of the actual thickness of the trench isolation 130, other parameters of the first cleaning process and the second cleaning process can also be adjusted, such as parameters such as the content of the cleaning solution, but this is not limiting.
[0068] As Figure 9 and Figure 10 shown, following the above-mentioned step S307, the deposition process, such as chemical vapor deposition process, can be further used to first form a gate oxide layer 180 in the opening 101, and then form a word line 190 to fill the remaining space of the opening 101. In one embodiment, the gate oxide layer 180 can be located on the inner sidewall of the opening 101, the word line 190 can cover the gate oxide layer 180, and the top surface is flush with the top surface of the first sidewall 171, but this is not limiting. The material of the gate oxide layer 180 can be an oxide, such as silicon dioxide, and the material of the word line 190 can be a conductive material, such as polysilicon, but this is not limiting.
[0069] It can be understood that after forming the word line 190, other components such as bit lines (not shown), source electrodes (not shown), drain electrodes (not shown), etc. can be further formed. This is the prior art and will not be elaborated in the present invention.
[0070] In addition, based on the same inventive concept, the present invention also provides a flash memory device formed by the preparation method of the flash memory device as described above. Among them, the flash memory device is a dual storage bit structure sharing word lines, and the specific formation process can refer to the explanation of the above-mentioned preparation method. The present invention will not elaborate on this.
[0071] In summary, the present invention provides a method for manufacturing a flash memory device, comprising: providing a substrate, forming a floating gate layer on the substrate, forming a plurality of trench isolations in the floating gate layer and a part of the substrate, and defining an active region adjacent to the trench isolations in the substrate, wherein the top surface of the trench isolations is flush with the top surface of the floating gate layer, forming an interlayer dielectric layer, a control gate layer and sidewalls stacked in sequence on the floating gate layer and the trench isolations, an opening is formed in the sidewalls to expose a part of the substrate or a part of the trench isolations at the bottom, performing a heat treatment on the substrate to change the density of the trench isolations exposed at the opening, performing a first cleaning process on the substrate to remove a part of the residues on the active region, measuring the thickness of the trench isolations exposed at the opening, and performing a second cleaning process on the substrate.
[0072] In the present invention, on the one hand, before forming the gate oxide layer, a heat treatment is first performed on the substrate formed with trench isolations to utilize the characteristic that the density of the insulating material (such as oxide) in the trench isolations can be changed during the heat treatment process, to avoid side etching of the trench isolations during subsequent wet cleaning (the first cleaning process and the second cleaning process), and to increase the distance between the word line and the control gate layer on the trench isolations, improving the problem of leakage due to the too-close distance between the control gate layer and the word line, that is, ensuring the insulating characteristics of the trench isolations.
[0073] On the other hand, before forming the gate oxide layer, the pre-cleaning process of the substrate is decomposed into two steps and combined with real-time online monitoring of the thickness of the trench isolations, to dynamically adjust process parameters such as the duration of the two cleaning processes by using the actual thickness of the trench isolations monitored in real time, to avoid side etching of the trench isolations caused by the wet cleaning process, and at the same time remove the residues (such as excess oxides) on the active region, that is, improving the reliability and performance of the NORD flash memory device.
[0074] The above are only the preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.
Claims
1. A method for preparing a flash memory device, characterized in that: include: providing a substrate; forming a floating gate layer on the substrate; Forming a plurality of trench isolations in the floating gate layer and a portion of the substrate, and defining an active area adjacent to the trench isolations in the substrate, wherein the top surface of the trench isolations is flush with the top surface of the floating gate layer; An interlayer dielectric layer, a control gate layer and a sidewall are sequentially stacked and located on the floating gate layer and the trench isolation, wherein an opening is provided in the sidewall, the bottom of which exposes a part of the substrate or a part of the trench isolation; performing a heat treatment on the substrate to change the density of the trench isolation exposed at the opening; Performing a first cleaning process on the substrate to remove some residues on the active area; The thickness of the trench isolation exposed at the opening is measured, and a second cleaning process is performed on the substrate.
2. The method for preparing a flash memory device according to claim 1, wherein: Also includes: forming a gate oxide layer on the inner surface of the opening; A word line is formed on the gate oxide layer, and the word line fills the opening.
3. The method for preparing a flash memory device according to claim 2, wherein: The heat treatment includes an annealing process.
4. The method for preparing a flash memory device according to claim 1, wherein: The step of performing heat treatment on the substrate comprises: Oxygen is introduced into a reaction chamber carrying the substrate, and the temperature of the reaction chamber is heated to a preset temperature.
5. The method for preparing a flash memory device according to claim 4, wherein: The preset temperature range is: 900°~1100°, and the duration is: 28s~35s.
6. The method for preparing a flash memory device according to claim 1, wherein: A duration of the first cleaning process is shorter than a duration of the second cleaning process.
7. The method for preparing a flash memory device according to claim 6, wherein: The first cleaning process and the second cleaning process include a wet etching process.
8. The method for preparing a flash memory device according to claim 1, wherein: Before forming the floating gate layer on the substrate, the preparation method further includes: A coupling oxide layer is formed on the substrate.
9. The method for preparing a flash memory device according to claim 1, wherein: The flash memory device includes a plurality of storage units, and the storage units are dual storage bit structures that share a word line.
10. A flash memory device, characterized in that: The flash memory device is prepared by the method for preparing the flash memory device according to any one of claims 1 to 9.