Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a buffer layer, a first channel layer, an etching mask layer, a first barrier layer, a second channel layer and a second barrier layer which are sequentially stacked, wherein the etching mask layer is composed of a plurality of strip-shaped structures, a strip-shaped groove is formed between every two adjacent strip-shaped structures, the extension direction of the strip-shaped grooves is the first direction, the strip-shaped grooves penetrate through the etching mask layer and partially penetrate through the first channel layer, and the first barrier layer is arranged in the strip-shaped grooves and on the etching mask layer in a shape-preserving mode; the first barrier layer comprises second grooves corresponding to the strip-shaped grooves. Longitudinal multiple channels and transverse multiple channels are designed at the same time, relative stability of transconductance in a large gate source bias voltage range is achieved while the two-dimensional electron gas concentration is improved and the channel on-resistance is reduced, the breakdown voltage is improved, the dynamic characteristic is improved, and therefore the linearity of the device is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and particularly to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] A high electron mobility transistor (HEMT) is a type of field effect transistor. It forms a heterostructure using two materials with different energy gaps and has a strong two-dimensional electron gas (2DEG). It can operate at high frequencies and is thus widely used in mobile phones, satellite TVs, and radars.

[0003] Compared with a single-channel heterostructure, a multi-channel heterostructure shows greater advantages. However, a high electron mobility transistor with a multi-channel heterostructure currently has problems such as a short transconductance stabilization period and poor linearity. Therefore, how to improve transconductance stability and linearity is an urgent problem for those skilled in the art. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof to improve the linearity of a high electron mobility transistor with a multi-channel heterostructure.

[0005] According to one aspect of the present disclosure, an embodiment of the present disclosure provides a semiconductor structure, characterized by including:

[0006] A substrate, a buffer layer, a first channel layer, an etching mask layer, a first barrier layer, a second channel layer, and a second barrier layer stacked in sequence;

[0007] Wherein, the etching mask layer is composed of a plurality of strip structures, and there are strip-shaped grooves between adjacent two of the strip structures. The extending direction of the strip-shaped grooves is the first direction. The strip-shaped grooves penetrate through the etching mask layer and partially penetrate through the first channel layer. The first barrier layer is conformally disposed in the strip-shaped grooves and on the etching mask layer. The first barrier layer includes a second groove corresponding to the strip-shaped grooves.

[0008] As an optional embodiment, the bandgap width of the first barrier layer is greater than that of the etching mask layer, and the bandgap width of the etching mask layer is greater than that of the first channel layer.

[0009] As an optional embodiment, the material of the first barrier layer includes AlN, the material of the etching mask layer includes AlGaN, and the material of the first channel layer includes GaN.

[0010] As an alternative embodiment, the strip structure of at least one of the etching mask layers has an Al component different from that of the strip structures of the other etching mask layers.

[0011] As an alternative embodiment, the surface of the second channel layer on the side away from the first barrier layer is a flat surface

[0012] As an alternative embodiment, the second channel layer is conformally disposed on the first barrier layer, and the second channel layer includes a third groove corresponding to the second groove.

[0013] As an alternative embodiment, the second barrier layer is conformally disposed on the second channel layer, and the second barrier layer includes a fourth groove corresponding to the third groove.

[0014] As an alternative embodiment, in a plane perpendicular to the first direction, the cross-section of the strip groove is rectangular, trapezoidal, V-shaped or bowl-shaped.

[0015] As an alternative embodiment, at least one of the strip grooves has an aspect ratio different from that of the other strip grooves.

[0016] As an alternative embodiment, the depth of the strip groove is constant and the width of the strip groove varies; or

[0017] the depth of the strip groove varies and the width of the strip groove is constant; or

[0018] the depth and width of the strip groove vary proportionally; or

[0019] the depth and width of the strip groove vary inversely.

[0020] As an alternative embodiment, the semiconductor structure further includes:

[0021] a source electrode and a drain electrode, located on the second barrier layer, and the direction from the source electrode to the drain electrode is parallel to the first direction;

[0022] a gate electrode, located on the second barrier layer and between the source electrode and the drain electrode;

[0023] a dielectric layer, located on the side of the gate electrode close to the second barrier layer.

[0024] As an alternative embodiment, the second channel layer, the second barrier layer, the dielectric layer and the gate electrode are sequentially conformally disposed on the first barrier layer, and the gate electrode has a fifth groove corresponding to the second groove.

[0025] As an alternative embodiment, the semiconductor structure further includes:

[0026] An anode and a cathode, located on the buffer layer and on both sides of the first channel layer, the etching mask layer, the first barrier layer, the second channel layer, and the second barrier layer, and the direction in which the anode points to the cathode is parallel to the first direction.

[0027] According to another aspect of the present disclosure, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, which is characterized by including the following steps:

[0028] S1. Provide a substrate, and sequentially stack a buffer layer, a first channel layer, and a plurality of strip-shaped etching mask layers on the substrate;

[0029] S2. Etch the first channel layer exposed by the etching mask layer, and the etching depth is less than the thickness of the first channel layer to form a plurality of strip-shaped grooves, and the extending direction of the strip-shaped grooves is the first direction;

[0030] S3. Conformally dispose a first barrier layer in the strip-shaped grooves and on the etching mask layer, and the first barrier layer includes a second groove corresponding to the strip-shaped grooves;

[0031] S4. Dispose a second channel layer on the first barrier layer;

[0032] S5. Dispose a second barrier layer on the second channel layer.

[0033] As an optional embodiment, the surface of the second channel layer away from the first barrier layer is a plane.

[0034] As an optional embodiment, the second channel layer is conformally disposed on the first barrier layer, and the second channel layer includes a third groove corresponding to the second groove.

[0035] As an optional embodiment, the second barrier layer is conformally disposed on the second channel layer, and the second barrier layer includes a fourth groove corresponding to the third groove.

[0036] As an optional embodiment, in a plane perpendicular to the first direction, the cross-section of the strip-shaped groove is rectangular, trapezoidal, V-shaped or bowl-shaped.

[0037] As an optional embodiment, at least one of the strip-shaped grooves has a different depth-width ratio from the other strip-shaped grooves.

[0038] The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate, a buffer layer, a first channel layer, an etching mask layer, a first barrier layer, a second channel layer, and a second barrier layer that are stacked in sequence; wherein, the etching mask layer is composed of a plurality of strip-shaped structures, and there are strip-shaped grooves between adjacent two strip-shaped structures. The extending direction of the strip-shaped grooves is the first direction. The strip-shaped grooves penetrate through the etching mask layer and partially penetrate the first channel layer. The first barrier layer is conformally disposed in the strip-shaped grooves and on the etching mask layer, and the first barrier layer includes second grooves corresponding to the strip-shaped grooves.

[0039] In the present disclosure, a plurality of strip-shaped grooves are designed in the first channel layer. The heterointerface between the first barrier layer on the sidewall of the strip-shaped groove and the first channel layer is substantially parallel to the polarization axis direction, with basically no polarization effect and no carrier generation. Therefore, the two-dimensional electron gas in the first channel layer can be confined to the bottom surface of the groove and the top surface between adjacent grooves, enabling the two-dimensional electron gas in the heterojunction structure to exhibit an approximately one-dimensional transport mode during migration, which can improve the carrier mobility. At the same time, the design of the lateral multi-channel is equivalent to a plurality of heterojunction structures connected in parallel between the source and drain electrodes. Compared with the planar heterojunction structure device, it is beneficial to realize the mutual compensation of different transconductances of the device, achieve relative stability of the transconductance within a large gate-source bias range, be beneficial to increasing the breakdown voltage, improving the dynamic characteristics, and thus improving the device linearity.

[0040] The heterointerface between the second channel layer and the second barrier layer of the present disclosure can generate a two-dimensional electron gas with high concentration and high mobility. The heterointerfaces between the first channel layer and the etching mask layer, between the etching mask layer and the first barrier layer, and between the first channel layer and the first barrier layer can supplement carriers, further increasing the two-dimensional electron gas concentration and reducing the channel on-resistance. The design of the longitudinal multi-channel can disperse the power lines and weaken the electric field strength while increasing the two-dimensional electron gas concentration and improving the carrier mobility, thereby increasing the breakdown voltage of the semiconductor structure. Description of the Drawings

[0041] Figure 1 The figure shows a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.

[0042] Figures 2a to 2c The figure shows a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.

[0043] Figures 3a to 3d The figure shows a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.

[0044] Figures 4a to 4d The figure shows a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.

[0045] Figure 5The figure shows a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.

[0046] Figure 6 The figure shows a flowchart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.

[0047] Figures 7 - 12 The figure shows an exploded schematic diagram of a semiconductor structure during manufacturing provided by an embodiment of the present disclosure. Detailed implementation manners

[0048] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.

[0049] In order to improve the linearity of high electron mobility transistors of a multi-channel heterostructure, the present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate, a buffer layer, a first channel layer, an etching mask layer, a first barrier layer, a second channel layer, and a second barrier layer that are sequentially stacked; wherein, the etching mask layer is composed of a plurality of strip structures, and a strip groove is formed between two adjacent strip structures. The extending direction of the strip groove is the first direction. The strip groove penetrates through the etching mask layer and partially penetrates through the first channel layer. The first barrier layer is conformally disposed in the strip groove and on the etching mask layer. The first barrier layer includes a second groove corresponding to the strip groove. The present disclosure designs both longitudinal multi-channels and transverse multi-channels, realizes the relative stability of the transconductance within a large gate-source bias range while increasing the two-dimensional electron gas concentration and reducing the channel conduction resistance, improves the breakdown voltage, and improves the dynamic characteristics, thereby improving the device linearity.

[0050] Next, in combination with Figures 1 to 12 A semiconductor structure and a manufacturing method thereof mentioned in the present disclosure will be further illustrated by examples.

[0051] Figure 1 The figure shows a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure. As Figure 1As shown, the semiconductor structure includes a substrate 10, a buffer layer 20, a first channel layer 30, an etching mask layer 40, a first barrier layer 50, a second channel layer 60, and a second barrier layer 70 which are sequentially stacked; wherein, the etching mask layer 40 is composed of a plurality of strip structures, and a strip groove 31 is formed between two adjacent strip structures. The extending direction of the strip groove 31 is the first direction. The strip groove 31 penetrates through the etching mask layer 40 and partially penetrates through the first channel layer 30. The first barrier layer 50 is conformally disposed in the strip groove 31 and on the etching mask layer 40. The first barrier layer 50 includes a second groove 51 corresponding to the strip groove 31. As Figure 1 shown, the semiconductor structure further includes: a source electrode 81 and a drain electrode 82, which are located on the second barrier layer 70, and the direction from the source electrode 81 to the drain electrode 82 is parallel to the first direction; a gate electrode 83, which is located on the second barrier layer 70 and between the source electrode 81 and the drain electrode 82; a dielectric layer 84, which is located on the side of the gate electrode 83 close to the second barrier layer 70. The material of the dielectric layer 84 includes at least one of aluminum oxide, aluminum nitride, and aluminum oxynitride. The material of the dielectric layer 84 has a strong ability to bind charges. In the formed external electric field, charges are not easily polarized, the polarized charges are few, and thus the polarized electric field is weak, effectively avoiding the short-channel effect of the semiconductor structure. By setting the dielectric layer 84 to form a MIS gate structure, the gate leakage current can be effectively reduced, the gate voltage swing and the drain current swing can be increased, and the device performance can be further improved.

[0052] In this embodiment, the bandgap of the first barrier layer 50 is greater than that of the etching mask layer 40, and the bandgap of the etching mask layer 40 is greater than that of the first channel layer 30. For example, in one embodiment, the material of the first barrier layer 50 includes AlN, the material of the etching mask layer 40 includes AlGaN, and the material of the first channel layer 30 includes GaN. Since the bandgap of the first barrier layer 50 is greater than that of the etching mask layer 40 and the bandgap of the etching mask layer 40 is greater than that of the first channel layer 30, a two-dimensional electron gas can be generated at the heterojunction interface between the first barrier layer 50 and the etching mask layer 40, and a two-dimensional electron gas will also be generated at the heterojunction interface between the etching mask layer 40 and the first channel layer 30, which can increase the two-dimensional electron gas concentration of the semiconductor structure and reduce the channel conduction resistance.

[0053] In one embodiment, the strip structure of at least one etching mask layer 40 has an Al component different from that of the strip structures of other etching mask layers 40. Increasing the Al component in the etching mask layer 40 can increase the two-dimensional electron gas density, thereby increasing the saturation current of the device. By changing the Al component in the etching mask layer 40 at different positions, the saturation current at different positions of the semiconductor structure can be adjusted, and further, the transconductance peak values of the heterojunction structure between the first barrier layer 50 and the etching mask layer 40 and the heterojunction structure between the etching mask layer 40 and the first channel layer 30 can be made to tend to be uniform. The semiconductor structure of the present disclosure can be regarded as a parallel connection of several devices with different transconductance distributions. Through this parallel connection structure, mutual compensation of different transconductances of the device is achieved, so as to achieve relative stability of the transconductance value within a relatively large gate-source bias range, making the semiconductor structure have good linearity.

[0054] Figures 2a to 2c The following is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure. In one embodiment, as Figure 1 shown, the surface of the second channel layer 60 away from the first barrier layer 50 can be a plane, so that the two-dimensional electron gas generated at the heterojunction interface between the second channel layer 60 and the second barrier layer 70 is located on the same horizontal plane. In another embodiment, as Figure 2a shown, the second channel layer 60 is conformally disposed on the first barrier layer 50, and the second channel layer 60 includes a third groove 61 corresponding to the second groove 51. Then, the two-dimensional electron gas generated at the heterojunction interface between the second channel layer 60 and the second barrier layer 70 is not on the same horizontal plane, further forming a lateral multi-channel structure, which is beneficial to realizing mutual compensation of different transconductances of the device, achieving relative stability of the transconductance within a relatively large gate-source bias range, being beneficial to increasing the breakdown voltage, improving the dynamic characteristics, and thus improving the device linearity. In yet another embodiment, as Figure 2b shown, while the second channel layer 60 is conformally disposed on the first barrier layer 50, the second barrier layer 70 is also conformally disposed on the second channel layer 60. The second barrier layer 70 includes a fourth groove 71 corresponding to the third groove 61. Then, the two-dimensional electron gas generated at the heterojunction interface between the second channel layer 60 and the second barrier layer 70 is not on the same horizontal plane and the gate 83 fills the fourth groove 71 in the second barrier layer 70. In addition to the effect of further forming a lateral multi-channel structure, the control ability of the gate 83 over carriers is greatly improved. Therefore, the breakdown voltage of the device can be significantly increased and the leakage problem can be reduced, and the efficiency and linearity of the radio frequency device can be improved. In other embodiments, as Figure 2c shown, the second channel layer 60, the second barrier layer 70, the dielectric layer 84, and the gate 83 are sequentially conformally disposed on the first barrier layer 50. The gate 83 has a fifth groove 85 corresponding to the second groove 51, which can further improve the control ability of the gate 83 over carriers and further improve the device linearity.

[0055] Figures 3a to 3d The following is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure. In one embodiment, in a plane perpendicular to the first direction, the cross-section of the strip-shaped groove 31 is rectangular (as shown in Figure 3a ), trapezoidal (as shown in Figure 3b ), V-shaped (as shown in Figure 3c ), or bowl-shaped (as shown in Figure 3d ). The present disclosure does not specifically limit the cross-sectional shape of the strip-shaped groove 31. By changing the shape of the strip-shaped groove 31, the shape of the first barrier layer 50 in the strip-shaped groove 31 can be changed, so that the generated two-dimensional electron gas can be modulated, and the linearity of the semiconductor structure can be further improved.

[0056] Figures 4a to 4d The following is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure. In one embodiment, at least one strip-shaped groove 31 has a different depth-to-width ratio from other strip-shaped grooves 31. As shown in Figure 4a , the depth of the strip-shaped groove 31 is constant and the width of the strip-shaped groove 31 changes; or as shown in Figure 4b , the depth of the strip-shaped groove 31 changes and the width of the strip-shaped groove 31 is constant; or as shown in Figure 4c , the depth and width of the strip-shaped groove 31 change in the same proportion; or as shown in Figure 4d , the depth and width of the strip-shaped groove 31 change inversely. By changing the depth and / or width of the strip-shaped groove 31, the transconductance peak value of the heterojunction structure at different positions can be changed, and the threshold voltage of the heterojunction structure at different positions can be changed. By superimposing multiple heterojunction structures, the linear working characteristics of the device can be improved.

[0057] Figure 5 The following is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure. In one embodiment, the semiconductor structure can be used to fabricate a diode. As shown in Figure 5 , the semiconductor structure further includes: an anode 91 and a cathode 92, which are located on the buffer layer 20 and on both sides of the first channel layer 30, the etching mask layer 40, the first barrier layer 50, the second channel layer 60, and the second barrier layer 70. The direction in which the anode 91 points to the cathode 92 is parallel to the first direction. The diode device fabricated with the semiconductor structure of the present disclosure can also improve the breakdown voltage, improve the dynamic characteristics, and improve the linearity of the device.

[0058] According to another aspect of the present disclosure, Figure 6 The following is a flowchart of a manufacturing method of a semiconductor structure provided by an embodiment of the present disclosure, Figures 7 - 12 The following is an exploded schematic diagram of a semiconductor structure during manufacturing provided by an embodiment of the present disclosure. As shown in Figure 6 , a manufacturing method of a semiconductor structure provided by an embodiment of the present disclosure includes the following steps:

[0059] As shown in Figure 7 Figure , step S1: Provide a substrate, and sequentially stack a buffer layer, a first channel layer, and a plurality of strip-shaped etching mask layers on the substrate.

[0060] Specifically, the material of the substrate 10 includes any one or a combination of Si, Al 2 O 3 , GaN, SiC, or AlN. The material of the buffer layer 20 is a group III nitride material, which may include one or more of GaN, AlGaN, and AlInGaN, and is not limited thereto. The bandgap width of the etching mask layer 40 is greater than the bandgap width of the first channel layer 30. For example, the material of the etching mask layer 40 includes AlGaN, the material of the first channel layer 30 includes GaN, and a two-dimensional electron gas can be generated at the heterojunction interface between the etching mask layer 40 and the first channel layer 30.

[0061] In this embodiment, the preparation method of the plurality of strip-shaped etching mask layers 40 may be to first grow a whole surface film layer and then use a photolithography method to etch away a part of the etching mask layer 40 to form a plurality of strip-shaped etching mask layers 40; the preparation method of the plurality of strip-shaped etching mask layers 40 may also be to first set a plurality of strip-shaped photoresist layers, and grow strip-shaped etching mask layers 40 between the photoresist layers and then strip the photoresist layers. The present disclosure does not specifically limit the preparation method of the plurality of strip-shaped etching mask layers 40.

[0062] As shown in Figure 8 Figure , step S2: Etch the first channel layer exposed by the etching mask layer, and the etching depth is less than the thickness of the first channel layer, to form a plurality of strip-shaped grooves, and the extending direction of the strip-shaped grooves is the first direction.

[0063] Specifically, etch the first channel layer 30 exposed by the etching mask layer 40, and the etching depth is less than the thickness of the first channel layer 30, to form a plurality of strip-shaped grooves 31, and the extending direction of the strip-shaped grooves 31 is the first direction.

[0064] As shown in Figure 9 Figure , step S3: Conformally set a first barrier layer in the strip-shaped grooves and on the etching mask layer, and the first barrier layer includes a second groove corresponding to the strip-shaped grooves.

[0065] Specifically, conformally set a first barrier layer 50 in the strip-shaped grooves 31 and on the etching mask layer 40. The first barrier layer 50 includes a second groove 51 corresponding to the strip-shaped grooves 31. The bandgap width of the first barrier layer 50 is greater than the bandgap width of the etching mask layer 40, and a two-dimensional electron gas can be generated at the heterojunction interface between the first barrier layer 50 and the etching mask layer 40.

[0066] As shown in Figure 10As shown, step S4: A second channel layer is disposed on the first barrier layer. As Figure 11 shown, step S5: A second barrier layer is disposed on the second channel layer.

[0067] Specifically, a second channel layer 60 is disposed on the first barrier layer 50, and a second barrier layer 70 is disposed on the second channel layer 60. The bandgap width of the second barrier layer 70 is greater than that of the second channel layer 60, and a high-concentration two-dimensional electron gas can be generated by the heterojunction structure between the second barrier layer 70 and the second channel layer 60.

[0068] Step S6: A dielectric layer, a source electrode, and a drain electrode located on the second barrier layer, and a gate electrode located on the dielectric layer and between the source electrode and the drain electrode are formed, and the direction from the source electrode to the drain electrode is parallel to the first direction.

[0069] Specifically, a dielectric layer 84, a source electrode 81, and a drain electrode 82 located on the second barrier layer 70, and a gate electrode 83 located on the dielectric layer 84 and between the source electrode 81 and the drain electrode 82 are formed, and the direction from the source electrode 81 to the drain electrode 82 is parallel to the first direction, forming a semiconductor structure as Figure 1 shown. The material of the dielectric layer 84 includes at least one of alumina, aluminum nitride, and aluminum oxynitride. The material of the dielectric layer 84 has a strong ability to bind charges. In the formed external electric field, charges are not easily polarized, there are few polarized charges, and thus the polarized electric field is weak, effectively avoiding the short-channel effect of the semiconductor structure. By setting the dielectric layer 84 to form a MIS gate structure, the gate leakage current can be effectively reduced, the gate voltage swing and the drain current swing can be increased, and the device performance can be further improved.

[0070] In one embodiment, the grown second channel layer 60 completely fills the groove of the first barrier layer 50 and becomes flat, that is, the surface of the second channel layer 60 away from the first barrier layer 50 is a plane, as Figure 1 shown, then the two-dimensional electron gas generated at the heterojunction interface between the second channel layer 60 and the second barrier layer 70 is located on the same horizontal plane. In another embodiment, the grown second channel layer 60 can be conformally disposed on the first barrier layer 50, and the second channel layer 60 includes a third groove 61 corresponding to the second groove 51, as Figure 2aAs shown, the two-dimensional electron gas generated at the heterojunction interface between the second channel layer 60 and the second barrier layer 70 is not on the same horizontal plane, further forming a transverse multi-channel structure, which is beneficial to realizing the mutual compensation of different transconductances of the device, realizing the relative stability of the transconductance within a large gate-source bias range, being beneficial to increasing the breakdown voltage, improving the dynamic characteristics, and thus improving the linearity of the device. In another embodiment, while the grown second channel layer 60 is conformally disposed on the first barrier layer 50, the grown second barrier layer 70 is also conformally disposed on the second channel layer 60. The second barrier layer 70 includes a fourth groove 71 corresponding to the third groove 61, and the gate 83 fills the fourth groove 71 in the second barrier layer 70, as Figure 2b shown, the two-dimensional electron gas generated at the heterojunction interface between the second channel layer 60 and the second barrier layer 70 is also not on the same horizontal plane. In addition to the effect of further forming a transverse multi-channel structure, the control ability of the gate 83 over carriers is greatly improved. Therefore, the breakdown voltage of the device can be significantly increased and the leakage problem can be reduced, and the efficiency and linearity of the radio frequency device can be improved. In other embodiments, as Figure 2c shown, the second channel layer 60, the second barrier layer 70, the dielectric layer 84, and the gate 83 are sequentially conformally disposed on the first barrier layer 50. The gate 83 has a fifth groove 85 corresponding to the second groove 51, which can further improve the control ability of the gate 83 over carriers and further improve the linearity of the device.

[0071] In one embodiment, in a plane perpendicular to the first direction, the cross-section of the strip-shaped groove 31 is rectangular (as Figure 3a shown), trapezoidal (as Figure 3b shown), V-shaped (as Figure 3c shown), or bowl-shaped (as Figure 3d shown). The present disclosure does not specifically limit the cross-sectional shape of the strip-shaped groove 31. By changing the shape of the strip-shaped groove 31, the shape of the first barrier layer 50 grown in the strip-shaped groove 31 can be changed, so that the generated two-dimensional electron gas can be modulated, and the linearity of the semiconductor structure can be further improved.

[0072] In one embodiment, the etched strip-shaped grooves 31 have different sizes, and at least one strip-shaped groove 31 has an aspect ratio different from that of other strip-shaped grooves 31. As Figure 4a shown, the depth of the strip-shaped groove 31 is constant and the width of the strip-shaped groove 31 changes; or as Figure 4b shown, the depth of the strip-shaped groove 31 changes and the width of the strip-shaped groove 31 is constant; or as Figure 4c shown, the depth and width of the strip-shaped groove 31 change in the same proportion; or as Figure 4dAs shown, the depth and width of the strip-shaped groove 31 vary inversely. By changing the depth and / or width of the strip-shaped groove 31, the transconductance peak of the heterojunction structure at different subsequent growth positions can be changed, and the threshold voltage of the heterojunction structure at different positions can be changed. Through the superposition of multiple heterojunction structures, the linear working characteristics of the device can be improved.

[0073] In one embodiment, the semiconductor structure can be used to fabricate a diode. After step S5 in the manufacturing method of the semiconductor structure, step S7 is further included: etching the second barrier layer, the second channel layer, the first barrier layer, the etching mask layer, and the first channel layer in the anode region and the cathode region until the buffer layer is exposed, setting an anode in the anode region and a cathode in the cathode region, and the direction in which the anode points to the cathode is parallel to the first direction. Specifically, as Figure 12 shown, etching the second barrier layer 70, the second channel layer 60, the first barrier layer 50, the etching mask layer 40, and the first channel layer 30 in the anode region and the cathode region until the buffer layer 20 is exposed, setting an anode 91 in the anode region and a cathode 92 in the cathode region, and the direction in which the anode 91 points to the cathode 92 is parallel to the first direction, to form a Figure 5 diode structure as shown. The diode device fabricated with the semiconductor structure of the present disclosure can also improve the breakdown voltage, improve the dynamic characteristics, and improve the device linearity.

[0074] The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate, a buffer layer, a first channel layer, an etching mask layer, a first barrier layer, a second channel layer, and a second barrier layer that are sequentially stacked; wherein, the etching mask layer is a plurality of strip-shaped structures, and a strip-shaped groove is formed between two adjacent strip-shaped structures. The extending direction of the strip-shaped groove is the first direction. The strip-shaped groove penetrates through the etching mask layer and partially penetrates through the first channel layer. The first barrier layer is conformally disposed in the strip-shaped groove and on the etching mask layer, and the first barrier layer includes a second groove corresponding to the strip-shaped groove. The present disclosure designs both longitudinal multi-channels and lateral multi-channels, realizing the relative stability of the transconductance within a large gate-source bias range while increasing the two-dimensional electron gas concentration and reducing the channel conduction resistance, improving the breakdown voltage and the dynamic characteristics, thereby improving the device linearity.

[0075] It should be understood that the term "including" and its variants used in this disclosure are open-ended, that is, "including but not limited to". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment". In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0076] The above are only the preferred embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent replacements, etc. made within the spirit and principles of this disclosure shall be included within the protection scope of this disclosure.

Claims

1. A semiconductor structure, characterized in that, it includes: a substrate (10), a buffer layer (20), a first channel layer (30), an etching mask layer (40), a first barrier layer (50), a second channel layer (60), and a second barrier layer (70) that are sequentially stacked; wherein, the etching mask layer (40) is composed of a plurality of strip-shaped structures, and a strip-shaped groove (31) is formed between two adjacent strip-shaped structures. The extending direction of the strip-shaped groove (31) is the first direction. The strip-shaped groove (31) penetrates through the etching mask layer (40) and partially penetrates through the first channel layer (30). The first barrier layer (50) is conformally disposed in the strip-shaped groove (31) and on the etching mask layer (40), and the first barrier layer (50) includes a second groove (51) corresponding to the strip-shaped groove (31).

2. The semiconductor structure according to claim 1, characterized in that, the bandgap width of the first barrier layer (50) is greater than the bandgap width of the etching mask layer (40), and the bandgap width of the etching mask layer (40) is greater than the bandgap width of the first channel layer (30).

3. The semiconductor structure according to claim 2, characterized in that, the material of the first barrier layer (50) includes AlN, the material of the etching mask layer (40) includes AlGaN, and the material of the first channel layer (30) includes GaN.

4. The semiconductor structure according to claim 3, characterized in that, at least one of the strip-shaped structures of the etching mask layer (40) has an Al composition different from that of the strip-shaped structures of the other etching mask layers (40).

5. The semiconductor structure according to claim 1, characterized in that, the surface of the second channel layer (60) on the side away from the first barrier layer (50) is a plane.

6. The semiconductor structure according to claim 1, characterized in that, the second channel layer (60) is conformally disposed on the first barrier layer (50), and the second channel layer (60) includes a third groove (61) corresponding to the second groove (51).

7. The semiconductor structure according to claim 6, characterized in that, the second barrier layer (70) is conformally disposed on the second channel layer (60), and the second barrier layer (70) includes a fourth groove (71) corresponding to the third groove (61).

8. The semiconductor structure according to claim 1, characterized in that, in a plane perpendicular to the first direction, the cross-section of the strip-shaped groove (31) is rectangular, trapezoidal, V-shaped, or bowl-shaped.

9. The semiconductor structure according to claim 1, characterized in that, at least one of the strip-shaped grooves (31) has an aspect ratio different from that of the other strip-shaped grooves (31).

10. The semiconductor structure according to claim 9, characterized in that, the depth of the strip-shaped groove (31) is constant and the width of the strip-shaped groove (31) varies; or the depth of the strip-shaped groove (31) varies and the width of the strip-shaped groove (31) is constant; or the depth and width of the strip-shaped groove (31) change in the same proportion; or The depth and width of the strip-shaped groove (31) vary inversely.

11. The semiconductor structure according to claim 1, wherein, the semiconductor structure further comprises: a source electrode (81) and a drain electrode (82), located on the second barrier layer (70), and the direction of the source electrode (81) pointing to the drain electrode (82) is parallel to the first direction; a gate electrode (83), located on the second barrier layer (70) and between the source electrode (81) and the drain electrode (82); a dielectric layer (84), located on the side of the gate electrode (83) close to the second barrier layer (70).

12. The semiconductor structure according to claim 11, wherein, the second channel layer (60), the second barrier layer (70), the dielectric layer (84), and the gate electrode (83) are sequentially conformally disposed on the first barrier layer (50), and the gate electrode (83) has a fifth groove (85) corresponding to the second groove (51).

13. The semiconductor structure according to claim 1, wherein, the semiconductor structure further comprises: an anode (91) and a cathode (92), located on the buffer layer (20) and on both sides of the first channel layer (30), the etching mask layer (40), the first barrier layer (50), the second channel layer (60), and the second barrier layer (70), and the direction of the anode (91) pointing to the cathode (92) is parallel to the first direction.

14. A manufacturing method of a semiconductor structure, wherein, it includes the following steps: S1. Provide a substrate (10), and sequentially stack a buffer layer (20), a first channel layer (30), and a plurality of strip-shaped etching mask layers (40) on the substrate (10); S2. Etch the first channel layer (30) exposed by the etching mask layer (40), and the etching depth is less than the thickness of the first channel layer (30) to form a plurality of strip-shaped grooves (31), and the extending direction of the strip-shaped grooves (31) is the first direction; S3. Conformally dispose a first barrier layer (50) in the strip-shaped grooves (31) and on the etching mask layer (40), and the first barrier layer (50) includes a second groove (51) corresponding to the strip-shaped grooves (31); S4. Dispose a second channel layer (60) on the first barrier layer (50); S5. Dispose a second barrier layer (70) on the second channel layer (60).

15. The manufacturing method of the semiconductor structure according to claim 14, wherein, the surface of the second channel layer (60) away from the first barrier layer (50) is a plane.

16. The manufacturing method of the semiconductor structure according to claim 14, wherein, the second channel layer (60) is conformally disposed on the first barrier layer (50), and the second channel layer (60) includes a third groove (61) corresponding to the second groove (51).

17. The manufacturing method of the semiconductor structure according to claim 16, wherein, The second barrier layer (70) is conformally disposed on the second channel layer (60), and the second barrier layer (70) includes a fourth groove (71) corresponding to the third groove (61).

18. The manufacturing method of the semiconductor structure according to claim 14, wherein, In a plane perpendicular to the first direction, the cross-section of the strip-shaped groove (31) is rectangular, trapezoidal, V-shaped or bowl-shaped.

19. The manufacturing method of the semiconductor structure according to claim 14, wherein, At least one of the strip-shaped grooves (31) has an aspect ratio different from that of the other strip-shaped grooves (31).

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