A power mos device and a method of manufacturing the same

Abstract

The application discloses a power MOS device and a preparation method thereof, and relates to the technical field of semiconductors. The power MOS device comprises a drift layer, a substrate layer arranged on the back of the drift layer, a high-thermal-conductivity layer arranged on both sides of the drift layer and having a stepped structure, a drain layer arranged on the back of the substrate layer, a first channel layer and a second channel layer arranged on the front of the high-thermal-conductivity layer, a P-type well arranged between the first channel layer and the second channel layer, an N-type doped region formed in the P-type well, a P-type doped region formed in the N-type doped region, a gate structure arranged on the front of the first channel layer and the second channel layer, a dielectric layer arranged on the front of the gate structure and covering the gate structure, and a connecting hole arranged in the dielectric layer, so that the source layer can be in contact with the N-type doped region and the P-type doped region through the connecting hole. The application effectively improves the heat dissipation capacity of the power MOS device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a power MOS device and a method for manufacturing the same. Background Art

[0002] In the field of modern power electronics, power MOS (Metal-Oxide-Semiconductor) devices have become indispensable key components in applications ranging from consumer electronics to industrial applications due to their significant advantages such as high efficiency, fast switching speed, and easy driving. These characteristics enable power MOS devices to play an important role in a wide range of scenarios and promote the rapid development of power electronics technology. However, with the continuous advancement of technology and the ever-changing market demand, the industry's pursuit of higher power density and smaller size has become more urgent, which has brought unprecedented challenges to the structural design of traditional power MOS devices. Among them, the most prominent problem is heat management.

[0003] Under high-power operation, the heat generated by conventional power MOS devices is difficult to dissipate quickly and effectively, resulting in a significant increase in device temperature. This temperature increase not only impairs device performance but also poses a serious threat to device reliability and service life. Summary of the Invention

[0004] The main purpose of this application is to provide a power MOS device and a preparation method thereof, aiming to effectively improve the heat dissipation capability of the power MOS device.

[0005] To achieve the above objectives, an embodiment of the present application provides a power MOS device, comprising:

[0006] drift layer;

[0007] a substrate layer, disposed on the back side of the drift layer;

[0008] a high thermal conductivity layer, disposed on both sides of the drift layer and the substrate layer, wherein the high thermal conductivity layer has a stepped structure;

[0009] a drain electrode layer, disposed on the back side of the substrate layer;

[0010] A first channel layer and a second channel layer are provided on the front surface of the high thermal conductivity layer;

[0011] A P-type well is provided between the first channel layer and the second channel layer, an N-type doping region is formed inside the P-type well, and a P-type doping region is formed inside the N-type doping region;

[0012] a gate structure, disposed on the front sides of the first channel layer and the second channel layer;

[0013] a dielectric layer, disposed on the front surface of the gate structure and covering the gate structure; the dielectric layer is provided with a connection hole;

[0014] The source layer is arranged on the front side of the dielectric layer and contacts the N-type doping region and the P-type doping region through the connection hole.

[0015] In one embodiment, the material of the high thermal conductivity layer includes diamond.

[0016] In one embodiment, the power MOS device further includes: a gate dielectric disposed between the gate structure and the channel layer, wherein the channel layer includes a first channel layer and / or a second channel layer.

[0017] In one embodiment, the drift layer has a thickness of 10 to 15 μm;

[0018] And / or, the thickness of the first channel layer and the second channel layer is 3-7 μm;

[0019] And / or, the thickness of the gate structure is 0.1 to 0.5 μm;

[0020] And / or, the thickness of the dielectric layer is 0.4 to 0.8 μm;

[0021] And / or, the thickness of the source layer is 1 to 3 μm;

[0022] And / or, the drain layer has a thickness of 1 to 3 μm.

[0023] In one embodiment, the material of the substrate layer includes: at least one of N-type silicon carbide, N-type gallium nitride, N-type aluminum nitride, and N-type silicon nitride;

[0024] And / or, the material of the drift layer includes: at least one of N-type silicon carbide, N-type gallium nitride, N-type gallium arsenide, N-type gallium oxide, N-type aluminum gallium nitride and N-type aluminum nitride;

[0025] And / or, the material of the gate structure includes: at least one of polysilicon, titanium nitride, tantalum nitride, tungsten and cobalt;

[0026] And / or, the material of the source layer includes: at least one of titanium, aluminum, copper, nickel, iridium, rhodium, ruthenium, platinum, gold, silver, palladium and cobalt;

[0027] And / or, the material of the drain electrode layer includes at least one of titanium, aluminum, copper, nickel, iridium, rhodium, ruthenium, platinum, gold, silver, palladium and cobalt.

[0028] To achieve the above-mentioned object, an embodiment of the present application provides a method for manufacturing a power MOS device, which is used to manufacture the power MOS device as described above. The method for manufacturing a power MOS device comprises the following steps:

[0029] Providing a substrate layer, and sequentially preparing a drift layer and a channel layer on the front surface of the substrate layer;

[0030] Performing P-type doping on a portion of the channel layer to obtain a P-type well;

[0031] Performing N-type doping on a portion of the P-type well to obtain an N-type doped region;

[0032] Performing P-type doping on a portion of the N-type doping region to obtain a P-type doping region;

[0033] A gate structure and a dielectric layer are sequentially prepared on the front surface of the channel layer, wherein the dielectric layer covers the gate structure;

[0034] Etching the substrate layer and the drift layer on both sides to form a stepped structure;

[0035] preparing a high thermal conductivity layer in the area corresponding to the stepped structure;

[0036] etching the dielectric layer to obtain a connection hole;

[0037] A source layer is prepared to obtain a power MOS device, wherein the source layer contacts the N-type doping region and the P-type doping region through the connection hole.

[0038] In one embodiment, the step of performing P-type doping on a portion of the channel layer to obtain a P-type well includes:

[0039] forming a first oxide layer on the front surface of the channel layer;

[0040] defining a first photoresist pattern on the front surface of the first oxide layer;

[0041] Etching the first oxide layer based on the first photoresist pattern to form a P-type well injection window;

[0042] P-type doping is performed on the channel layer exposed to the P-type well implantation window to obtain the P-type well.

[0043] In one embodiment, before the step of performing N-type doping on a portion of the P-type well, the method further includes:

[0044] forming a second oxide layer of a first thickness on the front surface of the first oxide layer;

[0045] The second oxide layer having a first thickness is etched to form sidewalls located on both sides of the P-type well injection window.

[0046] In one embodiment, the step of sequentially preparing a gate structure and a dielectric layer on the front surface of the channel layer includes:

[0047] preparing a gate layer on the front side of the channel layer;

[0048] Etching the gate layer to obtain the gate structure;

[0049] The dielectric layer is prepared on the front side of the gate structure.

[0050] In one embodiment, the N-type doping concentration of the substrate layer is 1e17-1e19 cm -3 ;

[0051] And / or, the N-type doping concentration of the drift layer is 1e14-1e16 cm -3 ;

[0052] And / or, the doping concentration of the P-type doping in the partial region of the channel layer is 1e17-5e17 cm -3 ;

[0053] And / or, the N-type doping concentration of the partial region of the P-type well is 1e18-1e19 cm -3 ;

[0054] And / or, the doping concentration of the P-type doping in the partial area of ​​the N-type doping region is 1e18-1e19 cm -3 .

[0055] The present invention provides a power MOS device, comprising: a drift layer; a substrate layer disposed on the back side of the drift layer; a high thermal conductivity layer having a stepped structure disposed on both sides of the drift layer and the substrate layer; a drain layer disposed on the back side of the substrate layer; a first channel layer and a second channel layer disposed on the front side of the high thermal conductivity layer; a P-type well disposed between the first channel layer and the second channel layer; an N-type doped region formed within the P-type well, and a P-type doped region formed within the N-type doped region; a gate structure disposed on the front side of the first channel layer and the second channel layer; a dielectric layer disposed on the front side of the gate structure and covering the gate structure; the dielectric layer further comprising a connection hole, such that the source layer can contact the N-type doped region and the P-type doped region through the connection hole. In a power MOS device, although the JFET (Junction Field-Effect Transistor) region is not the primary current flow path, its inherent on-resistance can still cause heat accumulation, thereby adversely affecting the overall thermal performance of the device. This heat accumulation will not only lead to local overheating, but also induce thermal stress, thereby reducing the working efficiency and long-term reliability of the device. In order to effectively solve this problem, the embodiment of the present application sets a high thermal conductivity layer in the JFET area of ​​the power MOS device, so that the heat generated by the device during operation can be quickly discharged, significantly reducing the thermal stress caused by local overheating, and effectively reducing the operating temperature of the device. At the same time, the high thermal conductivity layer adopts a unique stepped structure design. Compared with conventional regular area etching, the stepped structure can achieve higher etching accuracy and uniformity through step-by-step etching, reduce parasitic effects, and optimize the control of sidewall quality and etching depth. This stepped structure not only improves the stability and repeatability of the process, but also reduces etching damage, further improving the overall performance and reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 This is a schematic diagram of the structure of a power MOS device involved in an embodiment of the present application;

[0057] Figure 2 This is a flow chart of a method for preparing a power MOS device according to an embodiment of the present application;

[0058] Figure 3 The process flow of the power MOS device manufacturing method involved in the embodiment of this application is as follows Figure 1 ;

[0059] Figure 4 The process flow of the power MOS device manufacturing method involved in the embodiment of this application is as follows Figure 2 ;

[0060] Figure 5 The process flow of the power MOS device manufacturing method involved in the embodiment of this application is as follows Figure 3;

[0061] Figure 6 The process flow of the power MOS device manufacturing method involved in the embodiment of this application is as follows Figure 4 ;

[0062] Figure 7 The process flow of the power MOS device manufacturing method involved in the embodiment of this application is as follows Figure 5 ;

[0063] Figure 8 The process flow of the power MOS device manufacturing method involved in the embodiment of this application is as follows Figure 6 ;

[0064] Figure 9 The process flow of the power MOS device manufacturing method involved in the embodiment of this application is as follows Figure 7 ;

[0065] Figure 10 The process flow of the power MOS device manufacturing method involved in the embodiment of this application is as follows Figure 8 ;

[0066] Figure 11 The process flow of the power MOS device manufacturing method involved in the embodiment of this application is as follows Figure 9 ;

[0067] Figure 12 The process flow of the power MOS device manufacturing method involved in the embodiment of this application is as follows Figure 10 .

[0068] Description of reference numerals:

[0069] 110, drift layer; 120, substrate layer; 130, high thermal conductivity layer;

[0070] 140, drain layer; 150, channel layer; 151, first channel layer; 152, second channel layer;

[0071] 153. First oxide layer; 154. First photoresist pattern; 155. Sidewall;

[0072] 161, P-type well; 162, N-type doped region; 163, P-type doped region;

[0073] 170. Gate structure; 171. Gate dielectric;

[0074] 180, dielectric layer; 181, connection hole; 190, source layer.

[0075] The realization of the objectives, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0076] To make the purpose, technical solutions and advantages of the examples of the present application clearer, the technical solutions in the examples of the present application will be described clearly and completely below. Where specific conditions are not specified in the examples, conventional conditions or conditions recommended by the manufacturer are used. Where the manufacturer of the reagents or instruments is not specified, they are all conventional products that can be purchased commercially.

[0077] Below, the embodiments of the power MOS device and its manufacturing method of the present application are described in detail with appropriate reference to the accompanying drawings. However, unnecessary detailed descriptions may be omitted. For example, detailed descriptions of well-known matters and repeated descriptions of substantially identical structures may be omitted. This is to avoid the following description from becoming unnecessarily lengthy and to facilitate understanding by those skilled in the art. In addition, the accompanying drawings and the following description are provided to enable those skilled in the art to fully understand the present application and are not intended to limit the subject matter described in the claims.

[0078] The "ranges" disclosed herein are defined in terms of lower and upper limits, where a given range is defined by selecting a lower limit and an upper limit, and the selected lower and upper limits define the boundaries of the particular range. Ranges defined in this manner can be inclusive or exclusive of the end values ​​and can be combined arbitrarily, i.e., any lower limit can be combined with any upper limit to form a range. For example, if ranges of 60 to 120 and 80 to 110 are listed for a particular parameter, it is understood that ranges of 60 to 110 and 80 to 120 are also contemplated. Furthermore, if minimum range values ​​of 1 and 2 are listed, and if maximum range values ​​of 3, 4, and 5 are listed, the following ranges are all contemplated: 1 to 3, 1 to 4, 1 to 5, 2 to 3, 2 to 4, and 2 to 5. In this application, unless otherwise indicated, the numerical range "a to b" is a shorthand representation of any combination of real numbers between a and b, where a and b are both real numbers. For example, a numerical range of "0-5" indicates that all real numbers between "0-5" are listed herein, and "0-5" is simply an abbreviation for these numerical combinations. Furthermore, when a parameter is expressed as an integer ≥ 2, this is equivalent to disclosing that the parameter is, for example, an integer of 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, etc.

[0079] Unless otherwise specified, all embodiments and optional embodiments of the present application can be combined with each other to form a new technical solution.

[0080] Unless otherwise specified, all steps of the present application may be performed sequentially or randomly, preferably sequentially. For example, a method includes steps (a) and (b), which indicates that the method may include steps (a) and (b) performed sequentially, or may include steps (b) and (a) performed sequentially. For example, a method may further include step (c), which indicates that step (c) may be added to the method in any order, for example, the method may include steps (a), (b), and (c), or may include steps (a), (c), and (b), or may include steps (c), (a), and (b), etc.

[0081] To make the above-mentioned objects, features and advantages of the present application more clearly understood, the technical solutions of the present application are further described below with reference to the accompanying drawings and embodiments. However, the present application is not limited to the embodiments listed, but also includes any other known modifications within the scope of the rights claimed in the present application.

[0082] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0083] In conventional technology, when power MOS devices are operating at high power, the heat generated inside them is difficult to dissipate quickly and effectively, resulting in a significant increase in device temperature. This temperature increase not only weakens the performance of the device, but also poses a serious threat to the reliability and service life of the equipment. At the same time, the structural design of conventional power MOS devices has inherent limitations in terms of breakdown voltage. The low breakdown voltage restricts its widespread use in high-voltage applications. In addition, due to the weak heat dissipation capacity of the device itself, when the device size is reduced to the micro-nano scale, the problem of heat accumulation becomes more prominent, and performance often degrades significantly. These factors jointly restrict the further development of power MOS devices in high-performance, high-power density and high-voltage applications.

[0084] The embodiment of the present application provides a power MOS device. By providing a high thermal conductivity layer in the JFET region of the power MOS device, the heat generated by the device during operation can be quickly discharged, significantly reducing the thermal stress caused by local overheating, and effectively reducing the operating temperature of the device. At the same time, the high thermal conductivity layer adopts a unique stepped structure design. Compared with conventional regular area etching, the stepped structure can achieve higher etching accuracy and uniformity through step-by-step etching, reduce parasitic effects, and optimize the control of sidewall quality and etching depth. This stepped structure not only improves the stability and repeatability of the process, but also reduces etching damage, further improving the overall performance and reliability of the device.

[0085] The first embodiment of the present application provides a power MOS device, referring to Figure 1 ,include:

[0086] Drift layer 110 .

[0087] In one embodiment, the drift layer 110 is a crucial component of a power MOS device, primarily responsible for withstanding the high voltage across the device. It is typically composed of a semiconductor material with a low doping concentration. This design enables the drift layer 110 to maintain stable electrical performance under high voltage conditions. By precisely controlling the doping concentration and thickness of the drift layer 110, the device's breakdown voltage (BV) can be effectively adjusted to meet the withstand voltage requirements of different application scenarios. A low-doping drift layer 110 can significantly improve the device's withstand voltage capability, enabling it to operate safely in high-voltage environments.

[0088] The substrate layer 120 is disposed on the back side of the drift layer 110 .

[0089] In one embodiment, substrate layer 120 is the core infrastructure of a power MOS device. It is typically composed of a highly doped semiconductor material (such as silicon). This high doping property endows substrate layer 120 with exceptional physical and electrical properties. Physically, substrate layer 120 provides solid support for the device, ensuring structural stability and mechanical strength during complex manufacturing processes and long-term use. Electrically, substrate layer 120 plays a crucial role in isolation, effectively preventing leakage and suppressing parasitic effects, thereby ensuring that the device's electrical performance is not disrupted.

[0090] Optionally, the front side and the back side mentioned in the embodiments of the present application are two opposite directions, used to indicate the physical direction of the device and the relative positions of the functional layers.

[0091] Optionally, the front side may be a side surface of the power MOS device corresponding to the first direction, and the back side may be opposite to the front side, that is, a side surface away from the first direction.

[0092] Optionally, the front side may be the surface of the device that is first processed during the manufacturing process, and the back side may be the surface opposite to the front side.

[0093] The high thermal conductivity layer 130 is disposed on both sides of the drift layer 110 and the substrate layer 120 , wherein the high thermal conductivity layer 130 has a stepped structure.

[0094] In one embodiment, since the inherent on-resistance of the JFET region of the power MOS device will cause heat accumulation, but at the same time this region is not the main flow path of the current, therefore, in order to improve the heat dissipation capacity of the power MOS device, the embodiment of the present application sets a high thermal conductivity layer 130 made of a high thermal conductivity material in the JFET region of the power MOS device, so that the heat generated by the device during operation can be quickly discharged, significantly reducing the thermal stress caused by local overheating, and effectively reducing the operating temperature of the device, thereby optimizing the thermal management of the device. At the same time, in order to optimize the process of the MOS device, the embodiment of the present application sets the high thermal conductivity layer 130 to a stepped structure; compared with conventional regular area etching, the stepped structure can achieve higher etching accuracy and uniformity through step-by-step etching, reduce parasitic effects, and optimize the control of sidewall quality and etching depth. This stepped structure not only improves the stability and repeatability of the process, but also reduces etching damage, further improving the overall performance and reliability of the device.

[0095] The drain layer 140 is disposed on the backside of the substrate layer 120 and the high thermal conductivity layer 130 .

[0096] In one embodiment, the drain layer 140 is typically composed of a highly doped semiconductor material. Its primary function is to efficiently collect current transmitted from the drift layer 110 and stably conduct it to the external circuit. During device operation, the drain layer 140 is closely connected to the drift layer 110, and the two work together to withstand the high voltage across the device. This structural design not only ensures efficient current transmission but also further improves the stability and reliability of the device under high voltage conditions by optimizing the electrical properties of the drain layer 140.

[0097] The first channel layer 151 and the second channel layer 152 are disposed on the front sides of the high thermal conductivity layer 130 and the drift layer 110 .

[0098] In one embodiment, the channel layer (including the first channel layer 151 and the second channel layer 152) is a thin layer region in the MOS device that realizes current conduction, and is usually located below the gate layer. In an N-channel MOS device, the channel layer is composed of a P-type semiconductor material. Under the action of the gate voltage, an inversion layer is formed on the surface of the P-type semiconductor, which is transformed into an N-type conductive channel, thereby allowing current to flow from the source to the drain. On the contrary, in a P-channel MOS device, the channel layer is composed of an N-type semiconductor material, and an inversion layer is formed under the action of the gate voltage, which is transformed into a P-type conductive channel to realize current conduction. This channel design based on the inversion layer mechanism enables the MOS device to achieve efficient current transmission at extremely low on-resistance, while achieving precise switching control through the regulation of the gate voltage.

[0099] The P-type well 161 is disposed between the first channel layer 151 and the second channel layer 152 . An N-type doping region 162 is formed inside the P-type well 161 , and a P-type doping region 163 is formed inside the N-type doping region 162 .

[0100] In one embodiment, in an N-channel MOS device, the P-type well 161 is used to isolate different device units and prevent parasitic effects. It provides a substrate for the N-type source and drain. Under the action of a gate voltage, an inversion layer forms on the surface of the P-type well 161, i.e., an N-type conductive channel. Highly doped N-type regions formed within the P-type well 161 through diffusion or ion implantation can form a PN junction with the P-type well 161. When the gate voltage is sufficiently high, the inversion layer on the surface of the P-type well 161 connects to the N-type doped regions 162, forming a conductive channel. The P-type doped regions 163 formed within the N-type doped regions 162 can form a body diode junction with the N-type substrate. When the power MOS device is subjected to reverse voltage or current needs to flow in the reverse direction, the body diode can conduct, providing a freewheeling function and protecting the power MOS device from damage caused by reverse voltage and current.

[0101] The gate structure 170 is disposed on the front surface of the first channel layer 151 and the second channel layer 152 .

[0102] In one embodiment, gate structure 170 is the core control component of a power MOS device, capable of controlling the device's on and off states by applying voltage. For example, when the gate voltage reaches the threshold voltage, a conductive channel forms on the semiconductor surface beneath the gate, allowing current to flow from the source to the drain. Changes in gate voltage determine the device's switching speed and dynamic characteristics.

[0103] Illustratively, the gate structure 170 includes a first gate structure 170 (not shown in the drawings) and a second gate structure 170 (not shown in the drawings), which are respectively disposed on the front sides of the first channel layer 151 and the second channel layer 152 .

[0104] The dielectric layer 180 is disposed on the front surface of the gate structure 170 and covers the gate structure 170 . The dielectric layer 180 is provided with a connection hole 181 .

[0105] In one embodiment, the primary function of dielectric layer 180 is to isolate gate structure 170, prevent current leakage, and ensure that the gate voltage can effectively regulate channel formation. A high-quality dielectric layer 180 can withstand high voltages and prevent breakdown, thereby improving the device's withstand voltage capability.

[0106] Optionally, the dielectric layer 180 is provided with a connection hole 181 , and the N-type doping region 162 and the P-type doping region 163 are exposed through the connection hole 181 .

[0107] Exemplarily, the dielectric layer 180 includes a first dielectric layer 180 (not shown in the drawings) and a second dielectric layer 180 (not shown in the drawings), which are respectively arranged on the front sides of the first gate structure 170 and the second gate structure 170, and respectively cover the first gate structure 170 and the second gate structure 170.

[0108] The source layer 190 is disposed on the front surface of the dielectric layer 180 and contacts the N-type doping region 162 and the P-type doping region 163 through the connection hole 181 .

[0109] In one embodiment, the source layer 190 is the current outflow terminal of the power MOS device and is typically composed of highly doped N-type or P-type semiconductor material. Its doping type is closely related to the device's conductivity type. In an N-channel power MOS device, the source layer 190 acts as an electron injection terminal, responsible for injecting electrons into the channel layer, thereby enabling current transmission from the source to the drain. In a P-channel power MOS device, the source layer 190 acts as a hole injection terminal, injecting holes to enable current conduction. The high doping characteristics of the source layer 190 not only ensure low contact resistance, thereby reducing the device's conduction losses, but also improve the overall device performance by optimizing electrical characteristics.

[0110] In one feasible embodiment, the material of the high thermal conductivity layer 130 includes diamond.

[0111] As an emerging semiconductor material, diamond offers new possibilities for the development of power MOS devices due to its exceptional thermal management and electrical properties. The thermal conductivity of single-crystal diamond at room temperature is as high as 2400 W / (m·K), while the thermal conductivity of polycrystalline diamond is close to 2000 W / (m·K), making it an ideal high-thermal-conductivity material. During power device operation, diamond can rapidly conduct heat from the active region to the outside, effectively reducing the device's operating temperature and significantly improving its performance and reliability. Furthermore, diamond has an extremely high breakdown field strength of 10 MV / cm, which is 17 times that of gallium arsenide, twice that of gallium nitride, and 2.5 times that of silicon carbide. This high breakdown field strength gives diamond a significant advantage in high-voltage, high-power applications, significantly improving the device's voltage resistance and power capacity. Furthermore, diamond's wide bandgap (5.47 eV) and high carrier mobility (electron mobility up to 4500 cm) contribute significantly to its high performance. 2 / V·s) further enhances its potential for application in high-frequency, high-power semiconductor devices. By rationally selecting high-thermal conductivity materials and optimizing the structural design of high-thermal conductivity layer 130, the present embodiment enables the diamond high-thermal conductivity layer 130 to effectively address the thermal management issues faced by power MOS devices as they are scaled down to the micro- and nanoscale. Even at the micro- and nanoscale, the device maintains excellent performance, providing strong support for the development of high-performance and high-power density power MOS devices.

[0112] In one embodiment, the power MOS device further includes a gate dielectric 171 disposed between the gate structure 170 and the channel layer, wherein the channel layer includes the first channel layer 151 and / or the second channel layer 152. The most basic function of the gate dielectric 171 is to serve as an insulating layer, isolating the gate from the channel layer. This insulation prevents the gate current from flowing directly into the semiconductor substrate, thereby ensuring the voltage control characteristics of the device.

[0113] In one feasible embodiment, the thickness of the drift layer 110 is 10-15 um; for example, the thickness of the drift layer 110 is 10 um, 11 um, 12 um, 13 um, 14 um, 15 um, etc.

[0114] In one feasible embodiment, the thickness of the first channel layer 151 and the second channel layer 152 is 3-7 um; for example, 3 um, 4 um, 5 um, 6 um, 7 um, etc.

[0115] In one feasible implementation, the thickness of the gate structure 170 is 0.1-0.5 um; for example, the thickness of the gate structure 170 is 0.1 um, 0.2 um, 0.3 um, 0.4 um, 0.5 um, etc.

[0116] In one feasible implementation, the thickness of the dielectric layer 180 is 0.4-0.8 um; for example, the thickness of the dielectric layer 180 is 0.4 um, 0.5 um, 0.6 um, 0.7 um, 0.8 um, etc.

[0117] In one feasible embodiment, the thickness of the source layer 190 is 1-3 um; for example, the thickness of the source layer 190 is 1 um, 1.5 um, 2 um, 2.5 um, 3 um, etc.

[0118] In one feasible embodiment, the thickness of the drain electrode layer 140 is 1-3 um; for example, the thickness of the drain electrode layer 140 is 1 um, 1.5 um, 2 um, 2.5 um, 3 um, etc.

[0119] In one feasible embodiment, the material of the substrate layer 120 includes at least one of N-type silicon carbide, N-type gallium nitride, N-type aluminum nitride, and N-type silicon nitride.

[0120] In one feasible embodiment, the material of the drift layer 110 includes at least one of N-type silicon carbide, N-type gallium nitride, N-type gallium arsenide, N-type gallium oxide, N-type aluminum gallium nitride, and N-type aluminum nitride.

[0121] In one possible embodiment, the material of the gate structure 170 includes at least one of polysilicon, titanium nitride, tantalum nitride, tungsten, and cobalt.

[0122] In one possible embodiment, the material of the source layer 190 includes at least one of titanium, aluminum, copper, nickel, iridium, rhodium, ruthenium, platinum, gold, silver, palladium, and cobalt.

[0123] In one possible embodiment, the material of the drain electrode layer 140 includes at least one of titanium, aluminum, copper, nickel, iridium, rhodium, ruthenium, platinum, gold, silver, palladium, and cobalt.

[0124] In this embodiment, by providing a high thermal conductivity layer 130 in the JFET region of the power MOS device, the heat generated by the device during operation can be quickly dissipated, significantly reducing the thermal stress caused by local overheating, and effectively lowering the operating temperature of the device. At the same time, the high thermal conductivity layer 130 adopts a unique stepped structure design. Compared with conventional regular area etching, the stepped structure can achieve higher etching accuracy and uniformity through step-by-step etching, reduce parasitic effects, and optimize the control of sidewall quality and etching depth. This stepped structure not only improves the stability and repeatability of the process, but also reduces etching damage, further improving the overall performance and reliability of the device.

[0125] The second embodiment of the present application provides a method for preparing a power MOS device, referring to Figure 2 , including the following steps:

[0126] In step S10 , a substrate layer 120 is provided, and a drift layer 110 and a channel layer 150 are sequentially formed on the front surface of the substrate layer 120 .

[0127] In one embodiment, referring to Figure 3 , providing a clean substrate layer 120, and growing an epitaxial layer on the front surface of the substrate layer 120 to serve as a drift layer 110, wherein the N-type doping concentration of the drift layer 110 is 1e14-1e16 cm -3 The drift layer 110 is made of at least one of N-type silicon carbide, N-type gallium nitride, N-type gallium arsenide, N-type gallium oxide, N-type aluminum gallium nitride, and N-type aluminum nitride. Furthermore, a channel layer 150 is formed on the front surface of the drift layer 110 .

[0128] Optionally, the material of the substrate layer 120 includes at least one of N-type silicon carbide, N-type gallium nitride, N-type aluminum nitride, and N-type silicon nitride.

[0129] Optionally, the N-type doping concentration of the substrate layer 120 is 1e17-1e19 cm -3 .

[0130] Optionally, the drift layer 110 has a thickness of 10-15 um.

[0131] Optionally, the thickness of the channel layer 150 is 3-7 um.

[0132] Optionally, a portion of the drift layer 110 located at the surface is formed into the channel layer 150 by ion implantation and high-temperature activation.

[0133] In step S20 , a P-type doping is performed on a portion of the channel layer 150 to obtain a P-type well 161 .

[0134] In one feasible embodiment, a portion of the channel layer 150 is doped with P-type to obtain a P-type well 161, wherein the doping concentration of the P-type well 161 is 1e17-5e17 cm -3 .

[0135] In one feasible embodiment, step S20, performing P-type doping on a portion of the channel layer 150 to obtain the P-type well 161, includes:

[0136] Step S21 , forming a first oxide layer 153 on the front surface of the channel layer 150 ;

[0137] Step S22, defining a first photoresist pattern 154 on the front surface of the first oxide layer 153;

[0138] Step S23, etching the first oxide layer 153 based on the first photoresist pattern 154 to form an injection window for the P-type well 161;

[0139] In step S24 , the channel layer 150 exposed to the implantation window of the P-type well 161 is subjected to P-type doping to obtain the P-type well 161 .

[0140] In one possible embodiment, referring to Figure 4 , deposited on the front side of the channel layer 150 The first oxide layer 153 is formed, and a first photoresist pattern 154 is defined on the front surface of the first oxide layer 153. The first photoresist pattern 154 is used as an anti-etching layer to etch the first oxide layer 153 to form a P-type well 161 injection window (not shown in the drawings); and then the channel layer 150 exposed to the P-type well 161 injection window is subjected to a 1e17-5e17 / cm -3 The P-type well 161 is obtained by doping with a P-type doping concentration.

[0141] In step S30 , N-type doping is performed on a portion of the P-type well 161 to obtain an N-type doped region 162 .

[0142] In one embodiment, a 1e18-1e19 cm -3 The N-type doping concentration is obtained to obtain the N-type doping region 162.

[0143] In one feasible implementation, before step S30 of performing N-type doping on a portion of the P-type well 161, the method further includes:

[0144] Step S31, forming a second oxide layer of a first thickness on the front surface of the first oxide layer 153;

[0145] In step S32 , the second oxide layer is etched to a first thickness to form sidewall spacers 155 on both sides of the implantation window of the P-type well 161 .

[0146] In one possible embodiment, referring to Figure 5 , remove the first photoresist pattern 154, and prepare a first thickness (for example, ) and etch the second oxide layer of the first thickness to form the sidewalls 155 on both sides of the injection window of the P-type well 161. Figure 6 , shielded by the sidewall 155 , a portion of the P-type well 161 exposed to the injection window of the P-type well 161 is N-doped to obtain an N-type doped region 162 .

[0147] In step S40 , a portion of the N-type doping region 162 is subjected to P-type doping to obtain a P-type doping region 163 .

[0148] In one possible embodiment, referring to Figure 7 1e18~1e19 cm is injected into part of the N-type doping region 162 by photolithography. -3 The concentration of P-type impurities is increased to achieve P-type doping and obtain a P-type doped region 163.

[0149] In one feasible embodiment, before the step of sequentially preparing the gate structure 170 and the dielectric layer 180 on the front surface of the channel layer 150 in step S50, the following steps are further included: Figure 7 , remove the first oxide layer 153 and the sidewall 155, and thermally grow a layer on the front surface of the channel layer 150 Thermal oxide is used as the gate dielectric 171.

[0150] In step S50 , a gate structure 170 and a dielectric layer 180 are sequentially formed on the front surface of the channel layer 150 , wherein the dielectric layer 180 covers the gate structure 170 .

[0151] In one feasible embodiment, a gate structure 170 and a dielectric layer 180 covering the gate structure 170 are sequentially prepared on the front surface of the channel layer 150 .

[0152] In one feasible embodiment, step S50, the steps of sequentially forming the gate structure 170 and the dielectric layer 180 on the front surface of the channel layer 150, include:

[0153] Step S51 , preparing a gate layer on the front surface of the channel layer 150 ;

[0154] Step S52, etching the gate layer to obtain a gate structure 170;

[0155] In one possible embodiment, referring to Figure 8 A gate layer is deposited on the front surface of the channel layer 150 and a gate structure 170 is obtained by etching.

[0156] Step S53 , forming a dielectric layer 180 on the front surface of the gate structure 170 .

[0157] In one possible embodiment, referring to Figure 9 , a dielectric layer 180 is deposited on the front surface of the gate structure 170 to cover the gate structure 170 .

[0158] In step S60 , regions on both sides of the substrate layer 120 and the drift layer 110 are etched respectively to form a stepped structure.

[0159] In one possible embodiment, referring to Figure 10 , switching to the backside process, the substrate layer 120 and drift layer 110 in the JFET region are removed through multiple photolithographic etchings to form a stepped structure. Compared to conventional regular area etching, the stepped structure can achieve higher etching accuracy and uniformity through step-by-step etching, reduce parasitic effects, and optimize the control of sidewall quality and etching depth. This stepped structure not only improves process stability and repeatability, but also reduces etching damage, further improving the overall performance and reliability of the device.

[0160] Step S70 , preparing a high thermal conductivity layer 130 in the area corresponding to the stepped structure.

[0161] In one possible embodiment, referring to Figure 11 , the area corresponding to the stepped structure is filled with a high thermal conductivity material to form a high thermal conductivity layer 130, wherein the material of the high thermal conductivity layer 130 includes: diamond, for example, polycrystalline diamond, single crystal gold stone lamp. It can be understood that, Figure 11 The blue and green blocks included in the high thermal conductivity layer 130 are intended to highlight the stepped structure of the high thermal conductivity layer 130 . Both the blue and green blocks belong to the high thermal conductivity layer 130 .

[0162] Step S80 , etching the dielectric layer 180 to obtain the connection hole 181 .

[0163] In one possible embodiment, referring to Figure 12 , returning to the front side process, the dielectric layer 180 is etched to obtain a connection hole 181 , wherein the N-type doping region 162 and the P-type doping region 163 are exposed through the connection hole 181 .

[0164] In step S90 , a source layer 190 is prepared to obtain a power MOS device, wherein the source layer 190 contacts the N-type doping region 162 and the P-type doping region 163 through the connection hole 181 .

[0165] In one possible embodiment, referring to Figure 1 , prepare a source layer 190, and make the source layer 190 contact the N-type doping region 162 and the P-type doping region 163 through the connection hole 181 to obtain a power MOS device.

[0166] In this embodiment, by providing a high thermal conductivity layer 130 in the JFET region of the power MOS device, the heat generated by the device during operation can be quickly dissipated, significantly reducing the thermal stress caused by local overheating, and effectively lowering the operating temperature of the device. At the same time, the high thermal conductivity layer 130 adopts a unique stepped structure design. Compared with conventional regular area etching, the stepped structure can achieve higher etching accuracy and uniformity through step-by-step etching, reduce parasitic effects, and optimize the control of sidewall quality and etching depth. This stepped structure not only improves the stability and repeatability of the process, but also reduces etching damage, further improving the overall performance and reliability of the device.

[0167] The above are only preferred embodiments of the present application and are not intended to limit the scope of the present invention. Those skilled in the art will readily appreciate that various modifications and variations are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of the present invention.

Claims

1. A power MOS device, characterized in that: The power MOS device includes: drift layer; a substrate layer, disposed on the back side of the drift layer; a high thermal conductivity layer, disposed on both sides of the drift layer and the substrate layer, wherein the high thermal conductivity layer has a stepped structure; a drain electrode layer, disposed on the back side of the substrate layer; A first channel layer and a second channel layer are provided on the front surface of the high thermal conductivity layer; A P-type well is provided between the first channel layer and the second channel layer, an N-type doped region is formed inside the P-type well, and a P-type doped region is formed inside the N-type doped region, wherein the steps of preparing the P-type well include: preparing a first oxide layer on the front surface of the channel layer; defining a first photoresist pattern on the front surface of the first oxide layer; etching the first oxide layer based on the first photoresist pattern to form a P-type well injection window; and performing P-type doping on the channel layer exposed to the P-type well injection window to obtain the P-type well; a gate structure, disposed on the front sides of the first channel layer and the second channel layer; a dielectric layer, disposed on the front surface of the gate structure and covering the gate structure; the dielectric layer is provided with a connection hole; The source layer is arranged on the front side of the dielectric layer and contacts the N-type doping region and the P-type doping region through the connection hole.

2. The power MOS device according to claim 1, wherein: The material of the high thermal conductivity layer includes: diamond.

3. The power MOS device according to claim 1, wherein: The power MOS device further includes: a gate dielectric disposed between the gate structure and the channel layer, wherein the channel layer includes a first channel layer and / or a second channel layer.

4. The power MOS device according to claim 1, wherein: The thickness of the drift layer is 10 to 15 μm; And / or, the thickness of the first channel layer and the second channel layer is 3-7 μm; And / or, the thickness of the gate structure is 0.1 to 0.5 μm; And / or, the thickness of the dielectric layer is 0.4 to 0.8 μm; And / or, the thickness of the source layer is 1 to 3 μm; And / or, the drain layer has a thickness of 1 to 3 μm.

5. The power MOS device according to claim 1, wherein: The material of the substrate layer includes: at least one of N-type silicon carbide, N-type gallium nitride, N-type aluminum nitride, and N-type silicon nitride; And / or, the material of the drift layer includes: at least one of N-type silicon carbide, N-type gallium nitride, N-type gallium arsenide, N-type gallium oxide, N-type aluminum gallium nitride and N-type aluminum nitride; And / or, the material of the gate structure includes: at least one of polysilicon, titanium nitride, tantalum nitride, tungsten and cobalt; And / or, the material of the source layer includes: at least one of titanium, aluminum, copper, nickel, iridium, rhodium, ruthenium, platinum, gold, silver, palladium and cobalt; And / or, the material of the drain electrode layer includes at least one of titanium, aluminum, copper, nickel, iridium, rhodium, ruthenium, platinum, gold, silver, palladium and cobalt.

6. A method for preparing a power MOS device, characterized in that: The method for preparing a power MOS device is used to prepare the power MOS device according to any one of claims 1 to 5, comprising the following steps: Providing a substrate layer, and sequentially preparing a drift layer and a channel layer on the front surface of the substrate layer; forming a first oxide layer on the front surface of the channel layer; defining a first photoresist pattern on the front surface of the first oxide layer; Etching the first oxide layer based on the first photoresist pattern to form a P-type well injection window; Performing P-type doping on the channel layer exposed to the P-type well implantation window to obtain the P-type well; Performing N-type doping on a portion of the P-type well to obtain an N-type doped region; Performing P-type doping on a portion of the N-type doping region to obtain a P-type doping region; A gate structure and a dielectric layer are sequentially prepared on the front surface of the channel layer, wherein the dielectric layer covers the gate structure; Etching the substrate layer and the drift layer on both sides to form a stepped structure; preparing a high thermal conductivity layer in the area corresponding to the stepped structure; etching the dielectric layer to obtain a connection hole; A source layer is prepared to obtain a power MOS device, wherein the source layer contacts the N-type doping region and the P-type doping region through the connection hole.

7. The method for preparing a power MOS device according to claim 6, wherein: Before the step of performing N-type doping on a portion of the P-type well, the method further includes: forming a second oxide layer of a first thickness on the front surface of the first oxide layer; The second oxide layer having a first thickness is etched to form sidewalls located on both sides of the P-type well injection window.

8. The method for preparing a power MOS device according to claim 6, wherein: The step of sequentially preparing a gate structure and a dielectric layer on the front surface of the channel layer comprises: preparing a gate layer on the front side of the channel layer; Etching the gate layer to obtain the gate structure; The dielectric layer is prepared on the front side of the gate structure.

9. The method for preparing a power MOS device according to claim 6, wherein: The N-type doping concentration of the substrate layer is 1e17-1e19 cm -3 ; And / or, the N-type doping concentration of the drift layer is 1e14-1e16 cm -3 ; And / or, the doping concentration of the P-type doping in the partial region of the channel layer is 1e17-5e17 cm -3 ; And / or, the N-type doping concentration of the partial region of the P-type well is 1e18-1e19 cm -3 ; And / or, the doping concentration of the P-type doping in the partial area of ​​the N-type doping region is 1e18-1e19 cm -3 .

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