Power MOS device and preparation method thereof

Abstract

The invention discloses a power MOS (Metal Oxide Semiconductor) device and a preparation method thereof, relates to the technical field of semiconductors, and discloses the power MOS device which comprises a drift layer; the first substrate layer and the second substrate layer are respectively arranged on two sides of the drift layer; the drain electrode layer is arranged on the back surface of the drift layer; the first channel layer and the second channel layer are respectively arranged on the front surfaces of the first substrate layer and the second substrate layer; the P-type well is arranged between the first channel layer and the second channel layer, an N-type doped region is formed in the P-type well, and a P-type doped region is formed in the N-type doped region; the gate structure is arranged on the front surfaces of the first channel layer and the second channel layer; the dielectric layer is arranged on the front surface of the gate structure and wraps the gate structure; the dielectric layer is provided with a connecting hole; and the source electrode layer is arranged on the front surface of the dielectric layer and is in contact with the N-type doped region and the P-type doped region through connecting holes. According to the invention, the heat dissipation capability of the power MOS device is effectively improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a power MOS device and a method for manufacturing the same. Background Art

[0002] In the modern power electronics field, power MOS (Metal-Oxide-Semiconductor) devices are widely used due to their advantages such as high efficiency, fast switching speed, and easy driving. These characteristics make power MOS devices an essential part from consumer electronics to industrial applications. However, with technological progress and changing market demands, the need for higher power density and smaller size is increasing continuously, which poses new challenges to traditional power MOS structures.

[0003] One of the main problems focuses on heat management. In conventional power MOS structures, the heat generated during high-power operation is difficult to dissipate quickly, resulting in an increase in device temperature, which not only affects performance but also threatens the reliability and service life of the equipment. Summary of the Invention

[0004] The main objective of this application is to provide a power MOS device and a method for manufacturing the same, aiming to effectively improve the heat dissipation ability of the power MOS device.

[0005] To achieve the above objective, an embodiment of this application provides a power MOS device, including:

[0006] Drift layer;

[0007] A first substrate layer and a second substrate layer, respectively disposed on both sides of the drift layer, wherein the material of the first substrate layer and / or the second substrate layer is a high thermal conductivity material;

[0008] Drain layer, disposed on the back surface of the drift layer;

[0009] A first channel layer and a second channel layer, respectively disposed on the front surfaces of the first substrate layer and the second substrate layer;

[0010] P-type well, disposed between the first channel layer and the second channel layer, an N-type doped region is formed inside the P-type well, and a P-type doped region is formed inside the N-type doped region;

[0011] Gate structure, disposed on the front surfaces of the first channel layer and the second channel layer;

[0012] Dielectric layer, disposed on the front surface of the gate structure and covering the gate structure; the dielectric layer is provided with connection holes;

[0013] The source layer is disposed on the front side of the dielectric layer and is in contact with the N-type doped region and the P-type doped region through the connection hole.

[0014] In one embodiment, the material of the first substrate layer and / or the second substrate layer includes: diamond.

[0015] In one embodiment, the power MOS device further includes: a gate dielectric disposed between the gate structure and the channel layer, wherein the channel layer includes a first channel layer and / or a second channel layer.

[0016] In one embodiment, the thickness of the drift layer is 10 - 15 um;

[0017] And / or, the thickness of the first channel layer and the second channel layer is 3 - 7 um;

[0018] And / or, the thickness of the gate structure is 0.1 - 0.5 um;

[0019] And / or, the thickness of the dielectric layer is 0.4 - 0.8 um;

[0020] And / or, the thickness of the source layer is 1 - 3 um;

[0021] And / or, the thickness of the drain layer is 1 - 3 um.

[0022] In one embodiment, the material of the drift layer includes at least one of: N-type silicon carbide, N-type gallium nitride, N-type gallium arsenide, N-type gallium oxide, N-type aluminum gallium nitride, and N-type aluminum nitride;

[0023] And / or, the material of the gate structure includes at least one of: polysilicon, titanium nitride, tantalum nitride, tungsten, and cobalt;

[0024] And / or, the material of the source layer includes at least one of: titanium, aluminum, copper, nickel, iridium, rhodium, ruthenium, platinum, gold, silver, palladium, and cobalt;

[0025] And / or, the material of the drain layer includes at least one of: titanium, aluminum, copper, nickel, iridium, rhodium, ruthenium, platinum, gold, silver, palladium, and cobalt.

[0026] To achieve the above object, an embodiment of the present application provides a method for manufacturing a power MOS device for manufacturing the power MOS device as described above, and the method for manufacturing the power MOS device includes the following steps:

[0027] Etch the substrate layer to form a trench, wherein the material of the substrate layer is a high thermal conductivity material;

[0028] Prepare a drift layer in the trench;

[0029] Prepare a channel layer on the front side of the substrate layer and the drift layer;

[0030] Perform P-type doping on a partial area of the channel layer to obtain a P-type well;

[0031] Perform N-type doping on a partial area of the P-type well to obtain an N-type doped region;

[0032] Perform P-type doping on a partial area of the N-type doped region to obtain a P-type doped region;

[0033] Prepare a gate structure and a dielectric layer in sequence on the front side of the channel layer, wherein the dielectric layer coats the gate structure;

[0034] Etch the dielectric layer to obtain a contact hole;

[0035] Prepare a source layer, wherein the source layer is in contact with the N-type doped region and the P-type doped region through the contact hole;

[0036] Remove the substrate layer on the back side of the drift layer to expose the drift layer;

[0037] Prepare a drain layer on the back side of the drift layer to obtain a power MOS device.

[0038] In one embodiment, the step of performing P-type doping on a partial area of the channel layer to obtain a P-type well includes:

[0039] Prepare a first oxide layer on the front side of the channel layer;

[0040] Define a first photoresist pattern on the front side of the first oxide layer;

[0041] Etch the first oxide layer based on the first photoresist pattern to form a P-type well implantation window;

[0042] Perform P-type doping on the channel layer exposed to the P-type well implantation window to obtain the P-type well.

[0043] In one embodiment, before the step of performing N-type doping on a partial area of the P-type well, it further includes:

[0044] Prepare a second oxide layer with a first thickness on the front side of the first oxide layer;

[0045] Etch the second oxide layer with the first thickness to form sidewalls located on both sides of the P-type well implantation window.

[0046] In one embodiment, the step of preparing a gate structure and a dielectric layer in sequence on the front side of the channel layer includes:

[0047] Prepare a gate layer on the front side of the channel layer;

[0048] Etch the gate layer to obtain the gate structure;

[0049] Prepare the dielectric layer on the front side of the gate structure.

[0050] In one embodiment, the doping concentration of P-type doping for a partial region of the channel layer is 1e17 - 5e17 cm -3 ;

[0051] And / or, the doping concentration of N-type doping for a partial region of the P-type well is 1e18 - 1e19 cm -3 ;

[0052] And / or, the doping concentration of P-type doping for a partial region of the N-type doping region is 1e18 - 1e19cm -3 .

[0053] The embodiment of the present application provides a power MOS device, including: a drift layer; a first substrate layer and a second substrate layer, which are respectively disposed on both sides of the drift layer, wherein the material of the first substrate layer and / or the second substrate layer is a high thermal conductivity material; a drain layer, disposed on the back side of the drift layer; a first channel layer and a second channel layer, which are respectively disposed on the front sides of the first substrate layer and the second substrate layer; a P-type well, disposed between the first channel layer and the second channel layer, an N-type doping region is formed inside the P-type well, and a P-type doping region is formed inside the N-type doping region; a gate structure, disposed on the front sides of the first channel layer and the second channel layer; a dielectric layer, disposed on the front side of the gate structure and covering the gate structure; a connection hole is provided on the dielectric layer; a source layer, disposed on the front side of the dielectric layer and contacting the N-type doping region and the P-type doping region through the connection hole. In a power MOS device, although the JFET (Junction Field-Effect Transistor) region is not the main current conduction path, its inherent on-resistance will still cause heat accumulation, thereby affecting the overall thermal performance of the device. To effectively solve this problem, the embodiment of the present application can quickly export the heat generated during the operation of the device by providing the first substrate layer and the second substrate layer made of high thermal conductivity materials in the JFET region of the power MOS device, significantly reduce the thermal stress generated by local overheating, and thus effectively reduce the operating temperature of the device. By optimizing thermal management, the long-term reliability of the device is significantly improved, providing a strong guarantee for the performance stability under high-power operating conditions. Description of the Drawings

[0054] Figure 1It is a schematic structural diagram of a power MOS device related to the solution of the embodiment of the present application;

[0055] Figure 2 It is a flowchart of a method for manufacturing a power MOS device related to the solution of the embodiment of the present application;

[0056] Figure 3 It is the process flow of a method for manufacturing a power MOS device related to the solution of the embodiment of the present application Figure 1 ;

[0057] Figure 4 It is the process flow of a method for manufacturing a power MOS device related to the solution of the embodiment of the present application Figure 2 ;

[0058] Figure 5 It is the process flow of a method for manufacturing a power MOS device related to the solution of the embodiment of the present application Figure 3 ;

[0059] Figure 6 It is the process flow of a method for manufacturing a power MOS device related to the solution of the embodiment of the present application Figure 4 ;

[0060] Figure 7 It is the process flow of a method for manufacturing a power MOS device related to the solution of the embodiment of the present application Figure 5 ;

[0061] Figure 8 It is the process flow of a method for manufacturing a power MOS device related to the solution of the embodiment of the present application Figure 6 ;

[0062] Figure 9 It is the process flow of a method for manufacturing a power MOS device related to the solution of the embodiment of the present application Figure 7 ;

[0063] Figure 10 It is the process flow of a method for manufacturing a power MOS device related to the solution of the embodiment of the present application Figure 8 ;

[0064] Figure 11 It is the process flow of a method for manufacturing a power MOS device related to the solution of the embodiment of the present application Figure 9 ;

[0065] Figure 12 It is the process flow of a method for manufacturing a power MOS device related to the solution of the embodiment of the present application Figure 10 ;

[0066] Figure 13 It is the process flow of a method for manufacturing a power MOS device related to the solution of the embodiment of the present application Figure 10 One;

[0067] Figure 14 This is the process flow of the method for manufacturing a power MOS device according to the embodiment of the present application. Figure 10 II.

[0068] Figure 15 This is the process flow of the method for manufacturing a power MOS device according to the embodiment of the present application. Figure 10 III.

[0069] Explanation of reference numerals:

[0070] 110, drift layer; 120, substrate layer;

[0071] 121, first substrate layer; 122, second substrate layer; 123, trench;

[0072] 130, drain layer; 140, channel layer; 141, first channel layer; 142, second channel layer;

[0073] 143, first oxide layer; 144, first photoresist pattern; 145, sidewall;

[0074] 151, P-type well; 152, N-type doped region; 153, P-type doped region;

[0075] 160, gate structure; 161, gate dielectric;

[0076] 170, dielectric layer; 171, via hole; 180, source layer.

[0077] The realization of the object of the present application, functional features and advantages will be further described in conjunction with the embodiments with reference to the drawings. Detailed implementation manners

[0078] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below. Those not specified in the embodiments are carried out according to conventional conditions or conditions recommended by the manufacturer. Those reagents or instruments not specified by the manufacturer can all be obtained as conventional products through commercial purchase.

[0079] Hereinafter, the embodiments of the power MOS device and its manufacturing method of the present application will be specifically disclosed in detail with appropriate reference to the drawings. However, there may be cases where unnecessary detailed descriptions are omitted. For example, there are cases where detailed descriptions of well-known matters are omitted and repeated descriptions of actually identical structures are omitted. This is to avoid the following description from becoming unnecessarily lengthy and to facilitate the understanding of those skilled in the art. In addition, the drawings and the following description are provided for those skilled in the art to fully understand the present application and are not intended to limit the subject matter described in the claims.

[0080] The "ranges" disclosed in this application are defined in the form of a lower limit and an upper limit. A given range is defined by selecting a lower limit and an upper limit, and the selected lower limit and upper limit define the boundaries of a particular range. The ranges defined in this way can include or exclude the end values, and can be combined arbitrarily, that is, any lower limit can be combined with any upper limit to form a range. For example, if ranges of 60-120 and 80-110 are listed for a specific parameter, ranges of 60-110 and 80-120 are also contemplated. In addition, if the minimum range values 1 and 2 are listed, and if the maximum range values 3, 4, and 5 are listed, the following ranges are all contemplated: 1-3, 1-4, 1-5, 2-3, 2-4, and 2-5. In this application, unless otherwise specified, the numerical range "a-b" represents an abbreviated representation of any real number combination between a and b, where a and b are both real numbers. For example, the numerical range "0-5" means that all real numbers between "0-5" are fully listed herein, and "0-5" is only an abbreviated representation of these numerical combinations. Additionally, when stating that a certain parameter is an integer ≥2, it is equivalent to disclosing that the parameter is, for example, the integers 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, etc.

[0081] If there is no special instruction, all embodiments and optional embodiments of this application can be combined with each other to form new technical solutions.

[0082] If there is no special instruction, all steps of this application can be carried out in sequence or randomly, preferably in sequence. For example, the method includes steps (a) and (b), which means that the method can include steps (a) and (b) carried out in sequence, or can also include steps (b) and (a) carried out in sequence. For example, it is mentioned that the method may further include step (c), which means that step (c) can be added to the method in any order. For example, the method can include steps (a), (b), and (c), or can also include steps (a), (c), and (b), or can also include steps (c), (a), and (b), etc.

[0083] To make the above objects, features, and advantages of this application more obvious and understandable, the technical solutions of this application will be further described below in conjunction with the accompanying drawings and embodiments. However, this application is not limited to the listed embodiments, and should also include any other well-known changes within the scope of the rights required by this application.

[0084] To better understand the technical solutions of this application, the following will be described in detail in conjunction with the accompanying drawings of the specification and specific embodiments.

[0085] In conventional technology, when power MOS devices are running at high power, their internal heat is difficult to dissipate quickly, causing the device temperature to rise significantly. This not only affects the performance of the device, but also threatens the reliability and service life of the equipment. In addition, the structure of traditional power MOS devices has limitations in terms of breakdown voltage, and the low breakdown voltage limits its application in high-voltage application scenarios. At the same time, due to the weak heat dissipation capacity of the device, when the device size is reduced to the micro-nano scale, the performance often degrades due to heat accumulation.

[0086] The embodiment of the present application provides a power MOS device, which can quickly conduct away the heat generated by the device when it is working by setting a first substrate layer and a second substrate layer made of a high thermal conductivity material in the JFET region of the power MOS device, significantly reducing the thermal stress caused by local overheating, thereby effectively reducing the operating temperature of the device. By optimizing thermal management, the long-term reliability of the device can be significantly improved, providing a strong guarantee for the performance stability under high-power operation.

[0087] The first embodiment of the present application provides a power MOS device, referring to Figure 1 ,include:

[0088] Drift layer 110 .

[0089] In one embodiment, the drift layer 110 is a key area in the power MOS device for withstanding high voltage, and is usually composed of a low-doped semiconductor material. The main function of the drift layer 110 is to withstand the high voltage at both ends of the device. By controlling the doping concentration and thickness of the drift layer 110, the breakdown voltage (BV) of the device can be adjusted. The drift layer 110 with a low doping concentration can increase the withstand voltage of the device, but at the same time increase the on-resistance. When the device is turned on, the drift layer 110 is one of the main channels for current to flow from the drain to the source. Its resistance characteristics directly affect the conduction loss of the device.

[0090] The first substrate layer 121 and the second substrate layer 122 are respectively disposed on two sides of the drift layer 110 , wherein the material of the first substrate layer 121 and / or the second substrate layer 122 is a high thermal conductive material.

[0091] In one embodiment, the substrate layer (including the first substrate layer 121 and the second substrate layer 122) is the basic structure of the device, usually composed of a highly doped semiconductor material (such as silicon), which provides physical support for the device, ensuring the stability of the device during manufacturing and use; at the same time, it can also provide good electrical isolation to prevent leakage and parasitic effects. In the embodiment of the present application, by arranging the substrate layer on both sides of the drift layer 110 of the main current channel and using a high thermal conductivity material, the heat generated during the operation of the device can be quickly exported, significantly reducing the thermal stress caused by local overheating, and effectively reducing the operating temperature of the device, realizing the optimization of device thermal management.

[0092] The drain layer 130 is disposed on the back surface of the drift layer 110.

[0093] In one embodiment, the drain layer 130 is the negative electrode region of the power MOS device, usually composed of a highly doped semiconductor material. Its main function is to collect the current transmitted from the drift layer 110 and lead it out to the external circuit. The drain layer 130 is usually connected to the drift layer 110 and jointly bears the high voltage across the device.

[0094] Optionally, the front and back mentioned in the embodiment of the present application are two opposite directions, used to indicate the physical direction of the device and the relative position of the functional layers.

[0095] Optionally, the front can be the side surface corresponding to the first direction of the MOS device, and the back can be the side surface opposite to the front, that is, the side surface far from the first direction.

[0096] Optionally, the front can also be the surface that is first processed during the manufacturing process of the device, and the back can be the surface opposite to the front.

[0097] The first channel layer 141 and the second channel layer 142 are respectively disposed on the front surfaces of the first substrate layer 121 and the second substrate layer 122.

[0098] In one embodiment, the channel layer (including the first channel layer 141 and the second channel layer 142) is the thin layer region for conducting current in the MOS device, usually located under the gate layer. In an N-channel MOS device, the channel layer is formed by a P-type semiconductor material to form an inversion layer (i.e., an N-type conductive channel) under the action of the gate voltage, thereby allowing current to flow from the source to the drain. In a P-channel MOS device, the channel layer is formed by an N-type semiconductor material to form an inversion layer (i.e., a P-type conductive channel) under the action of the gate voltage.

[0099] The P-type well 151 is disposed between the first channel layer 141 and the second channel layer 142. An N-type doping region 152 is formed inside the P-type well 151, and a P-type doping region 153 is formed inside the N-type doping region 152.

[0100] In one embodiment, in an N-channel MOS device, the P-type well 151 is used to isolate different device units and prevent parasitic effects. It provides a substrate for the N-type source and drain. Meanwhile, under the action of the gate voltage, an inversion layer, i.e., an N-type conductive channel, will be formed on the surface of the P-type well 151. And the highly doped N-type region formed inside the P-type well 151 through diffusion or ion implantation processes can form a PN junction with the P-type well 151. When the gate voltage is high enough, the inversion layer on the surface of the P-type well 151 will connect these N-type doped regions 152 to form a conductive channel. And the P-type doped region 153 formed inside the N-type doped region 152 can form a body diode junction with the N-type substrate. When the power MOS device bears a reverse voltage or the current needs to flow in the reverse direction, the body diode can conduct to play a freewheeling role and protect the power MOS device from damage by reverse voltage and current.

[0101] The gate structure 160 is disposed on the front surfaces of the first channel layer 141 and the second channel layer 142.

[0102] In one embodiment, the gate structure 160 is the core control part of the power MOS device and can control the on and off states of the device by applying a voltage. For example, when the gate voltage reaches the threshold voltage, a conductive channel will be formed on the semiconductor surface under the gate, allowing current to flow from the source to the drain. And the change of the gate voltage determines the switching speed and dynamic characteristics of the device.

[0103] Exemplarily, the gate structure 160 includes a first gate structure 160 (not shown in the drawings) and a second gate structure 160 (not shown in the drawings), and are respectively disposed on the front surfaces of the first channel layer 141 and the second channel layer 142.

[0104] The dielectric layer 170 is disposed on the front surface of the gate structure 160 and wraps the gate structure 160; the dielectric layer 170 is provided with a connection hole 171.

[0105] In one embodiment, the main function of the dielectric layer 170 is to isolate the gate structure 160, prevent current leakage, and ensure that the gate voltage can effectively regulate the formation of the channel. And a high-quality dielectric layer 170 can withstand high voltages and prevent breakdown, thereby improving the breakdown voltage capability of the device.

[0106] Optionally, the dielectric layer 170 is provided with a connection hole 171, and the N-type doped region 152 and the P-type doped region 153 are exposed through the connection hole 171.

[0107] Exemplarily, the dielectric layer 170 includes a first dielectric layer 170 (not shown in the drawings) and a second dielectric layer 170 (not shown in the drawings), and are respectively disposed on the front surfaces of the first gate structure 160 and the second gate structure 160, and respectively wrap the first gate structure 160 and the second gate structure 160.

[0108] The source layer 180 is disposed on the front surface of the dielectric layer 170 and contacts the N-type doped region 152 and the P-type doped region 153 through the via hole 171.

[0109] In one embodiment, the source layer 180 is the current outflow end of the power MOS device and is usually composed of a highly doped N-type or P-type semiconductor material. In an N-channel MOS device, the source serves as the electron injection end; in a P-channel MOS device, the source serves as the hole injection end.

[0110] In a feasible embodiment, the material of the first substrate layer 121 and / or the second substrate layer 122 includes: diamond. As an emerging semiconductor material, diamond exhibits significant advantages in terms of heat conduction and high breakdown field strength when used as a substrate material in MOS devices. First of all, diamond has an extremely high thermal conductivity. The thermal conductivity of single-crystal diamond is as high as 2400 W / (m·K) at room temperature, and the thermal conductivity of polycrystalline diamond is also close to 2000 W / (m·K). This property makes it an ideal heat dissipation substrate. In power devices, diamond can quickly conduct heat away from the active region, effectively reducing the device operating temperature, thereby improving the performance and reliability of the device. In addition, diamond has an extremely high breakdown field strength, reaching 10 MV / cm, which is 17 times that of gallium arsenide, 2 times that of gallium nitride, and 2.5 times that of silicon carbide. This high breakdown field strength property enables diamond to perform excellently in high-voltage and high-power application scenarios, significantly enhancing the voltage withstand capacity and power capacity of the device. At the same time, the wide bandgap (5.47 eV) and high carrier mobility (the electron mobility can reach 4500 cm 2 / V·s) of diamond further enhance its application potential in high-frequency and high-power semiconductor devices. At the same time, through the selection of high thermal conductivity materials and the setting of the position of the substrate structure, when the size of the MOS device is reduced to the micro-nano scale, it can still maintain good performance.

[0111] In a feasible embodiment, the power MOS device further includes: a gate dielectric 161 disposed between the gate structure 160 and the channel layer, wherein the channel layer includes a first channel layer 141 and / or a second channel layer 142. The most basic function of the gate dielectric 161 is to act as an insulating layer to isolate the gate from the channel layer. This insulating effect can prevent the gate current from directly flowing into the semiconductor substrate, thereby ensuring the voltage control characteristics of the device.

[0112] In a feasible embodiment, the thickness of the drift layer 110 is 10 to 15 μm; for example, the thickness of the drift layer 110 is 10 μm, 11 μm, 12 μm, 13 μm, 14 μm, 15 μm, etc.

[0113] In a feasible embodiment, the thicknesses of the first channel layer 141 and the second channel layer 142 are 3 to 7 μm; for example, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, etc.

[0114] In a feasible embodiment, the thickness of the gate structure 160 is 0.1 to 0.5 μm; for example, the thickness of the gate structure 160 is 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, etc.

[0115] In a feasible embodiment, the thickness of the dielectric layer 170 is 0.4 to 0.8 μm; for example, the thickness of the dielectric layer 170 is 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, etc.

[0116] In a feasible embodiment, the thickness of the source layer 180 is 1 to 3 μm; for example, the thickness of the source layer 180 is 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, etc.

[0117] In a feasible embodiment, the thickness of the drain layer 130 is 1 to 3 μm; for example, the thickness of the drain layer 130 is 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, etc.

[0118] In a feasible embodiment, the thickness of the first substrate layer 121 and / or the second substrate layer 122 is 30 to 70 μm; for example, the thickness of the first substrate layer 121 and / or the second substrate layer 122 is 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, etc.

[0119] In a feasible embodiment, the material of the drift layer 110 includes at least one of N-type silicon carbide, N-type gallium nitride, N-type gallium arsenide, N-type gallium oxide, N-type aluminum gallium nitride, and N-type aluminum nitride.

[0120] In a feasible embodiment, the material of the gate structure 160 includes at least one of polysilicon, titanium nitride, tantalum nitride, tungsten, and cobalt.

[0121] In a feasible embodiment, the material of the source layer 180 includes at least one of titanium, aluminum, copper, nickel, iridium, rhodium, ruthenium, platinum, gold, silver, palladium, and cobalt.

[0122] In a feasible embodiment, the material of the drain layer 130 includes at least one of titanium, aluminum, copper, nickel, iridium, rhodium, ruthenium, platinum, gold, silver, palladium, and cobalt.

[0123] In this embodiment, although the JFET region of the power MOS device is not the main current-carrying path, its inherent on-resistance will still cause heat accumulation, which in turn affects the overall thermal performance of the device. To effectively solve this problem, in the embodiment of the present application, a first substrate layer 121 and a second substrate layer 122 made of a high thermal conductivity material are provided in the JFET region of the power MOS device, so that the heat generated during device operation can be quickly dissipated, significantly reducing the thermal stress caused by local overheating, and thus effectively reducing the operating temperature of the device. By optimizing thermal management, the long-term reliability of the device is significantly improved, providing a strong guarantee for the performance stability under high-power operating conditions.

[0124] The second embodiment of the present application provides a method for manufacturing a power MOS device, referring to Figure 2 , including the following steps:

[0125] Step S10, etching the substrate layer 120 to form a trench 123, wherein the material of the substrate layer 120 is a high thermal conductivity material.

[0126] In a feasible embodiment, referring to Figure 3 , a substrate layer 120 with a thickness of 80 - 120 um is provided, and the substrate layer 120 is etched to form a trench 123.

[0127] Optionally, the substrate can be patterned by photolithography to form a trench 123; for example, it can be achieved by lithography techniques such as EBL (electron beam lithography) and DUV (deep ultraviolet lithography). Exemplarily, the patterning step can include: cleaning, spin coating, exposure, development, and etching the substrate layer 120 using lithography techniques to form a trench 123 and a substrate layer 120 with a columnar structure.

[0128] Optionally, the material of the substrate layer 120 includes: diamond.

[0129] Step S20, preparing a drift layer 110 in the trench 123.

[0130] In a feasible embodiment, referring to Figure 4 , a drift layer 110 is prepared in the trench 123.

[0131] Exemplarily, an epitaxial layer is grown in the trench 123 and on the front surface of the substrate layer 120 as the drift layer 110, wherein the N-type doping concentration of the drift layer 110 is 1e15 - 1e17 cm -3 , and the material of the drift layer 110 includes at least one of N-type silicon carbide, N-type gallium nitride, N-type gallium arsenide, N-type gallium oxide, N-type aluminum gallium nitride, and N-type aluminum nitride.

[0132] Optionally, the thickness of the drift layer 110 is 10 - 15 um.

[0133] Step S30: Prepare a channel layer 140 on the front side of the substrate layer 120 and the drift layer 110.

[0134] In a feasible embodiment, refer to Figure 5 , and prepare a channel layer 140 on the front side of the substrate layer 120 and the drift layer 110.

[0135] Exemplarily, the surface drift layer 110 located on the front side of the substrate layer 120 is made into a channel layer 140 by means of ion implantation and high-temperature activation.

[0136] Step S40: Perform P-type doping on a partial area of the channel layer 140 to obtain a P-type well 151.

[0137] In a feasible embodiment, perform P-type doping on a partial area of the channel layer 140 to obtain a P-type well 151, where the doping concentration of the P-type well 151 is 1e17 - 5e17 cm -3 .

[0138] In a feasible implementation manner, step S40: The steps of performing P-type doping on a partial area of the channel layer 140 to obtain a P-type well 151 include:

[0139] Step S41: Prepare a first oxide layer 143 on the front side of the channel layer 140;

[0140] Step S42: Define a first photoresist pattern 144 on the front side of the first oxide layer 143;

[0141] Step S43: Etch the first oxide layer 143 based on the first photoresist pattern 144 to form a P-type well 151 implantation window;

[0142] Step S44: Perform P-type doping on the channel layer 140 exposed to the P-type well 151 implantation window to obtain a P-type well 151.

[0143] In a feasible embodiment, refer to Figure 6 , deposit a first oxide layer 143 on the front side of the channel layer 140, define a first photoresist pattern 144 on the front side of the first oxide layer 143, use the first photoresist pattern 144 as an anti-etching layer to etch the first oxide layer 143 to form a P-type well 151 implantation window (not shown in the drawings); and then perform P-type doping with a concentration of 1e17 - 5e17 / cm -3 on the channel layer 140 exposed to the P-type well 151 implantation window to obtain a P-type well 151.

[0144] Step S50: Perform N-type doping on a partial area of the P-type well 151 to obtain an N-type doped region 152.

[0145] In a feasible embodiment, a part of the P-type well 151 is subjected to N-type doping with a concentration of 1e18 to 1e19 cm -3 to obtain an N-type doped region 152.

[0146] In a feasible implementation manner, before the step of performing N-type doping on a part of the P-type well 151 in step S50, it further includes:

[0147] Step S51, preparing a second oxide layer with a first thickness on the front surface of the first oxide layer 143;

[0148] Step S52, etching the second oxide layer with the first thickness to form sidewalls 145 located on both sides of the implantation window of the P-type well 151.

[0149] In a feasible embodiment, referring to Figure 7 , removing the first photoresist pattern 144, preparing a second oxide layer with a first thickness (for example, ) on the front surface of the first oxide layer 143 (not shown in the drawing), and etching the second oxide layer with the first thickness, thereby forming sidewalls 145 located on both sides of the implantation window of the P-type well 151. Further, referring to Figure 8 , through the shielding of the sidewalls 145, a part of the P-type well 151 exposed to the implantation window of the P-type well 151 is subjected to N-type doping to obtain an N-type doped region 152.

[0150] Step S60, performing P-type doping on a part of the N-type doped region 152 to obtain a P-type doped region 153.

[0151] In a feasible embodiment, referring to Figure 9 , through photolithography, P-type impurities with a concentration of 1e18 to 1e19 cm -3 are implanted into a part of the N-type doped region 152 to achieve P-type doping and obtain a P-type doped region 153.

[0152] In a feasible implementation manner, before the step of sequentially preparing a gate structure 160 and a dielectric layer 170 on the front surface of the channel layer 140 in step S70, it further includes: referring to Figure 10 , removing the first oxide layer 143 and the sidewalls 145, and thermally growing a layer of thermal oxide on the front surface of the channel layer 140 as the gate dielectric 161.

[0153] Step S70, sequentially preparing a gate structure 160 and a dielectric layer 170 on the front surface of the channel layer 140, wherein the dielectric layer 170 coats the gate structure 160.

[0154] In a feasible embodiment, a gate structure 160 and a dielectric layer 170 that coats the gate structure 160 are sequentially prepared on the front surface of the channel layer 140.

[0155] In a feasible embodiment, step S70, the step of sequentially fabricating a gate structure 160 and a dielectric layer 170 on the front surface of the channel layer 140 includes:

[0156] Step S71, fabricating a gate layer on the front surface of the channel layer 140;

[0157] Step S72, etching the gate layer to obtain the gate structure 160;

[0158] In a feasible embodiment, referring to Figure 11 , deposit a gate layer on the front surface of the channel layer 140, and obtain the gate structure 160 through etching.

[0159] Step S73, fabricating a dielectric layer 170 on the front surface of the gate structure 160.

[0160] In a feasible embodiment, referring to Figure 12 , deposit a dielectric layer 170 on the front surface of the gate structure 160 to coat the gate structure 160.

[0161] Step S80, etching the dielectric layer 170 to obtain a via hole 171.

[0162] In a feasible embodiment, referring to Figure 13 , etch the dielectric layer 170 to obtain a via hole 171, wherein the N-type doped region 152 and the P-type doped region 153 are exposed through the via hole 171.

[0163] Step S90, fabricating a source layer 180, wherein the source layer 180 is in contact with the N-type doped region 152 and the P-type doped region 153 through the via hole 171.

[0164] In a feasible embodiment, referring to Figure 14 , fabricate a source layer 180 and make the source layer 180 in contact with the N-type doped region 152 and the P-type doped region 153 through the via hole 171.

[0165] Step S100, removing the substrate layer 120 located on the back surface of the drift layer 110 to expose the drift layer 110.

[0166] In a feasible embodiment, referring to Figure 15 , remove the substrate layer 120 located on the back surface of the drift layer 110 to expose the drift layer 110.

[0167] Step S110, fabricating a drain layer 130 on the back surface of the drift layer 110 to obtain a power MOS device.

[0168] In a feasible embodiment, referring to Figure 1 , fabricate a drain layer 130 on the back surface of the drift layer 110 to obtain a power MOS device.

[0169] In this embodiment, by providing the first substrate layer and the second substrate layer made of high thermal conductivity material in the JFET region of the power MOS device, the heat generated by the device during operation can be quickly conducted away, and the thermal stress caused by local overheating can be significantly reduced, thereby effectively reducing the operating temperature of the device. By optimizing thermal management, the long-term reliability of the device can be significantly improved, providing a strong guarantee for the performance stability under high-power operation.

[0170] The above are only preferred embodiments of the present application, and do not limit the scope of the present application. For those skilled in the art, the present application may have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the scope of patent protection of the present application.

Claims

1. A power MOS device, characterized in that: The power MOS device comprises: drift layer; A first substrate layer and a second substrate layer are respectively arranged on both sides of the drift layer, wherein the material of the first substrate layer and / or the second substrate layer is a high thermal conductivity material; A drain layer, disposed on the back side of the drift layer; A first channel layer and a second channel layer are respectively arranged on the front sides of the first substrate layer and the second substrate layer; A P-type well is disposed between the first channel layer and the second channel layer, an N-type doped region is formed inside the P-type well, and a P-type doped region is formed inside the N-type doped region; A gate structure, disposed on the front side of the first channel layer and the second channel layer; A dielectric layer is disposed on the front side of the gate structure and covers the gate structure; the dielectric layer is provided with a connection hole; The source layer is arranged on the front side of the dielectric layer and contacts the N-type doping region and the P-type doping region through the connecting hole.

2. The power MOS device according to claim 1, characterized in that: The material of the first substrate layer and / or the second substrate layer includes: diamond.

3. The power MOS device according to claim 1, characterized in that: The power MOS device further includes: a gate dielectric disposed between the gate structure and the channel layer, wherein the channel layer includes a first channel layer and / or a second channel layer.

4. The power MOS device according to claim 1, characterized in that: The thickness of the drift layer is 10-15 um; And / or, the thickness of the first channel layer and the second channel layer is 3-7 um; And / or, the thickness of the gate structure is 0.1-0.5 um; And / or, the thickness of the dielectric layer is 0.4-0.8 um; And / or, the thickness of the source layer is 1-3 um; And / or, the thickness of the drain electrode layer is 1-3 um.

5. The power MOS device according to claim 1, characterized in that: The material of the drift layer includes: at least one of N-type silicon carbide, N-type gallium nitride, N-type gallium arsenide, N-type gallium oxide, N-type aluminum gallium nitride and N-type aluminum nitride; And / or, the material of the gate structure includes: at least one of polysilicon, titanium nitride, tantalum nitride, tungsten and cobalt; And / or, the material of the source layer includes: at least one of titanium, aluminum, copper, nickel, iridium, rhodium, ruthenium, platinum, gold, silver, palladium and cobalt; And / or, the material of the drain electrode layer includes at least one of titanium, aluminum, copper, nickel, iridium, rhodium, ruthenium, platinum, gold, silver, palladium and cobalt.

6. A method for preparing a power MOS device, characterized in that: The method for preparing a power MOS device is used to prepare a power MOS device as claimed in any one of claims 1 to 5, comprising the following steps: Etching a substrate layer to form a groove, wherein the substrate layer is made of a high thermal conductivity material; preparing a drift layer in the trench; preparing a channel layer on the front side of the substrate layer and the drift layer; Performing P-type doping on a partial region of the channel layer to obtain a P-type well; Performing N-type doping on a partial area of ​​the P-type well to obtain an N-type doped area; Performing P-type doping on a portion of the N-type doping region to obtain a P-type doping region; A gate structure and a dielectric layer are sequentially prepared on the front side of the channel layer, wherein the dielectric layer covers the gate structure; Etching the dielectric layer to obtain a connecting hole; preparing a source layer, wherein the source layer contacts the N-type doping region and the P-type doping region through the connection hole; removing the substrate layer located at the back side of the drift layer to expose the drift layer; A drain layer is prepared on the back side of the drift layer to obtain a power MOS device.

7. The method for preparing a power MOS device according to claim 6, characterized in that: The step of performing P-type doping on a partial area of ​​the channel layer to obtain a P-type well comprises: Preparing a first oxide layer on the front side of the channel layer; defining a first photoresist pattern on the front surface of the first oxide layer; Etching the first oxide layer based on the first photoresist pattern to form a P-type well injection window; The channel layer exposed to the P-type well implantation window is subjected to P-type doping to obtain the P-type well.

8. The method for preparing a power MOS device according to claim 7, characterized in that: Before the step of performing N-type doping on a partial area of ​​the P-type well, the method further includes: forming a second oxide layer of a first thickness on the front side of the first oxide layer; The second oxide layer having a first thickness is etched to form sidewalls located on both sides of the P-type well injection window.

9. The method for preparing a power MOS device according to claim 6, wherein: The step of sequentially preparing a gate structure and a dielectric layer on the front side of the channel layer comprises: Preparing a gate layer on the front side of the channel layer; Etching the gate layer to obtain the gate structure; The dielectric layer is prepared on the front side of the gate structure.

10. The method for preparing a power MOS device according to claim 6, wherein: The doping concentration of the P-type doping in the partial area of ​​the channel layer is 1e17-5e17 cm -3 ; And / or, the doping concentration of the N-type doping in the partial area of ​​the P-type well is 1e18-1e19 cm -3 ; And / or, the doping concentration of the P-type doping of a part of the N-type doping region is 1e18-1e19 cm -3 .

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