Fully depleted semiconductor-on-insulator switch with built-in electrostatic discharge protection

Abstract

The invention relates to a fully depleted semiconductor-on-insulator switch with built-in electrostatic discharge protection. The disclosed semiconductor structure includes: a semiconductor layer including a switching region having a first portion and a second portion side by side; and an RF switch having built-in ESD / surge protection. In one embodiment, an RF switch includes transistors connected in series, the transistors including: source / drain regions within a first portion of a switching region and a channel region laterally between the source / drain regions; and parallel gates adjacent to the channel regions, respectively, the gates traversing the first portion of the switching region without further extending onto the second portion. The outer source / drain regions are silicided and contacted, while the inner source / drain regions are not silicided and contacted. A second portion of the switching region is in contact with the source / drain region in the first region, is not silicided, and is doped or lightly doped. Thus, the second portion forms a resistive element connected in parallel with the serially connected transistors.

Description

Technical Field

[0001] The present disclosure relates to switches, and more particularly, to fully depleted silicon-on-insulator radio frequency (RF) switches. Background Art

[0002] Switches configured for RF operation (also referred to herein as RF switches) are typically incorporated into devices such as transceivers. For example, a conventional transceiver front end may include an antenna, an input / output pad electrically connected to the antenna, and an RF switch configured to selectively connect a receiver branch to the input / output pad and thus to the antenna. One or more electrostatic discharge (ESD) protection structures, such as shunt inductors or other ESD protection structures, are typically integrated into the receiver branch between the RF switch and downstream components and / or between the RF switch and the input / output pad to provide electrostatic discharge. However, the RF switch is not configured to self-protect against ESD or other power surges. Summary of the Invention

[0003] Embodiments of a structure are disclosed herein. The structure may include a semiconductor layer having a switching region. The switching region may have a first portion and a second portion adjacent to the first portion. The structure may further include a switch. The switch may include transistors connected in series. The transistors connected in series together may include source / drain regions within the first portion of the switching region and a channel region laterally located between the source / drain regions. They may also include gates respectively adjacent to the channel region. The gates may only cross the first portion of the switching region such that the second portion of the switching region extends beyond the gates.

[0004] Some embodiments of a structure disclosed herein may include a semiconductor layer having a plurality of switching regions. Each switching region may have a first portion and a second portion adjacent to the first portion. The structure may further include a plurality of switches. Each switch may include a switching region (i.e., a respective one of the switching regions). Each switch may also include transistors connected in series. The transistors connected in series together may include source / drain regions within the first portion of the switching region and a channel region laterally located between the source / drain regions. They may also include gates respectively adjacent to the channel region. The gates may only cross the first portion of the switching region such that the second portion of the switching region extends beyond the gates. Each switch may also include a resistive element within the second portion of the switching region and connected in parallel with the transistors connected in series. In these embodiments, the switches may be connected in series. For example, adjacent source / drain regions of the transistors connected in series in different switching regions are electrically connected.

[0005] Other embodiments of a structure disclosed herein may include a semiconductor layer having a switching region. The switching region may include a first end, a second end opposite the first end, a first portion extending from the first end to the second end, and a second portion adjacent to the first portion and also extending from the first end to the second end. The structure may further include a plurality of switches. Each switch may include transistors connected in series. The transistors connected in series together may include a source / drain region within the first portion of the switching region and a channel region laterally located between the source / drain regions. The transistors connected in series together may further include gates respectively adjacent to the channel region. The gates may only cross the first portion of the switching region such that the second portion of the switching region extends beyond the gates. The switch may further include a resistive element within the second portion of the switching region and connected in parallel with the transistors connected in series. In these embodiments, the plurality of switches may include a first switch and a second switch connected in parallel. The source / drain regions of the first switch and the second switch may include a shared drain region within the first portion of the switching region.

[0006] It should be noted that all aspects, examples, and features of the disclosed embodiments mentioned above can be combined in any technically possible way. That is, two or more aspects of any disclosed embodiment, including those described in the summary of the invention section, can be combined to form embodiments not specifically described herein. Details of one or more embodiments are set forth in the drawings and the following description. Other features, objects, and advantages will be apparent from the specification, the drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure can be better understood by reference to the following detailed description of the drawings, which are not necessarily drawn to scale, in which:

[0008] Figure 1 is a schematic diagram showing an embodiment of a semiconductor structure including an RF switch;

[0009] Figure 2A is further showing Figure 1 an embodiment of the semiconductor structure in a layout view;

[0010] Figures 2B-1 to 2B-3 is Figure 2A an alternative cross-sectional view of the semiconductor structure, showing a different configuration of its second dielectric layer;

[0011] Figures 2C-2G are respectively Figure 2A additional cross-sectional views of the semiconductor structure;

[0012] Figure 3 is a layout view showing an embodiment of a semiconductor structure including a plurality of RF switches connected in series;

[0013] Figure 4 is a layout diagram showing an embodiment of a semiconductor structure including two RF switches connected in parallel;

[0014] Figure 5 is a flowchart showing an embodiment of the disclosed method; and

[0015] Figures 6A-6B , 7A - 7D, 8A - 8D, 9A - 9D, and 10A - 10D are diagrams showing Figure 5 the respective steps in the flowchart of. DETAILED DESCRIPTION

[0016] As described above, RF switches typically do not have self - protection configured for ESD or other electrical surges.

[0017] In view of the above, embodiments of a semiconductor structure (e.g., a fully depleted semiconductor-on-insulator structure, such as a fully depleted silicon-on-insulator (FDSOI) structure) are disclosed herein that include an RF switch having built-in protection against ESD or other electrical surges. Specifically, the semiconductor structure may include a semiconductor substrate, an insulator layer on the semiconductor substrate, and a semiconductor layer on the insulator layer. The semiconductor layer may have a switching region defined therein (e.g., by a trench isolation region). The switching region may have a first portion and a second portion side by side, each extending from opposite ends. The semiconductor structure may further include an RF switch. The RF switch may include a transistor (hereinafter referred to as a transistor) connected in series and a resistive element connected in parallel with the transistor. More specifically, the transistor may include a source / drain region within the first portion of the switching region and a channel region laterally located between the source / drain regions. The source / drain regions may have raised source / drain regions thereon. The transistor may further include parallel gates that are adjacent to the channel region respectively, that traverse the first portion of the switching region without further extending onto the second portion, and that are connected to the same gate control node via a resistor. The external source / drain regions (e.g., at opposite ends of the switching region) may be silicided and contacted, while the internal source / drain regions may be non-silicided and non-contacted. The second portion of the switching region (which extends beyond the ends of the gates) may be in contact with the source / drain regions in the first region, may be non-silicided, and may also be undoped or lightly doped. Thus, in the disclosed embodiments, the resistive element connected in parallel with the series-connected transistor is included within the second portion of the switching region of the semiconductor layer, which is different from MOL or back-end-of-line (BEOL) resistors that are connected to the source / drain regions of the transistor via mid-level-of-line (MOL) contacts. Accordingly, an ESD or any other electrical surge will minimize the likelihood of forming a low-resistance "wire" path between the input and output of the RF switch at the external source / drain regions. Thereby, potential damage to the RF switch is also reduced (i.e., the RF switch includes built-in ESD / surge protection). As discussed in more detail below, additional features may also be optionally incorporated into the transistors of the RF switch to further enhance this built-in ESD / surge protection, as described below. In addition, the additional embodiments disclosed herein may also include a circuit having a plurality of RF switches (similar to the series-connected or parallel-connected RF switches described above).

[0018] Figure 1 FIG. is a disclosed embodiment of a semiconductor structure 1 including an RF switch 100 having built-in protection against ESD or other electrical surges. Figure 2A is Figure 1 a layout diagram of an example of the semiconductor structure 1. Figure 2B-2 G are respectively Figure 2A different cross-sectional views of the semiconductor structure 1.

[0019] Reference Figure 1 , typically, the RF switch 100 may include a plurality of field effect transistors (FETs) 110, 120, 130 (i.e., a plurality of serially connected FETs) serially connected between an input terminal 181 for receiving an RF signal and an output terminal 182 for outputting an RF signal. For example, the FETs 110, 120, 130 may be N-channel FETs (NFETs). For illustrative purposes, three serially connected FETs are shown in the figure. Then, it should be understood that the drawings are not intended to be restrictive. The RF switch performance can be improved by increasing the number of stacked FETs. Thus, the RF switch 100 may at least include a first FET 110 at one end of the stack connected to the input terminal 181 and a second FET 120 at the opposite end of the stack connected to the output terminal 182. Optionally, the RF switch 100 may include one or more additional FETs (e.g., additional FET 130) serially connected between the first FET 110 and the second FET 120.

[0020] The FETs 110, 120, 130 may each include a channel region 113, 123, 133 laterally located between source / drain regions 111-112, 121-122, 131-132. The FETs 110, 120, 130 may each further include main gates 115, 125, 135 (also referred to herein as front gates) adjacent to the channel regions 113, 123, 133. The source / drain regions between the main gates of adjacent FETs (also referred to herein as internal source / drain regions) may be shared (e.g., see the internal source / drain region 112 / 131 between the main gates 115 and 135, and the internal source / drain regions 132 / 121 and 121 between the main gates 135 and 125). That is, they may be located in the same doped region. The external source / drain regions (e.g., see the source / drain region 111 of the FET 110 and the source / drain region 122 of the FET 120) may be the input and output terminals 181-182 of the RF switch 100, respectively, may be silicided (i.e., may have a silicide layer 185 thereon), and may be contacted (i.e., may have contacts landing thereon). The main gates 115, 135, 125 may be connected via resistors to the same main gate control node 183, which receives a main gate voltage (Vg) for controlling the on / off state of the RF switch 100.

[0021] As discussed in more detail below, the semiconductor structure 1 can be implemented in a fully depleted semiconductor-on-insulator technology processing platform (e.g., a fully depleted silicon-on-insulator (FDSOI) technology processing platform) such that each of the FETs 110, 120, 130 also has a secondary gate 114, 124, 134 (also referred to herein as a back gate). The secondary gates 114, 124, 134 can be electrically connected to a common secondary gate node that receives a secondary gate voltage (Vbg), e.g., for adjusting the threshold voltage (VT) of the FETs 110, 120, 130.

[0022] The RF switch 100 can further include resistive elements 119, 129, 139 (also referred to herein as resistors) connected in parallel with the series-connected FETs 110, 120, 130. However, these resistive elements 119, 129, 139 are not conventional back-end-of-line (BEOL) resistors electrically connected via contacts to the source / drain regions of the series-connected FETs of the RF switch, but can be included within a portion 192 of a switching region 190 of a front-end-of-line (FEOL) semiconductor layer 104. As discussed in more detail below, different portions 191 of the same switching region 190 can include active device regions for the FETs 110, 120, 130. By including the resistive elements 119, 129, 139 within the FEOL semiconductor layer 104, the internal source / drain regions 112 / 131, 132 / 121 do not need to be contacted to connect to BEOL resistors and thus do not need to have a silicide layer formed thereon. Instead, the internal source / drain regions 112 / 131, 132 / 121 can be non-silicided (e.g., can be protected by a silicide blocking layer), thereby minimizing the risk that an ESD or any other electrical surge will cause a low-resistance "filament" path to form between the input and output terminals 181 - 182.

[0023] More particularly, in conjunction with Figure 1 reference Figures 2A-2G , the semiconductor structure 1 can include a semiconductor substrate 101. For example, the semiconductor substrate 101 can be a single-crystalline silicon substrate or a substrate of any other suitable single-crystalline silicon semiconductor material (e.g., silicon-germanium, etc.). In some embodiments, the semiconductor substrate 101 can be doped to have a P-type conductivity with a relatively low conductivity level (e.g., to be a P semiconductor substrate).

[0024] The semiconductor structure 1 may further include a semiconductor-on-insulator region (e.g., a silicon-on-insulator (SOI) region). The semiconductor-on-insulator region may include an insulator layer 103 on a semiconductor substrate 101. For example, the insulator layer 103 may be a thin oxide layer (also referred to herein as a buried oxide (BOX) layer), such as a silicon dioxide layer. Alternatively, the insulator layer 103 may be a relatively thin layer of any other suitable insulator material. The semiconductor-on-insulator region may further include a thin semiconductor layer 104 on the insulator layer 103. For example, the semiconductor layer 104 may be a single-crystalline silicon layer or a layer of any other suitable single-crystalline semiconductor material (e.g., single-crystalline silicon germanium, etc.).

[0025] The semiconductor structure 1 may further include isolation regions 105. For example, the isolation regions 105 may be shallow trench isolation (STI) regions. Specifically, the isolation regions 105 may include trenches extending from the top surface of the semiconductor layer 104 to the insulator layer 103 and optionally into or through the insulator layer 103 (e.g., into the semiconductor substrate 101). The trenches may be filled with one or more layers of isolation material (e.g., silicon dioxide, silicon nitride, silicon oxynitride, etc.). These isolation regions 105 may laterally surround the switching region 190 of the semiconductor layer 104, thereby defining the boundary of the switching region 190. The switching region 190 may be substantially rectangular (e.g., when viewed in a horizontal cross-section). The switching region 190 may have opposite ends 196 and 197 and may further have contiguous side-by-side first and second portions 191 and 192 for FET active device regions and resistor elements 119, 129, 139, respectively.

[0026] The semiconductor structure 1 may further include an RF switch 100. The RF switch 100 may include a plurality of FETs 110, 120, 130 (e.g., NFETs) connected in series. Each FET 110, 120, 130 may include an active device region in a respective portion of the first portion 191 of the switching region 190, and each active device region may include a channel region 113, 123, 133 laterally located between source / drain regions 111-112, 131-132, 121-122. The source / drain regions 111-112, 121-122, 131-132 may have N-type conductivity (e.g., may be N-type source / drain regions), while the channel regions 113, 123, 133 may be intrinsic (i.e., undoped) or may have P-type conductivity at a relatively low conduction level (e.g., P-channel regions). The internal source / drain regions 112 / 131, 132 / 121 may be shared (i.e., may be the same N-doped diffusion region).

[0027] The FETs 110, 120, 130 may each further include a main gate 115, 125, 135 adjacent to their channel regions 113, 123, 133 (e.g., above and adjacent to the channel regions). The main gates 115, 125, 135 may be parallel to each other and may cross a first portion 191 of the switching region 190 without further extending onto a second portion 192. Specifically, each main gate 115, 125, 135 may have a first end section on the isolation region 105 adjacent to one side of the switching region 190, may have a main section that extends laterally across the first portion 191 towards the second portion 192, and may have a second end section near the second portion 192 on the transition region 191t of the first portion 191 of the switching region 190. Thus, the second portion 192 of the switching region 190 extends beyond the second end sections of the main gates 115, 125, and 135.

[0028] Each main gate 115, 125, 135 may include a gate dielectric layer 116, 126, 136 (including one or more layers of gate dielectric material) adjacent to the channel regions 113, 123, 133. Each main gate 115, 125, 135 may further include a gate conductor layer 117, 127, 137 (including one or more layers of gate conductor material) located on the gate dielectric layer 116, 126, 136. For example, in some embodiments, each main gate 115, 125, 135 may be a pre-gate high-k metal gate (HKMG) gate structure. For example, such an HKMG structure may include a gate dielectric layer that includes: an interface layer (e.g., a SiO2 layer and / or a SiON layer) of the first portion 191 of the switching region 190 adjacent to the semiconductor layer 104; and a high-k gate dielectric layer (i.e., a layer of dielectric material having a dielectric constant greater than 3.9, such as a hafnium (Hf)-based dielectric, such as hafnium oxide, hafnium silicate, hafnium silicon oxynitride, or hafnium aluminum oxide, or other suitable high-k dielectrics, such as aluminum oxide, tantalum oxide, or zirconium oxide) located on the interface layer. For example, such an HKMG structure may further include a gate conductor layer 117, 127, 137 that at least includes: one or more stacked metal layers (e.g., a metal capping layer and an additional metal material layer suitable for dipole formation on the metal capping layer) located on the high-k gate dielectric layer, and an N-doped polysilicon gate conductor layer (also referred to herein as a first polysilicon gate conductor layer) located on the metal gate conductor layer. As shown, the gate conductor layers 117, 127, 137 with the topmost layer being the first polysilicon gate conductor layer may be located in all sections of the main gates 115, 125, 135 (i.e., in the first end section, the second end section opposite the first end section, and the main section located laterally between the first end section and the second end section).

[0029] Optionally, the first end portions (over the isolation regions 105) and the main portions of the main gates 115, 125, 135 may further include additional gate conductor layers 118, 128, 138. The additional gate conductor layers 118, 128, 138 may be second polysilicon gate conductor layers 118, 128, 138 (e.g., another N-doped polysilicon gate conductor layer) located above and adjacent to the first polysilicon gate conductor layers 117, 127, 137 of the gate conductor layers. In this case, each main gate 115, 125, 135 has a first height (h1) in the second end portion (as measured from the top surface of the semiconductor layer 104), and a second height (h2) greater than h1 in the first end portion and the main portion.

[0030] The gate sidewall spacers 179 may be laterally adjacent to the sidewalls of each main gate (e.g., to electrically isolate the gate structure from adjacent source / drain regions). As shown, the top surfaces of the gate conductor layers 117, 127, 128 of each main gate 115, 125, 135 and the gate sidewall spacers 179 may be at substantially the same level above the semiconductor layer 104. The gate sidewall spacers 179 may be made of one or more dielectric materials, such as silicon dioxide, silicon oxynitride, silicon nitride, or any other suitable gate sidewall spacer material. Various gate sidewall spacer configurations are known in the art, and thus, a detailed description of these is omitted in this specification to allow the reader to focus on the salient aspects of the disclosed embodiments. It should be noted that the additional gate conductor layers 118, 128, 138 (which are the second gate polysilicon layers as described above) may be in-situ doped and epitaxially grown on the exposed surfaces of the first polysilicon gate conductor layers during processing. Thus, although not illustrated, some lateral growth may occur such that within the first end portions and the main portions of the main gates, the additional gate conductor layers 118, 128, 138 may laterally extend over the gate sidewall spacers 179.

[0031] Those skilled in the art will recognize that during FET processing, gates with gate sidewall spacers are typically formed across the semiconductor layer 104 at a uniform pitch such that non-functional gates (also referred to herein as dummy gates) fall outside of the device regions parallel to the functional gates (e.g., over the isolation regions 105). Such non-functional gates may be present in the final semiconductor structure. To avoid cluttering the drawings, non-functional gate structures are not shown in the figures. However, it should be understood that in the disclosed embodiments, non-functional gates with gate sidewall spacers may be located over the isolation regions 105 adjacent to the opposite ends of the switching regions 190 (e.g., laterally adjacent to the external source / drain regions of the FETs 110, 120 of the RF switch 100) and parallel to the main gates 115, 125, 135.

[0032] The FETs 110, 120, 130 may further include raised source / drain regions 111r-112r, 131r-132r, 121r-122r respectively located on the source / drain regions 111-112, 131-132, 121-122. For example, these raised source / drain regions 111r-112r, 131r-132r, 121r-122r may be epitaxial semiconductor layers doped in-situ (e.g., epitaxial silicon layers or epitaxial layers of some other suitable semiconductor material). During processing, such an epitaxial semiconductor layer may grow from the underlying source / drain region (which is single-crystalline in structure), and thus, the raised source / drain region may also be single-crystalline in structure. The epitaxial semiconductor layer may be further doped in-situ such that the raised source / drain regions 111r-112r, 131r-132r, 121r-122r have N-type conductivity with the same or higher conductivity level as the underlying source / drain regions. For example, the raised source / drain regions may be N+ source / drain regions. Optionally, the raised source / drain regions 111r-112r, 131r-132r, 121r-122r may only partially extend across the entire width of the first part 191 of the switching region 190. In such a case, the raised source / drain regions 111r-112r, 131r-132r, 121r-122r are located on opposite sides of the main portions of the main gates 115, 125, 135, and in the transition region 191t, the ends of the source / drain regions 111-112, 131-132, 121-122 extend towards the second part 192 of the switching region 190 beyond the raised source / drain regions 111r-112r, 131r-132r, 121r-122r and are located on opposite sides of the second end portions of the main gates 115, 125, 135.

[0033] The first dielectric layer 161 is above and adjacent to the top surfaces of the second part 192, the portions of the source / drain regions 111-112, 131-132, 121-122 in the transition region 191t, and the top surfaces of the first polysilicon gate conductors of the gate conductor layers 117, 127, 137 in the second end portions of the main gates 115, 125, 135. The first dielectric layer 161 may be a barrier material deposited and patterned during processing as discussed in detail below with respect to the method to prevent epitaxial semiconductor growth on these specific semiconductor surfaces. For example, the barrier material may be silicon nitride, silicon oxynitride, or any other dielectric material suitable for blocking epitaxial semiconductor growth.

[0034] The externally raised source / drain regions 111r and 122r of FETs 110 and 120 can be the input and output terminals 181 and 182 of the RF switch 100, respectively. The externally raised source / drain regions 111r, 122r can be silicided (i.e., can have a silicide layer 185 thereon) and can be contacted (i.e., can have contacts landing thereon). For example, the silicide layer 185 can be cobalt silicide (CoSi), nickel silicide (NiSi), tungsten silicide (WSi), titanium silicide (TiSi), or any other suitable metal silicide material. The internally raised source / drain regions (e.g., 112r / 131r of FETs 110 and 130, and 132r / 121r of FETs 130 and 120) can be non-silicided and non-contact.

[0035] Specifically, the second dielectric layer 162 can be located above and in immediate proximity to each internally raised source / drain region (e.g., see the second dielectric layer 162 covering the internally raised source / drain regions 121r / 131r and 132r / 121r). The second dielectric layer 162 can be an additional barrier material that has been deposited and patterned during processing as will be discussed in detail regarding the method below to prevent the formation of metal silicide on the internally raised source / drain regions 121r / 131r and 132r / 121r. For example, the additional barrier material can be silicon nitride, silicon oxynitride, or any other dielectric material suitable for forming a barrier to silicide. The additional barrier material can be the same barrier material as used for the first dielectric layer 161 or a different barrier material.

[0036] In any case, the second dielectric layer 162 can also be located above or in immediate proximity to the main segment of any internal main gate between two internally raised source / drain regions (e.g., see the second dielectric layer 162 of the additional gate conductor layer 138 covering the main segment of the main gate 135 of FET 130). Additionally, the second dielectric layer 162 can extend laterally over the main segments of the external main gates 115, 125 of FETs 110 and 120 without further laterally extending onto the externally raised source / drain regions 111r, 122r (e.g., as shown in Figure 2A and Figure 2B-1 ). Alternatively, the second dielectric layer 162 can extend laterally (and only partially) over the main segments of the external main gates 115, 125 of FETs 110 and 120 such that the main segments of the external main gates 115, 125 are partially silicided (e.g., as shown in Figure 2B-2(as shown in). Alternatively, the second dielectric layer 162 may extend laterally entirely over the main portions of the outer main gates 115, 125 of the FETs 110 and 120 and may further extend laterally onto adjacent portions of the outer raised source / drain regions 111r, 122r such that the outer raised source / drain regions 111r, 122r are only partially silicided (e.g., as shown in Figure 2A and Figure 2B-2 (as shown in). Optionally, the second dielectric layer 162 may also be located above and in immediate contact with the first dielectric layer 161 so as to partially or fully cover the first dielectric layer 161.

[0037] It should be noted that the first end portions of the main gates 115, 125, 135 (away from the second part 192 of the switching region 190 and located above the isolation region 105) may not have the first and second dielectric layers 161 - 162. Thus, as shown, these first end portions may include additional gate conductor layers 118, 128, 138 and silicide layers 185 thereon. Further, they may be electrically connected to the same main gate control node 183 through resistors (e.g., via middle-of-line (MOL) contacts and BEOL vias and / or wiring forming the resistors), which receives the main gate voltage (Vg) for controlling the on / off state of the RF switch 100.

[0038] For example, the second part 192 of the switching region 190 can be doped to have N-type conductivity. It should be noted that during processing, the second part 192 can be doped simultaneously with the source / drain regions 111-121, 121-122, 131-132 so as to initially have the same N-type conductivity and conduction level as the source / drain regions 111-121, 121-122, 131-132. However, due to the diffusion of N-type dopants from the elevated N+ source / drain regions 111r-112r, 131r-132r, 121r-122r to the underlying source / drain regions 111-112, 121-122, 131-132, in the final structure, the second part 192 may have a lower conductivity than the source / drain regions 111-121, 121-122, 131-132. Due to the fact that the second part 192 is in contact with the source / drain regions, is relatively thin, has a relatively low N-type conductivity and is not silicided, the segments of the second part 192 that extend beyond the ends of each main gate 115, 125, 135 (e.g., see the segments that extend beyond the main gate 115 between the source / drain regions 111 and 112 / 131, the segments that extend beyond the main gate 135 between the source / drain regions 112 / 131 and 132 / 121, and the segments that extend beyond the main gate 125 between the source / drain regions 132 / 121 and 122) effectively form resistance elements 119, 129, 139 that are connected in parallel with the FETs 110, 120, 130.

[0039] As described above, the semiconductor structure 1 can be implemented on a fully depleted semiconductor-on-insulator technology processing platform (e.g., a fully depleted silicon-on-insulator (FDSOI) technology processing platform) such that each of the FETs 110, 120, 130 also has a secondary gate 114, 124, 134 (also referred to herein as a back gate). More specifically, the well region 102 can be located within the semiconductor substrate 101 adjacent to and at the top surface of the insulator layer 103. The well region 102 can be aligned below the switching region 190. For the purposes of the present disclosure, a well region refers to a region of semiconductor material that is doped (e.g., via a dopant implantation process or any other suitable doping process) to have a specific conductivity type. The well region 102 can be doped to have N-type conductivity (i.e., an N-well). Alternatively, the well region 102 can also be doped to have P-type conductivity (i.e., a P-well). It should be understood that if the well region 102 is a P-well, then the semiconductor structure 1 can further include a buried N-well (not shown) that electrically isolates the P-well from adjacent P-wells (if any) and the lower part of the underlying P semiconductor substrate.

[0040] Those skilled in the art will recognize that one advantage of a fully depleted silicon-on-insulator (such as FDSOI) technology processing platform is that NFETs and PFETs can be formed on an insulator layer above an N-well or a P-well to implement different types of NFETs or PFETs with different VTs. As described above, FETs 110, 120, 130 can be NFETs. For ultra-low threshold voltage (SLVT) or low threshold voltage (LVT) NFETs, the switching region 190 can be defined above the N-well, while for regular threshold voltage (RVT) or high threshold voltage (HVT) NFETs, the switching region 190 can be defined above the P-well. Whether the NFET is an SLVT or LVT NFET or whether the NFET is an RVT or HVT NFET will depend on the design (such as device size, etc.) and process specifications (such as doping concentration, etc.).

[0041] Another advantage of a fully depleted silicon-on-insulator (such as FDSOI) technology processing platform is that back-gate biasing (referred to as back biasing) with a back-gate voltage (Vbg) can be employed to fine-tune the FET VT. More specifically, each of the FETs 110, 120, 130 can include a secondary gate 114, 124, 134 (also referred to as the back gate). Each of the secondary gates 114, 124, 134 can include a corresponding section of the insulator layer 103 and the underlying well region 102. By applying a specific Vbg to the well region 102, simultaneous back-gate biasing can be achieved. Forward back-gate biasing (FBB) refers to applying a specific Vbg to the back gate to lower the VT of the FET, while reverse back-gate biasing (RBB) refers to applying a specific Vbg to the back gate to increase the VT. Generally speaking, for NFETs, FBB is achieved by applying +Vbg to the back gate, while RBB is achieved by applying -Vbg.

[0042] To facilitate the biasing of the well region 102, it should be understood that the semiconductor structure 1 may further include a body region (also referred to as a hybrid region). The body region may not have an insulator layer, but instead includes one or more contact regions (also referred to as taps) located on the semiconductor substrate adjacent to the well region 102 and electrically isolated from the switching region 190 (e.g., by the isolation region 105). For example, each tap may include an epitaxially grown single-crystalline semiconductor layer (e.g., an epitaxially grown silicon layer or an epitaxially grown layer of any other suitable semiconductor material) on the top surface of the semiconductor substrate 101 adjacent to the well region 102. The epitaxially grown semiconductor layer may be further in-situ doped or subsequently implanted to have the same type of conductivity (e.g., a higher conductivity level) as the underlying well region 102. Optionally, each tap may further include a silicide layer thereon and may be electrically connected to receive Vbg. The body region with taps facilitates the biasing of the well region, and thus facilitates the back gate of the FET in a fully depleted semiconductor-on-insulator (such as FDSOI) structure, which is well known in the art. Therefore, these regions are omitted in the specification and drawings so that the reader can focus on the prominent aspects related to the configuration of the RF switch 100 in the disclosed embodiments (e.g., related to the resistive elements 119, 129, 139, which are located within the second portion 192 of the switching region 190 and are connected in parallel to the series-connected FETs 110, 120, 130 having an active device region within the first portion 191 of the switching region 190).

[0043] Additional semiconductor structure embodiments disclosed herein include circuits 300, 400 having multiple instances of RF switches 100 (e.g., see RF switches 100.1 and 100.2) connected in series (as shown) and in parallel (as shown). Figure 3 shown) and in parallel (as shown) Figure 4 shown).

[0044] Referring to Figure 3 and Figure 1 and Figures 2A-2G the semiconductor structure 1 therein, similar to Figure 3 the semiconductor structure 3 of Figure 1 andFigures 2A-2G The RF switches 100 in [[ ]] are configured substantially the same. That is, each of the RF switches 100.1 and 100.2 may include FETs 110, 120, 130 connected in series, which have active device regions located in the first part 191 of the corresponding switch regions 190.1 and 190.2, and resistive elements 119, 129, 139 located in the second part 192 of the corresponding switch regions 190.1 and 190.2, so as to be electrically connected in parallel with the FETs 110, 120, 130. In addition, the interconnect 189 may electrically connect the output terminal 182 of one RF switch 100.1 to the input terminal 181 of the other RF switch 100.2. For example, the interconnect 189 may be a local interconnect that is adjacent to the isolation region 105 between the two switch regions 190.1 and 190.2 and extends laterally across the isolation region 105 between the two switch regions 190.1 and 190.2. Alternatively, the interconnect 189 may include a combination of MOL contacts and BEOL wiring and / or vias.

[0045] Reference Figure 4 , with Figure 1 and Figures 2A-2G the semiconductor structure 1 in [[ ]] being similar, Figure 4 the semiconductor structure 4 in [[ ]] may include a semiconductor substrate 101, an insulator layer 103 on the semiconductor substrate 101, and a semiconductor layer 104 on the insulator layer 103. However, in this case, the semiconductor structure 4 may include a circuit 400 having multiple RF switch instances (e.g., see the RF switches 100.1 and 100.2) on the same switch region 190. That is, the semiconductor layer 104 may have a single switch region 190 defined therein by the isolation region 105. The switch region 190 may be aligned above the corresponding well region 102 in the semiconductor substrate 101. The RF switches 100.1 and 100.2 in the switch region 190 may be connected in parallel. Specifically, the RF switches 100.1 and 100.2 may be the same as those described in detail above Figure 1 and Figures 2A-2G ​The RF switches 100 in the switch area 190 are configured substantially identically. That is, the RF switches 100.1 and 100.2 may each have FETs 110, 120, 130 connected in series in a first portion 191 of the switch area 190, and have resistor elements 119, 129, 139 in a second portion of the switch area 190 so as to be electrically connected in parallel with the FETs 110, 120, 130 connected in series. However, in this case, the RF switches 100.1 and 100.2 are located on the same switch area 190, wherein the top and bottom of the FET stacks for the RF switches 100.1 and 100.2 are arranged in opposite directions. That is, the first FETs 110 of the RF switches 100.1 and 100.2 are adjacent to each other in the first portion 191 of the switch area 190, and have a shared internal source / drain region 111 (centered in the first portion 191), with a shared elevated source / drain region 111r thereon for a shared input terminal 181. The second FETs 120 of the RF switches 100.1 and 100.2 may be located at opposite ends of the switch region 190. Specifically, these second FETs 120 may have separate (i.e., non-shared) external source / drain regions 122 at first and second ends of the switch region 190 within the first portion 191, respectively, and external raised source / drain regions 122r for separate (i.e., non-shared) output terminals 182.

[0046] refer to Figure 5 , an embodiment of a method for forming a semiconductor structure having an RF switch as described above is disclosed herein. For illustration purposes, the method will be described below, and in the figure, the method of forming a semiconductor structure having an RF switch as described above will be described below. Figure 1 and Figures 2A-2G The method is illustrated in the semiconductor structure 1 of the RF switch 100. However, it should be understood that similar processing techniques can be used to form Figure 3 The semiconductor structure 3 or Figure 4 Semiconductor structure 4.

[0047] For example, the method may include forming an isolation region 105 on the initial semiconductor-on-insulator structure (see process 502 and Figures 6A-6B The initial semiconductor-on-insulator structure may include a single crystal semiconductor substrate 101 (e.g., a single crystal silicon (Si) substrate or a single crystal substrate having other suitable semiconductor materials such as silicon germanium (SiGe), germanium (Ge), etc.). For example, the semiconductor substrate 101 may be doped to have a relatively low conductivity level of P-type conductivity (e.g., a P-type semiconductor substrate). The initial semiconductor-on-insulator structure may further include an insulator layer 103 on the semiconductor substrate 101. The insulator layer 103 may be silicon dioxide (SiO 2) layer (also referred to herein as a buried oxide (BOX) layer) or some other insulator material layer suitable for a back-gate structure. The insulator layer 103 can be relatively thin (e.g., 50 nanometers or less). The initial insulator-on-semiconductor structure can further include a semiconductor layer 104 on the insulator layer 103. The semiconductor layer 104 can be a single-crystalline Si layer or a single-crystalline layer of some other suitable semiconductor material (e.g., SiGe, Ge, etc.). The semiconductor layer 104 can also be relatively thin (e.g., 22 nanometers or less). The isolation region 105 can be formed using conventional shallow trench isolation (STI) formation techniques in process 502 to define the boundaries of the switching region 190. For example, the trenches for the isolation region 105 can be patterned and etched using photolithography techniques such that they extend from the top surface of the semiconductor layer 104 through the insulator layer 103 into the semiconductor substrate 101. After trench formation, one or more layers of isolation material (e.g., silicon dioxide (SiO 2 ) or any other suitable isolation material) can be deposited to fill the trenches. Subsequently, a chemical mechanical polishing (CMP) process can be performed to remove any isolation material from the top surface of the semiconductor layer 104.

[0048] The method can further include forming a well region 102 in the semiconductor substrate 101 (see processes 504 and Figures 6A-6B ). For example, a masked dopant implantation process can be performed to form a well region 102 in the semiconductor substrate 101 adjacent to the bottom surface of the insulator layer 103 and aligned below the switching region 190. Techniques for using a masked dopant implantation process to form a well region in a semiconductor substrate are well known in the art. Therefore, these details are omitted from this specification so that the reader can focus on the prominent aspects of the disclosed embodiments. In any case, a masked dopant implantation process can be performed such that the resulting well region 102 is located below the entire switching region 190 and further extends laterally in a certain direction beyond the switching region 190 to facilitate contact via a well tap. As mentioned above regarding the structural embodiments, the well region 102 can be an N-well or a P-well. In the case of a P-well in a P-type semiconductor substrate, another dopant implantation process can be performed to form a buried N-well (not shown) in the semiconductor substrate 101 below and wider than the P-well such that the buried N-well electrically isolates the P-well from the lower part of the P semiconductor substrate. As described above, the well region 102 can be contacted via a well tap (not shown). The use of well taps in a fully depleted insulator-on-semiconductor (e.g., FDSOI) technology processing platform is well known in the art. Therefore, its details are omitted from the specification and drawings so that the reader can focus on the prominent aspects of the disclosed embodiments and avoid clutter in the drawings.

[0049] Parallel main gates 115, 125, 135 can be formed for each FET of the RF switch 100 (e.g., each serially-connected NFET) (see process 506 and Figures 7A-7D ). Forming the main gates can include depositing one or more layers of gate dielectric material for the gate dielectric layer and then depositing one or more layers of gate conductor material for the gate conductor layer. In some embodiments, the gate dielectric material deposited at process 506 can include an interface layer (e.g., SiO 2 layer and / or SiON layer) and a high-k gate dielectric layer (i.e., a layer of dielectric material having a dielectric constant greater than 3.9, e.g., including a hafnium (Hf)-based dielectric such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or hafnium aluminum oxide, or other suitable high-k dielectrics such as aluminum oxide, tantalum oxide, or zirconium oxide) on the interface layer. The gate conductor material deposited at process 506 can include: one or more stacked metal layers (e.g., a metal capping layer and an additional metal material layer suitable for forming a dipole on the metal capping layer) on the high-k gate dielectric layer, and an N-doped polysilicon gate conductor layer (referred to herein as the first polysilicon gate conductor layer) on the metal gate conductor layer. Subsequently, patterning (e.g., photolithographic patterning) and etching processes can be performed to form an initial gate stack for the main gates 115, 125, 135. Although such patterning and etching processes for forming the main gates of serially-connected FETs are well known in the art, in the disclosed embodiments, the pattern of the resulting main gates is unique. Specifically, in the disclosed embodiments, patterning can be performed such that the resulting main gates are parallel to each other and traverse a first portion 191 of the switch region 190 without further extending onto a second portion 192. More specifically, patterning can be performed such that each main gate 115, 125, 135 has a first end segment on the isolation region 105 adjacent to one side of the switch region 190, a main segment that extends laterally across the first portion 191 towards the second portion 192, and a second end segment near the second portion 192 on the transition region 191t of the first portion 191 of the switch region 190. Thus, the second portion 192 of the switch region 190 extends beyond the second end segments of the main gates 115, 125, and 135.

[0050] In addition, at process 506, gate sidewall spacers 179 can be formed on the main gates 115, 125, 135. For example, one or more layers of dielectric spacer material can be conformally deposited over the partially completed structure. For example, the dielectric spacer material can be silicon dioxide, silicon oxynitride, or any other suitable dielectric spacer material. Then, a selective anisotropic etching process can be performed to remove the spacer material from the horizontal surfaces, leaving it substantially intact on the vertical surfaces as sidewall spacers.

[0051] Those skilled in the art will recognize that during FET processing, gates with gate sidewall spacers are typically formed at a uniform pitch across semiconductor layer 104 such that non-functional gates (also referred to herein as dummy gates) also fall outside the device region (e.g., on isolation region 105) parallel to the functional gates. Such non-functional gates can be present in the final semiconductor structure. For the sake of avoiding clutter in the figures, the non-functional gate structures are not shown in the figures. However, it should be understood that in the disclosed embodiments, non-functional gates with gate sidewall spacers can be located on isolation region 105 adjacent to the opposite ends of switch region 190 (e.g., positioned laterally adjacent to the external source / drain regions of FETs 110, 120 of RF switch 100), and are parallel to main gates 115, 125, 135.

[0052] Optionally, a dopant implantation process can be performed after the formation of the gate sidewall spacers (see process 508). For example, an N-type dopant implantation process can be performed to dope the exposed semiconductor material in the first portion 191 of switch region 190 to form source / drain regions 111-112, 121-122, 131-132 on opposite sides of the main segments and the second end segments of main gates 115, 125, 135, respectively, and further dope the exposed semiconductor material in the second portion 192. The doping can be performed such that these doped regions have, for example, N-type conductivity with a relatively low conductivity level (e.g., thus they are N-regions).

[0053] A relatively thin first dielectric layer 161 can be deposited over the partially completed structure and patterned (e.g., by lithography) and etched (see processes 510 and Figures 8A-8D ). Specifically, the first dielectric layer 161 can be patterned and etched such that it remains above and adjacent to the top surfaces of the second portion 192 of switch region 190, the portions of source / drain regions 111-112, 131-132, 121-122 in transition region 191t, and the top surfaces of the first polysilicon gate conductor layers of gate conductor layers 117, 127, 128 in the second end segments of main gates 115, 125, 135. Thus, after process 508, the source / drain regions 111-112, 131-132, 121-122 on opposite sides of the main segments of main gates 115, 125, 135 and the portions of the first polysilicon gate conductor layers of gate conductor layers 117, 127, 137 in the first end segments and main segments of main gates 115, 125, 135 remain exposed. The first dielectric layer 161 can be made of a blocking material (referred to herein as an epitaxial semiconductor growth blocking material), such as silicon nitride, silicon oxynitride, or any other suitable dielectric material that blocks epitaxial semiconductor growth.

[0054] Subsequently, a selective epitaxial deposition process can be performed to deposit in-situ doped epitaxial semiconductor material on the exposed semiconductor surface (see processes 512 and Figures 9A-9D ). For example, the semiconductor material deposited at process 510 can be silicon-doped to have N-type conductivity with a relatively high conductivity level. As a result of this selective epitaxial deposition process, single-crystal raised source / drain regions 111r-112r, 131r-132r, 121r-122r are respectively formed on portions of the source / drain regions 111-112, 131-132, 121-122 on opposite sides of the main portions of the main gates 115, 125, 135. In addition, additional gate conductor layers 118, 128, 138 (i.e., second polysilicon gate conductor layers) are formed on the first end portions and the main portions of each of the main gates 115, 125, 135 adjacent to the first polysilicon gate conductor layers of the gate conductor layers 117, 127, 137.

[0055] A relatively thin second dielectric layer 162 can be deposited over the partially completed structure and patterned (e.g., by lithography) and etched (see processes 514 and Figures 10A-10D)。Specifically, the second dielectric layer 162 can be patterned and etched such that it is located above and adjacent to each internal raised source / drain region (e.g., see the second dielectric layer 162 covering the internal raised source / drain regions 112r / 131r and 132r / 121r), exposing each external raised source / drain region 111r and 122r. As shown, the second dielectric layer 162 can also be patterned and etched such that it remains above and adjacent to the main portion of any main gate between two internal raised source / drain regions (e.g., see the second dielectric layer 162 of the additional gate conductor layer 138 covering the main portion of the main gate 135 of the FET 130). Additionally, the second dielectric layer 162 can be patterned and etched such that it extends laterally above the main portions of the main gates 115, 125 without further extending laterally onto the external raised source / drain regions 111r, 122r (as shown). Alternatively, the second dielectric layer 162 can be patterned and etched such that it extends laterally (and only partially) above the main portions of the main gates 115, 125 or extends onto adjacent portions of the external raised source / drain regions 111r, 122r. Optionally, the second dielectric layer 162 can also be patterned and etched such that it remains above and adjacent to the first dielectric layer 161 to partially or fully cover the first dielectric layer 161. In any case, the second dielectric layer 162 can be an additional barrier material (referred to herein as a silicide barrier material), such as silicon nitride, silicon oxynitride, or any other dielectric material suitable for blocking silicide formation. Additionally, it can be the same barrier material as or a different barrier material from that used for the first dielectric layer 161.

[0056] A metal silicide layer 185 can then be formed on the exposed semiconductor surface (e.g., silicon or polysilicon surface), including but not limited to on the external raised source / drain regions 111r and 122r, on the second polysilicon gate conductor layer of the first end portions of the main gates 115, 125, 135, and on the well taps (not shown) (see processes 516 and Figures 2A-2G ). Depending on the patterning of the second dielectric layer 162, the silicide layer 185 can completely cover the top surface of the external raised source / drain regions (see Figure 2B-1 ), can partially cover the main portions of the main gates 115 and 125 (see Figure 2B-2 ), or can only partially cover the top surface of the external raised source / drain regions (see Figure 2B-3)。For example, the silicide layer 185 can be a layer of cobalt silicide, nickel silicide, tungsten silicide, titanium silicide, or a silicide of any other suitable metal or metal alloy material. Techniques for forming metal silicide layers are well known in the art, and thus, the details thereof are omitted in this specification so that the reader can focus on the prominent aspects of the disclosed embodiments.

[0057] After silicide formation, middle-of-line (MOL) processing can be performed (see process 518). For example, an MOL dielectric layer can be formed (e.g., grown, deposited, or otherwise formed) to cover the partially completed structure shown. For example, the MOL dielectric layer can include an etch stop layer and a blanket interlayer dielectric (ILD) material layer on the etch stop layer. For example, the etch stop layer can be a relatively thin conformal silicon nitride layer or a relatively thin conformal layer of some other suitable etch stop material. For example, the ILD material layer can be a blanket layer of silicon dioxide, doped silicon glass (e.g., phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG)), or a blanket layer of any other suitable ILD material. Conventional MOL contact formation techniques can be used to form MOL contacts. For example, such MOL contacts can include contacts to the silicide layer 185 located on the first end portions of the main gates 115, 125, 135, on the externally raised source / drain regions 111r and 122r, and on the well taps. Subsequently, back-end-of-line (BEOL) processing can be performed (see process 520). For example, the BEOL processing can include electrically connecting the contacts on the main gates 115, 125, 135 to the same main gate control node 183 via resistors using conventional BEOL processing techniques, and further electrically connecting the main gate control node 183 and the well taps to a bias voltage reference generator for receiving Vg and Vgb, respectively.

[0058] It should be understood that in the above structures and methods, a semiconductor material refers to a material whose electrical conductivity can be changed by doping impurities. Such semiconductor materials include, for example, silicon-based semiconductor materials (e.g., silicon, silicon germanium, silicon germanium carbide, silicon carbide, etc.) and III-V compound semiconductors (i.e., compounds obtained by combining group III elements such as aluminum (Al), gallium (Ga), or indium (In) with group V elements such as nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb)) (e.g., GaN, InP, GaAs, or GaP). A pure semiconductor material, more specifically, a semiconductor material that is not doped with impurities to increase its conductivity (i.e., an undoped semiconductor material) is referred to in the art as an intrinsic semiconductor. A semiconductor material doped with impurities to increase its conductivity (i.e., a doped semiconductor material) is referred to in the art as an extrinsic semiconductor and will be more conductive than an intrinsic semiconductor made of the same substrate. That is, extrinsic silicon is more conductive than intrinsic silicon; extrinsic silicon germanium is more conductive than intrinsic silicon germanium; and so on. In addition, it should be understood that different impurities (i.e., different dopants) can be used to achieve different conduction types (e.g., P-type conductivity and N-type conductivity), and the dopants can vary depending on the different semiconductor materials used. For example, silicon-based semiconductor materials (e.g., silicon, silicon germanium, etc.) are typically doped with group III dopants such as boron (B) or indium (In) to achieve P-type conductivity, while silicon-based semiconductor materials are typically doped with group V dopants such as arsenic (As), phosphorus (P), or antimony (Sb) to achieve N-type conductivity. Gallium nitride (GaN)-based semiconductor materials are typically doped with magnesium (Mg) to achieve P-type conductivity and doped with silicon (Si) or oxygen to achieve N-type conductivity. Those skilled in the art will also recognize that different conduction levels depend on the relative concentration levels of the (one or more) dopants in a given semiconductor region. In addition, when a semiconductor region or layer is described as being at a higher conduction level than another semiconductor region or layer, its conductivity is higher than that of the other semiconductor region or layer (lower resistance); while when a semiconductor region or layer is described as being at a lower conduction level than another semiconductor region or layer, its conductivity is lower than that of the other semiconductor region or layer (higher resistance).

[0059] The above method is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of the original wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in a packaged form. In the latter case, the chips are mounted in the form of a single-chip package (e.g., a plastic carrier, the leads of which are fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier, which has either or both surface interconnects or buried interconnects). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices, as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, ranging from toys and other low-end applications to high-end computer products with a display, a keyboard, or other input devices, and a central processing unit.

[0060] It should be understood that the terms used herein to describe the disclosed structures and methods are not intended to be limiting. For example, as used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms, unless the context clearly dictates otherwise. Additionally, as used herein, the terms "comprises", "comprising", "includes", and / or "including" specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Further, as used herein, when oriented and shown in the figures, terms such as "right", "left", "vertical", "horizontal", "top", "bottom", "upper", "lower", "below", "beneath", "underlying", "above", "overlying", "parallel", "perpendicular", etc. are intended to describe relative positions (unless otherwise stated), and terms such as "touch", "directly contact", "adjacent", "directly adjacent to", "immediately adjacent to" are intended to mean that at least one element is in physical contact with another element (with no other element separating the elements). The term "lateral" is used herein to describe the relative position of elements, and more specifically, when the elements are oriented and shown in the figures, it is used to indicate that one element is located on the side of another element, rather than above or below the other element. For example, an element located laterally adjacent to another element will be beside the other element, an element located laterally immediately adjacent to another element will be directly beside the other element, and an element located laterally around another element will be adjacent to and border the outer wall of the other element. All corresponding structures, materials, acts, and equivalents of the means or step plus function elements in the following claims are intended to include any structure, material, or act for performing the function in combination with other claimed elements specifically recited.

[0061] The descriptions of the various disclosed embodiments are given for illustrative purposes only and are not intended to be exhaustive or limiting. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosed embodiments. The terms used herein are chosen to best explain the principles of the embodiments, the practical application or technical improvement of technologies found in the marketplace, or to enable other ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A structure comprising: a semiconductor layer including a switching region having a first portion and a second portion adjacent to the first portion; as well as A switch comprising transistors connected in series, wherein the transistors connected in series comprise: source / drain regions within the first portion and a channel region laterally located between the source / drain regions; and Gates are respectively adjacent to the channel regions, wherein the gates traverse the first portions, and wherein the second portions extend beyond the gates.

2. The structure according to claim 1, wherein: The switch further includes a resistive element in the second portion and connected in parallel with the series-connected transistors.

3. The structure according to claim 1, wherein: The series-connected transistors further include elevated source / drain regions above the source / drain regions.

4. The structure according to claim 3, in, The switch region includes a first end and a second end opposite to the first end, wherein the source / drain region comprises an external source / drain region at the first end and the second end and at least one internal source / drain region, wherein the elevated source / drain region comprises an outer elevated source / drain region on the outer source / drain region and an inner elevated source / drain region on each inner source / drain region, and Wherein, the switch further comprises a silicide layer above and immediately adjacent to only the outer elevated source / drain regions of the elevated source / drain regions.

5. The structure according to claim 4, in, The gate has a main portion laterally located between the elevated source / drain regions and end portions extending from the main portion toward the second portion and beyond the elevated source / drain regions, respectively, wherein the end subdivision includes a first polysilicon gate conductor layer, and the main subdivision includes the first polysilicon gate conductor layer and a second polysilicon gate conductor layer on the first polysilicon gate conductor layer, and Wherein, the end section has a first height, and the main section has a second height greater than the first height.

6. The structure according to claim 5, further comprising: a first dielectric layer over and immediately adjacent to the second portion, extending onto a transition region of the first portion immediately adjacent to the second portion, and further extending over the first polysilicon gate conductor layer of the end portion of the gate; as well as A second dielectric layer, wherein the second dielectric layer is located above each inner elevated source / drain region above each inner source / drain region and is also located above and immediately adjacent to the second polysilicon gate semiconductor layer of the main portion of the gate.

7. The structure according to claim 6, wherein: The second dielectric layer extends laterally over an outer gate of the gate and onto the outer raised source / drain regions.

8. The structure according to claim 6, wherein: The second dielectric layer extends laterally over an outer gate of the gate without extending further onto the outer raised source / drain regions.

9. The structure according to claim 6, wherein: The second dielectric layer extends laterally partially over an outer gate of the gate.

10. The structure according to claim 1, in, The series-connected transistors are N-channel field effect transistors, wherein the source / drain region has N-type conductivity, and The second portion has N-type conductivity at a lower conductivity level than the source / drain region.

11. The structure according to claim 1, further comprising: Semiconductor substrate; a well region in the semiconductor substrate; an insulator layer on the semiconductor substrate, wherein the semiconductor layer is on the insulator layer; as well as A trench isolation region extends through the semiconductor layer to define a boundary of the switch region above the well region.

12. A structure comprising: a semiconductor layer including a plurality of switching regions, wherein each switching region has a first portion and a second portion adjacent to the first portion; and Multiple switches, Each switch includes: Switch area; A series connection of transistors comprising: source / drain regions within the first portion of the switching region and a channel region laterally located between the source / drain regions; and a gate each adjacent to the channel region, wherein the gate traverses the first portion of the switch region, and wherein the second portion of the switch region extends beyond the gate; and a resistive element connected in parallel with the series-connected transistors in the second portion of the switching region, and Wherein, the switches are connected in series.

13. The structure according to claim 12, wherein: The series-connected transistors further include elevated source / drain regions above the source / drain regions.

14. The structure according to claim 13, in, the source / drain region comprises an outer source / drain region and at least one inner source / drain region at opposite ends of the first portion, wherein the elevated source / drain region comprises an outer elevated source / drain region on the outer source / drain region and an inner elevated source / drain region on each inner source / drain region, and Wherein each switch further comprises a silicide layer above and immediately adjacent only the outer elevated source / drain regions of the elevated source / drain regions.

15. The structure according to claim 14, in, The gate has a main portion laterally located between the elevated source / drain regions and end portions extending from the main portion toward the second portion and beyond the elevated source / drain regions, respectively, wherein the end subdivision includes a first polysilicon gate conductor layer, and the main subdivision includes the first polysilicon gate conductor layer and a second polysilicon gate conductor layer on the first polysilicon gate conductor layer, wherein the end section has a first height and the main section has a second height greater than the first height, and Each switch further comprises: a first dielectric layer over and immediately adjacent to the second portion, extending onto a transition region of the first portion immediately adjacent to the second portion, and further extending over the first polysilicon gate conductor layer of the end portion of the gate; and A second dielectric layer is located on each inner elevated source / drain region and is located above and immediately adjacent to the second polysilicon gate semiconductor layer of the main portion of the gate.

16. The structure of claim 12, further comprising: Semiconductor substrate; a well region in the semiconductor substrate; an insulator layer on the semiconductor substrate, wherein the semiconductor layer is on the insulator layer; as well as A trench isolation region extends through the semiconductor layer to define a boundary of the switch region above the well region.

17. A structure comprising: a semiconductor layer including a switch region, wherein the switch region includes a first end, a second end opposite to the first end, a first portion extending from the first end to the second end, and a second portion adjacent to the first portion and extending from the first end to the second end; and A plurality of switches, wherein each switch comprises: A series connection of transistors comprising: source / drain regions within the first portion of the switching region and a channel region laterally located between the source / drain regions; and a gate each adjacent to the channel region, wherein the gate traverses the first portion of the switch region, and wherein the second portion of the switch region extends beyond the gate; and a resistor element connected in parallel with the series-connected transistors in the second portion of the switch region, wherein the plurality of switches include a first switch and a second switch connected in parallel, and wherein the source / drain region of the series-connected transistor of the first switch and the source / drain region of the series-connected transistor of the second switch comprise a shared internal source / drain region centered within the first portion of the switch area.

18. The structure according to claim 17, wherein: The series-connected transistors further include elevated source / drain regions above the source / drain regions.

19. The structure according to claim 18, in, the source / drain regions of the series-connected transistor of the first switch and the series-connected transistor of the second switch include separate external source / drain regions at the first end and the second end, respectively, and wherein the structure further comprises a silicide layer on the shared source / drain region, the first external source / drain region and the second external source / drain region, and All other source / drain regions in the structure are not silicided.

20. The structure according to claim 19, in, The gate has a main portion laterally located between the elevated source / drain regions and end portions extending from the main portion toward the second portion and beyond the elevated source / drain regions, respectively, wherein the end subdivision includes a first polysilicon gate conductor layer, and the main subdivision includes the first polysilicon gate conductor layer and a second polysilicon gate conductor layer on the first polysilicon gate conductor layer, wherein the end section has a first height and the main section has a second height greater than the first height, and Wherein, the switch further comprises: a first dielectric layer over and immediately adjacent to the second portion, extending onto a transition region of the first portion immediately adjacent to the second portion, and also extending over the first polysilicon gate conductor layer of the end portion of the gate; and A second dielectric layer overlies any source / drain region between the shared drain region and the first external source region or between the shared drain region and the second external source region and also overlies and is immediately adjacent to the second polysilicon gate conductor layer of the main portion of the gate.

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